stm32f10x_rcc.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f10x_rcc.c
00004   * @author  MCD Application Team
00005   * @version V3.5.0
00006   * @date    11-March-2011
00007   * @brief   This file provides all the RCC firmware functions.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00012   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00013   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00014   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00015   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00016   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00017   *
00018   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00019   ******************************************************************************
00020   */
00021 
00022 /* Includes ------------------------------------------------------------------*/
00023 #include "stm32f10x_rcc.h"
00024 
00025 /** @addtogroup STM32F10x_StdPeriph_Driver
00026   * @{
00027   */
00028 
00029 /** @defgroup RCC 
00030   * @brief RCC driver modules
00031   * @{
00032   */ 
00033 
00034 /** @defgroup RCC_Private_TypesDefinitions
00035   * @{
00036   */
00037 
00038 /**
00039   * @}
00040   */
00041 
00042 /** @defgroup RCC_Private_Defines
00043   * @{
00044   */
00045 
00046 /* ------------ RCC registers bit address in the alias region ----------- */
00047 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
00048 
00049 /* --- CR Register ---*/
00050 
00051 /* Alias word address of HSION bit */
00052 #define CR_OFFSET                 (RCC_OFFSET + 0x00)
00053 #define HSION_BitNumber           0x00
00054 #define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
00055 
00056 /* Alias word address of PLLON bit */
00057 #define PLLON_BitNumber           0x18
00058 #define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
00059 
00060 #ifdef STM32F10X_CL
00061  /* Alias word address of PLL2ON bit */
00062  #define PLL2ON_BitNumber          0x1A
00063  #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
00064 
00065  /* Alias word address of PLL3ON bit */
00066  #define PLL3ON_BitNumber          0x1C
00067  #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
00068 #endif /* STM32F10X_CL */ 
00069 
00070 /* Alias word address of CSSON bit */
00071 #define CSSON_BitNumber           0x13
00072 #define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
00073 
00074 /* --- CFGR Register ---*/
00075 
00076 /* Alias word address of USBPRE bit */
00077 #define CFGR_OFFSET               (RCC_OFFSET + 0x04)
00078 
00079 #ifndef STM32F10X_CL
00080  #define USBPRE_BitNumber          0x16
00081  #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
00082 #else
00083  #define OTGFSPRE_BitNumber        0x16
00084  #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
00085 #endif /* STM32F10X_CL */ 
00086 
00087 /* --- BDCR Register ---*/
00088 
00089 /* Alias word address of RTCEN bit */
00090 #define BDCR_OFFSET               (RCC_OFFSET + 0x20)
00091 #define RTCEN_BitNumber           0x0F
00092 #define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
00093 
00094 /* Alias word address of BDRST bit */
00095 #define BDRST_BitNumber           0x10
00096 #define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
00097 
00098 /* --- CSR Register ---*/
00099 
00100 /* Alias word address of LSION bit */
00101 #define CSR_OFFSET                (RCC_OFFSET + 0x24)
00102 #define LSION_BitNumber           0x00
00103 #define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
00104 
00105 #ifdef STM32F10X_CL
00106 /* --- CFGR2 Register ---*/
00107 
00108  /* Alias word address of I2S2SRC bit */
00109  #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
00110  #define I2S2SRC_BitNumber         0x11
00111  #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
00112 
00113  /* Alias word address of I2S3SRC bit */
00114  #define I2S3SRC_BitNumber         0x12
00115  #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
00116 #endif /* STM32F10X_CL */
00117 
00118 /* ---------------------- RCC registers bit mask ------------------------ */
00119 
00120 /* CR register bit mask */
00121 #define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
00122 #define CR_HSEBYP_Set             ((uint32_t)0x00040000)
00123 #define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
00124 #define CR_HSEON_Set              ((uint32_t)0x00010000)
00125 #define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
00126 
00127 /* CFGR register bit mask */
00128 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
00129  #define CFGR_PLL_Mask            ((uint32_t)0xFFC2FFFF)
00130 #else
00131  #define CFGR_PLL_Mask            ((uint32_t)0xFFC0FFFF)
00132 #endif /* STM32F10X_CL */ 
00133 
00134 #define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
00135 #define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
00136 #define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
00137 #define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
00138 #define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
00139 #define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
00140 #define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
00141 #define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
00142 #define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
00143 #define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
00144 #define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
00145 #define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
00146 #define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
00147 
00148 /* CSR register bit mask */
00149 #define CSR_RMVF_Set              ((uint32_t)0x01000000)
00150 
00151 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 
00152 /* CFGR2 register bit mask */
00153  #define CFGR2_PREDIV1SRC         ((uint32_t)0x00010000)
00154  #define CFGR2_PREDIV1            ((uint32_t)0x0000000F)
00155 #endif
00156 #ifdef STM32F10X_CL
00157  #define CFGR2_PREDIV2            ((uint32_t)0x000000F0)
00158  #define CFGR2_PLL2MUL            ((uint32_t)0x00000F00)
00159  #define CFGR2_PLL3MUL            ((uint32_t)0x0000F000)
00160 #endif /* STM32F10X_CL */ 
00161 
00162 /* RCC Flag Mask */
00163 #define FLAG_Mask                 ((uint8_t)0x1F)
00164 
00165 /* CIR register byte 2 (Bits[15:8]) base address */
00166 #define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
00167 
00168 /* CIR register byte 3 (Bits[23:16]) base address */
00169 #define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
00170 
00171 /* CFGR register byte 4 (Bits[31:24]) base address */
00172 #define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
00173 
00174 /* BDCR register base address */
00175 #define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
00176 
00177 /**
00178   * @}
00179   */ 
00180 
00181 /** @defgroup RCC_Private_Macros
00182   * @{
00183   */ 
00184 
00185 /**
00186   * @}
00187   */ 
00188 
00189 /** @defgroup RCC_Private_Variables
00190   * @{
00191   */ 
00192 
00193 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
00194 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
00195 
00196 /**
00197   * @}
00198   */
00199 
00200 /** @defgroup RCC_Private_FunctionPrototypes
00201   * @{
00202   */
00203 
00204 /**
00205   * @}
00206   */
00207 
00208 /** @defgroup RCC_Private_Functions
00209   * @{
00210   */
00211 
00212 /**
00213   * @brief  Resets the RCC clock configuration to the default reset state.
00214   * @param  None
00215   * @retval None
00216   */
00217 void RCC_DeInit(void)
00218 {
00219   /* Set HSION bit */
00220   RCC->CR |= (uint32_t)0x00000001;
00221 
00222   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
00223 #ifndef STM32F10X_CL
00224   RCC->CFGR &= (uint32_t)0xF8FF0000;
00225 #else
00226   RCC->CFGR &= (uint32_t)0xF0FF0000;
00227 #endif /* STM32F10X_CL */   
00228   
00229   /* Reset HSEON, CSSON and PLLON bits */
00230   RCC->CR &= (uint32_t)0xFEF6FFFF;
00231 
00232   /* Reset HSEBYP bit */
00233   RCC->CR &= (uint32_t)0xFFFBFFFF;
00234 
00235   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
00236   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00237 
00238 #ifdef STM32F10X_CL
00239   /* Reset PLL2ON and PLL3ON bits */
00240   RCC->CR &= (uint32_t)0xEBFFFFFF;
00241 
00242   /* Disable all interrupts and clear pending bits  */
00243   RCC->CIR = 0x00FF0000;
00244 
00245   /* Reset CFGR2 register */
00246   RCC->CFGR2 = 0x00000000;
00247 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00248   /* Disable all interrupts and clear pending bits  */
00249   RCC->CIR = 0x009F0000;
00250 
00251   /* Reset CFGR2 register */
00252   RCC->CFGR2 = 0x00000000;      
00253 #else
00254   /* Disable all interrupts and clear pending bits  */
00255   RCC->CIR = 0x009F0000;
00256 #endif /* STM32F10X_CL */
00257 
00258 }
00259 
00260 /**
00261   * @brief  Configures the External High Speed oscillator (HSE).
00262   * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.
00263   * @param  RCC_HSE: specifies the new state of the HSE.
00264   *   This parameter can be one of the following values:
00265   *     @arg RCC_HSE_OFF: HSE oscillator OFF
00266   *     @arg RCC_HSE_ON: HSE oscillator ON
00267   *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
00268   * @retval None
00269   */
00270 void RCC_HSEConfig(uint32_t RCC_HSE)
00271 {
00272   /* Check the parameters */
00273   assert_param(IS_RCC_HSE(RCC_HSE));
00274   /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
00275   /* Reset HSEON bit */
00276   RCC->CR &= CR_HSEON_Reset;
00277   /* Reset HSEBYP bit */
00278   RCC->CR &= CR_HSEBYP_Reset;
00279   /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
00280   switch(RCC_HSE)
00281   {
00282     case RCC_HSE_ON:
00283       /* Set HSEON bit */
00284       RCC->CR |= CR_HSEON_Set;
00285       break;
00286       
00287     case RCC_HSE_Bypass:
00288       /* Set HSEBYP and HSEON bits */
00289       RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00290       break;
00291       
00292     default:
00293       break;
00294   }
00295 }
00296 
00297 /**
00298   * @brief  Waits for HSE start-up.
00299   * @param  None
00300   * @retval An ErrorStatus enumuration value:
00301   * - SUCCESS: HSE oscillator is stable and ready to use
00302   * - ERROR: HSE oscillator not yet ready
00303   */
00304 ErrorStatus RCC_WaitForHSEStartUp(void)
00305 {
00306   __IO uint32_t StartUpCounter = 0;
00307   ErrorStatus status = ERROR;
00308   FlagStatus HSEStatus = RESET;
00309   
00310   /* Wait till HSE is ready and if Time out is reached exit */
00311   do
00312   {
00313     HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
00314     StartUpCounter++;  
00315   } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
00316   
00317   if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00318   {
00319     status = SUCCESS;
00320   }
00321   else
00322   {
00323     status = ERROR;
00324   }  
00325   return (status);
00326 }
00327 
00328 /**
00329   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00330   * @param  HSICalibrationValue: specifies the calibration trimming value.
00331   *   This parameter must be a number between 0 and 0x1F.
00332   * @retval None
00333   */
00334 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
00335 {
00336   uint32_t tmpreg = 0;
00337   /* Check the parameters */
00338   assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
00339   tmpreg = RCC->CR;
00340   /* Clear HSITRIM[4:0] bits */
00341   tmpreg &= CR_HSITRIM_Mask;
00342   /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
00343   tmpreg |= (uint32_t)HSICalibrationValue << 3;
00344   /* Store the new value */
00345   RCC->CR = tmpreg;
00346 }
00347 
00348 /**
00349   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00350   * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.
00351   * @param  NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
00352   * @retval None
00353   */
00354 void RCC_HSICmd(FunctionalState NewState)
00355 {
00356   /* Check the parameters */
00357   assert_param(IS_FUNCTIONAL_STATE(NewState));
00358   *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
00359 }
00360 
00361 /**
00362   * @brief  Configures the PLL clock source and multiplication factor.
00363   * @note   This function must be used only when the PLL is disabled.
00364   * @param  RCC_PLLSource: specifies the PLL entry clock source.
00365   *   For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, 
00366   *   this parameter can be one of the following values:
00367   *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
00368   *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
00369   *   For @b other_STM32_devices, this parameter can be one of the following values:
00370   *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
00371   *     @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
00372   *     @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry 
00373   * @param  RCC_PLLMul: specifies the PLL multiplication factor.
00374   *   For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
00375   *   For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]  
00376   * @retval None
00377   */
00378 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
00379 {
00380   uint32_t tmpreg = 0;
00381 
00382   /* Check the parameters */
00383   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
00384   assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
00385 
00386   tmpreg = RCC->CFGR;
00387   /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
00388   tmpreg &= CFGR_PLL_Mask;
00389   /* Set the PLL configuration bits */
00390   tmpreg |= RCC_PLLSource | RCC_PLLMul;
00391   /* Store the new value */
00392   RCC->CFGR = tmpreg;
00393 }
00394 
00395 /**
00396   * @brief  Enables or disables the PLL.
00397   * @note   The PLL can not be disabled if it is used as system clock.
00398   * @param  NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
00399   * @retval None
00400   */
00401 void RCC_PLLCmd(FunctionalState NewState)
00402 {
00403   /* Check the parameters */
00404   assert_param(IS_FUNCTIONAL_STATE(NewState));
00405 
00406   *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
00407 }
00408 
00409 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
00410 /**
00411   * @brief  Configures the PREDIV1 division factor.
00412   * @note 
00413   *   - This function must be used only when the PLL is disabled.
00414   *   - This function applies only to STM32 Connectivity line and Value line 
00415   *     devices.
00416   * @param  RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
00417   *   This parameter can be one of the following values:
00418   *     @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
00419   *     @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
00420   * @note 
00421   *   For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE  
00422   * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
00423   *   This parameter can be RCC_PREDIV1_Divx where x:[1,16]
00424   * @retval None
00425   */
00426 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
00427 {
00428   uint32_t tmpreg = 0;
00429   
00430   /* Check the parameters */
00431   assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
00432   assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
00433 
00434   tmpreg = RCC->CFGR2;
00435   /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
00436   tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
00437   /* Set the PREDIV1 clock source and division factor */
00438   tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
00439   /* Store the new value */
00440   RCC->CFGR2 = tmpreg;
00441 }
00442 #endif
00443 
00444 #ifdef STM32F10X_CL
00445 /**
00446   * @brief  Configures the PREDIV2 division factor.
00447   * @note 
00448   *   - This function must be used only when both PLL2 and PLL3 are disabled.
00449   *   - This function applies only to STM32 Connectivity line devices.
00450   * @param  RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
00451   *   This parameter can be RCC_PREDIV2_Divx where x:[1,16]
00452   * @retval None
00453   */
00454 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
00455 {
00456   uint32_t tmpreg = 0;
00457 
00458   /* Check the parameters */
00459   assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
00460 
00461   tmpreg = RCC->CFGR2;
00462   /* Clear PREDIV2[3:0] bits */
00463   tmpreg &= ~CFGR2_PREDIV2;
00464   /* Set the PREDIV2 division factor */
00465   tmpreg |= RCC_PREDIV2_Div;
00466   /* Store the new value */
00467   RCC->CFGR2 = tmpreg;
00468 }
00469 
00470 /**
00471   * @brief  Configures the PLL2 multiplication factor.
00472   * @note
00473   *   - This function must be used only when the PLL2 is disabled.
00474   *   - This function applies only to STM32 Connectivity line devices.
00475   * @param  RCC_PLL2Mul: specifies the PLL2 multiplication factor.
00476   *   This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
00477   * @retval None
00478   */
00479 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
00480 {
00481   uint32_t tmpreg = 0;
00482 
00483   /* Check the parameters */
00484   assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
00485 
00486   tmpreg = RCC->CFGR2;
00487   /* Clear PLL2Mul[3:0] bits */
00488   tmpreg &= ~CFGR2_PLL2MUL;
00489   /* Set the PLL2 configuration bits */
00490   tmpreg |= RCC_PLL2Mul;
00491   /* Store the new value */
00492   RCC->CFGR2 = tmpreg;
00493 }
00494 
00495 
00496 /**
00497   * @brief  Enables or disables the PLL2.
00498   * @note 
00499   *   - The PLL2 can not be disabled if it is used indirectly as system clock
00500   *     (i.e. it is used as PLL clock entry that is used as System clock).
00501   *   - This function applies only to STM32 Connectivity line devices.
00502   * @param  NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
00503   * @retval None
00504   */
00505 void RCC_PLL2Cmd(FunctionalState NewState)
00506 {
00507   /* Check the parameters */
00508   assert_param(IS_FUNCTIONAL_STATE(NewState));
00509 
00510   *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
00511 }
00512 
00513 
00514 /**
00515   * @brief  Configures the PLL3 multiplication factor.
00516   * @note 
00517   *   - This function must be used only when the PLL3 is disabled.
00518   *   - This function applies only to STM32 Connectivity line devices.
00519   * @param  RCC_PLL3Mul: specifies the PLL3 multiplication factor.
00520   *   This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
00521   * @retval None
00522   */
00523 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
00524 {
00525   uint32_t tmpreg = 0;
00526 
00527   /* Check the parameters */
00528   assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
00529 
00530   tmpreg = RCC->CFGR2;
00531   /* Clear PLL3Mul[3:0] bits */
00532   tmpreg &= ~CFGR2_PLL3MUL;
00533   /* Set the PLL3 configuration bits */
00534   tmpreg |= RCC_PLL3Mul;
00535   /* Store the new value */
00536   RCC->CFGR2 = tmpreg;
00537 }
00538 
00539 
00540 /**
00541   * @brief  Enables or disables the PLL3.
00542   * @note   This function applies only to STM32 Connectivity line devices.
00543   * @param  NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
00544   * @retval None
00545   */
00546 void RCC_PLL3Cmd(FunctionalState NewState)
00547 {
00548   /* Check the parameters */
00549 
00550   assert_param(IS_FUNCTIONAL_STATE(NewState));
00551   *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
00552 }
00553 #endif /* STM32F10X_CL */
00554 
00555 /**
00556   * @brief  Configures the system clock (SYSCLK).
00557   * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
00558   *   This parameter can be one of the following values:
00559   *     @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
00560   *     @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
00561   *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
00562   * @retval None
00563   */
00564 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
00565 {
00566   uint32_t tmpreg = 0;
00567   /* Check the parameters */
00568   assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
00569   tmpreg = RCC->CFGR;
00570   /* Clear SW[1:0] bits */
00571   tmpreg &= CFGR_SW_Mask;
00572   /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
00573   tmpreg |= RCC_SYSCLKSource;
00574   /* Store the new value */
00575   RCC->CFGR = tmpreg;
00576 }
00577 
00578 /**
00579   * @brief  Returns the clock source used as system clock.
00580   * @param  None
00581   * @retval The clock source used as system clock. The returned value can
00582   *   be one of the following:
00583   *     - 0x00: HSI used as system clock
00584   *     - 0x04: HSE used as system clock
00585   *     - 0x08: PLL used as system clock
00586   */
00587 uint8_t RCC_GetSYSCLKSource(void)
00588 {
00589   return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
00590 }
00591 
00592 /**
00593   * @brief  Configures the AHB clock (HCLK).
00594   * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
00595   *   the system clock (SYSCLK).
00596   *   This parameter can be one of the following values:
00597   *     @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
00598   *     @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
00599   *     @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
00600   *     @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
00601   *     @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
00602   *     @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
00603   *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
00604   *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
00605   *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
00606   * @retval None
00607   */
00608 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
00609 {
00610   uint32_t tmpreg = 0;
00611   /* Check the parameters */
00612   assert_param(IS_RCC_HCLK(RCC_SYSCLK));
00613   tmpreg = RCC->CFGR;
00614   /* Clear HPRE[3:0] bits */
00615   tmpreg &= CFGR_HPRE_Reset_Mask;
00616   /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
00617   tmpreg |= RCC_SYSCLK;
00618   /* Store the new value */
00619   RCC->CFGR = tmpreg;
00620 }
00621 
00622 /**
00623   * @brief  Configures the Low Speed APB clock (PCLK1).
00624   * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
00625   *   the AHB clock (HCLK).
00626   *   This parameter can be one of the following values:
00627   *     @arg RCC_HCLK_Div1: APB1 clock = HCLK
00628   *     @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
00629   *     @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
00630   *     @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
00631   *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
00632   * @retval None
00633   */
00634 void RCC_PCLK1Config(uint32_t RCC_HCLK)
00635 {
00636   uint32_t tmpreg = 0;
00637   /* Check the parameters */
00638   assert_param(IS_RCC_PCLK(RCC_HCLK));
00639   tmpreg = RCC->CFGR;
00640   /* Clear PPRE1[2:0] bits */
00641   tmpreg &= CFGR_PPRE1_Reset_Mask;
00642   /* Set PPRE1[2:0] bits according to RCC_HCLK value */
00643   tmpreg |= RCC_HCLK;
00644   /* Store the new value */
00645   RCC->CFGR = tmpreg;
00646 }
00647 
00648 /**
00649   * @brief  Configures the High Speed APB clock (PCLK2).
00650   * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
00651   *   the AHB clock (HCLK).
00652   *   This parameter can be one of the following values:
00653   *     @arg RCC_HCLK_Div1: APB2 clock = HCLK
00654   *     @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
00655   *     @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
00656   *     @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
00657   *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
00658   * @retval None
00659   */
00660 void RCC_PCLK2Config(uint32_t RCC_HCLK)
00661 {
00662   uint32_t tmpreg = 0;
00663   /* Check the parameters */
00664   assert_param(IS_RCC_PCLK(RCC_HCLK));
00665   tmpreg = RCC->CFGR;
00666   /* Clear PPRE2[2:0] bits */
00667   tmpreg &= CFGR_PPRE2_Reset_Mask;
00668   /* Set PPRE2[2:0] bits according to RCC_HCLK value */
00669   tmpreg |= RCC_HCLK << 3;
00670   /* Store the new value */
00671   RCC->CFGR = tmpreg;
00672 }
00673 
00674 /**
00675   * @brief  Enables or disables the specified RCC interrupts.
00676   * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
00677   * 
00678   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
00679   *   of the following values        
00680   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
00681   *     @arg RCC_IT_LSERDY: LSE ready interrupt
00682   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
00683   *     @arg RCC_IT_HSERDY: HSE ready interrupt
00684   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
00685   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
00686   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
00687   * 
00688   *   For @b other_STM32_devices, this parameter can be any combination of the 
00689   *   following values        
00690   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
00691   *     @arg RCC_IT_LSERDY: LSE ready interrupt
00692   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
00693   *     @arg RCC_IT_HSERDY: HSE ready interrupt
00694   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
00695   *       
00696   * @param  NewState: new state of the specified RCC interrupts.
00697   *   This parameter can be: ENABLE or DISABLE.
00698   * @retval None
00699   */
00700 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
00701 {
00702   /* Check the parameters */
00703   assert_param(IS_RCC_IT(RCC_IT));
00704   assert_param(IS_FUNCTIONAL_STATE(NewState));
00705   if (NewState != DISABLE)
00706   {
00707     /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
00708     *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
00709   }
00710   else
00711   {
00712     /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
00713     *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00714   }
00715 }
00716 
00717 #ifndef STM32F10X_CL
00718 /**
00719   * @brief  Configures the USB clock (USBCLK).
00720   * @param  RCC_USBCLKSource: specifies the USB clock source. This clock is 
00721   *   derived from the PLL output.
00722   *   This parameter can be one of the following values:
00723   *     @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB 
00724   *                                     clock source
00725   *     @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
00726   * @retval None
00727   */
00728 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
00729 {
00730   /* Check the parameters */
00731   assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
00732 
00733   *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00734 }
00735 #else
00736 /**
00737   * @brief  Configures the USB OTG FS clock (OTGFSCLK).
00738   *   This function applies only to STM32 Connectivity line devices.
00739   * @param  RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
00740   *   This clock is derived from the PLL output.
00741   *   This parameter can be one of the following values:
00742   *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
00743   *     @arg  RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
00744   * @retval None
00745   */
00746 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
00747 {
00748   /* Check the parameters */
00749   assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
00750 
00751   *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
00752 }
00753 #endif /* STM32F10X_CL */ 
00754 
00755 /**
00756   * @brief  Configures the ADC clock (ADCCLK).
00757   * @param  RCC_PCLK2: defines the ADC clock divider. This clock is derived from 
00758   *   the APB2 clock (PCLK2).
00759   *   This parameter can be one of the following values:
00760   *     @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
00761   *     @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
00762   *     @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
00763   *     @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
00764   * @retval None
00765   */
00766 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
00767 {
00768   uint32_t tmpreg = 0;
00769   /* Check the parameters */
00770   assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
00771   tmpreg = RCC->CFGR;
00772   /* Clear ADCPRE[1:0] bits */
00773   tmpreg &= CFGR_ADCPRE_Reset_Mask;
00774   /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
00775   tmpreg |= RCC_PCLK2;
00776   /* Store the new value */
00777   RCC->CFGR = tmpreg;
00778 }
00779 
00780 #ifdef STM32F10X_CL
00781 /**
00782   * @brief  Configures the I2S2 clock source(I2S2CLK).
00783   * @note
00784   *   - This function must be called before enabling I2S2 APB clock.
00785   *   - This function applies only to STM32 Connectivity line devices.
00786   * @param  RCC_I2S2CLKSource: specifies the I2S2 clock source.
00787   *   This parameter can be one of the following values:
00788   *     @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
00789   *     @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
00790   * @retval None
00791   */
00792 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
00793 {
00794   /* Check the parameters */
00795   assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
00796 
00797   *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
00798 }
00799 
00800 /**
00801   * @brief  Configures the I2S3 clock source(I2S2CLK).
00802   * @note
00803   *   - This function must be called before enabling I2S3 APB clock.
00804   *   - This function applies only to STM32 Connectivity line devices.
00805   * @param  RCC_I2S3CLKSource: specifies the I2S3 clock source.
00806   *   This parameter can be one of the following values:
00807   *     @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
00808   *     @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
00809   * @retval None
00810   */
00811 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
00812 {
00813   /* Check the parameters */
00814   assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
00815 
00816   *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
00817 }
00818 #endif /* STM32F10X_CL */
00819 
00820 /**
00821   * @brief  Configures the External Low Speed oscillator (LSE).
00822   * @param  RCC_LSE: specifies the new state of the LSE.
00823   *   This parameter can be one of the following values:
00824   *     @arg RCC_LSE_OFF: LSE oscillator OFF
00825   *     @arg RCC_LSE_ON: LSE oscillator ON
00826   *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
00827   * @retval None
00828   */
00829 void RCC_LSEConfig(uint8_t RCC_LSE)
00830 {
00831   /* Check the parameters */
00832   assert_param(IS_RCC_LSE(RCC_LSE));
00833   /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
00834   /* Reset LSEON bit */
00835   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
00836   /* Reset LSEBYP bit */
00837   *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
00838   /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
00839   switch(RCC_LSE)
00840   {
00841     case RCC_LSE_ON:
00842       /* Set LSEON bit */
00843       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
00844       break;
00845       
00846     case RCC_LSE_Bypass:
00847       /* Set LSEBYP and LSEON bits */
00848       *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00849       break;            
00850       
00851     default:
00852       break;      
00853   }
00854 }
00855 
00856 /**
00857   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00858   * @note   LSI can not be disabled if the IWDG is running.
00859   * @param  NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
00860   * @retval None
00861   */
00862 void RCC_LSICmd(FunctionalState NewState)
00863 {
00864   /* Check the parameters */
00865   assert_param(IS_FUNCTIONAL_STATE(NewState));
00866   *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
00867 }
00868 
00869 /**
00870   * @brief  Configures the RTC clock (RTCCLK).
00871   * @note   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
00872   * @param  RCC_RTCCLKSource: specifies the RTC clock source.
00873   *   This parameter can be one of the following values:
00874   *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
00875   *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
00876   *     @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
00877   * @retval None
00878   */
00879 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
00880 {
00881   /* Check the parameters */
00882   assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
00883   /* Select the RTC clock source */
00884   RCC->BDCR |= RCC_RTCCLKSource;
00885 }
00886 
00887 /**
00888   * @brief  Enables or disables the RTC clock.
00889   * @note   This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
00890   * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
00891   * @retval None
00892   */
00893 void RCC_RTCCLKCmd(FunctionalState NewState)
00894 {
00895   /* Check the parameters */
00896   assert_param(IS_FUNCTIONAL_STATE(NewState));
00897   *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
00898 }
00899 
00900 /**
00901   * @brief  Returns the frequencies of different on chip clocks.
00902   * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
00903   *         the clocks frequencies.
00904   * @note   The result of this function could be not correct when using 
00905   *         fractional value for HSE crystal.  
00906   * @retval None
00907   */
00908 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
00909 {
00910   uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
00911 
00912 #ifdef  STM32F10X_CL
00913   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
00914 #endif /* STM32F10X_CL */
00915 
00916 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00917   uint32_t prediv1factor = 0;
00918 #endif
00919     
00920   /* Get SYSCLK source -------------------------------------------------------*/
00921   tmp = RCC->CFGR & CFGR_SWS_Mask;
00922   
00923   switch (tmp)
00924   {
00925     case 0x00:  /* HSI used as system clock */
00926       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00927       break;
00928     case 0x04:  /* HSE used as system clock */
00929       RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
00930       break;
00931     case 0x08:  /* PLL used as system clock */
00932 
00933       /* Get PLL clock source and multiplication factor ----------------------*/
00934       pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00935       pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
00936       
00937 #ifndef STM32F10X_CL      
00938       pllmull = ( pllmull >> 18) + 2;
00939       
00940       if (pllsource == 0x00)
00941       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
00942         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
00943       }
00944       else
00945       {
00946  #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
00947        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
00948        /* HSE oscillator clock selected as PREDIV1 clock entry */
00949        RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
00950  #else
00951         /* HSE selected as PLL clock entry */
00952         if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00953         {/* HSE oscillator clock divided by 2 */
00954           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
00955         }
00956         else
00957         {
00958           RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
00959         }
00960  #endif
00961       }
00962 #else
00963       pllmull = pllmull >> 18;
00964       
00965       if (pllmull != 0x0D)
00966       {
00967          pllmull += 2;
00968       }
00969       else
00970       { /* PLL multiplication factor = PLL input clock * 6.5 */
00971         pllmull = 13 / 2; 
00972       }
00973             
00974       if (pllsource == 0x00)
00975       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
00976         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
00977       }
00978       else
00979       {/* PREDIV1 selected as PLL clock entry */
00980         
00981         /* Get PREDIV1 clock source and division factor */
00982         prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
00983         prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
00984         
00985         if (prediv1source == 0)
00986         { /* HSE oscillator clock selected as PREDIV1 clock entry */
00987           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
00988         }
00989         else
00990         {/* PLL2 clock selected as PREDIV1 clock entry */
00991           
00992           /* Get PREDIV2 division factor and PLL2 multiplication factor */
00993           prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
00994           pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
00995           RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
00996         }
00997       }
00998 #endif /* STM32F10X_CL */ 
00999       break;
01000 
01001     default:
01002       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
01003       break;
01004   }
01005 
01006   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
01007   /* Get HCLK prescaler */
01008   tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
01009   tmp = tmp >> 4;
01010   presc = APBAHBPrescTable[tmp];
01011   /* HCLK clock frequency */
01012   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
01013   /* Get PCLK1 prescaler */
01014   tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
01015   tmp = tmp >> 8;
01016   presc = APBAHBPrescTable[tmp];
01017   /* PCLK1 clock frequency */
01018   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01019   /* Get PCLK2 prescaler */
01020   tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
01021   tmp = tmp >> 11;
01022   presc = APBAHBPrescTable[tmp];
01023   /* PCLK2 clock frequency */
01024   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
01025   /* Get ADCCLK prescaler */
01026   tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
01027   tmp = tmp >> 14;
01028   presc = ADCPrescTable[tmp];
01029   /* ADCCLK clock frequency */
01030   RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
01031 }
01032 
01033 /**
01034   * @brief  Enables or disables the AHB peripheral clock.
01035   * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
01036   *   
01037   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
01038   *   of the following values:        
01039   *     @arg RCC_AHBPeriph_DMA1
01040   *     @arg RCC_AHBPeriph_DMA2
01041   *     @arg RCC_AHBPeriph_SRAM
01042   *     @arg RCC_AHBPeriph_FLITF
01043   *     @arg RCC_AHBPeriph_CRC
01044   *     @arg RCC_AHBPeriph_OTG_FS    
01045   *     @arg RCC_AHBPeriph_ETH_MAC   
01046   *     @arg RCC_AHBPeriph_ETH_MAC_Tx
01047   *     @arg RCC_AHBPeriph_ETH_MAC_Rx
01048   * 
01049   *   For @b other_STM32_devices, this parameter can be any combination of the 
01050   *   following values:        
01051   *     @arg RCC_AHBPeriph_DMA1
01052   *     @arg RCC_AHBPeriph_DMA2
01053   *     @arg RCC_AHBPeriph_SRAM
01054   *     @arg RCC_AHBPeriph_FLITF
01055   *     @arg RCC_AHBPeriph_CRC
01056   *     @arg RCC_AHBPeriph_FSMC
01057   *     @arg RCC_AHBPeriph_SDIO
01058   *   
01059   * @note SRAM and FLITF clock can be disabled only during sleep mode.
01060   * @param  NewState: new state of the specified peripheral clock.
01061   *   This parameter can be: ENABLE or DISABLE.
01062   * @retval None
01063   */
01064 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01065 {
01066   /* Check the parameters */
01067   assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
01068   assert_param(IS_FUNCTIONAL_STATE(NewState));
01069 
01070   if (NewState != DISABLE)
01071   {
01072     RCC->AHBENR |= RCC_AHBPeriph;
01073   }
01074   else
01075   {
01076     RCC->AHBENR &= ~RCC_AHBPeriph;
01077   }
01078 }
01079 
01080 /**
01081   * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
01082   * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
01083   *   This parameter can be any combination of the following values:
01084   *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
01085   *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
01086   *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
01087   *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
01088   *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
01089   *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
01090   *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11     
01091   * @param  NewState: new state of the specified peripheral clock.
01092   *   This parameter can be: ENABLE or DISABLE.
01093   * @retval None
01094   */
01095 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01096 {
01097   /* Check the parameters */
01098   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01099   assert_param(IS_FUNCTIONAL_STATE(NewState));
01100   if (NewState != DISABLE)
01101   {
01102     RCC->APB2ENR |= RCC_APB2Periph;
01103   }
01104   else
01105   {
01106     RCC->APB2ENR &= ~RCC_APB2Periph;
01107   }
01108 }
01109 
01110 /**
01111   * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
01112   * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
01113   *   This parameter can be any combination of the following values:
01114   *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
01115   *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
01116   *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
01117   *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
01118   *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
01119   *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
01120   *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
01121   *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
01122   * @param  NewState: new state of the specified peripheral clock.
01123   *   This parameter can be: ENABLE or DISABLE.
01124   * @retval None
01125   */
01126 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01127 {
01128   /* Check the parameters */
01129   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01130   assert_param(IS_FUNCTIONAL_STATE(NewState));
01131   if (NewState != DISABLE)
01132   {
01133     RCC->APB1ENR |= RCC_APB1Periph;
01134   }
01135   else
01136   {
01137     RCC->APB1ENR &= ~RCC_APB1Periph;
01138   }
01139 }
01140 
01141 #ifdef STM32F10X_CL
01142 /**
01143   * @brief  Forces or releases AHB peripheral reset.
01144   * @note   This function applies only to STM32 Connectivity line devices.
01145   * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
01146   *   This parameter can be any combination of the following values:
01147   *     @arg RCC_AHBPeriph_OTG_FS 
01148   *     @arg RCC_AHBPeriph_ETH_MAC
01149   * @param  NewState: new state of the specified peripheral reset.
01150   *   This parameter can be: ENABLE or DISABLE.
01151   * @retval None
01152   */
01153 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
01154 {
01155   /* Check the parameters */
01156   assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
01157   assert_param(IS_FUNCTIONAL_STATE(NewState));
01158 
01159   if (NewState != DISABLE)
01160   {
01161     RCC->AHBRSTR |= RCC_AHBPeriph;
01162   }
01163   else
01164   {
01165     RCC->AHBRSTR &= ~RCC_AHBPeriph;
01166   }
01167 }
01168 #endif /* STM32F10X_CL */ 
01169 
01170 /**
01171   * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
01172   * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
01173   *   This parameter can be any combination of the following values:
01174   *     @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
01175   *          RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
01176   *          RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
01177   *          RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
01178   *          RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
01179   *          RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
01180   *          RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11  
01181   * @param  NewState: new state of the specified peripheral reset.
01182   *   This parameter can be: ENABLE or DISABLE.
01183   * @retval None
01184   */
01185 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
01186 {
01187   /* Check the parameters */
01188   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
01189   assert_param(IS_FUNCTIONAL_STATE(NewState));
01190   if (NewState != DISABLE)
01191   {
01192     RCC->APB2RSTR |= RCC_APB2Periph;
01193   }
01194   else
01195   {
01196     RCC->APB2RSTR &= ~RCC_APB2Periph;
01197   }
01198 }
01199 
01200 /**
01201   * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
01202   * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
01203   *   This parameter can be any combination of the following values:
01204   *     @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
01205   *          RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
01206   *          RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
01207   *          RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
01208   *          RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
01209   *          RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
01210   *          RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
01211   *          RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14  
01212   * @param  NewState: new state of the specified peripheral clock.
01213   *   This parameter can be: ENABLE or DISABLE.
01214   * @retval None
01215   */
01216 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
01217 {
01218   /* Check the parameters */
01219   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
01220   assert_param(IS_FUNCTIONAL_STATE(NewState));
01221   if (NewState != DISABLE)
01222   {
01223     RCC->APB1RSTR |= RCC_APB1Periph;
01224   }
01225   else
01226   {
01227     RCC->APB1RSTR &= ~RCC_APB1Periph;
01228   }
01229 }
01230 
01231 /**
01232   * @brief  Forces or releases the Backup domain reset.
01233   * @param  NewState: new state of the Backup domain reset.
01234   *   This parameter can be: ENABLE or DISABLE.
01235   * @retval None
01236   */
01237 void RCC_BackupResetCmd(FunctionalState NewState)
01238 {
01239   /* Check the parameters */
01240   assert_param(IS_FUNCTIONAL_STATE(NewState));
01241   *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
01242 }
01243 
01244 /**
01245   * @brief  Enables or disables the Clock Security System.
01246   * @param  NewState: new state of the Clock Security System..
01247   *   This parameter can be: ENABLE or DISABLE.
01248   * @retval None
01249   */
01250 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
01251 {
01252   /* Check the parameters */
01253   assert_param(IS_FUNCTIONAL_STATE(NewState));
01254   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
01255 }
01256 
01257 /**
01258   * @brief  Selects the clock source to output on MCO pin.
01259   * @param  RCC_MCO: specifies the clock source to output.
01260   *   
01261   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01262   *   following values:       
01263   *     @arg RCC_MCO_NoClock: No clock selected
01264   *     @arg RCC_MCO_SYSCLK: System clock selected
01265   *     @arg RCC_MCO_HSI: HSI oscillator clock selected
01266   *     @arg RCC_MCO_HSE: HSE oscillator clock selected
01267   *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
01268   *     @arg RCC_MCO_PLL2CLK: PLL2 clock selected                     
01269   *     @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected   
01270   *     @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected  
01271   *     @arg RCC_MCO_PLL3CLK: PLL3 clock selected 
01272   * 
01273   *   For  @b other_STM32_devices, this parameter can be one of the following values:        
01274   *     @arg RCC_MCO_NoClock: No clock selected
01275   *     @arg RCC_MCO_SYSCLK: System clock selected
01276   *     @arg RCC_MCO_HSI: HSI oscillator clock selected
01277   *     @arg RCC_MCO_HSE: HSE oscillator clock selected
01278   *     @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
01279   *   
01280   * @retval None
01281   */
01282 void RCC_MCOConfig(uint8_t RCC_MCO)
01283 {
01284   /* Check the parameters */
01285   assert_param(IS_RCC_MCO(RCC_MCO));
01286 
01287   /* Perform Byte access to MCO bits to select the MCO source */
01288   *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
01289 }
01290 
01291 /**
01292   * @brief  Checks whether the specified RCC flag is set or not.
01293   * @param  RCC_FLAG: specifies the flag to check.
01294   *   
01295   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01296   *   following values:
01297   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01298   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01299   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01300   *     @arg RCC_FLAG_PLL2RDY: PLL2 clock ready      
01301   *     @arg RCC_FLAG_PLL3RDY: PLL3 clock ready                           
01302   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01303   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01304   *     @arg RCC_FLAG_PINRST: Pin reset
01305   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01306   *     @arg RCC_FLAG_SFTRST: Software reset
01307   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01308   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01309   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01310   * 
01311   *   For @b other_STM32_devices, this parameter can be one of the following values:        
01312   *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
01313   *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
01314   *     @arg RCC_FLAG_PLLRDY: PLL clock ready
01315   *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
01316   *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
01317   *     @arg RCC_FLAG_PINRST: Pin reset
01318   *     @arg RCC_FLAG_PORRST: POR/PDR reset
01319   *     @arg RCC_FLAG_SFTRST: Software reset
01320   *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
01321   *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset
01322   *     @arg RCC_FLAG_LPWRRST: Low Power reset
01323   *   
01324   * @retval The new state of RCC_FLAG (SET or RESET).
01325   */
01326 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
01327 {
01328   uint32_t tmp = 0;
01329   uint32_t statusreg = 0;
01330   FlagStatus bitstatus = RESET;
01331   /* Check the parameters */
01332   assert_param(IS_RCC_FLAG(RCC_FLAG));
01333 
01334   /* Get the RCC register index */
01335   tmp = RCC_FLAG >> 5;
01336   if (tmp == 1)               /* The flag to check is in CR register */
01337   {
01338     statusreg = RCC->CR;
01339   }
01340   else if (tmp == 2)          /* The flag to check is in BDCR register */
01341   {
01342     statusreg = RCC->BDCR;
01343   }
01344   else                       /* The flag to check is in CSR register */
01345   {
01346     statusreg = RCC->CSR;
01347   }
01348 
01349   /* Get the flag position */
01350   tmp = RCC_FLAG & FLAG_Mask;
01351   if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
01352   {
01353     bitstatus = SET;
01354   }
01355   else
01356   {
01357     bitstatus = RESET;
01358   }
01359 
01360   /* Return the flag status */
01361   return bitstatus;
01362 }
01363 
01364 /**
01365   * @brief  Clears the RCC reset flags.
01366   * @note   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
01367   *   RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
01368   * @param  None
01369   * @retval None
01370   */
01371 void RCC_ClearFlag(void)
01372 {
01373   /* Set RMVF bit to clear the reset flags */
01374   RCC->CSR |= CSR_RMVF_Set;
01375 }
01376 
01377 /**
01378   * @brief  Checks whether the specified RCC interrupt has occurred or not.
01379   * @param  RCC_IT: specifies the RCC interrupt source to check.
01380   *   
01381   *   For @b STM32_Connectivity_line_devices, this parameter can be one of the
01382   *   following values:
01383   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01384   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01385   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01386   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01387   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01388   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
01389   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
01390   *     @arg RCC_IT_CSS: Clock Security System interrupt
01391   * 
01392   *   For @b other_STM32_devices, this parameter can be one of the following values:        
01393   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01394   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01395   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01396   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01397   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01398   *     @arg RCC_IT_CSS: Clock Security System interrupt
01399   *   
01400   * @retval The new state of RCC_IT (SET or RESET).
01401   */
01402 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
01403 {
01404   ITStatus bitstatus = RESET;
01405   /* Check the parameters */
01406   assert_param(IS_RCC_GET_IT(RCC_IT));
01407 
01408   /* Check the status of the specified RCC interrupt */
01409   if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
01410   {
01411     bitstatus = SET;
01412   }
01413   else
01414   {
01415     bitstatus = RESET;
01416   }
01417 
01418   /* Return the RCC_IT status */
01419   return  bitstatus;
01420 }
01421 
01422 /**
01423   * @brief  Clears the RCC's interrupt pending bits.
01424   * @param  RCC_IT: specifies the interrupt pending bit to clear.
01425   *   
01426   *   For @b STM32_Connectivity_line_devices, this parameter can be any combination
01427   *   of the following values:
01428   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01429   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01430   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01431   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01432   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01433   *     @arg RCC_IT_PLL2RDY: PLL2 ready interrupt 
01434   *     @arg RCC_IT_PLL3RDY: PLL3 ready interrupt                      
01435   *     @arg RCC_IT_CSS: Clock Security System interrupt
01436   * 
01437   *   For @b other_STM32_devices, this parameter can be any combination of the
01438   *   following values:        
01439   *     @arg RCC_IT_LSIRDY: LSI ready interrupt
01440   *     @arg RCC_IT_LSERDY: LSE ready interrupt
01441   *     @arg RCC_IT_HSIRDY: HSI ready interrupt
01442   *     @arg RCC_IT_HSERDY: HSE ready interrupt
01443   *     @arg RCC_IT_PLLRDY: PLL ready interrupt
01444   *   
01445   *     @arg RCC_IT_CSS: Clock Security System interrupt
01446   * @retval None
01447   */
01448 void RCC_ClearITPendingBit(uint8_t RCC_IT)
01449 {
01450   /* Check the parameters */
01451   assert_param(IS_RCC_CLEAR_IT(RCC_IT));
01452 
01453   /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
01454      pending bits */
01455   *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
01456 }
01457 
01458 /**
01459   * @}
01460   */
01461 
01462 /**
01463   * @}
01464   */
01465 
01466 /**
01467   * @}
01468   */
01469 
01470 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/