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cyclone_tcp/drivers/lpc18xx_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file lpc18xx_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief LPC1800 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "lpc18xx.h"
Sergunb 0:8918a71cdbe9 34 #include "core/net.h"
Sergunb 0:8918a71cdbe9 35 #include "drivers/lpc18xx_eth.h"
Sergunb 0:8918a71cdbe9 36 #include "debug.h"
Sergunb 0:8918a71cdbe9 37
Sergunb 0:8918a71cdbe9 38 //Underlying network interface
Sergunb 0:8918a71cdbe9 39 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 40
Sergunb 0:8918a71cdbe9 41 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 42 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //Transmit buffer
Sergunb 0:8918a71cdbe9 45 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 46 static uint8_t txBuffer[LPC18XX_ETH_TX_BUFFER_COUNT][LPC18XX_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 47 //Receive buffer
Sergunb 0:8918a71cdbe9 48 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 49 static uint8_t rxBuffer[LPC18XX_ETH_RX_BUFFER_COUNT][LPC18XX_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 50 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 51 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 52 static Lpc18xxTxDmaDesc txDmaDesc[LPC18XX_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 53 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 54 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 55 static Lpc18xxRxDmaDesc rxDmaDesc[LPC18XX_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 56
Sergunb 0:8918a71cdbe9 57 //ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 58 #else
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //Transmit buffer
Sergunb 0:8918a71cdbe9 61 static uint8_t txBuffer[LPC18XX_ETH_TX_BUFFER_COUNT][LPC18XX_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 62 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 63 //Receive buffer
Sergunb 0:8918a71cdbe9 64 static uint8_t rxBuffer[LPC18XX_ETH_RX_BUFFER_COUNT][LPC18XX_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 65 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 66 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 67 static Lpc18xxTxDmaDesc txDmaDesc[LPC18XX_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 68 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 69 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 70 static Lpc18xxRxDmaDesc rxDmaDesc[LPC18XX_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 71 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 72
Sergunb 0:8918a71cdbe9 73 #endif
Sergunb 0:8918a71cdbe9 74
Sergunb 0:8918a71cdbe9 75 //Pointer to the current TX DMA descriptor
Sergunb 0:8918a71cdbe9 76 static Lpc18xxTxDmaDesc *txCurDmaDesc;
Sergunb 0:8918a71cdbe9 77 //Pointer to the current RX DMA descriptor
Sergunb 0:8918a71cdbe9 78 static Lpc18xxRxDmaDesc *rxCurDmaDesc;
Sergunb 0:8918a71cdbe9 79
Sergunb 0:8918a71cdbe9 80
Sergunb 0:8918a71cdbe9 81 /**
Sergunb 0:8918a71cdbe9 82 * @brief LPC18xx Ethernet MAC driver
Sergunb 0:8918a71cdbe9 83 **/
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 const NicDriver lpc18xxEthDriver =
Sergunb 0:8918a71cdbe9 86 {
Sergunb 0:8918a71cdbe9 87 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 88 ETH_MTU,
Sergunb 0:8918a71cdbe9 89 lpc18xxEthInit,
Sergunb 0:8918a71cdbe9 90 lpc18xxEthTick,
Sergunb 0:8918a71cdbe9 91 lpc18xxEthEnableIrq,
Sergunb 0:8918a71cdbe9 92 lpc18xxEthDisableIrq,
Sergunb 0:8918a71cdbe9 93 lpc18xxEthEventHandler,
Sergunb 0:8918a71cdbe9 94 lpc18xxEthSendPacket,
Sergunb 0:8918a71cdbe9 95 lpc18xxEthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 96 lpc18xxEthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 97 lpc18xxEthWritePhyReg,
Sergunb 0:8918a71cdbe9 98 lpc18xxEthReadPhyReg,
Sergunb 0:8918a71cdbe9 99 TRUE,
Sergunb 0:8918a71cdbe9 100 TRUE,
Sergunb 0:8918a71cdbe9 101 TRUE,
Sergunb 0:8918a71cdbe9 102 FALSE
Sergunb 0:8918a71cdbe9 103 };
Sergunb 0:8918a71cdbe9 104
Sergunb 0:8918a71cdbe9 105
Sergunb 0:8918a71cdbe9 106 /**
Sergunb 0:8918a71cdbe9 107 * @brief LPC18xx Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 108 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 109 * @return Error code
Sergunb 0:8918a71cdbe9 110 **/
Sergunb 0:8918a71cdbe9 111
Sergunb 0:8918a71cdbe9 112 error_t lpc18xxEthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 113 {
Sergunb 0:8918a71cdbe9 114 error_t error;
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 //Debug message
Sergunb 0:8918a71cdbe9 117 TRACE_INFO("Initializing LPC18xx Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 118
Sergunb 0:8918a71cdbe9 119 //Save underlying network interface
Sergunb 0:8918a71cdbe9 120 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 //Enable Ethernet peripheral clock
Sergunb 0:8918a71cdbe9 123 LPC_CCU1->CLK_M3_ETHERNET_CFG |= CCU1_CLK_M3_ETHERNET_CFG_RUN_Msk;
Sergunb 0:8918a71cdbe9 124 while(!(LPC_CCU1->CLK_M3_ETHERNET_STAT & CCU1_CLK_M3_ETHERNET_STAT_RUN_Msk));
Sergunb 0:8918a71cdbe9 125
Sergunb 0:8918a71cdbe9 126 //Reset DMA
Sergunb 0:8918a71cdbe9 127 LPC_RGU->RESET_EXT_STAT19 |= RGU_RESET_EXT_STAT19_MASTER_RESET_Msk;
Sergunb 0:8918a71cdbe9 128 LPC_RGU->RESET_EXT_STAT19 &= ~RGU_RESET_EXT_STAT19_MASTER_RESET_Msk;
Sergunb 0:8918a71cdbe9 129
Sergunb 0:8918a71cdbe9 130 //Reset Ethernet peripheral
Sergunb 0:8918a71cdbe9 131 LPC_RGU->RESET_EXT_STAT22 |= RGU_RESET_EXT_STAT22_MASTER_RESET_Msk;
Sergunb 0:8918a71cdbe9 132 LPC_RGU->RESET_EXT_STAT22 &= ~RGU_RESET_EXT_STAT22_MASTER_RESET_Msk;
Sergunb 0:8918a71cdbe9 133
Sergunb 0:8918a71cdbe9 134 //GPIO configuration
Sergunb 0:8918a71cdbe9 135 lpc18xxEthInitGpio(interface);
Sergunb 0:8918a71cdbe9 136
Sergunb 0:8918a71cdbe9 137 //Reset Ethernet peripheral
Sergunb 0:8918a71cdbe9 138 LPC_RGU->RESET_CTRL0 = RGU_RESET_CTRL0_ETHERNET_RST_Msk;
Sergunb 0:8918a71cdbe9 139 while(!(LPC_RGU->RESET_ACTIVE_STATUS0 & RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk));
Sergunb 0:8918a71cdbe9 140
Sergunb 0:8918a71cdbe9 141 //Perform a software reset
Sergunb 0:8918a71cdbe9 142 LPC_ETHERNET->DMA_BUS_MODE |= ETHERNET_DMA_BUS_MODE_SWR_Msk;
Sergunb 0:8918a71cdbe9 143 //Wait for the reset to complete
Sergunb 0:8918a71cdbe9 144 while(LPC_ETHERNET->DMA_BUS_MODE & ETHERNET_DMA_BUS_MODE_SWR_Msk);
Sergunb 0:8918a71cdbe9 145
Sergunb 0:8918a71cdbe9 146 //Adjust MDC clock range
Sergunb 0:8918a71cdbe9 147 LPC_ETHERNET->MAC_MII_ADDR = ETHERNET_MAC_MII_ADDR_CR_DIV62;
Sergunb 0:8918a71cdbe9 148
Sergunb 0:8918a71cdbe9 149 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 150 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 151 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 152 if(error)
Sergunb 0:8918a71cdbe9 153 return error;
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 //Use default MAC configuration
Sergunb 0:8918a71cdbe9 156 LPC_ETHERNET->MAC_CONFIG = ETHERNET_MAC_CONFIG_DO_Msk;
Sergunb 0:8918a71cdbe9 157
Sergunb 0:8918a71cdbe9 158 //Set the MAC address
Sergunb 0:8918a71cdbe9 159 LPC_ETHERNET->MAC_ADDR0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 160 LPC_ETHERNET->MAC_ADDR0_HIGH = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 161
Sergunb 0:8918a71cdbe9 162 //Initialize hash table
Sergunb 0:8918a71cdbe9 163 LPC_ETHERNET->MAC_HASHTABLE_LOW = 0;
Sergunb 0:8918a71cdbe9 164 LPC_ETHERNET->MAC_HASHTABLE_HIGH = 0;
Sergunb 0:8918a71cdbe9 165
Sergunb 0:8918a71cdbe9 166 //Configure the receive filter
Sergunb 0:8918a71cdbe9 167 LPC_ETHERNET->MAC_FRAME_FILTER = ETHERNET_MAC_FRAME_FILTER_HPF_Msk |
Sergunb 0:8918a71cdbe9 168 ETHERNET_MAC_FRAME_FILTER_HMC_Msk;
Sergunb 0:8918a71cdbe9 169
Sergunb 0:8918a71cdbe9 170 //Disable flow control
Sergunb 0:8918a71cdbe9 171 LPC_ETHERNET->MAC_FLOW_CTRL = 0;
Sergunb 0:8918a71cdbe9 172 //Set the threshold level of the transmit and receive FIFOs
Sergunb 0:8918a71cdbe9 173 LPC_ETHERNET->DMA_OP_MODE = ETHERNET_DMA_OP_MODE_TTC_64 | ETHERNET_DMA_OP_MODE_RTC_32;
Sergunb 0:8918a71cdbe9 174
Sergunb 0:8918a71cdbe9 175 //Configure DMA bus mode
Sergunb 0:8918a71cdbe9 176 LPC_ETHERNET->DMA_BUS_MODE = ETHERNET_DMA_BUS_MODE_AAL_Msk | ETHERNET_DMA_BUS_MODE_USP_Msk |
Sergunb 0:8918a71cdbe9 177 ETHERNET_DMA_BUS_MODE_RPBL_1 | ETHERNET_DMA_BUS_MODE_PR_1_1 |
Sergunb 0:8918a71cdbe9 178 ETHERNET_DMA_BUS_MODE_PBL_1 | ETHERNET_DMA_BUS_MODE_ATDS_Msk;
Sergunb 0:8918a71cdbe9 179
Sergunb 0:8918a71cdbe9 180 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 181 lpc18xxEthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 182
Sergunb 0:8918a71cdbe9 183 //Disable MAC interrupts
Sergunb 0:8918a71cdbe9 184 LPC_ETHERNET->MAC_INTR_MASK = ETHERNET_MAC_INTR_MASK_TSIM_Msk |
Sergunb 0:8918a71cdbe9 185 ETHERNET_MAC_INTR_MASK_PMTIM_Msk;
Sergunb 0:8918a71cdbe9 186
Sergunb 0:8918a71cdbe9 187 //Enable the desired DMA interrupts
Sergunb 0:8918a71cdbe9 188 LPC_ETHERNET->DMA_INT_EN = ETHERNET_DMA_INT_EN_NIE_Msk |
Sergunb 0:8918a71cdbe9 189 ETHERNET_DMA_INT_EN_RIE_Msk | ETHERNET_DMA_INT_EN_TIE_Msk;
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191 //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 192 NVIC_SetPriorityGrouping(LPC18XX_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 193
Sergunb 0:8918a71cdbe9 194 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 195 NVIC_SetPriority(ETHERNET_IRQn, NVIC_EncodePriority(LPC18XX_ETH_IRQ_PRIORITY_GROUPING,
Sergunb 0:8918a71cdbe9 196 LPC18XX_ETH_IRQ_GROUP_PRIORITY, LPC18XX_ETH_IRQ_SUB_PRIORITY));
Sergunb 0:8918a71cdbe9 197
Sergunb 0:8918a71cdbe9 198 //Enable MAC transmission and reception
Sergunb 0:8918a71cdbe9 199 LPC_ETHERNET->MAC_CONFIG |= ETHERNET_MAC_CONFIG_TE_Msk | ETHERNET_MAC_CONFIG_RE_Msk;
Sergunb 0:8918a71cdbe9 200 //Enable DMA transmission and reception
Sergunb 0:8918a71cdbe9 201 LPC_ETHERNET->DMA_OP_MODE |= ETHERNET_DMA_OP_MODE_ST_Msk | ETHERNET_DMA_OP_MODE_SR_Msk;
Sergunb 0:8918a71cdbe9 202
Sergunb 0:8918a71cdbe9 203 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 204 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 205
Sergunb 0:8918a71cdbe9 206 //Successful initialization
Sergunb 0:8918a71cdbe9 207 return NO_ERROR;
Sergunb 0:8918a71cdbe9 208 }
Sergunb 0:8918a71cdbe9 209
Sergunb 0:8918a71cdbe9 210
Sergunb 0:8918a71cdbe9 211 //LPC1830-Xplorer evaluation board?
Sergunb 0:8918a71cdbe9 212 #if defined(USE_LPC1830_XPLORER)
Sergunb 0:8918a71cdbe9 213
Sergunb 0:8918a71cdbe9 214 /**
Sergunb 0:8918a71cdbe9 215 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 216 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 217 **/
Sergunb 0:8918a71cdbe9 218
Sergunb 0:8918a71cdbe9 219 void lpc18xxEthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 220 {
Sergunb 0:8918a71cdbe9 221 //Enable GPIO peripheral clock
Sergunb 0:8918a71cdbe9 222 LPC_CCU1->CLK_M3_GPIO_CFG |= CCU1_CLK_M3_GPIO_CFG_RUN_Msk;
Sergunb 0:8918a71cdbe9 223 while(!(LPC_CCU1->CLK_M3_GPIO_STAT & CCU1_CLK_M3_GPIO_STAT_RUN_Msk));
Sergunb 0:8918a71cdbe9 224
Sergunb 0:8918a71cdbe9 225 //Select RMII operation mode
Sergunb 0:8918a71cdbe9 226 LPC_CREG->CREG6 &= ~CREG_CREG6_ETHMODE_Msk;
Sergunb 0:8918a71cdbe9 227 LPC_CREG->CREG6 |= CREG6_ETHMODE_RMII;
Sergunb 0:8918a71cdbe9 228
Sergunb 0:8918a71cdbe9 229 //Configure P0.0 (ENET_RXD1)
Sergunb 0:8918a71cdbe9 230 LPC_SCU->SFSP0_0 = SCU_SFSP0_0_EZI_Msk | SCU_SFSP0_0_EHS_Msk | (2 & SCU_SFSP0_0_MODE_Msk);
Sergunb 0:8918a71cdbe9 231 //Configure P0.1 (ENET_TX_EN)
Sergunb 0:8918a71cdbe9 232 LPC_SCU->SFSP0_1 = SCU_SFSP0_1_EHS_Msk | (6 & SCU_SFSP0_1_MODE_Msk);
Sergunb 0:8918a71cdbe9 233
Sergunb 0:8918a71cdbe9 234 //Configure P1.15 (ENET_RXD0)
Sergunb 0:8918a71cdbe9 235 LPC_SCU->SFSP1_15 = SCU_SFSP1_15_EZI_Msk | SCU_SFSP1_15_EHS_Msk | (3 & SCU_SFSP1_15_MODE_Msk);
Sergunb 0:8918a71cdbe9 236 //Configure P1.16 (ENET_RX_DV)
Sergunb 0:8918a71cdbe9 237 LPC_SCU->SFSP1_16 = SCU_SFSP1_16_EZI_Msk | SCU_SFSP1_16_EHS_Msk | (7 & SCU_SFSP1_16_MODE_Msk);
Sergunb 0:8918a71cdbe9 238 //Configure P1.17 (ENET_MDIO)
Sergunb 0:8918a71cdbe9 239 LPC_SCU->SFSP1_17 = SCU_SFSP1_17_EZI_Msk | (3 & SCU_SFSP1_17_MODE_Msk);
Sergunb 0:8918a71cdbe9 240 //Configure P1.18 (ENET_TXD0)
Sergunb 0:8918a71cdbe9 241 LPC_SCU->SFSP1_18 = SCU_SFSP1_18_EHS_Msk | (3 & SCU_SFSP1_18_MODE_Msk);
Sergunb 0:8918a71cdbe9 242 //Configure P1.19 (ENET_REF_CLK)
Sergunb 0:8918a71cdbe9 243 LPC_SCU->SFSP1_19 = SCU_SFSP1_19_EZI_Msk | SCU_SFSP1_19_EHS_Msk | (0 & SCU_SFSP1_19_MODE_Msk);
Sergunb 0:8918a71cdbe9 244 //Configure P1.20 (ENET_TXD1)
Sergunb 0:8918a71cdbe9 245 LPC_SCU->SFSP1_20 = SCU_SFSP1_20_EHS_Msk | (3 & SCU_SFSP1_20_MODE_Msk);
Sergunb 0:8918a71cdbe9 246
Sergunb 0:8918a71cdbe9 247 //Configure P2.0 (ENET_MDC)
Sergunb 0:8918a71cdbe9 248 LPC_SCU->SFSP2_0 = (7 & SCU_SFSP2_0_MODE_Msk);
Sergunb 0:8918a71cdbe9 249 }
Sergunb 0:8918a71cdbe9 250
Sergunb 0:8918a71cdbe9 251 #endif
Sergunb 0:8918a71cdbe9 252
Sergunb 0:8918a71cdbe9 253
Sergunb 0:8918a71cdbe9 254 /**
Sergunb 0:8918a71cdbe9 255 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 256 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 257 **/
Sergunb 0:8918a71cdbe9 258
Sergunb 0:8918a71cdbe9 259 void lpc18xxEthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 260 {
Sergunb 0:8918a71cdbe9 261 uint_t i;
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 264 for(i = 0; i < LPC18XX_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 265 {
Sergunb 0:8918a71cdbe9 266 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 267 txDmaDesc[i].tdes0 = ETH_TDES0_IC | ETH_TDES0_TCH;
Sergunb 0:8918a71cdbe9 268 //Initialize transmit buffer size
Sergunb 0:8918a71cdbe9 269 txDmaDesc[i].tdes1 = 0;
Sergunb 0:8918a71cdbe9 270 //Transmit buffer address
Sergunb 0:8918a71cdbe9 271 txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 272 //Next descriptor address
Sergunb 0:8918a71cdbe9 273 txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 274 //Reserved fields
Sergunb 0:8918a71cdbe9 275 txDmaDesc[i].tdes4 = 0;
Sergunb 0:8918a71cdbe9 276 txDmaDesc[i].tdes5 = 0;
Sergunb 0:8918a71cdbe9 277 //Transmit frame time stamp
Sergunb 0:8918a71cdbe9 278 txDmaDesc[i].tdes6 = 0;
Sergunb 0:8918a71cdbe9 279 txDmaDesc[i].tdes7 = 0;
Sergunb 0:8918a71cdbe9 280 }
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 283 txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 284 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 285 txCurDmaDesc = &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 286
Sergunb 0:8918a71cdbe9 287 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 288 for(i = 0; i < LPC18XX_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 289 {
Sergunb 0:8918a71cdbe9 290 //The descriptor is initially owned by the DMA
Sergunb 0:8918a71cdbe9 291 rxDmaDesc[i].rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 292 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 293 rxDmaDesc[i].rdes1 = ETH_RDES1_RCH | (LPC18XX_ETH_RX_BUFFER_SIZE & ETH_RDES1_RBS1);
Sergunb 0:8918a71cdbe9 294 //Receive buffer address
Sergunb 0:8918a71cdbe9 295 rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 296 //Next descriptor address
Sergunb 0:8918a71cdbe9 297 rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 298 //Extended status
Sergunb 0:8918a71cdbe9 299 rxDmaDesc[i].rdes4 = 0;
Sergunb 0:8918a71cdbe9 300 //Reserved field
Sergunb 0:8918a71cdbe9 301 rxDmaDesc[i].rdes5 = 0;
Sergunb 0:8918a71cdbe9 302 //Receive frame time stamp
Sergunb 0:8918a71cdbe9 303 rxDmaDesc[i].rdes6 = 0;
Sergunb 0:8918a71cdbe9 304 rxDmaDesc[i].rdes7 = 0;
Sergunb 0:8918a71cdbe9 305 }
Sergunb 0:8918a71cdbe9 306
Sergunb 0:8918a71cdbe9 307 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 308 rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 309 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 310 rxCurDmaDesc = &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 311
Sergunb 0:8918a71cdbe9 312 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 313 LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t) txDmaDesc;
Sergunb 0:8918a71cdbe9 314 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 315 LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t) rxDmaDesc;
Sergunb 0:8918a71cdbe9 316 }
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318
Sergunb 0:8918a71cdbe9 319 /**
Sergunb 0:8918a71cdbe9 320 * @brief LPC18xx Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 321 *
Sergunb 0:8918a71cdbe9 322 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 323 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 324 *
Sergunb 0:8918a71cdbe9 325 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 326 **/
Sergunb 0:8918a71cdbe9 327
Sergunb 0:8918a71cdbe9 328 void lpc18xxEthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 329 {
Sergunb 0:8918a71cdbe9 330 //Handle periodic operations
Sergunb 0:8918a71cdbe9 331 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 332 }
Sergunb 0:8918a71cdbe9 333
Sergunb 0:8918a71cdbe9 334
Sergunb 0:8918a71cdbe9 335 /**
Sergunb 0:8918a71cdbe9 336 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 337 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 338 **/
Sergunb 0:8918a71cdbe9 339
Sergunb 0:8918a71cdbe9 340 void lpc18xxEthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 341 {
Sergunb 0:8918a71cdbe9 342 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 343 NVIC_EnableIRQ(ETHERNET_IRQn);
Sergunb 0:8918a71cdbe9 344 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 345 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 346 }
Sergunb 0:8918a71cdbe9 347
Sergunb 0:8918a71cdbe9 348
Sergunb 0:8918a71cdbe9 349 /**
Sergunb 0:8918a71cdbe9 350 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 351 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 352 **/
Sergunb 0:8918a71cdbe9 353
Sergunb 0:8918a71cdbe9 354 void lpc18xxEthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 355 {
Sergunb 0:8918a71cdbe9 356 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 357 NVIC_DisableIRQ(ETHERNET_IRQn);
Sergunb 0:8918a71cdbe9 358 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 359 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 360 }
Sergunb 0:8918a71cdbe9 361
Sergunb 0:8918a71cdbe9 362
Sergunb 0:8918a71cdbe9 363 /**
Sergunb 0:8918a71cdbe9 364 * @brief LPC18xx Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 365 **/
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367 void ETHERNET_IRQHandler(void)
Sergunb 0:8918a71cdbe9 368 {
Sergunb 0:8918a71cdbe9 369 bool_t flag;
Sergunb 0:8918a71cdbe9 370 uint32_t status;
Sergunb 0:8918a71cdbe9 371
Sergunb 0:8918a71cdbe9 372 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 373 osEnterIsr();
Sergunb 0:8918a71cdbe9 374
Sergunb 0:8918a71cdbe9 375 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 376 flag = FALSE;
Sergunb 0:8918a71cdbe9 377
Sergunb 0:8918a71cdbe9 378 //Read DMA status register
Sergunb 0:8918a71cdbe9 379 status = LPC_ETHERNET->DMA_STAT;
Sergunb 0:8918a71cdbe9 380
Sergunb 0:8918a71cdbe9 381 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 382 if(status & ETHERNET_DMA_STAT_TI_Msk)
Sergunb 0:8918a71cdbe9 383 {
Sergunb 0:8918a71cdbe9 384 //Clear TI interrupt flag
Sergunb 0:8918a71cdbe9 385 LPC_ETHERNET->DMA_STAT = ETHERNET_DMA_STAT_TI_Msk;
Sergunb 0:8918a71cdbe9 386
Sergunb 0:8918a71cdbe9 387 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 388 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 389 {
Sergunb 0:8918a71cdbe9 390 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 391 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 392 }
Sergunb 0:8918a71cdbe9 393 }
Sergunb 0:8918a71cdbe9 394
Sergunb 0:8918a71cdbe9 395 //A packet has been received?
Sergunb 0:8918a71cdbe9 396 if(status & ETHERNET_DMA_STAT_RI_Msk)
Sergunb 0:8918a71cdbe9 397 {
Sergunb 0:8918a71cdbe9 398 //Disable RIE interrupt
Sergunb 0:8918a71cdbe9 399 LPC_ETHERNET->DMA_INT_EN &= ~ETHERNET_DMA_INT_EN_RIE_Msk;
Sergunb 0:8918a71cdbe9 400
Sergunb 0:8918a71cdbe9 401 //Set event flag
Sergunb 0:8918a71cdbe9 402 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 403 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 404 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 405 }
Sergunb 0:8918a71cdbe9 406
Sergunb 0:8918a71cdbe9 407 //Clear NIS interrupt flag
Sergunb 0:8918a71cdbe9 408 LPC_ETHERNET->DMA_STAT = ETHERNET_DMA_STAT_NIS_Msk;
Sergunb 0:8918a71cdbe9 409
Sergunb 0:8918a71cdbe9 410 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 411 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 412 }
Sergunb 0:8918a71cdbe9 413
Sergunb 0:8918a71cdbe9 414
Sergunb 0:8918a71cdbe9 415 /**
Sergunb 0:8918a71cdbe9 416 * @brief LPC18xx Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 417 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 418 **/
Sergunb 0:8918a71cdbe9 419
Sergunb 0:8918a71cdbe9 420 void lpc18xxEthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 421 {
Sergunb 0:8918a71cdbe9 422 error_t error;
Sergunb 0:8918a71cdbe9 423
Sergunb 0:8918a71cdbe9 424 //Packet received?
Sergunb 0:8918a71cdbe9 425 if(LPC_ETHERNET->DMA_STAT & ETHERNET_DMA_STAT_RI_Msk)
Sergunb 0:8918a71cdbe9 426 {
Sergunb 0:8918a71cdbe9 427 //Clear interrupt flag
Sergunb 0:8918a71cdbe9 428 LPC_ETHERNET->DMA_STAT = ETHERNET_DMA_STAT_RI_Msk;
Sergunb 0:8918a71cdbe9 429
Sergunb 0:8918a71cdbe9 430 //Process all pending packets
Sergunb 0:8918a71cdbe9 431 do
Sergunb 0:8918a71cdbe9 432 {
Sergunb 0:8918a71cdbe9 433 //Read incoming packet
Sergunb 0:8918a71cdbe9 434 error = lpc18xxEthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 435
Sergunb 0:8918a71cdbe9 436 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 437 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 438 }
Sergunb 0:8918a71cdbe9 439
Sergunb 0:8918a71cdbe9 440 //Re-enable DMA interrupts
Sergunb 0:8918a71cdbe9 441 LPC_ETHERNET->DMA_INT_EN |= ETHERNET_DMA_INT_EN_NIE_Msk |
Sergunb 0:8918a71cdbe9 442 ETHERNET_DMA_INT_EN_RIE_Msk | ETHERNET_DMA_INT_EN_TIE_Msk;
Sergunb 0:8918a71cdbe9 443 }
Sergunb 0:8918a71cdbe9 444
Sergunb 0:8918a71cdbe9 445
Sergunb 0:8918a71cdbe9 446 /**
Sergunb 0:8918a71cdbe9 447 * @brief Send a packet
Sergunb 0:8918a71cdbe9 448 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 449 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 450 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 451 * @return Error code
Sergunb 0:8918a71cdbe9 452 **/
Sergunb 0:8918a71cdbe9 453
Sergunb 0:8918a71cdbe9 454 error_t lpc18xxEthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 455 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 456 {
Sergunb 0:8918a71cdbe9 457 size_t length;
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 460 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 461
Sergunb 0:8918a71cdbe9 462 //Check the frame length
Sergunb 0:8918a71cdbe9 463 if(length > LPC18XX_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 464 {
Sergunb 0:8918a71cdbe9 465 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 466 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 467 //Report an error
Sergunb 0:8918a71cdbe9 468 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 469 }
Sergunb 0:8918a71cdbe9 470
Sergunb 0:8918a71cdbe9 471 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 472 if(txCurDmaDesc->tdes0 & ETH_TDES0_OWN)
Sergunb 0:8918a71cdbe9 473 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 474
Sergunb 0:8918a71cdbe9 475 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 476 netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
Sergunb 0:8918a71cdbe9 477
Sergunb 0:8918a71cdbe9 478 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 479 txCurDmaDesc->tdes1 = length & ETH_TDES1_TBS1;
Sergunb 0:8918a71cdbe9 480 //Set LS and FS flags as the data fits in a single buffer
Sergunb 0:8918a71cdbe9 481 txCurDmaDesc->tdes0 |= ETH_TDES0_LS | ETH_TDES0_FS;
Sergunb 0:8918a71cdbe9 482 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 483 txCurDmaDesc->tdes0 |= ETH_TDES0_OWN;
Sergunb 0:8918a71cdbe9 484
Sergunb 0:8918a71cdbe9 485 //Clear TU flag to resume processing
Sergunb 0:8918a71cdbe9 486 LPC_ETHERNET->DMA_STAT = ETHERNET_DMA_STAT_TU_Msk;
Sergunb 0:8918a71cdbe9 487 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 488 LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 0;
Sergunb 0:8918a71cdbe9 489
Sergunb 0:8918a71cdbe9 490 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 491 txCurDmaDesc = (Lpc18xxTxDmaDesc *) txCurDmaDesc->tdes3;
Sergunb 0:8918a71cdbe9 492
Sergunb 0:8918a71cdbe9 493 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 494 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 495 {
Sergunb 0:8918a71cdbe9 496 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 497 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 498 }
Sergunb 0:8918a71cdbe9 499
Sergunb 0:8918a71cdbe9 500 //Data successfully written
Sergunb 0:8918a71cdbe9 501 return NO_ERROR;
Sergunb 0:8918a71cdbe9 502 }
Sergunb 0:8918a71cdbe9 503
Sergunb 0:8918a71cdbe9 504
Sergunb 0:8918a71cdbe9 505 /**
Sergunb 0:8918a71cdbe9 506 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 507 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 508 * @return Error code
Sergunb 0:8918a71cdbe9 509 **/
Sergunb 0:8918a71cdbe9 510
Sergunb 0:8918a71cdbe9 511 error_t lpc18xxEthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 512 {
Sergunb 0:8918a71cdbe9 513 error_t error;
Sergunb 0:8918a71cdbe9 514 size_t n;
Sergunb 0:8918a71cdbe9 515
Sergunb 0:8918a71cdbe9 516 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 517 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_OWN))
Sergunb 0:8918a71cdbe9 518 {
Sergunb 0:8918a71cdbe9 519 //FS and LS flags should be set
Sergunb 0:8918a71cdbe9 520 if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) && (rxCurDmaDesc->rdes0 & ETH_RDES0_LS))
Sergunb 0:8918a71cdbe9 521 {
Sergunb 0:8918a71cdbe9 522 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 523 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_ES))
Sergunb 0:8918a71cdbe9 524 {
Sergunb 0:8918a71cdbe9 525 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 526 n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
Sergunb 0:8918a71cdbe9 527 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 528 n = MIN(n, LPC18XX_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 529
Sergunb 0:8918a71cdbe9 530 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 531 nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
Sergunb 0:8918a71cdbe9 532
Sergunb 0:8918a71cdbe9 533 //Valid packet received
Sergunb 0:8918a71cdbe9 534 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 535 }
Sergunb 0:8918a71cdbe9 536 else
Sergunb 0:8918a71cdbe9 537 {
Sergunb 0:8918a71cdbe9 538 //The received packet contains an error
Sergunb 0:8918a71cdbe9 539 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 540 }
Sergunb 0:8918a71cdbe9 541 }
Sergunb 0:8918a71cdbe9 542 else
Sergunb 0:8918a71cdbe9 543 {
Sergunb 0:8918a71cdbe9 544 //The packet is not valid
Sergunb 0:8918a71cdbe9 545 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 546 }
Sergunb 0:8918a71cdbe9 547
Sergunb 0:8918a71cdbe9 548 //Give the ownership of the descriptor back to the DMA
Sergunb 0:8918a71cdbe9 549 rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 550 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 551 rxCurDmaDesc = (Lpc18xxRxDmaDesc *) rxCurDmaDesc->rdes3;
Sergunb 0:8918a71cdbe9 552 }
Sergunb 0:8918a71cdbe9 553 else
Sergunb 0:8918a71cdbe9 554 {
Sergunb 0:8918a71cdbe9 555 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 556 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 557 }
Sergunb 0:8918a71cdbe9 558
Sergunb 0:8918a71cdbe9 559 //Clear RU flag to resume processing
Sergunb 0:8918a71cdbe9 560 LPC_ETHERNET->DMA_STAT = ETHERNET_DMA_STAT_RU_Msk;
Sergunb 0:8918a71cdbe9 561 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 562 LPC_ETHERNET->DMA_REC_POLL_DEMAND = 0;
Sergunb 0:8918a71cdbe9 563
Sergunb 0:8918a71cdbe9 564 //Return status code
Sergunb 0:8918a71cdbe9 565 return error;
Sergunb 0:8918a71cdbe9 566 }
Sergunb 0:8918a71cdbe9 567
Sergunb 0:8918a71cdbe9 568
Sergunb 0:8918a71cdbe9 569 /**
Sergunb 0:8918a71cdbe9 570 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 571 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 572 * @return Error code
Sergunb 0:8918a71cdbe9 573 **/
Sergunb 0:8918a71cdbe9 574
Sergunb 0:8918a71cdbe9 575 error_t lpc18xxEthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 576 {
Sergunb 0:8918a71cdbe9 577 uint_t i;
Sergunb 0:8918a71cdbe9 578 uint_t k;
Sergunb 0:8918a71cdbe9 579 uint32_t crc;
Sergunb 0:8918a71cdbe9 580 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 581 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 582
Sergunb 0:8918a71cdbe9 583 //Debug message
Sergunb 0:8918a71cdbe9 584 TRACE_DEBUG("Updating LPC18xx hash table...\r\n");
Sergunb 0:8918a71cdbe9 585
Sergunb 0:8918a71cdbe9 586 //Clear hash table
Sergunb 0:8918a71cdbe9 587 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 588 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 589
Sergunb 0:8918a71cdbe9 590 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 591 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 592 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 593 {
Sergunb 0:8918a71cdbe9 594 //Point to the current entry
Sergunb 0:8918a71cdbe9 595 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 596
Sergunb 0:8918a71cdbe9 597 //Valid entry?
Sergunb 0:8918a71cdbe9 598 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 599 {
Sergunb 0:8918a71cdbe9 600 //Compute CRC over the current MAC address
Sergunb 0:8918a71cdbe9 601 crc = lpc18xxEthCalcCrc(&entry->addr, sizeof(MacAddr));
Sergunb 0:8918a71cdbe9 602
Sergunb 0:8918a71cdbe9 603 //The upper 6 bits in the CRC register are used to index the
Sergunb 0:8918a71cdbe9 604 //contents of the hash table
Sergunb 0:8918a71cdbe9 605 k = (crc >> 26) & 0x3F;
Sergunb 0:8918a71cdbe9 606
Sergunb 0:8918a71cdbe9 607 //Update hash table contents
Sergunb 0:8918a71cdbe9 608 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 609 }
Sergunb 0:8918a71cdbe9 610 }
Sergunb 0:8918a71cdbe9 611
Sergunb 0:8918a71cdbe9 612 //Write the hash table
Sergunb 0:8918a71cdbe9 613 LPC_ETHERNET->MAC_HASHTABLE_LOW = hashTable[0];
Sergunb 0:8918a71cdbe9 614 LPC_ETHERNET->MAC_HASHTABLE_HIGH = hashTable[1];
Sergunb 0:8918a71cdbe9 615
Sergunb 0:8918a71cdbe9 616 //Debug message
Sergunb 0:8918a71cdbe9 617 TRACE_DEBUG(" MAC_HASHTABLE_LOW = %08" PRIX32 "\r\n", LPC_ETHERNET->MAC_HASHTABLE_LOW);
Sergunb 0:8918a71cdbe9 618 TRACE_DEBUG(" MAC_HASHTABLE_HIGH = %08" PRIX32 "\r\n", LPC_ETHERNET->MAC_HASHTABLE_HIGH);
Sergunb 0:8918a71cdbe9 619
Sergunb 0:8918a71cdbe9 620 //Successful processing
Sergunb 0:8918a71cdbe9 621 return NO_ERROR;
Sergunb 0:8918a71cdbe9 622 }
Sergunb 0:8918a71cdbe9 623
Sergunb 0:8918a71cdbe9 624
Sergunb 0:8918a71cdbe9 625 /**
Sergunb 0:8918a71cdbe9 626 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 627 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 628 * @return Error code
Sergunb 0:8918a71cdbe9 629 **/
Sergunb 0:8918a71cdbe9 630
Sergunb 0:8918a71cdbe9 631 error_t lpc18xxEthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 632 {
Sergunb 0:8918a71cdbe9 633 uint32_t config;
Sergunb 0:8918a71cdbe9 634
Sergunb 0:8918a71cdbe9 635 //Read current MAC configuration
Sergunb 0:8918a71cdbe9 636 config = LPC_ETHERNET->MAC_CONFIG;
Sergunb 0:8918a71cdbe9 637
Sergunb 0:8918a71cdbe9 638 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 639 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 640 config |= ETHERNET_MAC_CONFIG_FES_Msk;
Sergunb 0:8918a71cdbe9 641 else
Sergunb 0:8918a71cdbe9 642 config &= ~ETHERNET_MAC_CONFIG_FES_Msk;
Sergunb 0:8918a71cdbe9 643
Sergunb 0:8918a71cdbe9 644 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 645 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 646 config |= ETHERNET_MAC_CONFIG_DM_Msk;
Sergunb 0:8918a71cdbe9 647 else
Sergunb 0:8918a71cdbe9 648 config &= ~ETHERNET_MAC_CONFIG_DM_Msk;
Sergunb 0:8918a71cdbe9 649
Sergunb 0:8918a71cdbe9 650 //Update MAC configuration register
Sergunb 0:8918a71cdbe9 651 LPC_ETHERNET->MAC_CONFIG = config;
Sergunb 0:8918a71cdbe9 652
Sergunb 0:8918a71cdbe9 653 //Successful processing
Sergunb 0:8918a71cdbe9 654 return NO_ERROR;
Sergunb 0:8918a71cdbe9 655 }
Sergunb 0:8918a71cdbe9 656
Sergunb 0:8918a71cdbe9 657
Sergunb 0:8918a71cdbe9 658 /**
Sergunb 0:8918a71cdbe9 659 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 660 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 661 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 662 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 663 **/
Sergunb 0:8918a71cdbe9 664
Sergunb 0:8918a71cdbe9 665 void lpc18xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 666 {
Sergunb 0:8918a71cdbe9 667 uint32_t value;
Sergunb 0:8918a71cdbe9 668
Sergunb 0:8918a71cdbe9 669 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 670 value = LPC_ETHERNET->MAC_MII_ADDR & ETHERNET_MAC_MII_ADDR_CR_Msk;
Sergunb 0:8918a71cdbe9 671 //Set up a write operation
Sergunb 0:8918a71cdbe9 672 value |= ETHERNET_MAC_MII_ADDR_W_Msk | ETHERNET_MAC_MII_ADDR_GB_Msk;
Sergunb 0:8918a71cdbe9 673 //PHY address
Sergunb 0:8918a71cdbe9 674 value |= (phyAddr << ETHERNET_MAC_MII_ADDR_PA_Pos) & ETHERNET_MAC_MII_ADDR_PA_Msk;
Sergunb 0:8918a71cdbe9 675 //Register address
Sergunb 0:8918a71cdbe9 676 value |= (regAddr << ETHERNET_MAC_MII_ADDR_GR_Pos) & ETHERNET_MAC_MII_ADDR_GR_Msk;
Sergunb 0:8918a71cdbe9 677
Sergunb 0:8918a71cdbe9 678 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 679 LPC_ETHERNET->MAC_MII_DATA = data & ETHERNET_MAC_MII_DATA_GD_Msk;
Sergunb 0:8918a71cdbe9 680
Sergunb 0:8918a71cdbe9 681 //Start a write operation
Sergunb 0:8918a71cdbe9 682 LPC_ETHERNET->MAC_MII_ADDR = value;
Sergunb 0:8918a71cdbe9 683 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 684 while(LPC_ETHERNET->MAC_MII_ADDR & ETHERNET_MAC_MII_ADDR_GB_Msk);
Sergunb 0:8918a71cdbe9 685 }
Sergunb 0:8918a71cdbe9 686
Sergunb 0:8918a71cdbe9 687
Sergunb 0:8918a71cdbe9 688 /**
Sergunb 0:8918a71cdbe9 689 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 690 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 691 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 692 * @return Register value
Sergunb 0:8918a71cdbe9 693 **/
Sergunb 0:8918a71cdbe9 694
Sergunb 0:8918a71cdbe9 695 uint16_t lpc18xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 696 {
Sergunb 0:8918a71cdbe9 697 uint32_t value;
Sergunb 0:8918a71cdbe9 698
Sergunb 0:8918a71cdbe9 699 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 700 value = LPC_ETHERNET->MAC_MII_ADDR & ETHERNET_MAC_MII_ADDR_CR_Msk;
Sergunb 0:8918a71cdbe9 701 //Set up a read operation
Sergunb 0:8918a71cdbe9 702 value |= ETHERNET_MAC_MII_ADDR_GB_Msk;
Sergunb 0:8918a71cdbe9 703 //PHY address
Sergunb 0:8918a71cdbe9 704 value |= (phyAddr << ETHERNET_MAC_MII_ADDR_PA_Pos) & ETHERNET_MAC_MII_ADDR_PA_Msk;
Sergunb 0:8918a71cdbe9 705 //Register address
Sergunb 0:8918a71cdbe9 706 value |= (regAddr << ETHERNET_MAC_MII_ADDR_GR_Pos) & ETHERNET_MAC_MII_ADDR_GR_Msk;
Sergunb 0:8918a71cdbe9 707
Sergunb 0:8918a71cdbe9 708 //Start a read operation
Sergunb 0:8918a71cdbe9 709 LPC_ETHERNET->MAC_MII_ADDR = value;
Sergunb 0:8918a71cdbe9 710 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 711 while(LPC_ETHERNET->MAC_MII_ADDR & ETHERNET_MAC_MII_ADDR_GB_Msk);
Sergunb 0:8918a71cdbe9 712
Sergunb 0:8918a71cdbe9 713 //Return PHY register contents
Sergunb 0:8918a71cdbe9 714 return LPC_ETHERNET->MAC_MII_DATA & ETHERNET_MAC_MII_DATA_GD_Msk;
Sergunb 0:8918a71cdbe9 715 }
Sergunb 0:8918a71cdbe9 716
Sergunb 0:8918a71cdbe9 717
Sergunb 0:8918a71cdbe9 718 /**
Sergunb 0:8918a71cdbe9 719 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 720 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 721 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 722 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 723 **/
Sergunb 0:8918a71cdbe9 724
Sergunb 0:8918a71cdbe9 725 uint32_t lpc18xxEthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 726 {
Sergunb 0:8918a71cdbe9 727 uint_t i;
Sergunb 0:8918a71cdbe9 728 uint_t j;
Sergunb 0:8918a71cdbe9 729
Sergunb 0:8918a71cdbe9 730 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 731 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 732 //CRC preset value
Sergunb 0:8918a71cdbe9 733 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 734
Sergunb 0:8918a71cdbe9 735 //Loop through data
Sergunb 0:8918a71cdbe9 736 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 737 {
Sergunb 0:8918a71cdbe9 738 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 739 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 740 {
Sergunb 0:8918a71cdbe9 741 //Update CRC value
Sergunb 0:8918a71cdbe9 742 if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
Sergunb 0:8918a71cdbe9 743 crc = (crc << 1) ^ 0x04C11DB7;
Sergunb 0:8918a71cdbe9 744 else
Sergunb 0:8918a71cdbe9 745 crc = crc << 1;
Sergunb 0:8918a71cdbe9 746 }
Sergunb 0:8918a71cdbe9 747 }
Sergunb 0:8918a71cdbe9 748
Sergunb 0:8918a71cdbe9 749 //Return CRC value
Sergunb 0:8918a71cdbe9 750 return ~crc;
Sergunb 0:8918a71cdbe9 751 }
Sergunb 0:8918a71cdbe9 752