Sergey Pastor / 1

Webserver+3d print

Dependents:   Nucleo

cyclone_tcp/drivers/dp83620.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file dp83620.h
Sergunb 0:8918a71cdbe9 3 * @brief DP83620 Ethernet PHY transceiver
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _DP83620_H
Sergunb 0:8918a71cdbe9 30 #define _DP83620_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //PHY address
Sergunb 0:8918a71cdbe9 36 #ifndef DP83620_PHY_ADDR
Sergunb 0:8918a71cdbe9 37 #define DP83620_PHY_ADDR 1
Sergunb 0:8918a71cdbe9 38 #elif (DP83620_PHY_ADDR < 0 || DP83620_PHY_ADDR > 31)
Sergunb 0:8918a71cdbe9 39 #error DP83620_PHY_ADDR parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //DP83620 registers
Sergunb 0:8918a71cdbe9 43 #define DP83620_PHY_REG_BMCR 0x00
Sergunb 0:8918a71cdbe9 44 #define DP83620_PHY_REG_BMSR 0x01
Sergunb 0:8918a71cdbe9 45 #define DP83620_PHY_REG_PHYIDR1 0x02
Sergunb 0:8918a71cdbe9 46 #define DP83620_PHY_REG_PHYIDR2 0x03
Sergunb 0:8918a71cdbe9 47 #define DP83620_PHY_REG_ANAR 0x04
Sergunb 0:8918a71cdbe9 48 #define DP83620_PHY_REG_ANLPAR 0x05
Sergunb 0:8918a71cdbe9 49 #define DP83620_PHY_REG_ANER 0x06
Sergunb 0:8918a71cdbe9 50 #define DP83620_PHY_REG_ANNPTR 0x07
Sergunb 0:8918a71cdbe9 51 #define DP83620_PHY_REG_PHYSTS 0x10
Sergunb 0:8918a71cdbe9 52 #define DP83620_PHY_REG_MICR 0x11
Sergunb 0:8918a71cdbe9 53 #define DP83620_PHY_REG_MISR 0x12
Sergunb 0:8918a71cdbe9 54 #define DP83620_PHY_REG_PAGESEL 0x13
Sergunb 0:8918a71cdbe9 55
Sergunb 0:8918a71cdbe9 56 //Extended registers (page 0)
Sergunb 0:8918a71cdbe9 57 #define DP83620_PHY_REG_FCSCR 0x14
Sergunb 0:8918a71cdbe9 58 #define DP83620_PHY_REG_RECR 0x15
Sergunb 0:8918a71cdbe9 59 #define DP83620_PHY_REG_PCSR 0x16
Sergunb 0:8918a71cdbe9 60 #define DP83620_PHY_REG_RBR 0x17
Sergunb 0:8918a71cdbe9 61 #define DP83620_PHY_REG_LEDCR 0x18
Sergunb 0:8918a71cdbe9 62 #define DP83620_PHY_REG_PHYCR 0x19
Sergunb 0:8918a71cdbe9 63 #define DP83620_PHY_REG_10BTSCR 0x1A
Sergunb 0:8918a71cdbe9 64 #define DP83620_PHY_REG_CDCTRL1 0x1B
Sergunb 0:8918a71cdbe9 65 #define DP83620_PHY_REG_PHYCR2 0x1C
Sergunb 0:8918a71cdbe9 66 #define DP83620_PHY_REG_EDCR 0x1D
Sergunb 0:8918a71cdbe9 67 #define DP83620_PHY_REG_PCFCR 0x1F
Sergunb 0:8918a71cdbe9 68
Sergunb 0:8918a71cdbe9 69 //Extended registers (page 1)
Sergunb 0:8918a71cdbe9 70 #define DP83620_PHY_REG_SD_CNFG 0x1E
Sergunb 0:8918a71cdbe9 71
Sergunb 0:8918a71cdbe9 72 //Extended registers (page 2)
Sergunb 0:8918a71cdbe9 73 #define DP83620_PHY_REG_LEN100_DET 0x14
Sergunb 0:8918a71cdbe9 74 #define DP83620_PHY_REG_FREQ100 0x15
Sergunb 0:8918a71cdbe9 75 #define DP83620_PHY_REG_TDR_CTRL 0x16
Sergunb 0:8918a71cdbe9 76 #define DP83620_PHY_REG_TDR_WIN 0x17
Sergunb 0:8918a71cdbe9 77 #define DP83620_PHY_REG_TDR_PEAK 0x18
Sergunb 0:8918a71cdbe9 78 #define DP83620_PHY_REG_TDR_THR 0x19
Sergunb 0:8918a71cdbe9 79 #define DP83620_PHY_REG_VAR_CTRL 0x1A
Sergunb 0:8918a71cdbe9 80 #define DP83620_PHY_REG_VAR_DAT 0x1B
Sergunb 0:8918a71cdbe9 81 #define DP83620_PHY_REG_LQMR 0x1D
Sergunb 0:8918a71cdbe9 82 #define DP83620_PHY_REG_LQDR 0x1E
Sergunb 0:8918a71cdbe9 83 #define DP83620_PHY_REG_LQMR2 0x1F
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 //Extended registers (page 5)
Sergunb 0:8918a71cdbe9 86 #define DP83620_PHY_REG_PSF_CFG 0x18
Sergunb 0:8918a71cdbe9 87
Sergunb 0:8918a71cdbe9 88 //BMCR register
Sergunb 0:8918a71cdbe9 89 #define BMCR_RESET (1 << 15)
Sergunb 0:8918a71cdbe9 90 #define BMCR_LOOPBACK (1 << 14)
Sergunb 0:8918a71cdbe9 91 #define BMCR_SPEED_SEL (1 << 13)
Sergunb 0:8918a71cdbe9 92 #define BMCR_AN_EN (1 << 12)
Sergunb 0:8918a71cdbe9 93 #define BMCR_POWER_DOWN (1 << 11)
Sergunb 0:8918a71cdbe9 94 #define BMCR_ISOLATE (1 << 10)
Sergunb 0:8918a71cdbe9 95 #define BMCR_RESTART_AN (1 << 9)
Sergunb 0:8918a71cdbe9 96 #define BMCR_DUPLEX_MODE (1 << 8)
Sergunb 0:8918a71cdbe9 97 #define BMCR_COL_TEST (1 << 7)
Sergunb 0:8918a71cdbe9 98 #define BMCR_UNIDIRECTIONAL_EN (1 << 5)
Sergunb 0:8918a71cdbe9 99
Sergunb 0:8918a71cdbe9 100 //BMSR register
Sergunb 0:8918a71cdbe9 101 #define BMSR_100BT4 (1 << 15)
Sergunb 0:8918a71cdbe9 102 #define BMSR_100BTX_FD (1 << 14)
Sergunb 0:8918a71cdbe9 103 #define BMSR_100BTX (1 << 13)
Sergunb 0:8918a71cdbe9 104 #define BMSR_10BT_FD (1 << 12)
Sergunb 0:8918a71cdbe9 105 #define BMSR_10BT (1 << 11)
Sergunb 0:8918a71cdbe9 106 #define BMSR_UNIDIRECTIONAL_ABLE (1 << 7)
Sergunb 0:8918a71cdbe9 107 #define BMSR_NO_PREAMBLE (1 << 6)
Sergunb 0:8918a71cdbe9 108 #define BMSR_AN_COMPLETE (1 << 5)
Sergunb 0:8918a71cdbe9 109 #define BMSR_REMOTE_FAULT (1 << 4)
Sergunb 0:8918a71cdbe9 110 #define BMSR_AN_ABLE (1 << 3)
Sergunb 0:8918a71cdbe9 111 #define BMSR_LINK_STATUS (1 << 2)
Sergunb 0:8918a71cdbe9 112 #define BMSR_JABBER_DETECT (1 << 1)
Sergunb 0:8918a71cdbe9 113 #define BMSR_EXTENDED_CAP (1 << 0)
Sergunb 0:8918a71cdbe9 114
Sergunb 0:8918a71cdbe9 115 //ANAR register
Sergunb 0:8918a71cdbe9 116 #define ANAR_NP (1 << 15)
Sergunb 0:8918a71cdbe9 117 #define ANAR_RF (1 << 13)
Sergunb 0:8918a71cdbe9 118 #define ANAR_ASM_DIR (1 << 11)
Sergunb 0:8918a71cdbe9 119 #define ANAR_PAUSE (1 << 10)
Sergunb 0:8918a71cdbe9 120 #define ANAR_100BT4 (1 << 9)
Sergunb 0:8918a71cdbe9 121 #define ANAR_100BTX_FD (1 << 8)
Sergunb 0:8918a71cdbe9 122 #define ANAR_100BTX (1 << 7)
Sergunb 0:8918a71cdbe9 123 #define ANAR_10BT_FD (1 << 6)
Sergunb 0:8918a71cdbe9 124 #define ANAR_10BT (1 << 5)
Sergunb 0:8918a71cdbe9 125 #define ANAR_SELECTOR4 (1 << 4)
Sergunb 0:8918a71cdbe9 126 #define ANAR_SELECTOR3 (1 << 3)
Sergunb 0:8918a71cdbe9 127 #define ANAR_SELECTOR2 (1 << 2)
Sergunb 0:8918a71cdbe9 128 #define ANAR_SELECTOR1 (1 << 1)
Sergunb 0:8918a71cdbe9 129 #define ANAR_SELECTOR0 (1 << 0)
Sergunb 0:8918a71cdbe9 130
Sergunb 0:8918a71cdbe9 131 //ANLPAR register
Sergunb 0:8918a71cdbe9 132 #define ANLPAR_NP (1 << 15)
Sergunb 0:8918a71cdbe9 133 #define ANLPAR_ACK (1 << 14)
Sergunb 0:8918a71cdbe9 134 #define ANLPAR_RF (1 << 13)
Sergunb 0:8918a71cdbe9 135 #define ANLPAR_ASM_DIR (1 << 11)
Sergunb 0:8918a71cdbe9 136 #define ANLPAR_PAUSE (1 << 10)
Sergunb 0:8918a71cdbe9 137 #define ANLPAR_100BT4 (1 << 9)
Sergunb 0:8918a71cdbe9 138 #define ANLPAR_100BTX_FD (1 << 8)
Sergunb 0:8918a71cdbe9 139 #define ANLPAR_100BTX (1 << 7)
Sergunb 0:8918a71cdbe9 140 #define ANLPAR_10BT_FD (1 << 6)
Sergunb 0:8918a71cdbe9 141 #define ANLPAR_10BT (1 << 5)
Sergunb 0:8918a71cdbe9 142 #define ANLPAR_SELECTOR4 (1 << 4)
Sergunb 0:8918a71cdbe9 143 #define ANLPAR_SELECTOR3 (1 << 3)
Sergunb 0:8918a71cdbe9 144 #define ANLPAR_SELECTOR2 (1 << 2)
Sergunb 0:8918a71cdbe9 145 #define ANLPAR_SELECTOR1 (1 << 1)
Sergunb 0:8918a71cdbe9 146 #define ANLPAR_SELECTOR0 (1 << 0)
Sergunb 0:8918a71cdbe9 147
Sergunb 0:8918a71cdbe9 148 //ANER register
Sergunb 0:8918a71cdbe9 149 #define ANER_PDF (1 << 4)
Sergunb 0:8918a71cdbe9 150 #define ANER_LP_NP_ABLE (1 << 3)
Sergunb 0:8918a71cdbe9 151 #define ANER_NP_ABLE (1 << 2)
Sergunb 0:8918a71cdbe9 152 #define ANER_PAGE_RX (1 << 1)
Sergunb 0:8918a71cdbe9 153 #define ANER_LP_AN_ABLE (1 << 0)
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 //ANNPTR register
Sergunb 0:8918a71cdbe9 156 #define ANNPTR_NP (1 << 15)
Sergunb 0:8918a71cdbe9 157 #define ANNPTR_MP (1 << 13)
Sergunb 0:8918a71cdbe9 158 #define ANNPTR_ACK2 (1 << 12)
Sergunb 0:8918a71cdbe9 159 #define ANNPTR_TOG_TX (1 << 11)
Sergunb 0:8918a71cdbe9 160 #define ANNPTR_CODE10 (1 << 10)
Sergunb 0:8918a71cdbe9 161 #define ANNPTR_CODE9 (1 << 9)
Sergunb 0:8918a71cdbe9 162 #define ANNPTR_CODE8 (1 << 8)
Sergunb 0:8918a71cdbe9 163 #define ANNPTR_CODE7 (1 << 7)
Sergunb 0:8918a71cdbe9 164 #define ANNPTR_CODE6 (1 << 6)
Sergunb 0:8918a71cdbe9 165 #define ANNPTR_CODE5 (1 << 5)
Sergunb 0:8918a71cdbe9 166 #define ANNPTR_CODE4 (1 << 4)
Sergunb 0:8918a71cdbe9 167 #define ANNPTR_CODE3 (1 << 3)
Sergunb 0:8918a71cdbe9 168 #define ANNPTR_CODE2 (1 << 2)
Sergunb 0:8918a71cdbe9 169 #define ANNPTR_CODE1 (1 << 1)
Sergunb 0:8918a71cdbe9 170 #define ANNPTR_CODE0 (1 << 0)
Sergunb 0:8918a71cdbe9 171
Sergunb 0:8918a71cdbe9 172 //PHYSTS register
Sergunb 0:8918a71cdbe9 173 #define PHYSTS_MDIX_MODE (1 << 14)
Sergunb 0:8918a71cdbe9 174 #define PHYSTS_RX_ERROR_LATCH (1 << 13)
Sergunb 0:8918a71cdbe9 175 #define PHYSTS_POLARITY_STATUS (1 << 12)
Sergunb 0:8918a71cdbe9 176 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
Sergunb 0:8918a71cdbe9 177 #define PHYSTS_SIGNAL_DETECT (1 << 10)
Sergunb 0:8918a71cdbe9 178 #define PHYSTS_DESCRAMBLER_LOCK (1 << 9)
Sergunb 0:8918a71cdbe9 179 #define PHYSTS_PAGE_RECEIVED (1 << 8)
Sergunb 0:8918a71cdbe9 180 #define PHYSTS_MII_INTERRUPT (1 << 7)
Sergunb 0:8918a71cdbe9 181 #define PHYSTS_REMOTE_FAULT (1 << 6)
Sergunb 0:8918a71cdbe9 182 #define PHYSTS_JABBER_DETECT (1 << 5)
Sergunb 0:8918a71cdbe9 183 #define PHYSTS_AN_COMPLETE (1 << 4)
Sergunb 0:8918a71cdbe9 184 #define PHYSTS_LOOPBACK_STATUS (1 << 3)
Sergunb 0:8918a71cdbe9 185 #define PHYSTS_DUPLEX_STATUS (1 << 2)
Sergunb 0:8918a71cdbe9 186 #define PHYSTS_SPEED_STATUS (1 << 1)
Sergunb 0:8918a71cdbe9 187 #define PHYSTS_LINK_STATUS (1 << 0)
Sergunb 0:8918a71cdbe9 188
Sergunb 0:8918a71cdbe9 189 //MICR register
Sergunb 0:8918a71cdbe9 190 #define MICR_TINT (1 << 2)
Sergunb 0:8918a71cdbe9 191 #define MICR_INTEN (1 << 1)
Sergunb 0:8918a71cdbe9 192 #define MICR_INT_OE (1 << 0)
Sergunb 0:8918a71cdbe9 193
Sergunb 0:8918a71cdbe9 194 //MISR register
Sergunb 0:8918a71cdbe9 195 #define MISR_ED_INT (1 << 14)
Sergunb 0:8918a71cdbe9 196 #define MISR_LINK_INT (1 << 13)
Sergunb 0:8918a71cdbe9 197 #define MISR_SPD_INT (1 << 12)
Sergunb 0:8918a71cdbe9 198 #define MISR_DUP_INT (1 << 11)
Sergunb 0:8918a71cdbe9 199 #define MISR_ANC_INT (1 << 10)
Sergunb 0:8918a71cdbe9 200 #define MISR_FHF_INT (1 << 9)
Sergunb 0:8918a71cdbe9 201 #define MISR_RHF_INT (1 << 8)
Sergunb 0:8918a71cdbe9 202 #define MISR_LQ_INT_EN (1 << 7)
Sergunb 0:8918a71cdbe9 203 #define MISR_ED_INT_EN (1 << 6)
Sergunb 0:8918a71cdbe9 204 #define MISR_LINK_INT_EN (1 << 5)
Sergunb 0:8918a71cdbe9 205 #define MISR_SPD_INT_EN (1 << 4)
Sergunb 0:8918a71cdbe9 206 #define MISR_DUP_INT_EN (1 << 3)
Sergunb 0:8918a71cdbe9 207 #define MISR_ANC_INT_EN (1 << 2)
Sergunb 0:8918a71cdbe9 208 #define MISR_FHF_INT_EN (1 << 1)
Sergunb 0:8918a71cdbe9 209 #define MISR_RHF_INT_EN (1 << 0)
Sergunb 0:8918a71cdbe9 210
Sergunb 0:8918a71cdbe9 211 //PAGESEL register
Sergunb 0:8918a71cdbe9 212 #define PAGESEL_PAGE_SEL2 (1 << 2)
Sergunb 0:8918a71cdbe9 213 #define PAGESEL_PAGE_SEL1 (1 << 1)
Sergunb 0:8918a71cdbe9 214 #define PAGESEL_PAGE_SEL0 (1 << 0)
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216 //FCSCR register
Sergunb 0:8918a71cdbe9 217 #define FCSCR_FCSCNT7 (1 << 7)
Sergunb 0:8918a71cdbe9 218 #define FCSCR_FCSCNT6 (1 << 6)
Sergunb 0:8918a71cdbe9 219 #define FCSCR_FCSCNT5 (1 << 5)
Sergunb 0:8918a71cdbe9 220 #define FCSCR_FCSCNT4 (1 << 4)
Sergunb 0:8918a71cdbe9 221 #define FCSCR_FCSCNT3 (1 << 3)
Sergunb 0:8918a71cdbe9 222 #define FCSCR_FCSCNT2 (1 << 2)
Sergunb 0:8918a71cdbe9 223 #define FCSCR_FCSCNT1 (1 << 1)
Sergunb 0:8918a71cdbe9 224 #define FCSCR_FCSCNT0 (1 << 0)
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 //RECR register
Sergunb 0:8918a71cdbe9 227 #define RECR_RXERCNT7 (1 << 7)
Sergunb 0:8918a71cdbe9 228 #define RECR_RXERCNT6 (1 << 6)
Sergunb 0:8918a71cdbe9 229 #define RECR_RXERCNT5 (1 << 5)
Sergunb 0:8918a71cdbe9 230 #define RECR_RXERCNT4 (1 << 4)
Sergunb 0:8918a71cdbe9 231 #define RECR_RXERCNT3 (1 << 3)
Sergunb 0:8918a71cdbe9 232 #define RECR_RXERCNT2 (1 << 2)
Sergunb 0:8918a71cdbe9 233 #define RECR_RXERCNT1 (1 << 1)
Sergunb 0:8918a71cdbe9 234 #define RECR_RXERCNT0 (1 << 0)
Sergunb 0:8918a71cdbe9 235
Sergunb 0:8918a71cdbe9 236 //PCSR register
Sergunb 0:8918a71cdbe9 237 #define PCSR_AUTO_CROSSOVER (1 << 15)
Sergunb 0:8918a71cdbe9 238 #define PCSR_FREE_CLK (1 << 11)
Sergunb 0:8918a71cdbe9 239 #define PCSR_TQ_EN (1 << 10)
Sergunb 0:8918a71cdbe9 240 #define PCSR_SD_FORCE_PMA (1 << 9)
Sergunb 0:8918a71cdbe9 241 #define PCSR_SD_OPTION (1 << 8)
Sergunb 0:8918a71cdbe9 242 #define PCSR_DESC_TIME (1 << 7)
Sergunb 0:8918a71cdbe9 243 #define PCSR_FX_EN (1 << 6)
Sergunb 0:8918a71cdbe9 244 #define PCSR_FORCE_100_OK (1 << 5)
Sergunb 0:8918a71cdbe9 245 #define PCSR_FEFI_EN (1 << 3)
Sergunb 0:8918a71cdbe9 246 #define PCSR_NRZI_BYPASS (1 << 2)
Sergunb 0:8918a71cdbe9 247 #define PCSR_SCRAM_BYPASS (1 << 1)
Sergunb 0:8918a71cdbe9 248 #define PCSR_DESCRAM_BYPASS (1 << 0)
Sergunb 0:8918a71cdbe9 249
Sergunb 0:8918a71cdbe9 250 //RBR register
Sergunb 0:8918a71cdbe9 251 #define RBR_RMII_MASTER (1 << 14)
Sergunb 0:8918a71cdbe9 252 #define RBR_DIS_TX_OPT (1 << 13)
Sergunb 0:8918a71cdbe9 253 #define RBR_PMD_LOOP (1 << 8)
Sergunb 0:8918a71cdbe9 254 #define RBR_SCMII_RX (1 << 7)
Sergunb 0:8918a71cdbe9 255 #define RBR_SCMII_TX (1 << 6)
Sergunb 0:8918a71cdbe9 256 #define RBR_RMII_MODE (1 << 5)
Sergunb 0:8918a71cdbe9 257 #define RBR_RMII_REV1_0 (1 << 4)
Sergunb 0:8918a71cdbe9 258 #define RBR_RX_OVF_STS (1 << 3)
Sergunb 0:8918a71cdbe9 259 #define RBR_RX_UNF_STS (1 << 2)
Sergunb 0:8918a71cdbe9 260 #define RBR_ELAST_BUF1 (1 << 1)
Sergunb 0:8918a71cdbe9 261 #define RBR_ELAST_BUF0 (1 << 0)
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263 //LEDCR register
Sergunb 0:8918a71cdbe9 264 #define LEDCR_DIS_SPDLED (1 << 11)
Sergunb 0:8918a71cdbe9 265 #define LEDCR_DIS_LNKLED (1 << 10)
Sergunb 0:8918a71cdbe9 266 #define LEDCR_DIS_ACTLED (1 << 9)
Sergunb 0:8918a71cdbe9 267 #define LEDCR_LEDACT_RX (1 << 8)
Sergunb 0:8918a71cdbe9 268 #define LEDCR_BLINK_FREQ1 (1 << 7)
Sergunb 0:8918a71cdbe9 269 #define LEDCR_BLINK_FREQ0 (1 << 6)
Sergunb 0:8918a71cdbe9 270 #define LEDCR_DRV_SPDLED (1 << 5)
Sergunb 0:8918a71cdbe9 271 #define LEDCR_DRV_LNKLED (1 << 4)
Sergunb 0:8918a71cdbe9 272 #define LEDCR_DRV_ACTLED (1 << 3)
Sergunb 0:8918a71cdbe9 273 #define LEDCR_SPDLED (1 << 2)
Sergunb 0:8918a71cdbe9 274 #define LEDCR_LNKLED (1 << 1)
Sergunb 0:8918a71cdbe9 275 #define LEDCR_ACTLED (1 << 0)
Sergunb 0:8918a71cdbe9 276
Sergunb 0:8918a71cdbe9 277 #define LEDCR_BLINK_FREQ_6HZ (0 << 6)
Sergunb 0:8918a71cdbe9 278 #define LEDCR_BLINK_FREQ_12HZ (1 << 6)
Sergunb 0:8918a71cdbe9 279 #define LEDCR_BLINK_FREQ_24HZ (2 << 6)
Sergunb 0:8918a71cdbe9 280 #define LEDCR_BLINK_FREQ_48HZ (3 << 6)
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 //PHYCR register
Sergunb 0:8918a71cdbe9 283 #define PHYCR_MDIX_EN (1 << 15)
Sergunb 0:8918a71cdbe9 284 #define PHYCR_FORCE_MDIX (1 << 14)
Sergunb 0:8918a71cdbe9 285 #define PHYCR_PAUSE_RX (1 << 13)
Sergunb 0:8918a71cdbe9 286 #define PHYCR_PAUSE_TX (1 << 12)
Sergunb 0:8918a71cdbe9 287 #define PHYCR_BIST_FE (1 << 11)
Sergunb 0:8918a71cdbe9 288 #define PHYCR_PSR_15 (1 << 10)
Sergunb 0:8918a71cdbe9 289 #define PHYCR_BIST_STATUS (1 << 9)
Sergunb 0:8918a71cdbe9 290 #define PHYCR_BIST_START (1 << 8)
Sergunb 0:8918a71cdbe9 291 #define PHYCR_BP_STRETCH (1 << 7)
Sergunb 0:8918a71cdbe9 292 #define PHYCR_LED_CNFG1 (1 << 6)
Sergunb 0:8918a71cdbe9 293 #define PHYCR_LED_CNFG0 (1 << 5)
Sergunb 0:8918a71cdbe9 294 #define PHYCR_PHYADDR4 (1 << 4)
Sergunb 0:8918a71cdbe9 295 #define PHYCR_PHYADDR3 (1 << 3)
Sergunb 0:8918a71cdbe9 296 #define PHYCR_PHYADDR2 (1 << 2)
Sergunb 0:8918a71cdbe9 297 #define PHYCR_PHYADDR1 (1 << 1)
Sergunb 0:8918a71cdbe9 298 #define PHYCR_PHYADDR0 (1 << 0)
Sergunb 0:8918a71cdbe9 299
Sergunb 0:8918a71cdbe9 300 //10BTSCR register
Sergunb 0:8918a71cdbe9 301 #define _10BTSCR_10BT_SERIAL (1 << 15)
Sergunb 0:8918a71cdbe9 302 #define _10BTSCR_SQUELCH2 (1 << 11)
Sergunb 0:8918a71cdbe9 303 #define _10BTSCR_SQUELCH1 (1 << 10)
Sergunb 0:8918a71cdbe9 304 #define _10BTSCR_SQUELCH0 (1 << 9)
Sergunb 0:8918a71cdbe9 305 #define _10BTSCR_LOOPBACK_10_DIS (1 << 8)
Sergunb 0:8918a71cdbe9 306 #define _10BTSCR_LP_DIS (1 << 7)
Sergunb 0:8918a71cdbe9 307 #define _10BTSCR_FORCE_LINK_10 (1 << 6)
Sergunb 0:8918a71cdbe9 308 #define _10BTSCR_POLARITY (1 << 4)
Sergunb 0:8918a71cdbe9 309 #define _10BTSCR_AUTOPOL_DIS (1 << 3)
Sergunb 0:8918a71cdbe9 310 #define _10BTSCR_10BT_SCALE_MSB (1 << 2)
Sergunb 0:8918a71cdbe9 311 #define _10BTSCR_HEARTBEAT_DIS (1 << 1)
Sergunb 0:8918a71cdbe9 312 #define _10BTSCR_JABBER_DIS (1 << 0)
Sergunb 0:8918a71cdbe9 313
Sergunb 0:8918a71cdbe9 314 //CDCTRL1 register
Sergunb 0:8918a71cdbe9 315 #define CDCTRL1_BIST_ERROR_COUNT7 (1 << 15)
Sergunb 0:8918a71cdbe9 316 #define CDCTRL1_BIST_ERROR_COUNT6 (1 << 14)
Sergunb 0:8918a71cdbe9 317 #define CDCTRL1_BIST_ERROR_COUNT5 (1 << 13)
Sergunb 0:8918a71cdbe9 318 #define CDCTRL1_BIST_ERROR_COUNT4 (1 << 12)
Sergunb 0:8918a71cdbe9 319 #define CDCTRL1_BIST_ERROR_COUNT3 (1 << 11)
Sergunb 0:8918a71cdbe9 320 #define CDCTRL1_BIST_ERROR_COUNT2 (1 << 10)
Sergunb 0:8918a71cdbe9 321 #define CDCTRL1_BIST_ERROR_COUNT1 (1 << 9)
Sergunb 0:8918a71cdbe9 322 #define CDCTRL1_BIST_ERROR_COUNT0 (1 << 8)
Sergunb 0:8918a71cdbe9 323 #define CDCTRL1_MII_CLOCK_EN (1 << 6)
Sergunb 0:8918a71cdbe9 324 #define CDCTRL1_BIST_CONT (1 << 5)
Sergunb 0:8918a71cdbe9 325 #define CDCTRL1_CDPATTEN_10 (1 << 4)
Sergunb 0:8918a71cdbe9 326 #define CDCTRL1_MDIO_PULL_EN (1 << 3)
Sergunb 0:8918a71cdbe9 327 #define CDCTRL1_PATT_GAP_10M (1 << 2)
Sergunb 0:8918a71cdbe9 328 #define CDCTRL1_CDPATTSEL1 (1 << 1)
Sergunb 0:8918a71cdbe9 329 #define CDCTRL1_CDPATTSEL0 (1 << 0)
Sergunb 0:8918a71cdbe9 330
Sergunb 0:8918a71cdbe9 331 //PHYCR2 register
Sergunb 0:8918a71cdbe9 332 #define PHYCR2_SYNC_ENET_EN (1 << 13)
Sergunb 0:8918a71cdbe9 333 #define PHYCR2_CLK_OUT RXCLK (1 << 12)
Sergunb 0:8918a71cdbe9 334 #define PHYCR2_BC_WRITE (1 << 11)
Sergunb 0:8918a71cdbe9 335 #define PHYCR2_PHYTER_COMP (1 << 10)
Sergunb 0:8918a71cdbe9 336 #define PHYCR2_SOFT_RESET (1 << 9)
Sergunb 0:8918a71cdbe9 337 #define PHYCR2_CLK_OUT_DIS (1 << 1)
Sergunb 0:8918a71cdbe9 338
Sergunb 0:8918a71cdbe9 339 //EDCR register
Sergunb 0:8918a71cdbe9 340 #define EDCR_ED_EN (1 << 15)
Sergunb 0:8918a71cdbe9 341 #define EDCR_ED_AUTO_UP (1 << 14)
Sergunb 0:8918a71cdbe9 342 #define EDCR_ED_AUTO_DOWN (1 << 13)
Sergunb 0:8918a71cdbe9 343 #define EDCR_ED_MAN (1 << 12)
Sergunb 0:8918a71cdbe9 344 #define EDCR_ED_BURST_DIS (1 << 11)
Sergunb 0:8918a71cdbe9 345 #define EDCR_ED_PWR_STATE (1 << 10)
Sergunb 0:8918a71cdbe9 346 #define EDCR_ED_ERR_MET (1 << 9)
Sergunb 0:8918a71cdbe9 347 #define EDCR_ED_DATA_MET (1 << 8)
Sergunb 0:8918a71cdbe9 348 #define EDCR_ED_ERR_COUNT3 (1 << 7)
Sergunb 0:8918a71cdbe9 349 #define EDCR_ED_ERR_COUNT2 (1 << 6)
Sergunb 0:8918a71cdbe9 350 #define EDCR_ED_ERR_COUNT1 (1 << 5)
Sergunb 0:8918a71cdbe9 351 #define EDCR_ED_ERR_COUNT0 (1 << 4)
Sergunb 0:8918a71cdbe9 352 #define EDCR_ED_DATA_COUNT3 (1 << 3)
Sergunb 0:8918a71cdbe9 353 #define EDCR_ED_DATA_COUNT2 (1 << 2)
Sergunb 0:8918a71cdbe9 354 #define EDCR_ED_DATA_COUNT1 (1 << 1)
Sergunb 0:8918a71cdbe9 355 #define EDCR_ED_DATA_COUNT0 (1 << 0)
Sergunb 0:8918a71cdbe9 356
Sergunb 0:8918a71cdbe9 357 //PCFCR register
Sergunb 0:8918a71cdbe9 358 #define PCFCR_PCF_STS_ERR (1 << 15)
Sergunb 0:8918a71cdbe9 359 #define PCFCR_PCF_STS_OK (1 << 14)
Sergunb 0:8918a71cdbe9 360 #define PCFCR_PCF_DA_SEL (1 << 8)
Sergunb 0:8918a71cdbe9 361 #define PCFCR_PCF_INT_CTL1 (1 << 7)
Sergunb 0:8918a71cdbe9 362 #define PCFCR_PCF_INT_CTL0 (1 << 6)
Sergunb 0:8918a71cdbe9 363 #define PCFCR_PCF_BC_DIS (1 << 5)
Sergunb 0:8918a71cdbe9 364 #define PCFCR_PCF_BUF3 (1 << 4)
Sergunb 0:8918a71cdbe9 365 #define PCFCR_PCF_BUF2 (1 << 3)
Sergunb 0:8918a71cdbe9 366 #define PCFCR_PCF_BUF1 (1 << 2)
Sergunb 0:8918a71cdbe9 367 #define PCFCR_PCF_BUF0 (1 << 1)
Sergunb 0:8918a71cdbe9 368 #define PCFCR_PCF_EN (1 << 0)
Sergunb 0:8918a71cdbe9 369
Sergunb 0:8918a71cdbe9 370 //SD_CNFG register
Sergunb 0:8918a71cdbe9 371 #define SD_CNFG_SD_TIME (1 << 8)
Sergunb 0:8918a71cdbe9 372
Sergunb 0:8918a71cdbe9 373 //LEN100_DET register
Sergunb 0:8918a71cdbe9 374 #define LEN100_DET_CABLE_LEN7 (1 << 7)
Sergunb 0:8918a71cdbe9 375 #define LEN100_DET_CABLE_LEN6 (1 << 6)
Sergunb 0:8918a71cdbe9 376 #define LEN100_DET_CABLE_LEN5 (1 << 5)
Sergunb 0:8918a71cdbe9 377 #define LEN100_DET_CABLE_LEN4 (1 << 4)
Sergunb 0:8918a71cdbe9 378 #define LEN100_DET_CABLE_LEN3 (1 << 3)
Sergunb 0:8918a71cdbe9 379 #define LEN100_DET_CABLE_LEN2 (1 << 2)
Sergunb 0:8918a71cdbe9 380 #define LEN100_DET_CABLE_LEN1 (1 << 1)
Sergunb 0:8918a71cdbe9 381 #define LEN100_DET_CABLE_LEN0 (1 << 0)
Sergunb 0:8918a71cdbe9 382
Sergunb 0:8918a71cdbe9 383 //FREQ100 register
Sergunb 0:8918a71cdbe9 384 #define FREQ100_SAMPLE_FREQ (1 << 15)
Sergunb 0:8918a71cdbe9 385 #define FREQ100_SEL_FC (1 << 8)
Sergunb 0:8918a71cdbe9 386 #define FREQ100_FREQ_OFFSET7 (1 << 7)
Sergunb 0:8918a71cdbe9 387 #define FREQ100_FREQ_OFFSET6 (1 << 6)
Sergunb 0:8918a71cdbe9 388 #define FREQ100_FREQ_OFFSET5 (1 << 5)
Sergunb 0:8918a71cdbe9 389 #define FREQ100_FREQ_OFFSET4 (1 << 4)
Sergunb 0:8918a71cdbe9 390 #define FREQ100_FREQ_OFFSET3 (1 << 3)
Sergunb 0:8918a71cdbe9 391 #define FREQ100_FREQ_OFFSET2 (1 << 2)
Sergunb 0:8918a71cdbe9 392 #define FREQ100_FREQ_OFFSET1 (1 << 1)
Sergunb 0:8918a71cdbe9 393 #define FREQ100_FREQ_OFFSET0 (1 << 0)
Sergunb 0:8918a71cdbe9 394
Sergunb 0:8918a71cdbe9 395 //TDR_CTRL register
Sergunb 0:8918a71cdbe9 396 #define TDR_CTRL_TDR_ENABLE (1 << 15)
Sergunb 0:8918a71cdbe9 397 #define TDR_CTRL_TDR_100MB (1 << 14)
Sergunb 0:8918a71cdbe9 398 #define TDR_CTRL_TX_CHANNEL (1 << 13)
Sergunb 0:8918a71cdbe9 399 #define TDR_CTRL_RX_CHANNEL (1 << 12)
Sergunb 0:8918a71cdbe9 400 #define TDR_CTRL_SEND_TDR (1 << 11)
Sergunb 0:8918a71cdbe9 401 #define TDR_CTRL_TDR_WIDTH2 (1 << 10)
Sergunb 0:8918a71cdbe9 402 #define TDR_CTRL_TDR_WIDTH1 (1 << 9)
Sergunb 0:8918a71cdbe9 403 #define TDR_CTRL_TDR_WIDTH0 (1 << 8)
Sergunb 0:8918a71cdbe9 404 #define TDR_CTRL_TDR_MIN_MODE (1 << 7)
Sergunb 0:8918a71cdbe9 405 #define TDR_CTRL_RX_THRESHOLD5 (1 << 5)
Sergunb 0:8918a71cdbe9 406 #define TDR_CTRL_RX_THRESHOLD4 (1 << 4)
Sergunb 0:8918a71cdbe9 407 #define TDR_CTRL_RX_THRESHOLD3 (1 << 3)
Sergunb 0:8918a71cdbe9 408 #define TDR_CTRL_RX_THRESHOLD2 (1 << 2)
Sergunb 0:8918a71cdbe9 409 #define TDR_CTRL_RX_THRESHOLD1 (1 << 1)
Sergunb 0:8918a71cdbe9 410 #define TDR_CTRL_RX_THRESHOLD0 (1 << 0)
Sergunb 0:8918a71cdbe9 411
Sergunb 0:8918a71cdbe9 412 //TDR_WIN register
Sergunb 0:8918a71cdbe9 413 #define TDR_WIN_TDR_START7 (1 << 15)
Sergunb 0:8918a71cdbe9 414 #define TDR_WIN_TDR_START6 (1 << 14)
Sergunb 0:8918a71cdbe9 415 #define TDR_WIN_TDR_START5 (1 << 13)
Sergunb 0:8918a71cdbe9 416 #define TDR_WIN_TDR_START4 (1 << 12)
Sergunb 0:8918a71cdbe9 417 #define TDR_WIN_TDR_START3 (1 << 11)
Sergunb 0:8918a71cdbe9 418 #define TDR_WIN_TDR_START2 (1 << 10)
Sergunb 0:8918a71cdbe9 419 #define TDR_WIN_TDR_START1 (1 << 9)
Sergunb 0:8918a71cdbe9 420 #define TDR_WIN_TDR_START0 (1 << 8)
Sergunb 0:8918a71cdbe9 421 #define TDR_WIN_TDR_STOP7 (1 << 7)
Sergunb 0:8918a71cdbe9 422 #define TDR_WIN_TDR_STOP6 (1 << 6)
Sergunb 0:8918a71cdbe9 423 #define TDR_WIN_TDR_STOP5 (1 << 5)
Sergunb 0:8918a71cdbe9 424 #define TDR_WIN_TDR_STOP4 (1 << 4)
Sergunb 0:8918a71cdbe9 425 #define TDR_WIN_TDR_STOP3 (1 << 3)
Sergunb 0:8918a71cdbe9 426 #define TDR_WIN_TDR_STOP2 (1 << 2)
Sergunb 0:8918a71cdbe9 427 #define TDR_WIN_TDR_STOP1 (1 << 1)
Sergunb 0:8918a71cdbe9 428 #define TDR_WIN_TDR_STOP0 (1 << 0)
Sergunb 0:8918a71cdbe9 429
Sergunb 0:8918a71cdbe9 430 //TDR_PEAK register
Sergunb 0:8918a71cdbe9 431 #define TDR_PEAK_TDR_PEAK5 (1 << 13)
Sergunb 0:8918a71cdbe9 432 #define TDR_PEAK_TDR_PEAK4 (1 << 12)
Sergunb 0:8918a71cdbe9 433 #define TDR_PEAK_TDR_PEAK3 (1 << 11)
Sergunb 0:8918a71cdbe9 434 #define TDR_PEAK_TDR_PEAK2 (1 << 10)
Sergunb 0:8918a71cdbe9 435 #define TDR_PEAK_TDR_PEAK1 (1 << 9)
Sergunb 0:8918a71cdbe9 436 #define TDR_PEAK_TDR_PEAK0 (1 << 8)
Sergunb 0:8918a71cdbe9 437 #define TDR_PEAK_TDR_PEAK_TIME7 (1 << 7)
Sergunb 0:8918a71cdbe9 438 #define TDR_PEAK_TDR_PEAK_TIME6 (1 << 6)
Sergunb 0:8918a71cdbe9 439 #define TDR_PEAK_TDR_PEAK_TIME5 (1 << 5)
Sergunb 0:8918a71cdbe9 440 #define TDR_PEAK_TDR_PEAK_TIME4 (1 << 4)
Sergunb 0:8918a71cdbe9 441 #define TDR_PEAK_TDR_PEAK_TIME3 (1 << 3)
Sergunb 0:8918a71cdbe9 442 #define TDR_PEAK_TDR_PEAK_TIME2 (1 << 2)
Sergunb 0:8918a71cdbe9 443 #define TDR_PEAK_TDR_PEAK_TIME1 (1 << 1)
Sergunb 0:8918a71cdbe9 444 #define TDR_PEAK_TDR_PEAK_TIME0 (1 << 0)
Sergunb 0:8918a71cdbe9 445
Sergunb 0:8918a71cdbe9 446 //TDR_THR register
Sergunb 0:8918a71cdbe9 447 #define TDR_THR_TDR_THR_MET (1 << 8)
Sergunb 0:8918a71cdbe9 448 #define TDR_THR_TDR_THR_TIME7 (1 << 7)
Sergunb 0:8918a71cdbe9 449 #define TDR_THR_TDR_THR_TIME6 (1 << 6)
Sergunb 0:8918a71cdbe9 450 #define TDR_THR_TDR_THR_TIME5 (1 << 5)
Sergunb 0:8918a71cdbe9 451 #define TDR_THR_TDR_THR_TIME4 (1 << 4)
Sergunb 0:8918a71cdbe9 452 #define TDR_THR_TDR_THR_TIME3 (1 << 3)
Sergunb 0:8918a71cdbe9 453 #define TDR_THR_TDR_THR_TIME2 (1 << 2)
Sergunb 0:8918a71cdbe9 454 #define TDR_THR_TDR_THR_TIME1 (1 << 1)
Sergunb 0:8918a71cdbe9 455 #define TDR_THR_TDR_THR_TIME0 (1 << 0)
Sergunb 0:8918a71cdbe9 456
Sergunb 0:8918a71cdbe9 457 //VAR_CTRL register
Sergunb 0:8918a71cdbe9 458 #define VAR_CTRL_VAR_RDY (1 << 15)
Sergunb 0:8918a71cdbe9 459 #define VAR_CTRL_VAR_FREEZE (1 << 3)
Sergunb 0:8918a71cdbe9 460 #define VAR_CTRL_VAR_TIMER1 (1 << 2)
Sergunb 0:8918a71cdbe9 461 #define VAR_CTRL_VAR_TIMER0 (1 << 1)
Sergunb 0:8918a71cdbe9 462 #define VAR_CTRL_VAR_ENABLE (1 << 0)
Sergunb 0:8918a71cdbe9 463
Sergunb 0:8918a71cdbe9 464 //LQMR register
Sergunb 0:8918a71cdbe9 465 #define LQMR_LQM_ENABLE (1 << 15)
Sergunb 0:8918a71cdbe9 466 #define LQMR_RESTART_ON_FC (1 << 14)
Sergunb 0:8918a71cdbe9 467 #define LQMR_RESTART_ON_FREQ (1 << 13)
Sergunb 0:8918a71cdbe9 468 #define LQMR_RESTART_ON_DBLW (1 << 12)
Sergunb 0:8918a71cdbe9 469 #define LQMR_RESTART_ON_DAGC (1 << 11)
Sergunb 0:8918a71cdbe9 470 #define LQMR_RESTART_ON_C1 (1 << 10)
Sergunb 0:8918a71cdbe9 471 #define LQMR_FC_HI_WARN (1 << 9)
Sergunb 0:8918a71cdbe9 472 #define LQMR_FC_LO_WARN (1 << 8)
Sergunb 0:8918a71cdbe9 473 #define LQMR_FREQ_HI_WARN (1 << 7)
Sergunb 0:8918a71cdbe9 474 #define LQMR_FREQ_LO_WARN (1 << 6)
Sergunb 0:8918a71cdbe9 475 #define LQMR_DBLW_HI_WARN (1 << 5)
Sergunb 0:8918a71cdbe9 476 #define LQMR_DBLW_LO_WARN (1 << 4)
Sergunb 0:8918a71cdbe9 477 #define LQMR_DAGC_HI_WARN (1 << 3)
Sergunb 0:8918a71cdbe9 478 #define LQMR_DAGC_LO_WARN (1 << 2)
Sergunb 0:8918a71cdbe9 479 #define LQMR_C1_HI_WARN (1 << 1)
Sergunb 0:8918a71cdbe9 480 #define LQMR_C1_LO_WARN (1 << 0)
Sergunb 0:8918a71cdbe9 481
Sergunb 0:8918a71cdbe9 482 //LQDR register
Sergunb 0:8918a71cdbe9 483 #define LQDR_SAMPLE_PARAM (1 << 13)
Sergunb 0:8918a71cdbe9 484 #define LQDR_WRITE_LQ_THR (1 << 12)
Sergunb 0:8918a71cdbe9 485 #define LQDR_LQ_PARAM_SEL2 (1 << 11)
Sergunb 0:8918a71cdbe9 486 #define LQDR_LQ_PARAM_SEL1 (1 << 10)
Sergunb 0:8918a71cdbe9 487 #define LQDR_LQ_PARAM_SEL0 (1 << 9)
Sergunb 0:8918a71cdbe9 488 #define LQDR_LQ_THR_SEL (1 << 8)
Sergunb 0:8918a71cdbe9 489 #define LQDR_LQ_THR_DATA7 (1 << 7)
Sergunb 0:8918a71cdbe9 490 #define LQDR_LQ_THR_DATA6 (1 << 6)
Sergunb 0:8918a71cdbe9 491 #define LQDR_LQ_THR_DATA5 (1 << 5)
Sergunb 0:8918a71cdbe9 492 #define LQDR_LQ_THR_DATA4 (1 << 4)
Sergunb 0:8918a71cdbe9 493 #define LQDR_LQ_THR_DATA3 (1 << 3)
Sergunb 0:8918a71cdbe9 494 #define LQDR_LQ_THR_DATA2 (1 << 2)
Sergunb 0:8918a71cdbe9 495 #define LQDR_LQ_THR_DATA1 (1 << 1)
Sergunb 0:8918a71cdbe9 496 #define LQDR_LQ_THR_DATA0 (1 << 0)
Sergunb 0:8918a71cdbe9 497
Sergunb 0:8918a71cdbe9 498 //LQMR2 register
Sergunb 0:8918a71cdbe9 499 #define LQMR2_RESTART_ON_VAR (1 << 10)
Sergunb 0:8918a71cdbe9 500 #define LQMR2_VAR_HI_WARN (1 << 1)
Sergunb 0:8918a71cdbe9 501
Sergunb 0:8918a71cdbe9 502 //PSF_CFG register
Sergunb 0:8918a71cdbe9 503 #define PSF_CFG_MAC_SRC_ADD1 (1 << 12)
Sergunb 0:8918a71cdbe9 504 #define PSF_CFG_MAC_SRC_ADD0 (1 << 11)
Sergunb 0:8918a71cdbe9 505 #define PSF_CFG_MIN_PRE2 (1 << 10)
Sergunb 0:8918a71cdbe9 506 #define PSF_CFG_MIN_PRE1 (1 << 9)
Sergunb 0:8918a71cdbe9 507 #define PSF_CFG_MIN_PRE0 (1 << 8)
Sergunb 0:8918a71cdbe9 508 #define PSF_CFG_PSF_ENDIAN (1 << 7)
Sergunb 0:8918a71cdbe9 509 #define PSF_CFG_PSF_IPV4 (1 << 6)
Sergunb 0:8918a71cdbe9 510 #define PSF_CFG_PSF_PCF_RD (1 << 5)
Sergunb 0:8918a71cdbe9 511 #define PSF_CFG_PSF_ERR_EN (1 << 4)
Sergunb 0:8918a71cdbe9 512
Sergunb 0:8918a71cdbe9 513 //DP83620 Ethernet PHY driver
Sergunb 0:8918a71cdbe9 514 extern const PhyDriver dp83620PhyDriver;
Sergunb 0:8918a71cdbe9 515
Sergunb 0:8918a71cdbe9 516 //DP83620 related functions
Sergunb 0:8918a71cdbe9 517 error_t dp83620Init(NetInterface *interface);
Sergunb 0:8918a71cdbe9 518
Sergunb 0:8918a71cdbe9 519 void dp83620Tick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 520
Sergunb 0:8918a71cdbe9 521 void dp83620EnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 522 void dp83620DisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 523
Sergunb 0:8918a71cdbe9 524 void dp83620EventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 525
Sergunb 0:8918a71cdbe9 526 void dp83620WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
Sergunb 0:8918a71cdbe9 527 uint16_t dp83620ReadPhyReg(NetInterface *interface, uint8_t address);
Sergunb 0:8918a71cdbe9 528
Sergunb 0:8918a71cdbe9 529 void dp83620DumpPhyReg(NetInterface *interface);
Sergunb 0:8918a71cdbe9 530
Sergunb 0:8918a71cdbe9 531 #endif
Sergunb 0:8918a71cdbe9 532