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cyclone_tcp/drivers/a2fxxxm3_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file a2fxxxm3_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief SmartFusion (A2FxxxM3) Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "a2fxxxm3.h"
Sergunb 0:8918a71cdbe9 34 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_regs.h"
Sergunb 0:8918a71cdbe9 35 #include "drivers/mss_ethernet_mac/mss_ethernet_mac_desc.h"
Sergunb 0:8918a71cdbe9 36 #include "core/net.h"
Sergunb 0:8918a71cdbe9 37 #include "drivers/a2fxxxm3_eth.h"
Sergunb 0:8918a71cdbe9 38 #include "debug.h"
Sergunb 0:8918a71cdbe9 39
Sergunb 0:8918a71cdbe9 40 //Underlying network interface
Sergunb 0:8918a71cdbe9 41 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 42
Sergunb 0:8918a71cdbe9 43 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 44 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 45
Sergunb 0:8918a71cdbe9 46 //Transmit buffer
Sergunb 0:8918a71cdbe9 47 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 48 static uint8_t txBuffer[A2FXXXM3_ETH_TX_BUFFER_COUNT][A2FXXXM3_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 49 //Receive buffer
Sergunb 0:8918a71cdbe9 50 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 51 static uint8_t rxBuffer[A2FXXXM3_ETH_RX_BUFFER_COUNT][A2FXXXM3_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 52 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 53 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 54 static A2fxxxm3TxDmaDesc txDmaDesc[A2FXXXM3_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 55 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 56 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 57 static A2fxxxm3RxDmaDesc rxDmaDesc[A2FXXXM3_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 58
Sergunb 0:8918a71cdbe9 59 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 60 #else
Sergunb 0:8918a71cdbe9 61
Sergunb 0:8918a71cdbe9 62 //Transmit buffer
Sergunb 0:8918a71cdbe9 63 static uint8_t txBuffer[A2FXXXM3_ETH_TX_BUFFER_COUNT][A2FXXXM3_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 64 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 65 //Receive buffer
Sergunb 0:8918a71cdbe9 66 static uint8_t rxBuffer[A2FXXXM3_ETH_RX_BUFFER_COUNT][A2FXXXM3_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 67 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 68 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 69 static A2fxxxm3TxDmaDesc txDmaDesc[A2FXXXM3_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 70 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 71 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 72 static A2fxxxm3RxDmaDesc rxDmaDesc[A2FXXXM3_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 73 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 74
Sergunb 0:8918a71cdbe9 75 #endif
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //Pointer to the current TX DMA descriptor
Sergunb 0:8918a71cdbe9 78 static A2fxxxm3TxDmaDesc *txCurDmaDesc;
Sergunb 0:8918a71cdbe9 79 //Pointer to the current RX DMA descriptor
Sergunb 0:8918a71cdbe9 80 static A2fxxxm3RxDmaDesc *rxCurDmaDesc;
Sergunb 0:8918a71cdbe9 81
Sergunb 0:8918a71cdbe9 82
Sergunb 0:8918a71cdbe9 83 /**
Sergunb 0:8918a71cdbe9 84 * @brief A2FxxxM3 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 85 **/
Sergunb 0:8918a71cdbe9 86
Sergunb 0:8918a71cdbe9 87 const NicDriver a2fxxxm3EthDriver =
Sergunb 0:8918a71cdbe9 88 {
Sergunb 0:8918a71cdbe9 89 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 90 ETH_MTU,
Sergunb 0:8918a71cdbe9 91 a2fxxxm3EthInit,
Sergunb 0:8918a71cdbe9 92 a2fxxxm3EthTick,
Sergunb 0:8918a71cdbe9 93 a2fxxxm3EthEnableIrq,
Sergunb 0:8918a71cdbe9 94 a2fxxxm3EthDisableIrq,
Sergunb 0:8918a71cdbe9 95 a2fxxxm3EthEventHandler,
Sergunb 0:8918a71cdbe9 96 a2fxxxm3EthSendPacket,
Sergunb 0:8918a71cdbe9 97 a2fxxxm3EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 98 a2fxxxm3EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 99 a2fxxxm3EthWritePhyReg,
Sergunb 0:8918a71cdbe9 100 a2fxxxm3EthReadPhyReg,
Sergunb 0:8918a71cdbe9 101 TRUE,
Sergunb 0:8918a71cdbe9 102 TRUE,
Sergunb 0:8918a71cdbe9 103 TRUE,
Sergunb 0:8918a71cdbe9 104 FALSE
Sergunb 0:8918a71cdbe9 105 };
Sergunb 0:8918a71cdbe9 106
Sergunb 0:8918a71cdbe9 107
Sergunb 0:8918a71cdbe9 108 /**
Sergunb 0:8918a71cdbe9 109 * @brief A2FxxxM3 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 110 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 111 * @return Error code
Sergunb 0:8918a71cdbe9 112 **/
Sergunb 0:8918a71cdbe9 113
Sergunb 0:8918a71cdbe9 114 error_t a2fxxxm3EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 115 {
Sergunb 0:8918a71cdbe9 116 error_t error;
Sergunb 0:8918a71cdbe9 117
Sergunb 0:8918a71cdbe9 118 //Debug message
Sergunb 0:8918a71cdbe9 119 TRACE_INFO("Initializing A2FxxxM3 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 120
Sergunb 0:8918a71cdbe9 121 //Save underlying network interface
Sergunb 0:8918a71cdbe9 122 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 123
Sergunb 0:8918a71cdbe9 124 //Perform a software reset
Sergunb 0:8918a71cdbe9 125 MAC->CSR0 |= CSR0_SWR_MASK;
Sergunb 0:8918a71cdbe9 126 //Wait for the reset to complete
Sergunb 0:8918a71cdbe9 127 while(MAC->CSR0 & CSR0_SWR_MASK);
Sergunb 0:8918a71cdbe9 128
Sergunb 0:8918a71cdbe9 129 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 130 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 131 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 132 if(error)
Sergunb 0:8918a71cdbe9 133 return error;
Sergunb 0:8918a71cdbe9 134
Sergunb 0:8918a71cdbe9 135 //Enable store and forward mode
Sergunb 0:8918a71cdbe9 136 MAC->CSR6 |= CSR6_SF_MASK;
Sergunb 0:8918a71cdbe9 137
Sergunb 0:8918a71cdbe9 138 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 139 a2fxxxm3EthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 140
Sergunb 0:8918a71cdbe9 141 //Enable the desired Ethernet interrupts
Sergunb 0:8918a71cdbe9 142 MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
Sergunb 0:8918a71cdbe9 143
Sergunb 0:8918a71cdbe9 144 //Set priority grouping (5 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 145 NVIC_SetPriorityGrouping(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 146
Sergunb 0:8918a71cdbe9 147 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 148 NVIC_SetPriority(EthernetMAC_IRQn, NVIC_EncodePriority(A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING,
Sergunb 0:8918a71cdbe9 149 A2FXXXM3_ETH_IRQ_GROUP_PRIORITY, A2FXXXM3_ETH_IRQ_SUB_PRIORITY));
Sergunb 0:8918a71cdbe9 150
Sergunb 0:8918a71cdbe9 151 //Enable transmission and reception
Sergunb 0:8918a71cdbe9 152 MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
Sergunb 0:8918a71cdbe9 153
Sergunb 0:8918a71cdbe9 154 //Set MAC address
Sergunb 0:8918a71cdbe9 155 error = a2fxxxm3EthSendSetup(interface);
Sergunb 0:8918a71cdbe9 156 //Any error to report?
Sergunb 0:8918a71cdbe9 157 if(error)
Sergunb 0:8918a71cdbe9 158 return error;
Sergunb 0:8918a71cdbe9 159
Sergunb 0:8918a71cdbe9 160 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 161 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 162
Sergunb 0:8918a71cdbe9 163 //Successful initialization
Sergunb 0:8918a71cdbe9 164 return NO_ERROR;
Sergunb 0:8918a71cdbe9 165 }
Sergunb 0:8918a71cdbe9 166
Sergunb 0:8918a71cdbe9 167
Sergunb 0:8918a71cdbe9 168 /**
Sergunb 0:8918a71cdbe9 169 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 170 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 171 **/
Sergunb 0:8918a71cdbe9 172
Sergunb 0:8918a71cdbe9 173 void a2fxxxm3EthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 174 {
Sergunb 0:8918a71cdbe9 175 uint_t i;
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 178 for(i = 0; i < A2FXXXM3_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 179 {
Sergunb 0:8918a71cdbe9 180 //The descriptor is initially owned by the user
Sergunb 0:8918a71cdbe9 181 txDmaDesc[i].tdes0 = 0;
Sergunb 0:8918a71cdbe9 182 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 183 txDmaDesc[i].tdes1 = TDES1_TCH;
Sergunb 0:8918a71cdbe9 184 //Transmit buffer address
Sergunb 0:8918a71cdbe9 185 txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 186 //Next descriptor address
Sergunb 0:8918a71cdbe9 187 txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 188 }
Sergunb 0:8918a71cdbe9 189
Sergunb 0:8918a71cdbe9 190 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 191 txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 192 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 193 txCurDmaDesc = &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 194
Sergunb 0:8918a71cdbe9 195 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 196 for(i = 0; i < A2FXXXM3_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 197 {
Sergunb 0:8918a71cdbe9 198 //The descriptor is initially owned by the DMA
Sergunb 0:8918a71cdbe9 199 rxDmaDesc[i].rdes0 = RDES0_OWN;
Sergunb 0:8918a71cdbe9 200 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 201 rxDmaDesc[i].rdes1 = RDES1_RCH | (A2FXXXM3_ETH_RX_BUFFER_SIZE & RDES1_RBS1_MASK);
Sergunb 0:8918a71cdbe9 202 //Receive buffer address
Sergunb 0:8918a71cdbe9 203 rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 204 //Next descriptor address
Sergunb 0:8918a71cdbe9 205 rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 206 }
Sergunb 0:8918a71cdbe9 207
Sergunb 0:8918a71cdbe9 208 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 209 rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 210 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 211 rxCurDmaDesc = &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 212
Sergunb 0:8918a71cdbe9 213 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 214 MAC->CSR4 = (uint32_t) txDmaDesc;
Sergunb 0:8918a71cdbe9 215 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 216 MAC->CSR3 = (uint32_t) rxDmaDesc;
Sergunb 0:8918a71cdbe9 217 }
Sergunb 0:8918a71cdbe9 218
Sergunb 0:8918a71cdbe9 219
Sergunb 0:8918a71cdbe9 220 /**
Sergunb 0:8918a71cdbe9 221 * @brief A2FxxxM3 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 222 *
Sergunb 0:8918a71cdbe9 223 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 224 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 225 *
Sergunb 0:8918a71cdbe9 226 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 227 **/
Sergunb 0:8918a71cdbe9 228
Sergunb 0:8918a71cdbe9 229 void a2fxxxm3EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 230 {
Sergunb 0:8918a71cdbe9 231 //Handle periodic operations
Sergunb 0:8918a71cdbe9 232 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 233 }
Sergunb 0:8918a71cdbe9 234
Sergunb 0:8918a71cdbe9 235
Sergunb 0:8918a71cdbe9 236 /**
Sergunb 0:8918a71cdbe9 237 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 238 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 239 **/
Sergunb 0:8918a71cdbe9 240
Sergunb 0:8918a71cdbe9 241 void a2fxxxm3EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 242 {
Sergunb 0:8918a71cdbe9 243 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 244 NVIC_EnableIRQ(EthernetMAC_IRQn);
Sergunb 0:8918a71cdbe9 245 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 246 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 247 }
Sergunb 0:8918a71cdbe9 248
Sergunb 0:8918a71cdbe9 249
Sergunb 0:8918a71cdbe9 250 /**
Sergunb 0:8918a71cdbe9 251 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 252 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 253 **/
Sergunb 0:8918a71cdbe9 254
Sergunb 0:8918a71cdbe9 255 void a2fxxxm3EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 256 {
Sergunb 0:8918a71cdbe9 257 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 258 NVIC_DisableIRQ(EthernetMAC_IRQn);
Sergunb 0:8918a71cdbe9 259 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 260 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 261 }
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263
Sergunb 0:8918a71cdbe9 264 /**
Sergunb 0:8918a71cdbe9 265 * @brief A2FxxxM3 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 266 **/
Sergunb 0:8918a71cdbe9 267
Sergunb 0:8918a71cdbe9 268 void EthernetMAC_IRQHandler(void)
Sergunb 0:8918a71cdbe9 269 {
Sergunb 0:8918a71cdbe9 270 bool_t flag;
Sergunb 0:8918a71cdbe9 271 uint32_t status;
Sergunb 0:8918a71cdbe9 272
Sergunb 0:8918a71cdbe9 273 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 274 osEnterIsr();
Sergunb 0:8918a71cdbe9 275
Sergunb 0:8918a71cdbe9 276 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 277 flag = FALSE;
Sergunb 0:8918a71cdbe9 278
Sergunb 0:8918a71cdbe9 279 //Read interrupt status register
Sergunb 0:8918a71cdbe9 280 status = MAC->CSR5;
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 283 if(status & CSR5_TI_MASK)
Sergunb 0:8918a71cdbe9 284 {
Sergunb 0:8918a71cdbe9 285 //Clear TI interrupt flag
Sergunb 0:8918a71cdbe9 286 MAC->CSR5 = CSR5_TI_MASK;
Sergunb 0:8918a71cdbe9 287
Sergunb 0:8918a71cdbe9 288 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 289 if(!(txCurDmaDesc->tdes0 & TDES0_OWN))
Sergunb 0:8918a71cdbe9 290 {
Sergunb 0:8918a71cdbe9 291 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 292 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 293 }
Sergunb 0:8918a71cdbe9 294 }
Sergunb 0:8918a71cdbe9 295
Sergunb 0:8918a71cdbe9 296 //A packet has been received?
Sergunb 0:8918a71cdbe9 297 if(status & CSR5_RI_MASK)
Sergunb 0:8918a71cdbe9 298 {
Sergunb 0:8918a71cdbe9 299 //Disable RIE interrupt
Sergunb 0:8918a71cdbe9 300 MAC->CSR7 &= ~CSR7_RIE_MASK;
Sergunb 0:8918a71cdbe9 301
Sergunb 0:8918a71cdbe9 302 //Set event flag
Sergunb 0:8918a71cdbe9 303 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 304 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 305 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 306 }
Sergunb 0:8918a71cdbe9 307
Sergunb 0:8918a71cdbe9 308 //Clear NIS interrupt flag
Sergunb 0:8918a71cdbe9 309 MAC->CSR5 = CSR5_NIS_MASK;
Sergunb 0:8918a71cdbe9 310
Sergunb 0:8918a71cdbe9 311 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 312 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 313 }
Sergunb 0:8918a71cdbe9 314
Sergunb 0:8918a71cdbe9 315
Sergunb 0:8918a71cdbe9 316 /**
Sergunb 0:8918a71cdbe9 317 * @brief A2FxxxM3 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 318 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 319 **/
Sergunb 0:8918a71cdbe9 320
Sergunb 0:8918a71cdbe9 321 void a2fxxxm3EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 322 {
Sergunb 0:8918a71cdbe9 323 error_t error;
Sergunb 0:8918a71cdbe9 324
Sergunb 0:8918a71cdbe9 325 //Packet received?
Sergunb 0:8918a71cdbe9 326 if(MAC->CSR5 & CSR5_RI_MASK)
Sergunb 0:8918a71cdbe9 327 {
Sergunb 0:8918a71cdbe9 328 //Clear interrupt flag
Sergunb 0:8918a71cdbe9 329 MAC->CSR5 = CSR5_RI_MASK;
Sergunb 0:8918a71cdbe9 330
Sergunb 0:8918a71cdbe9 331 //Process all pending packets
Sergunb 0:8918a71cdbe9 332 do
Sergunb 0:8918a71cdbe9 333 {
Sergunb 0:8918a71cdbe9 334 //Read incoming packet
Sergunb 0:8918a71cdbe9 335 error = a2fxxxm3EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 336
Sergunb 0:8918a71cdbe9 337 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 338 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 339 }
Sergunb 0:8918a71cdbe9 340
Sergunb 0:8918a71cdbe9 341 //Re-enable Ethernet interrupts
Sergunb 0:8918a71cdbe9 342 MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK;
Sergunb 0:8918a71cdbe9 343 }
Sergunb 0:8918a71cdbe9 344
Sergunb 0:8918a71cdbe9 345
Sergunb 0:8918a71cdbe9 346 /**
Sergunb 0:8918a71cdbe9 347 * @brief Send a setup frame
Sergunb 0:8918a71cdbe9 348 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 349 * @return Error code
Sergunb 0:8918a71cdbe9 350 **/
Sergunb 0:8918a71cdbe9 351
Sergunb 0:8918a71cdbe9 352 error_t a2fxxxm3EthSendSetup(NetInterface *interface)
Sergunb 0:8918a71cdbe9 353 {
Sergunb 0:8918a71cdbe9 354 A2fxxxm3HashTableSetupFrame *setupFrame;
Sergunb 0:8918a71cdbe9 355
Sergunb 0:8918a71cdbe9 356 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 357 if(txCurDmaDesc->tdes0 & TDES0_OWN)
Sergunb 0:8918a71cdbe9 358 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 359
Sergunb 0:8918a71cdbe9 360 //Point to the buffer where to format the setup frame
Sergunb 0:8918a71cdbe9 361 setupFrame = (A2fxxxm3HashTableSetupFrame *) txCurDmaDesc->tdes2;
Sergunb 0:8918a71cdbe9 362
Sergunb 0:8918a71cdbe9 363 //Clear contents
Sergunb 0:8918a71cdbe9 364 memset(setupFrame, 0, sizeof(A2fxxxm3HashTableSetupFrame));
Sergunb 0:8918a71cdbe9 365
Sergunb 0:8918a71cdbe9 366 //Set MAC address
Sergunb 0:8918a71cdbe9 367 setupFrame->physicalAddr[0] = interface->macAddr.w[0];
Sergunb 0:8918a71cdbe9 368 setupFrame->physicalAddr[1] = interface->macAddr.w[1];
Sergunb 0:8918a71cdbe9 369 setupFrame->physicalAddr[2] = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 370
Sergunb 0:8918a71cdbe9 371 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 372 txCurDmaDesc->tdes1 = sizeof(A2fxxxm3HashTableSetupFrame) & TDES1_TBS1_MASK;
Sergunb 0:8918a71cdbe9 373 //The SET flag indicates that this is a setup frame descriptor
Sergunb 0:8918a71cdbe9 374 txCurDmaDesc->tdes1 |= TDES1_SET | TDES1_TCH | TDES1_FT0;
Sergunb 0:8918a71cdbe9 375 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 376 txCurDmaDesc->tdes0 |= TDES0_OWN;
Sergunb 0:8918a71cdbe9 377
Sergunb 0:8918a71cdbe9 378 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 379 MAC->CSR1 = 1;
Sergunb 0:8918a71cdbe9 380
Sergunb 0:8918a71cdbe9 381 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 382 txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
Sergunb 0:8918a71cdbe9 383
Sergunb 0:8918a71cdbe9 384 //Data successfully written
Sergunb 0:8918a71cdbe9 385 return NO_ERROR;
Sergunb 0:8918a71cdbe9 386 }
Sergunb 0:8918a71cdbe9 387
Sergunb 0:8918a71cdbe9 388
Sergunb 0:8918a71cdbe9 389 /**
Sergunb 0:8918a71cdbe9 390 * @brief Send a packet
Sergunb 0:8918a71cdbe9 391 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 392 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 393 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 394 * @return Error code
Sergunb 0:8918a71cdbe9 395 **/
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397 error_t a2fxxxm3EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 398 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 399 {
Sergunb 0:8918a71cdbe9 400 size_t length;
Sergunb 0:8918a71cdbe9 401
Sergunb 0:8918a71cdbe9 402 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 403 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 404
Sergunb 0:8918a71cdbe9 405 //Check the frame length
Sergunb 0:8918a71cdbe9 406 if(length > A2FXXXM3_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 407 {
Sergunb 0:8918a71cdbe9 408 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 409 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 410 //Report an error
Sergunb 0:8918a71cdbe9 411 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 412 }
Sergunb 0:8918a71cdbe9 413
Sergunb 0:8918a71cdbe9 414 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 415 if(txCurDmaDesc->tdes0 & TDES0_OWN)
Sergunb 0:8918a71cdbe9 416 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 417
Sergunb 0:8918a71cdbe9 418 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 419 netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
Sergunb 0:8918a71cdbe9 420
Sergunb 0:8918a71cdbe9 421 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 422 txCurDmaDesc->tdes1 = length & TDES1_TBS1_MASK;
Sergunb 0:8918a71cdbe9 423 //Set LS and FS flags as the data fits in a single buffer
Sergunb 0:8918a71cdbe9 424 txCurDmaDesc->tdes1 |= TDES1_IC | TDES1_LS | TDES1_FS | TDES1_TCH;
Sergunb 0:8918a71cdbe9 425 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 426 txCurDmaDesc->tdes0 |= TDES0_OWN;
Sergunb 0:8918a71cdbe9 427
Sergunb 0:8918a71cdbe9 428 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 429 MAC->CSR1 = 1;
Sergunb 0:8918a71cdbe9 430
Sergunb 0:8918a71cdbe9 431 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 432 txCurDmaDesc = (A2fxxxm3TxDmaDesc *) txCurDmaDesc->tdes3;
Sergunb 0:8918a71cdbe9 433
Sergunb 0:8918a71cdbe9 434 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 435 if(!(txCurDmaDesc->tdes0 & TDES0_OWN))
Sergunb 0:8918a71cdbe9 436 {
Sergunb 0:8918a71cdbe9 437 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 438 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 439 }
Sergunb 0:8918a71cdbe9 440
Sergunb 0:8918a71cdbe9 441 //Data successfully written
Sergunb 0:8918a71cdbe9 442 return NO_ERROR;
Sergunb 0:8918a71cdbe9 443 }
Sergunb 0:8918a71cdbe9 444
Sergunb 0:8918a71cdbe9 445
Sergunb 0:8918a71cdbe9 446 /**
Sergunb 0:8918a71cdbe9 447 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 448 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 449 * @return Error code
Sergunb 0:8918a71cdbe9 450 **/
Sergunb 0:8918a71cdbe9 451
Sergunb 0:8918a71cdbe9 452 error_t a2fxxxm3EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 453 {
Sergunb 0:8918a71cdbe9 454 error_t error;
Sergunb 0:8918a71cdbe9 455 size_t n;
Sergunb 0:8918a71cdbe9 456
Sergunb 0:8918a71cdbe9 457 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 458 if(!(rxCurDmaDesc->rdes0 & RDES0_OWN))
Sergunb 0:8918a71cdbe9 459 {
Sergunb 0:8918a71cdbe9 460 //FS and LS flags should be set
Sergunb 0:8918a71cdbe9 461 if((rxCurDmaDesc->rdes0 & RDES0_FS) && (rxCurDmaDesc->rdes0 & RDES0_LS))
Sergunb 0:8918a71cdbe9 462 {
Sergunb 0:8918a71cdbe9 463 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 464 if(!(rxCurDmaDesc->rdes0 & RDES0_ES))
Sergunb 0:8918a71cdbe9 465 {
Sergunb 0:8918a71cdbe9 466 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 467 n = (rxCurDmaDesc->rdes0 >> RDES0_FL_OFFSET) & RDES0_FL_MASK;
Sergunb 0:8918a71cdbe9 468 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 469 n = MIN(n, A2FXXXM3_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 470
Sergunb 0:8918a71cdbe9 471 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 472 nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
Sergunb 0:8918a71cdbe9 473
Sergunb 0:8918a71cdbe9 474 //Valid packet received
Sergunb 0:8918a71cdbe9 475 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 476 }
Sergunb 0:8918a71cdbe9 477 else
Sergunb 0:8918a71cdbe9 478 {
Sergunb 0:8918a71cdbe9 479 //The received packet contains an error
Sergunb 0:8918a71cdbe9 480 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 481 }
Sergunb 0:8918a71cdbe9 482 }
Sergunb 0:8918a71cdbe9 483 else
Sergunb 0:8918a71cdbe9 484 {
Sergunb 0:8918a71cdbe9 485 //The packet is not valid
Sergunb 0:8918a71cdbe9 486 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 487 }
Sergunb 0:8918a71cdbe9 488
Sergunb 0:8918a71cdbe9 489 //Give the ownership of the descriptor back to the DMA
Sergunb 0:8918a71cdbe9 490 rxCurDmaDesc->rdes0 = RDES0_OWN;
Sergunb 0:8918a71cdbe9 491 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 492 rxCurDmaDesc = (A2fxxxm3RxDmaDesc *) rxCurDmaDesc->rdes3;
Sergunb 0:8918a71cdbe9 493 }
Sergunb 0:8918a71cdbe9 494 else
Sergunb 0:8918a71cdbe9 495 {
Sergunb 0:8918a71cdbe9 496 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 497 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 498 }
Sergunb 0:8918a71cdbe9 499
Sergunb 0:8918a71cdbe9 500 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 501 MAC->CSR2 = 1;
Sergunb 0:8918a71cdbe9 502
Sergunb 0:8918a71cdbe9 503 //Return status code
Sergunb 0:8918a71cdbe9 504 return error;
Sergunb 0:8918a71cdbe9 505 }
Sergunb 0:8918a71cdbe9 506
Sergunb 0:8918a71cdbe9 507
Sergunb 0:8918a71cdbe9 508 /**
Sergunb 0:8918a71cdbe9 509 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 510 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 511 * @return Error code
Sergunb 0:8918a71cdbe9 512 **/
Sergunb 0:8918a71cdbe9 513
Sergunb 0:8918a71cdbe9 514 error_t a2fxxxm3EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 515 {
Sergunb 0:8918a71cdbe9 516 uint_t i;
Sergunb 0:8918a71cdbe9 517 bool_t acceptMulticast;
Sergunb 0:8918a71cdbe9 518
Sergunb 0:8918a71cdbe9 519 //This flag will be set if multicast addresses should be accepted
Sergunb 0:8918a71cdbe9 520 acceptMulticast = FALSE;
Sergunb 0:8918a71cdbe9 521
Sergunb 0:8918a71cdbe9 522 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 523 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 524 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 525 {
Sergunb 0:8918a71cdbe9 526 //Valid entry?
Sergunb 0:8918a71cdbe9 527 if(interface->macMulticastFilter[i].refCount > 0)
Sergunb 0:8918a71cdbe9 528 {
Sergunb 0:8918a71cdbe9 529 //Accept multicast addresses
Sergunb 0:8918a71cdbe9 530 acceptMulticast = TRUE;
Sergunb 0:8918a71cdbe9 531 //We are done
Sergunb 0:8918a71cdbe9 532 break;
Sergunb 0:8918a71cdbe9 533 }
Sergunb 0:8918a71cdbe9 534 }
Sergunb 0:8918a71cdbe9 535
Sergunb 0:8918a71cdbe9 536 //Enable the reception of multicast frames if necessary
Sergunb 0:8918a71cdbe9 537 if(acceptMulticast)
Sergunb 0:8918a71cdbe9 538 MAC->CSR6 |= CSR6_PM_MASK;
Sergunb 0:8918a71cdbe9 539 else
Sergunb 0:8918a71cdbe9 540 MAC->CSR6 &= ~CSR6_PM_MASK;
Sergunb 0:8918a71cdbe9 541
Sergunb 0:8918a71cdbe9 542 //Successful processing
Sergunb 0:8918a71cdbe9 543 return NO_ERROR;
Sergunb 0:8918a71cdbe9 544 }
Sergunb 0:8918a71cdbe9 545
Sergunb 0:8918a71cdbe9 546
Sergunb 0:8918a71cdbe9 547 /**
Sergunb 0:8918a71cdbe9 548 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 549 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 550 * @return Error code
Sergunb 0:8918a71cdbe9 551 **/
Sergunb 0:8918a71cdbe9 552
Sergunb 0:8918a71cdbe9 553 error_t a2fxxxm3EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 554 {
Sergunb 0:8918a71cdbe9 555 //Stop transmission
Sergunb 0:8918a71cdbe9 556 while(((MAC->CSR5 & CSR5_TS_MASK) >> CSR5_TS_SHIFT) != CSR5_TS_STOPPED)
Sergunb 0:8918a71cdbe9 557 MAC->CSR6 &= ~CSR6_ST_MASK;
Sergunb 0:8918a71cdbe9 558
Sergunb 0:8918a71cdbe9 559 //Stop reception
Sergunb 0:8918a71cdbe9 560 while(((MAC->CSR5 & CSR5_RS_MASK) >> CSR5_RS_SHIFT) != CSR5_RS_STOPPED)
Sergunb 0:8918a71cdbe9 561 MAC->CSR6 &= ~CSR6_SR_MASK;
Sergunb 0:8918a71cdbe9 562
Sergunb 0:8918a71cdbe9 563 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 564 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 565 MAC->CSR6 |= CSR6_TTM_MASK;
Sergunb 0:8918a71cdbe9 566 else
Sergunb 0:8918a71cdbe9 567 MAC->CSR6 &= ~CSR6_TTM_MASK;
Sergunb 0:8918a71cdbe9 568
Sergunb 0:8918a71cdbe9 569 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 570 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 571 MAC->CSR6 |= CSR6_FD_MASK;
Sergunb 0:8918a71cdbe9 572 else
Sergunb 0:8918a71cdbe9 573 MAC->CSR6 &= ~CSR6_FD_MASK;
Sergunb 0:8918a71cdbe9 574
Sergunb 0:8918a71cdbe9 575 //Restart transmission and reception
Sergunb 0:8918a71cdbe9 576 MAC->CSR6 |= CSR6_ST_MASK | CSR6_SR_MASK;
Sergunb 0:8918a71cdbe9 577
Sergunb 0:8918a71cdbe9 578 //Successful processing
Sergunb 0:8918a71cdbe9 579 return NO_ERROR;
Sergunb 0:8918a71cdbe9 580 }
Sergunb 0:8918a71cdbe9 581
Sergunb 0:8918a71cdbe9 582
Sergunb 0:8918a71cdbe9 583 /**
Sergunb 0:8918a71cdbe9 584 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 585 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 586 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 587 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 588 **/
Sergunb 0:8918a71cdbe9 589
Sergunb 0:8918a71cdbe9 590 void a2fxxxm3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 591 {
Sergunb 0:8918a71cdbe9 592 //Synchronization pattern
Sergunb 0:8918a71cdbe9 593 a2fxxxm3EthWriteSmi(SMI_SYNC, 32);
Sergunb 0:8918a71cdbe9 594 //Start of frame
Sergunb 0:8918a71cdbe9 595 a2fxxxm3EthWriteSmi(SMI_START, 2);
Sergunb 0:8918a71cdbe9 596 //Set up a write operation
Sergunb 0:8918a71cdbe9 597 a2fxxxm3EthWriteSmi(SMI_WRITE, 2);
Sergunb 0:8918a71cdbe9 598 //Write PHY address
Sergunb 0:8918a71cdbe9 599 a2fxxxm3EthWriteSmi(phyAddr, 5);
Sergunb 0:8918a71cdbe9 600 //Write register address
Sergunb 0:8918a71cdbe9 601 a2fxxxm3EthWriteSmi(regAddr, 5);
Sergunb 0:8918a71cdbe9 602 //Turnaround
Sergunb 0:8918a71cdbe9 603 a2fxxxm3EthWriteSmi(SMI_TA, 2);
Sergunb 0:8918a71cdbe9 604 //Write register value
Sergunb 0:8918a71cdbe9 605 a2fxxxm3EthWriteSmi(data, 16);
Sergunb 0:8918a71cdbe9 606 //Release MDIO
Sergunb 0:8918a71cdbe9 607 a2fxxxm3EthReadSmi(1);
Sergunb 0:8918a71cdbe9 608 }
Sergunb 0:8918a71cdbe9 609
Sergunb 0:8918a71cdbe9 610
Sergunb 0:8918a71cdbe9 611 /**
Sergunb 0:8918a71cdbe9 612 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 613 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 614 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 615 * @return Register value
Sergunb 0:8918a71cdbe9 616 **/
Sergunb 0:8918a71cdbe9 617
Sergunb 0:8918a71cdbe9 618 uint16_t a2fxxxm3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 619 {
Sergunb 0:8918a71cdbe9 620 uint16_t data;
Sergunb 0:8918a71cdbe9 621
Sergunb 0:8918a71cdbe9 622 //Synchronization pattern
Sergunb 0:8918a71cdbe9 623 a2fxxxm3EthWriteSmi(SMI_SYNC, 32);
Sergunb 0:8918a71cdbe9 624 //Start of frame
Sergunb 0:8918a71cdbe9 625 a2fxxxm3EthWriteSmi(SMI_START, 2);
Sergunb 0:8918a71cdbe9 626 //Set up a read operation
Sergunb 0:8918a71cdbe9 627 a2fxxxm3EthWriteSmi(SMI_READ, 2);
Sergunb 0:8918a71cdbe9 628 //Write PHY address
Sergunb 0:8918a71cdbe9 629 a2fxxxm3EthWriteSmi(phyAddr, 5);
Sergunb 0:8918a71cdbe9 630 //Write register address
Sergunb 0:8918a71cdbe9 631 a2fxxxm3EthWriteSmi(regAddr, 5);
Sergunb 0:8918a71cdbe9 632 //Turnaround to avoid contention
Sergunb 0:8918a71cdbe9 633 a2fxxxm3EthReadSmi(1);
Sergunb 0:8918a71cdbe9 634 //Read register value
Sergunb 0:8918a71cdbe9 635 data = a2fxxxm3EthReadSmi(16);
Sergunb 0:8918a71cdbe9 636 //Force the PHY to release the MDIO pin
Sergunb 0:8918a71cdbe9 637 a2fxxxm3EthReadSmi(1);
Sergunb 0:8918a71cdbe9 638
Sergunb 0:8918a71cdbe9 639 //Return PHY register contents
Sergunb 0:8918a71cdbe9 640 return data;
Sergunb 0:8918a71cdbe9 641 }
Sergunb 0:8918a71cdbe9 642
Sergunb 0:8918a71cdbe9 643
Sergunb 0:8918a71cdbe9 644 /**
Sergunb 0:8918a71cdbe9 645 * @brief SMI write operation
Sergunb 0:8918a71cdbe9 646 * @param[in] data Raw data to be written
Sergunb 0:8918a71cdbe9 647 * @param[in] length Number of bits to be written
Sergunb 0:8918a71cdbe9 648 **/
Sergunb 0:8918a71cdbe9 649
Sergunb 0:8918a71cdbe9 650 void a2fxxxm3EthWriteSmi(uint32_t data, uint_t length)
Sergunb 0:8918a71cdbe9 651 {
Sergunb 0:8918a71cdbe9 652 //Skip the most significant bits since they are meaningless
Sergunb 0:8918a71cdbe9 653 data <<= 32 - length;
Sergunb 0:8918a71cdbe9 654
Sergunb 0:8918a71cdbe9 655 //Configure MDIO as an output
Sergunb 0:8918a71cdbe9 656 MAC->CSR9 |= CSR9_MDEN_MASK;
Sergunb 0:8918a71cdbe9 657
Sergunb 0:8918a71cdbe9 658 //Write the specified number of bits
Sergunb 0:8918a71cdbe9 659 while(length--)
Sergunb 0:8918a71cdbe9 660 {
Sergunb 0:8918a71cdbe9 661 //Write MDIO
Sergunb 0:8918a71cdbe9 662 if(data & 0x80000000)
Sergunb 0:8918a71cdbe9 663 MAC->CSR9 |= CSR9_MDO_MASK;
Sergunb 0:8918a71cdbe9 664 else
Sergunb 0:8918a71cdbe9 665 MAC->CSR9 &= ~CSR9_MDO_MASK;
Sergunb 0:8918a71cdbe9 666
Sergunb 0:8918a71cdbe9 667 //Assert MDC
Sergunb 0:8918a71cdbe9 668 usleep(1);
Sergunb 0:8918a71cdbe9 669 MAC->CSR9 |= CSR9_MDC_MASK;
Sergunb 0:8918a71cdbe9 670 //Deassert MDC
Sergunb 0:8918a71cdbe9 671 usleep(1);
Sergunb 0:8918a71cdbe9 672 MAC->CSR9 &= ~CSR9_MDC_MASK;
Sergunb 0:8918a71cdbe9 673
Sergunb 0:8918a71cdbe9 674 //Rotate data
Sergunb 0:8918a71cdbe9 675 data <<= 1;
Sergunb 0:8918a71cdbe9 676 }
Sergunb 0:8918a71cdbe9 677 }
Sergunb 0:8918a71cdbe9 678
Sergunb 0:8918a71cdbe9 679
Sergunb 0:8918a71cdbe9 680 /**
Sergunb 0:8918a71cdbe9 681 * @brief SMI read operation
Sergunb 0:8918a71cdbe9 682 * @param[in] length Number of bits to be read
Sergunb 0:8918a71cdbe9 683 * @return Data resulting from the MDIO read operation
Sergunb 0:8918a71cdbe9 684 **/
Sergunb 0:8918a71cdbe9 685
Sergunb 0:8918a71cdbe9 686 uint32_t a2fxxxm3EthReadSmi(uint_t length)
Sergunb 0:8918a71cdbe9 687 {
Sergunb 0:8918a71cdbe9 688 uint32_t data = 0;
Sergunb 0:8918a71cdbe9 689
Sergunb 0:8918a71cdbe9 690 //Configure MDIO as an input
Sergunb 0:8918a71cdbe9 691 MAC->CSR9 &= ~CSR9_MDEN_MASK;
Sergunb 0:8918a71cdbe9 692
Sergunb 0:8918a71cdbe9 693 //Read the specified number of bits
Sergunb 0:8918a71cdbe9 694 while(length--)
Sergunb 0:8918a71cdbe9 695 {
Sergunb 0:8918a71cdbe9 696 //Rotate data
Sergunb 0:8918a71cdbe9 697 data <<= 1;
Sergunb 0:8918a71cdbe9 698
Sergunb 0:8918a71cdbe9 699 //Assert MDC
Sergunb 0:8918a71cdbe9 700 MAC->CSR9 |= CSR9_MDC_MASK;
Sergunb 0:8918a71cdbe9 701 usleep(1);
Sergunb 0:8918a71cdbe9 702 //Deassert MDC
Sergunb 0:8918a71cdbe9 703 MAC->CSR9 &= ~CSR9_MDC_MASK;
Sergunb 0:8918a71cdbe9 704 usleep(1);
Sergunb 0:8918a71cdbe9 705
Sergunb 0:8918a71cdbe9 706 //Check MDIO state
Sergunb 0:8918a71cdbe9 707 if(MAC->CSR9 & CSR9_MDI_MASK)
Sergunb 0:8918a71cdbe9 708 data |= 0x00000001;
Sergunb 0:8918a71cdbe9 709 }
Sergunb 0:8918a71cdbe9 710
Sergunb 0:8918a71cdbe9 711 //Return the received data
Sergunb 0:8918a71cdbe9 712 return data;
Sergunb 0:8918a71cdbe9 713 }
Sergunb 0:8918a71cdbe9 714
Sergunb 0:8918a71cdbe9 715
Sergunb 0:8918a71cdbe9 716 /**
Sergunb 0:8918a71cdbe9 717 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 718 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 719 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 720 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 721 **/
Sergunb 0:8918a71cdbe9 722
Sergunb 0:8918a71cdbe9 723 uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 724 {
Sergunb 0:8918a71cdbe9 725 uint_t i;
Sergunb 0:8918a71cdbe9 726 uint_t j;
Sergunb 0:8918a71cdbe9 727
Sergunb 0:8918a71cdbe9 728 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 729 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 730 //CRC preset value
Sergunb 0:8918a71cdbe9 731 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 732
Sergunb 0:8918a71cdbe9 733 //Loop through data
Sergunb 0:8918a71cdbe9 734 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 735 {
Sergunb 0:8918a71cdbe9 736 //Update CRC value
Sergunb 0:8918a71cdbe9 737 crc ^= p[i];
Sergunb 0:8918a71cdbe9 738
Sergunb 0:8918a71cdbe9 739 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 740 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 741 {
Sergunb 0:8918a71cdbe9 742 //Update CRC value
Sergunb 0:8918a71cdbe9 743 if(crc & 0x00000001)
Sergunb 0:8918a71cdbe9 744 crc = (crc >> 1) ^ 0xEDB88320;
Sergunb 0:8918a71cdbe9 745 else
Sergunb 0:8918a71cdbe9 746 crc = crc >> 1;
Sergunb 0:8918a71cdbe9 747 }
Sergunb 0:8918a71cdbe9 748 }
Sergunb 0:8918a71cdbe9 749
Sergunb 0:8918a71cdbe9 750 //Return CRC value
Sergunb 0:8918a71cdbe9 751 return crc;
Sergunb 0:8918a71cdbe9 752 }
Sergunb 0:8918a71cdbe9 753