Руслан Урядинский
libuav original
Dependents: UAVCAN UAVCAN_Subscriber
LPC_SSP_T Struct Reference
[CHIP: LPC11xx SSP register block and driver]
SSP register block structure. More...
#include <ssp_11xx.h>
Data Fields | |
| __IO uint32_t | CR0 |
| __IO uint32_t | CR1 |
| __IO uint32_t | DR |
| __I uint32_t | SR |
| __IO uint32_t | CPSR |
| __IO uint32_t | IMSC |
| __I uint32_t | RIS |
| __I uint32_t | MIS |
| __O uint32_t | ICR |
Detailed Description
SSP register block structure.
Definition at line 47 of file ssp_11xx.h.
Field Documentation
| __IO uint32_t CPSR |
Clock Prescale Register
Definition at line 52 of file ssp_11xx.h.
| __IO uint32_t CR0 |
< SSPn Structure Control Register 0. Selects the serial clock rate, bus type, and data size.
Definition at line 48 of file ssp_11xx.h.
| __IO uint32_t CR1 |
Control Register 1. Selects master/slave and other modes.
Definition at line 49 of file ssp_11xx.h.
| __IO uint32_t DR |
Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
Definition at line 50 of file ssp_11xx.h.
| __O uint32_t ICR |
SSPICR Interrupt Clear Register
Definition at line 56 of file ssp_11xx.h.
| __IO uint32_t IMSC |
Interrupt Mask Set and Clear Register
Definition at line 53 of file ssp_11xx.h.
| __I uint32_t MIS |
Masked Interrupt Status Register
Definition at line 55 of file ssp_11xx.h.
| __I uint32_t RIS |
Raw Interrupt Status Register
Definition at line 54 of file ssp_11xx.h.
| __I uint32_t SR |
Status Register
Definition at line 51 of file ssp_11xx.h.
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