ssp_11xx.h

00001 /*
00002  * @brief LPC11xx SSP Registers and control functions
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2012
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __SSP_11XX_H_
00033 #define __SSP_11XX_H_
00034 
00035 #ifdef __cplusplus
00036 extern "C" {
00037 #endif
00038 
00039 /** @defgroup SSP_11XX CHIP: LPC11xx SSP register block and driver
00040  * @ingroup CHIP_11XX_Drivers
00041  * @{
00042  */
00043 
00044 /**
00045  * @brief SSP register block structure
00046  */
00047 typedef struct {            /*!< SSPn Structure         */
00048     __IO uint32_t CR0 ;      /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
00049     __IO uint32_t CR1 ;      /*!< Control Register 1. Selects master/slave and other modes. */
00050     __IO uint32_t DR ;       /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
00051     __I  uint32_t SR ;       /*!< Status Register        */
00052     __IO uint32_t CPSR ;     /*!< Clock Prescale Register */
00053     __IO uint32_t IMSC ;     /*!< Interrupt Mask Set and Clear Register */
00054     __I  uint32_t RIS ;      /*!< Raw Interrupt Status Register */
00055     __I  uint32_t MIS ;      /*!< Masked Interrupt Status Register */
00056     __O  uint32_t ICR ;      /*!< SSPICR Interrupt Clear Register */
00057 } LPC_SSP_T;
00058 
00059 /**
00060  * Macro defines for CR0 register
00061  */
00062 
00063 /** SSP data size select, must be 4 bits to 16 bits */
00064 #define SSP_CR0_DSS(n)          ((uint32_t) ((n) & 0xF))
00065 /** SSP control 0 Motorola SPI mode */
00066 #define SSP_CR0_FRF_SPI         ((uint32_t) (0 << 4))
00067 /** SSP control 0 TI synchronous serial mode */
00068 #define SSP_CR0_FRF_TI          ((uint32_t) (1 << 4))
00069 /** SSP control 0 National Micro-wire mode */
00070 #define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
00071 /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
00072    bus clock high between frames, (0) = low */
00073 #define SSP_CR0_CPOL_LO     ((uint32_t) (0))
00074 #define SSP_CR0_CPOL_HI     ((uint32_t) (1 << 6))
00075 /** SPI clock out phase bit (used in SPI mode only), (1) = captures data
00076    on the second clock transition of the frame, (0) = first */
00077 #define SSP_CR0_CPHA_FIRST  ((uint32_t) (0))
00078 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
00079 /** SSP serial clock rate value load macro, divider rate is
00080    PERIPH_CLK / (cpsr * (SCR + 1)) */
00081 #define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
00082 /** SSP CR0 bit mask */
00083 #define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
00084 /** SSP CR0 bit mask */
00085 #define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
00086 /** SSP serial clock rate value load macro, divider rate is
00087    PERIPH_CLK / (cpsr * (SCR + 1)) */
00088 #define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
00089 
00090 /**
00091  * Macro defines for CR1 register
00092  */
00093 
00094 /** SSP control 1 loopback mode enable bit */
00095 #define SSP_CR1_LBM_EN      ((uint32_t) (1 << 0))
00096 /** SSP control 1 enable bit */
00097 #define SSP_CR1_SSP_EN      ((uint32_t) (1 << 1))
00098 /** SSP control 1 slave enable */
00099 #define SSP_CR1_SLAVE_EN    ((uint32_t) (1 << 2))
00100 #define SSP_CR1_MASTER_EN   ((uint32_t) (0))
00101 /** SSP control 1 slave out disable bit, disables transmit line in slave
00102    mode */
00103 #define SSP_CR1_SO_DISABLE  ((uint32_t) (1 << 3))
00104 /** SSP CR1 bit mask */
00105 #define SSP_CR1_BITMASK     ((uint32_t) (0x0F))
00106 
00107 /** SSP CPSR bit mask */
00108 #define SSP_CPSR_BITMASK    ((uint32_t) (0xFF))
00109 /**
00110  * Macro defines for DR register
00111  */
00112 
00113 /** SSP data bit mask */
00114 #define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
00115 
00116 /**
00117  * Macro defines for SR register
00118  */
00119 
00120 /** SSP SR bit mask */
00121 #define SSP_SR_BITMASK  ((uint32_t) (0x1F))
00122 
00123 /** ICR bit mask */
00124 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
00125 
00126 /**
00127  * @brief SSP Type of Status
00128  */
00129 typedef enum _SSP_STATUS {
00130     SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
00131     SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
00132     SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
00133     SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
00134     SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
00135 } SSP_STATUS_T;
00136 
00137 /**
00138  * @brief SSP Type of Interrupt Mask
00139  */
00140 typedef enum _SSP_INTMASK {
00141     SSP_RORIM = ((uint32_t)(1 << 0)),   /**< Overun */
00142     SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
00143     SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
00144     SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
00145     SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
00146 } SSP_INTMASK_T;
00147 
00148 /**
00149  * @brief SSP Type of Mask Interrupt Status
00150  */
00151 typedef enum _SSP_MASKINTSTATUS {
00152     SSP_RORMIS = ((uint32_t)(1 << 0)),  /**< Overun */
00153     SSP_RTMIS = ((uint32_t)(1 << 1)),   /**< TimeOut */
00154     SSP_RXMIS = ((uint32_t)(1 << 2)),   /**< Rx FIFO is at least half full */
00155     SSP_TXMIS = ((uint32_t)(1 << 3)),   /**< Tx FIFO is at least half empty */
00156     SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
00157 } SSP_MASKINTSTATUS_T;
00158 
00159 /**
00160  * @brief SSP Type of Raw Interrupt Status
00161  */
00162 typedef enum _SSP_RAWINTSTATUS {
00163     SSP_RORRIS = ((uint32_t)(1 << 0)),  /**< Overun */
00164     SSP_RTRIS = ((uint32_t)(1 << 1)),   /**< TimeOut */
00165     SSP_RXRIS = ((uint32_t)(1 << 2)),   /**< Rx FIFO is at least half full */
00166     SSP_TXRIS = ((uint32_t)(1 << 3)),   /**< Tx FIFO is at least half empty */
00167     SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
00168 } SSP_RAWINTSTATUS_T;
00169 
00170 typedef enum _SSP_INTCLEAR {
00171     SSP_RORIC = 0x0,
00172     SSP_RTIC = 0x1,
00173     SSP_INT_CLEAR_BITMASK = 0x3,
00174 } SSP_INTCLEAR_T;
00175 
00176 /*
00177  * @brief SSP clock format
00178  */
00179 typedef enum CHIP_SSP_CLOCK_FORMAT  {
00180     SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),       /**< CPHA = 0, CPOL = 0 */
00181     SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),      /**< CPHA = 0, CPOL = 1 */
00182     SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),      /**< CPHA = 1, CPOL = 0 */
00183     SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),      /**< CPHA = 1, CPOL = 1 */
00184     SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
00185     SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
00186     SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
00187     SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
00188 } CHIP_SSP_CLOCK_MODE_T;
00189 
00190 /*
00191  * @brief SSP frame format
00192  */
00193 typedef enum CHIP_SSP_FRAME_FORMAT  {
00194     SSP_FRAMEFORMAT_SPI = (0 << 4),         /**< Frame format: SPI */
00195     CHIP_SSP_FRAME_FORMAT_TI = (1u << 4),           /**< Frame format: TI SSI */
00196     SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),  /**< Frame format: Microwire */
00197 } CHIP_SSP_FRAME_FORMAT_T;
00198 
00199 /*
00200  * @brief Number of bits per frame
00201  */
00202 typedef enum CHIP_SSP_BITS  {
00203     SSP_BITS_4  = (3u << 0),     /*!< 4 bits/frame */
00204     SSP_BITS_5  = (4u << 0),     /*!< 5 bits/frame */
00205     SSP_BITS_6  = (5u << 0),     /*!< 6 bits/frame */
00206     SSP_BITS_7  = (6u << 0),     /*!< 7 bits/frame */
00207     SSP_BITS_8  = (7u << 0),     /*!< 8 bits/frame */
00208     SSP_BITS_9  = (8u << 0),     /*!< 9 bits/frame */
00209     SSP_BITS_10  = (9u << 0),    /*!< 10 bits/frame */
00210     SSP_BITS_11  = (10u << 0),   /*!< 11 bits/frame */
00211     SSP_BITS_12  = (11u << 0),   /*!< 12 bits/frame */
00212     SSP_BITS_13  = (12u << 0),   /*!< 13 bits/frame */
00213     SSP_BITS_14  = (13u << 0),   /*!< 14 bits/frame */
00214     SSP_BITS_15  = (14u << 0),   /*!< 15 bits/frame */
00215     SSP_BITS_16  = (15u << 0),   /*!< 16 bits/frame */
00216 } CHIP_SSP_BITS_T;
00217 
00218 /*
00219  * @brief SSP config format
00220  */
00221 typedef struct SSP_ConfigFormat {
00222     CHIP_SSP_BITS_T bits;                   /*!< Format config: bits/frame */
00223     CHIP_SSP_CLOCK_MODE_T clockMode;    /*!< Format config: clock phase/polarity */
00224     CHIP_SSP_FRAME_FORMAT_T frameFormat;    /*!< Format config: SPI/TI/Microwire */
00225 } SSP_ConfigFormat;
00226 
00227 /**
00228  * @brief   Enable SSP operation
00229  * @param   pSSP        : The base of SSP peripheral on the chip
00230  * @return   Nothing
00231  */
00232 STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
00233 {
00234     pSSP->CR1  |= SSP_CR1_SSP_EN;
00235 }
00236 
00237 /**
00238  * @brief   Disable SSP operation
00239  * @param   pSSP        : The base of SSP peripheral on the chip
00240  * @return   Nothing
00241  */
00242 STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
00243 {
00244     pSSP->CR1  &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
00245 }
00246 
00247 /**
00248  * @brief   Enable loopback mode
00249  * @param   pSSP        : The base of SSP peripheral on the chip
00250  * @return   Nothing
00251  * @note    Serial input is taken from the serial output (MOSI or MISO) rather
00252  * than the serial input pin
00253  */
00254 STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
00255 {
00256     pSSP->CR1  |= SSP_CR1_LBM_EN;
00257 }
00258 
00259 /**
00260  * @brief   Disable loopback mode
00261  * @param   pSSP        : The base of SSP peripheral on the chip
00262  * @return   Nothing
00263  * @note    Serial input is taken from the serial output (MOSI or MISO) rather
00264  * than the serial input pin
00265  */
00266 STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
00267 {
00268     pSSP->CR1  &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
00269 }
00270 
00271 /**
00272  * @brief   Get the current status of SSP controller
00273  * @param   pSSP    : The base of SSP peripheral on the chip
00274  * @param   Stat    : Type of status, should be :
00275  *                      - SSP_STAT_TFE
00276  *                      - SSP_STAT_TNF
00277  *                      - SSP_STAT_RNE
00278  *                      - SSP_STAT_RFF
00279  *                      - SSP_STAT_BSY
00280  * @return   SSP controller status, SET or RESET
00281  */
00282 STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
00283 {
00284     return (pSSP->SR  & Stat) ? SET : RESET;
00285 }
00286 
00287 /**
00288  * @brief   Get the masked interrupt status
00289  * @param   pSSP    : The base of SSP peripheral on the chip
00290  * @return   SSP Masked Interrupt Status Register value
00291  * @note    The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
00292  */
00293 STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
00294 {
00295     return pSSP->MIS ;
00296 }
00297 
00298 /**
00299  * @brief   Get the raw interrupt status
00300  * @param   pSSP    : The base of SSP peripheral on the chip
00301  * @param   RawInt  : Interrupt condition to be get status, shoud be :
00302  *                      - SSP_RORRIS
00303  *                      - SSP_RTRIS
00304  *                      - SSP_RXRIS
00305  *                      - SSP_TXRIS
00306  * @return   Raw interrupt status corresponding to interrupt condition , SET or RESET
00307  * @note    Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
00308  */
00309 STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
00310 {
00311     return (pSSP->RIS  & RawInt) ? SET : RESET;
00312 }
00313 
00314 /**
00315  * @brief   Get the number of bits transferred in each frame
00316  * @param   pSSP    : The base of SSP peripheral on the chip
00317  * @return   the number of bits transferred in each frame minus one
00318  * @note    The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
00319  */
00320 STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
00321 {
00322     return SSP_CR0_DSS(pSSP->CR0 );
00323 }
00324 
00325 /**
00326  * @brief   Clear the corresponding interrupt condition(s) in the SSP controller
00327  * @param   pSSP    : The base of SSP peripheral on the chip
00328  * @param   IntClear: Type of cleared interrupt, should be :
00329  *                      - SSP_RORIC
00330  *                      - SSP_RTIC
00331  * @return   Nothing
00332  * @note    Software can clear one or more interrupt condition(s) in the SSP controller
00333  */
00334 STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
00335 {
00336     pSSP->ICR  = IntClear;
00337 }
00338 
00339 /**
00340  * @brief   Enable interrupt for the SSP
00341  * @param   pSSP        : The base of SSP peripheral on the chip
00342  * @return   Nothing
00343  */
00344 STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
00345 {
00346     pSSP->IMSC  |= SSP_TXIM;
00347 }
00348 
00349 /**
00350  * @brief   Disable interrupt for the SSP
00351  * @param   pSSP        : The base of SSP peripheral on the chip
00352  * @return   Nothing
00353  */
00354 STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
00355 {
00356     pSSP->IMSC  &= (~SSP_TXIM);
00357 }
00358 
00359 /**
00360  * @brief   Get received SSP data
00361  * @param   pSSP    : The base of SSP peripheral on the chip
00362  * @return   SSP 16-bit data received
00363  */
00364 STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
00365 {
00366     return (uint16_t) (SSP_DR_BITMASK(pSSP->DR ));
00367 }
00368 
00369 /**
00370  * @brief   Send SSP 16-bit data
00371  * @param   pSSP    : The base of SSP peripheral on the chip
00372  * @param   tx_data : SSP 16-bit data to be transmited
00373  * @return   Nothing
00374  */
00375 STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
00376 {
00377     pSSP->DR  = SSP_DR_BITMASK(tx_data);
00378 }
00379 
00380 /**
00381  * @brief   Set up output clocks per bit for SSP bus
00382  * @param   pSSP        : The base of SSP peripheral on the chip
00383  * @param   clk_rate    fs: The number of prescaler-output clocks per bit on the bus, minus one
00384  * @param   prescale    : The factor by which the Prescaler divides the SSP peripheral clock PCLK
00385  * @return   Nothing
00386  * @note    The bit frequency is PCLK / (prescale x[clk_rate+1])
00387  */
00388 void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
00389 
00390 /**
00391  * @brief   Set up the SSP frame format
00392  * @param   pSSP        : The base of SSP peripheral on the chip
00393  * @param   bits        : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
00394  * @param   frameFormat : Frame format, should be :
00395  *                          - SSP_FRAMEFORMAT_SPI
00396  *                          - SSP_FRAME_FORMAT_TI
00397  *                          - SSP_FRAMEFORMAT_MICROWIRE
00398  * @param   clockMode   : Select Clock polarity and Clock phase, should be :
00399  *                          - SSP_CLOCK_CPHA0_CPOL0
00400  *                          - SSP_CLOCK_CPHA0_CPOL1
00401  *                          - SSP_CLOCK_CPHA1_CPOL0
00402  *                          - SSP_CLOCK_CPHA1_CPOL1
00403  * @return   Nothing
00404  * @note    Note: The clockFormat is only used in SPI mode
00405  */
00406 STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
00407 {
00408     pSSP->CR0  = (pSSP->CR0  & ~0xFF) | bits | frameFormat | clockMode;
00409 }
00410 
00411 /**
00412  * @brief   Set the SSP working as master or slave mode
00413  * @param   pSSP    : The base of SSP peripheral on the chip
00414  * @param   mode    : Operating mode, should be
00415  *                      - SSP_MODE_MASTER
00416  *                      - SSP_MODE_SLAVE
00417  * @return   Nothing
00418  */
00419 STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
00420 {
00421     pSSP->CR1  = (pSSP->CR1  & ~(1 << 2)) | mode;
00422 }
00423 
00424 /*
00425  * @brief SSP mode
00426  */
00427 typedef enum CHIP_SSP_MODE  {
00428     SSP_MODE_MASTER = (0 << 2), /**< Master mode */
00429     SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */
00430 } CHIP_SSP_MODE_T;
00431 
00432 /*
00433  * @brief SPI address
00434  */
00435 typedef struct {
00436     uint8_t port;   /*!< Port Number */
00437     uint8_t pin;    /*!< Pin number */
00438 } SPI_Address_t;
00439 
00440 /*
00441  * @brief SSP data setup structure
00442  */
00443 typedef struct {
00444     void      *tx_data; /*!< Pointer to transmit data */
00445     uint32_t  tx_cnt;   /*!< Transmit counter */
00446     void      *rx_data; /*!< Pointer to transmit data */
00447     uint32_t  rx_cnt;   /*!< Receive counter */
00448     uint32_t  length;   /*!< Length of transfer data */
00449 } Chip_SSP_DATA_SETUP_T;
00450 
00451 /** SSP configuration parameter defines */
00452 /** Clock phase control bit */
00453 #define SSP_CPHA_FIRST          SSP_CR0_CPHA_FIRST
00454 #define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
00455 
00456 /** Clock polarity control bit */
00457 /* There's no bug here!!!
00458  * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
00459  * That means the active clock is in HI state.
00460  * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
00461  * high between frames. That means the active clock is in LO state.
00462  */
00463 #define SSP_CPOL_HI             SSP_CR0_CPOL_LO
00464 #define SSP_CPOL_LO             SSP_CR0_CPOL_HI
00465 
00466 /** SSP master mode enable */
00467 #define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
00468 #define SSP_MASTER_MODE         SSP_CR1_MASTER_EN
00469 
00470 /**
00471  * @brief   Clean all data in RX FIFO of SSP
00472  * @param   pSSP            : The base SSP peripheral on the chip
00473  * @return  Nothing
00474  */
00475 void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
00476 
00477 /**
00478  * @brief   SSP Interrupt Read/Write with 8-bit frame width
00479  * @param   pSSP            : The base SSP peripheral on the chip
00480  * @param   xf_setup        : Pointer to a SSP_DATA_SETUP_T structure that contains specified
00481  *                          information about transmit/receive data configuration
00482  * @return  SUCCESS or ERROR
00483  */
00484 Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
00485 
00486 /**
00487  * @brief   SSP Interrupt Read/Write with 16-bit frame width
00488  * @param   pSSP            : The base SSP peripheral on the chip
00489  * @param   xf_setup        : Pointer to a SSP_DATA_SETUP_T structure that contains specified
00490  *                          information about transmit/receive data configuration
00491  * @return  SUCCESS or ERROR
00492  */
00493 Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
00494 
00495 /**
00496  * @brief   SSP Polling Read/Write in blocking mode
00497  * @param   pSSP            : The base SSP peripheral on the chip
00498  * @param   xf_setup        : Pointer to a SSP_DATA_SETUP_T structure that contains specified
00499  *                          information about transmit/receive data configuration
00500  * @return  Actual data length has been transferred
00501  * @note
00502  * This function can be used in both master and slave mode. It starts with writing phase and after that,
00503  * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
00504  * through xf_setup param.
00505  */
00506 uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
00507 
00508 /**
00509  * @brief   SSP Polling Write in blocking mode
00510  * @param   pSSP            : The base SSP peripheral on the chip
00511  * @param   buffer          : Buffer address
00512  * @param   buffer_len      : Buffer length
00513  * @return  Actual data length has been transferred
00514  * @note
00515  * This function can be used in both master and slave mode. First, a writing operation will send
00516  * the needed data. After that, a dummy reading operation is generated to clear data buffer
00517  */
00518 uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
00519 
00520 /**
00521  * @brief   SSP Polling Read in blocking mode
00522  * @param   pSSP            : The base SSP peripheral on the chip
00523  * @param   buffer          : Buffer address
00524  * @param   buffer_len      : The length of buffer
00525  * @return  Actual data length has been transferred
00526  * @note
00527  * This function can be used in both master and slave mode. First, a dummy writing operation is generated
00528  * to clear data buffer. After that, a reading operation will receive the needed data
00529  */
00530 uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
00531 
00532 /**
00533  * @brief   Initialize the SSP
00534  * @param   pSSP            : The base SSP peripheral on the chip
00535  * @return  Nothing
00536  */
00537 void Chip_SSP_Init(LPC_SSP_T *pSSP);
00538 
00539 /**
00540  * @brief   Deinitialise the SSP
00541  * @param   pSSP    : The base of SSP peripheral on the chip
00542  * @return  Nothing
00543  * @note    The SSP controller is disabled
00544  */
00545 void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
00546 
00547 /**
00548  * @brief   Set the SSP operating modes, master or slave
00549  * @param   pSSP            : The base SSP peripheral on the chip
00550  * @param   master          : 1 to set master, 0 to set slave
00551  * @return  Nothing
00552  */
00553 void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
00554 
00555 /**
00556  * @brief   Set the clock frequency for SSP interface
00557  * @param   pSSP            : The base SSP peripheral on the chip
00558  * @param   bitRate     : The SSP bit rate
00559  * @return  Nothing
00560  */
00561 void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
00562 
00563 /**
00564  * @}
00565  */
00566 
00567 #ifdef __cplusplus
00568 }
00569 #endif
00570 
00571 #endif /* __SSP_11XX_H_ */