Rob Kluin / nRF51822

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Fork of nRF51822 by Nordic Semiconductor

nordic-sdk/components/drivers_nrf/hal/nrf51.h@343:6675661fa600, 2015-06-19 (annotated)

Committer:
rgrover1
Date:
Fri Jun 19 15:55:34 2015 +0100
Revision:
343:6675661fa600
Parent:
103:138bdc859cc9
Child:
345:dfde56236c36
Synchronized with git rev 6d1bf116

Author: Rohit Grover

fix #1: update license headers for all sources obtained from nordic-SDK using a new template obtained from Nordic.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 343:6675661fa600 1 /*
rgrover1 343:6675661fa600 2 * Copyright (c) Nordic Semiconductor ASA
rgrover1 343:6675661fa600 3 * All rights reserved.
rgrover1 343:6675661fa600 4 *
rgrover1 343:6675661fa600 5 * Redistribution and use in source and binary forms, with or without modification,
rgrover1 343:6675661fa600 6 * are permitted provided that the following conditions are met:
rgrover1 343:6675661fa600 7 *
rgrover1 343:6675661fa600 8 * 1. Redistributions of source code must retain the above copyright notice, this
rgrover1 343:6675661fa600 9 * list of conditions and the following disclaimer.
rgrover1 343:6675661fa600 10 *
rgrover1 343:6675661fa600 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
rgrover1 343:6675661fa600 12 * list of conditions and the following disclaimer in the documentation and/or
rgrover1 343:6675661fa600 13 * other materials provided with the distribution.
rgrover1 343:6675661fa600 14 *
rgrover1 343:6675661fa600 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
rgrover1 343:6675661fa600 16 * contributors to this software may be used to endorse or promote products
rgrover1 343:6675661fa600 17 * derived from this software without specific prior written permission.
rgrover1 343:6675661fa600 18 *
rgrover1 343:6675661fa600 19 *
rgrover1 343:6675661fa600 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
rgrover1 343:6675661fa600 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
rgrover1 343:6675661fa600 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 343:6675661fa600 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
rgrover1 343:6675661fa600 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
rgrover1 343:6675661fa600 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
rgrover1 343:6675661fa600 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
rgrover1 343:6675661fa600 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
rgrover1 343:6675661fa600 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
rgrover1 343:6675661fa600 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 343:6675661fa600 30 *
rgrover1 343:6675661fa600 31 */
rgrover1 343:6675661fa600 32
rgrover1 343:6675661fa600 33 /** @addtogroup nRF51
rgrover1 343:6675661fa600 34 * @{
rgrover1 343:6675661fa600 35 */
rgrover1 343:6675661fa600 36
rgrover1 343:6675661fa600 37 #ifndef NRF51_H
rgrover1 343:6675661fa600 38 #define NRF51_H
rgrover1 343:6675661fa600 39
rgrover1 343:6675661fa600 40 #ifdef __cplusplus
rgrover1 343:6675661fa600 41 extern "C" {
rgrover1 343:6675661fa600 42 #endif
rgrover1 343:6675661fa600 43
rgrover1 343:6675661fa600 44
rgrover1 343:6675661fa600 45 /* ------------------------- Interrupt Number Definition ------------------------ */
rgrover1 343:6675661fa600 46
rgrover1 343:6675661fa600 47 typedef enum {
rgrover1 343:6675661fa600 48 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
rgrover1 343:6675661fa600 49 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
rgrover1 343:6675661fa600 50 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
rgrover1 343:6675661fa600 51 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
rgrover1 343:6675661fa600 52 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
rgrover1 343:6675661fa600 53 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
rgrover1 343:6675661fa600 54 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
rgrover1 343:6675661fa600 55 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
rgrover1 343:6675661fa600 56 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
rgrover1 343:6675661fa600 57 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
rgrover1 343:6675661fa600 58 RADIO_IRQn = 1, /*!< 1 RADIO */
rgrover1 343:6675661fa600 59 UART0_IRQn = 2, /*!< 2 UART0 */
rgrover1 343:6675661fa600 60 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
rgrover1 343:6675661fa600 61 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
rgrover1 343:6675661fa600 62 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
rgrover1 343:6675661fa600 63 ADC_IRQn = 7, /*!< 7 ADC */
rgrover1 343:6675661fa600 64 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
rgrover1 343:6675661fa600 65 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
rgrover1 343:6675661fa600 66 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
rgrover1 343:6675661fa600 67 RTC0_IRQn = 11, /*!< 11 RTC0 */
rgrover1 343:6675661fa600 68 TEMP_IRQn = 12, /*!< 12 TEMP */
rgrover1 343:6675661fa600 69 RNG_IRQn = 13, /*!< 13 RNG */
rgrover1 343:6675661fa600 70 ECB_IRQn = 14, /*!< 14 ECB */
rgrover1 343:6675661fa600 71 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
rgrover1 343:6675661fa600 72 WDT_IRQn = 16, /*!< 16 WDT */
rgrover1 343:6675661fa600 73 RTC1_IRQn = 17, /*!< 17 RTC1 */
rgrover1 343:6675661fa600 74 QDEC_IRQn = 18, /*!< 18 QDEC */
rgrover1 343:6675661fa600 75 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
rgrover1 343:6675661fa600 76 SWI0_IRQn = 20, /*!< 20 SWI0 */
rgrover1 343:6675661fa600 77 SWI1_IRQn = 21, /*!< 21 SWI1 */
rgrover1 343:6675661fa600 78 SWI2_IRQn = 22, /*!< 22 SWI2 */
rgrover1 343:6675661fa600 79 SWI3_IRQn = 23, /*!< 23 SWI3 */
rgrover1 343:6675661fa600 80 SWI4_IRQn = 24, /*!< 24 SWI4 */
rgrover1 343:6675661fa600 81 SWI5_IRQn = 25 /*!< 25 SWI5 */
rgrover1 343:6675661fa600 82 } IRQn_Type;
rgrover1 343:6675661fa600 83
rgrover1 343:6675661fa600 84
rgrover1 343:6675661fa600 85 /** @addtogroup Configuration_of_CMSIS
rgrover1 343:6675661fa600 86 * @{
rgrover1 343:6675661fa600 87 */
rgrover1 343:6675661fa600 88
rgrover1 343:6675661fa600 89
rgrover1 343:6675661fa600 90 /* ================================================================================ */
rgrover1 343:6675661fa600 91 /* ================ Processor and Core Peripheral Section ================ */
rgrover1 343:6675661fa600 92 /* ================================================================================ */
rgrover1 343:6675661fa600 93
rgrover1 343:6675661fa600 94 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
rgrover1 343:6675661fa600 95 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
rgrover1 343:6675661fa600 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
rgrover1 343:6675661fa600 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
rgrover1 343:6675661fa600 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rgrover1 343:6675661fa600 99 /** @} */ /* End of group Configuration_of_CMSIS */
rgrover1 343:6675661fa600 100
rgrover1 343:6675661fa600 101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
rgrover1 343:6675661fa600 102 #include "system_nrf51.h" /*!< nRF51 System */
rgrover1 343:6675661fa600 103
rgrover1 343:6675661fa600 104
rgrover1 343:6675661fa600 105 /* ================================================================================ */
rgrover1 343:6675661fa600 106 /* ================ Device Specific Peripheral Section ================ */
rgrover1 343:6675661fa600 107 /* ================================================================================ */
rgrover1 343:6675661fa600 108
rgrover1 343:6675661fa600 109
rgrover1 343:6675661fa600 110 /** @addtogroup Device_Peripheral_Registers
rgrover1 343:6675661fa600 111 * @{
rgrover1 343:6675661fa600 112 */
rgrover1 343:6675661fa600 113
rgrover1 343:6675661fa600 114
rgrover1 343:6675661fa600 115 /* ------------------- Start of section using anonymous unions ------------------ */
rgrover1 343:6675661fa600 116 #if defined(__CC_ARM)
rgrover1 343:6675661fa600 117 #pragma push
rgrover1 343:6675661fa600 118 #pragma anon_unions
rgrover1 343:6675661fa600 119 #elif defined(__ICCARM__)
rgrover1 343:6675661fa600 120 #pragma language=extended
rgrover1 343:6675661fa600 121 #elif defined(__GNUC__)
rgrover1 343:6675661fa600 122 /* anonymous unions are enabled by default */
rgrover1 343:6675661fa600 123 #elif defined(__TMS470__)
rgrover1 343:6675661fa600 124 /* anonymous unions are enabled by default */
rgrover1 343:6675661fa600 125 #elif defined(__TASKING__)
rgrover1 343:6675661fa600 126 #pragma warning 586
rgrover1 343:6675661fa600 127 #else
rgrover1 343:6675661fa600 128 #warning Not supported compiler type
rgrover1 343:6675661fa600 129 #endif
rgrover1 343:6675661fa600 130
rgrover1 343:6675661fa600 131
rgrover1 343:6675661fa600 132 typedef struct {
rgrover1 343:6675661fa600 133 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
rgrover1 343:6675661fa600 134 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
rgrover1 343:6675661fa600 135 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
rgrover1 343:6675661fa600 136 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
rgrover1 343:6675661fa600 137 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
rgrover1 343:6675661fa600 138 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
rgrover1 343:6675661fa600 139 } AMLI_RAMPRI_Type;
rgrover1 343:6675661fa600 140
rgrover1 343:6675661fa600 141 typedef struct {
rgrover1 343:6675661fa600 142 __IO uint32_t SCK; /*!< Pin select for SCK. */
rgrover1 343:6675661fa600 143 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
rgrover1 343:6675661fa600 144 __IO uint32_t MISO; /*!< Pin select for MISO. */
rgrover1 343:6675661fa600 145 } SPIM_PSEL_Type;
rgrover1 343:6675661fa600 146
rgrover1 343:6675661fa600 147 typedef struct {
rgrover1 343:6675661fa600 148 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 343:6675661fa600 149 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
rgrover1 343:6675661fa600 150 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
rgrover1 343:6675661fa600 151 } SPIM_RXD_Type;
rgrover1 343:6675661fa600 152
rgrover1 343:6675661fa600 153 typedef struct {
rgrover1 343:6675661fa600 154 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 343:6675661fa600 155 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
rgrover1 343:6675661fa600 156 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
rgrover1 343:6675661fa600 157 } SPIM_TXD_Type;
rgrover1 343:6675661fa600 158
rgrover1 343:6675661fa600 159 typedef struct {
rgrover1 343:6675661fa600 160 __O uint32_t EN; /*!< Enable channel group. */
rgrover1 343:6675661fa600 161 __O uint32_t DIS; /*!< Disable channel group. */
rgrover1 343:6675661fa600 162 } PPI_TASKS_CHG_Type;
rgrover1 343:6675661fa600 163
rgrover1 343:6675661fa600 164 typedef struct {
rgrover1 343:6675661fa600 165 __IO uint32_t EEP; /*!< Channel event end-point. */
rgrover1 343:6675661fa600 166 __IO uint32_t TEP; /*!< Channel task end-point. */
rgrover1 343:6675661fa600 167 } PPI_CH_Type;
rgrover1 343:6675661fa600 168
rgrover1 343:6675661fa600 169 typedef struct {
rgrover1 343:6675661fa600 170 __I uint32_t PART; /*!< Part code */
rgrover1 343:6675661fa600 171 __I uint32_t VARIANT; /*!< Part variant */
rgrover1 343:6675661fa600 172 __I uint32_t PACKAGE; /*!< Package option */
rgrover1 343:6675661fa600 173 __I uint32_t RAM; /*!< RAM variant */
rgrover1 343:6675661fa600 174 __I uint32_t FLASH; /*!< Flash variant */
rgrover1 343:6675661fa600 175 __I uint32_t RESERVED[3]; /*!< Reserved */
rgrover1 343:6675661fa600 176 } FICR_INFO_Type;
rgrover1 343:6675661fa600 177
rgrover1 343:6675661fa600 178
rgrover1 343:6675661fa600 179 /* ================================================================================ */
rgrover1 343:6675661fa600 180 /* ================ POWER ================ */
rgrover1 343:6675661fa600 181 /* ================================================================================ */
rgrover1 343:6675661fa600 182
rgrover1 343:6675661fa600 183
rgrover1 343:6675661fa600 184 /**
rgrover1 343:6675661fa600 185 * @brief Power Control. (POWER)
rgrover1 343:6675661fa600 186 */
rgrover1 343:6675661fa600 187
rgrover1 343:6675661fa600 188 typedef struct { /*!< POWER Structure */
rgrover1 343:6675661fa600 189 __I uint32_t RESERVED0[30];
rgrover1 343:6675661fa600 190 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
rgrover1 343:6675661fa600 191 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
rgrover1 343:6675661fa600 192 __I uint32_t RESERVED1[34];
rgrover1 343:6675661fa600 193 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
rgrover1 343:6675661fa600 194 __I uint32_t RESERVED2[126];
rgrover1 343:6675661fa600 195 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 196 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 197 __I uint32_t RESERVED3[61];
rgrover1 343:6675661fa600 198 __IO uint32_t RESETREAS; /*!< Reset reason. */
rgrover1 343:6675661fa600 199 __I uint32_t RESERVED4[9];
rgrover1 343:6675661fa600 200 __I uint32_t RAMSTATUS; /*!< Ram status register. */
rgrover1 343:6675661fa600 201 __I uint32_t RESERVED5[53];
rgrover1 343:6675661fa600 202 __O uint32_t SYSTEMOFF; /*!< System off register. */
rgrover1 343:6675661fa600 203 __I uint32_t RESERVED6[3];
rgrover1 343:6675661fa600 204 __IO uint32_t POFCON; /*!< Power failure configuration. */
rgrover1 343:6675661fa600 205 __I uint32_t RESERVED7[2];
rgrover1 343:6675661fa600 206 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
rgrover1 343:6675661fa600 207 register. */
rgrover1 343:6675661fa600 208 __I uint32_t RESERVED8;
rgrover1 343:6675661fa600 209 __IO uint32_t RAMON; /*!< Ram on/off. */
rgrover1 343:6675661fa600 210 __I uint32_t RESERVED9[7];
rgrover1 343:6675661fa600 211 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
rgrover1 343:6675661fa600 212 is a retained register. */
rgrover1 343:6675661fa600 213 __I uint32_t RESERVED10[3];
rgrover1 343:6675661fa600 214 __IO uint32_t RAMONB; /*!< Ram on/off. */
rgrover1 343:6675661fa600 215 __I uint32_t RESERVED11[8];
rgrover1 343:6675661fa600 216 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
rgrover1 343:6675661fa600 217 __I uint32_t RESERVED12[291];
rgrover1 343:6675661fa600 218 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
rgrover1 343:6675661fa600 219 } NRF_POWER_Type;
rgrover1 343:6675661fa600 220
rgrover1 343:6675661fa600 221
rgrover1 343:6675661fa600 222 /* ================================================================================ */
rgrover1 343:6675661fa600 223 /* ================ CLOCK ================ */
rgrover1 343:6675661fa600 224 /* ================================================================================ */
rgrover1 343:6675661fa600 225
rgrover1 343:6675661fa600 226
rgrover1 343:6675661fa600 227 /**
rgrover1 343:6675661fa600 228 * @brief Clock control. (CLOCK)
rgrover1 343:6675661fa600 229 */
rgrover1 343:6675661fa600 230
rgrover1 343:6675661fa600 231 typedef struct { /*!< CLOCK Structure */
rgrover1 343:6675661fa600 232 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
rgrover1 343:6675661fa600 233 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
rgrover1 343:6675661fa600 234 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
rgrover1 343:6675661fa600 235 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
rgrover1 343:6675661fa600 236 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
rgrover1 343:6675661fa600 237 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
rgrover1 343:6675661fa600 238 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
rgrover1 343:6675661fa600 239 __I uint32_t RESERVED0[57];
rgrover1 343:6675661fa600 240 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
rgrover1 343:6675661fa600 241 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
rgrover1 343:6675661fa600 242 __I uint32_t RESERVED1;
rgrover1 343:6675661fa600 243 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
rgrover1 343:6675661fa600 244 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
rgrover1 343:6675661fa600 245 __I uint32_t RESERVED2[124];
rgrover1 343:6675661fa600 246 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 247 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 248 __I uint32_t RESERVED3[63];
rgrover1 343:6675661fa600 249 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
rgrover1 343:6675661fa600 250 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
rgrover1 343:6675661fa600 251 __I uint32_t RESERVED4;
rgrover1 343:6675661fa600 252 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
rgrover1 343:6675661fa600 253 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
rgrover1 343:6675661fa600 254 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
rgrover1 343:6675661fa600 255 triggered. */
rgrover1 343:6675661fa600 256 __I uint32_t RESERVED5[62];
rgrover1 343:6675661fa600 257 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
rgrover1 343:6675661fa600 258 __I uint32_t RESERVED6[7];
rgrover1 343:6675661fa600 259 __IO uint32_t CTIV; /*!< Calibration timer interval. */
rgrover1 343:6675661fa600 260 __I uint32_t RESERVED7[5];
rgrover1 343:6675661fa600 261 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
rgrover1 343:6675661fa600 262 } NRF_CLOCK_Type;
rgrover1 343:6675661fa600 263
rgrover1 343:6675661fa600 264
rgrover1 343:6675661fa600 265 /* ================================================================================ */
rgrover1 343:6675661fa600 266 /* ================ MPU ================ */
rgrover1 343:6675661fa600 267 /* ================================================================================ */
rgrover1 343:6675661fa600 268
rgrover1 343:6675661fa600 269
rgrover1 343:6675661fa600 270 /**
rgrover1 343:6675661fa600 271 * @brief Memory Protection Unit. (MPU)
rgrover1 343:6675661fa600 272 */
rgrover1 343:6675661fa600 273
rgrover1 343:6675661fa600 274 typedef struct { /*!< MPU Structure */
rgrover1 343:6675661fa600 275 __I uint32_t RESERVED0[330];
rgrover1 343:6675661fa600 276 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
rgrover1 343:6675661fa600 277 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
rgrover1 343:6675661fa600 278 __I uint32_t RESERVED1[52];
rgrover1 343:6675661fa600 279 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
rgrover1 343:6675661fa600 280 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
rgrover1 343:6675661fa600 281 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
rgrover1 343:6675661fa600 282 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
rgrover1 343:6675661fa600 283 } NRF_MPU_Type;
rgrover1 343:6675661fa600 284
rgrover1 343:6675661fa600 285
rgrover1 343:6675661fa600 286 /* ================================================================================ */
rgrover1 343:6675661fa600 287 /* ================ PU ================ */
rgrover1 343:6675661fa600 288 /* ================================================================================ */
rgrover1 343:6675661fa600 289
rgrover1 343:6675661fa600 290
rgrover1 343:6675661fa600 291 /**
rgrover1 343:6675661fa600 292 * @brief Patch unit. (PU)
rgrover1 343:6675661fa600 293 */
rgrover1 343:6675661fa600 294
rgrover1 343:6675661fa600 295 typedef struct { /*!< PU Structure */
rgrover1 343:6675661fa600 296 __I uint32_t RESERVED0[448];
rgrover1 343:6675661fa600 297 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
rgrover1 343:6675661fa600 298 __I uint32_t RESERVED1[24];
rgrover1 343:6675661fa600 299 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
rgrover1 343:6675661fa600 300 __I uint32_t RESERVED2[24];
rgrover1 343:6675661fa600 301 __IO uint32_t PATCHEN; /*!< Patch enable register. */
rgrover1 343:6675661fa600 302 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
rgrover1 343:6675661fa600 303 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
rgrover1 343:6675661fa600 304 } NRF_PU_Type;
rgrover1 343:6675661fa600 305
rgrover1 343:6675661fa600 306
rgrover1 343:6675661fa600 307 /* ================================================================================ */
rgrover1 343:6675661fa600 308 /* ================ AMLI ================ */
rgrover1 343:6675661fa600 309 /* ================================================================================ */
rgrover1 343:6675661fa600 310
rgrover1 343:6675661fa600 311
rgrover1 343:6675661fa600 312 /**
rgrover1 343:6675661fa600 313 * @brief AHB Multi-Layer Interface. (AMLI)
rgrover1 343:6675661fa600 314 */
rgrover1 343:6675661fa600 315
rgrover1 343:6675661fa600 316 typedef struct { /*!< AMLI Structure */
rgrover1 343:6675661fa600 317 __I uint32_t RESERVED0[896];
rgrover1 343:6675661fa600 318 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
rgrover1 343:6675661fa600 319 } NRF_AMLI_Type;
rgrover1 343:6675661fa600 320
rgrover1 343:6675661fa600 321
rgrover1 343:6675661fa600 322 /* ================================================================================ */
rgrover1 343:6675661fa600 323 /* ================ RADIO ================ */
rgrover1 343:6675661fa600 324 /* ================================================================================ */
rgrover1 343:6675661fa600 325
rgrover1 343:6675661fa600 326
rgrover1 343:6675661fa600 327 /**
rgrover1 343:6675661fa600 328 * @brief The radio. (RADIO)
rgrover1 343:6675661fa600 329 */
rgrover1 343:6675661fa600 330
rgrover1 343:6675661fa600 331 typedef struct { /*!< RADIO Structure */
rgrover1 343:6675661fa600 332 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
rgrover1 343:6675661fa600 333 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
rgrover1 343:6675661fa600 334 __O uint32_t TASKS_START; /*!< Start radio. */
rgrover1 343:6675661fa600 335 __O uint32_t TASKS_STOP; /*!< Stop radio. */
rgrover1 343:6675661fa600 336 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
rgrover1 343:6675661fa600 337 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
rgrover1 343:6675661fa600 338 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
rgrover1 343:6675661fa600 339 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
rgrover1 343:6675661fa600 340 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
rgrover1 343:6675661fa600 341 __I uint32_t RESERVED0[55];
rgrover1 343:6675661fa600 342 __IO uint32_t EVENTS_READY; /*!< Ready event. */
rgrover1 343:6675661fa600 343 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
rgrover1 343:6675661fa600 344 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
rgrover1 343:6675661fa600 345 __IO uint32_t EVENTS_END; /*!< End event. */
rgrover1 343:6675661fa600 346 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
rgrover1 343:6675661fa600 347 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
rgrover1 343:6675661fa600 348 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
rgrover1 343:6675661fa600 349 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
rgrover1 343:6675661fa600 350 sample is ready for readout at the RSSISAMPLE register. */
rgrover1 343:6675661fa600 351 __I uint32_t RESERVED1[2];
rgrover1 343:6675661fa600 352 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
rgrover1 343:6675661fa600 353 __I uint32_t RESERVED2[53];
rgrover1 343:6675661fa600 354 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
rgrover1 343:6675661fa600 355 __I uint32_t RESERVED3[64];
rgrover1 343:6675661fa600 356 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 357 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 358 __I uint32_t RESERVED4[61];
rgrover1 343:6675661fa600 359 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
rgrover1 343:6675661fa600 360 __I uint32_t CD; /*!< Carrier detect. */
rgrover1 343:6675661fa600 361 __I uint32_t RXMATCH; /*!< Received address. */
rgrover1 343:6675661fa600 362 __I uint32_t RXCRC; /*!< Received CRC. */
rgrover1 343:6675661fa600 363 __I uint32_t DAI; /*!< Device address match index. */
rgrover1 343:6675661fa600 364 __I uint32_t RESERVED5[60];
rgrover1 343:6675661fa600 365 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
rgrover1 343:6675661fa600 366 __IO uint32_t FREQUENCY; /*!< Frequency. */
rgrover1 343:6675661fa600 367 __IO uint32_t TXPOWER; /*!< Output power. */
rgrover1 343:6675661fa600 368 __IO uint32_t MODE; /*!< Data rate and modulation. */
rgrover1 343:6675661fa600 369 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
rgrover1 343:6675661fa600 370 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
rgrover1 343:6675661fa600 371 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
rgrover1 343:6675661fa600 372 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
rgrover1 343:6675661fa600 373 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
rgrover1 343:6675661fa600 374 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
rgrover1 343:6675661fa600 375 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
rgrover1 343:6675661fa600 376 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
rgrover1 343:6675661fa600 377 __IO uint32_t CRCCNF; /*!< CRC configuration. */
rgrover1 343:6675661fa600 378 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
rgrover1 343:6675661fa600 379 __IO uint32_t CRCINIT; /*!< CRC initial value. */
rgrover1 343:6675661fa600 380 __IO uint32_t TEST; /*!< Test features enable register. */
rgrover1 343:6675661fa600 381 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
rgrover1 343:6675661fa600 382 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
rgrover1 343:6675661fa600 383 __I uint32_t RESERVED6;
rgrover1 343:6675661fa600 384 __I uint32_t STATE; /*!< Current radio state. */
rgrover1 343:6675661fa600 385 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
rgrover1 343:6675661fa600 386 __I uint32_t RESERVED7[2];
rgrover1 343:6675661fa600 387 __IO uint32_t BCC; /*!< Bit counter compare. */
rgrover1 343:6675661fa600 388 __I uint32_t RESERVED8[39];
rgrover1 343:6675661fa600 389 __IO uint32_t DAB[8]; /*!< Device address base segment. */
rgrover1 343:6675661fa600 390 __IO uint32_t DAP[8]; /*!< Device address prefix. */
rgrover1 343:6675661fa600 391 __IO uint32_t DACNF; /*!< Device address match configuration. */
rgrover1 343:6675661fa600 392 __I uint32_t RESERVED9[56];
rgrover1 343:6675661fa600 393 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
rgrover1 343:6675661fa600 394 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
rgrover1 343:6675661fa600 395 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
rgrover1 343:6675661fa600 396 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
rgrover1 343:6675661fa600 397 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
rgrover1 343:6675661fa600 398 __I uint32_t RESERVED10[561];
rgrover1 343:6675661fa600 399 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 400 } NRF_RADIO_Type;
rgrover1 343:6675661fa600 401
rgrover1 343:6675661fa600 402
rgrover1 343:6675661fa600 403 /* ================================================================================ */
rgrover1 343:6675661fa600 404 /* ================ UART ================ */
rgrover1 343:6675661fa600 405 /* ================================================================================ */
rgrover1 343:6675661fa600 406
rgrover1 343:6675661fa600 407
rgrover1 343:6675661fa600 408 /**
rgrover1 343:6675661fa600 409 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
rgrover1 343:6675661fa600 410 */
rgrover1 343:6675661fa600 411
rgrover1 343:6675661fa600 412 typedef struct { /*!< UART Structure */
rgrover1 343:6675661fa600 413 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
rgrover1 343:6675661fa600 414 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
rgrover1 343:6675661fa600 415 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
rgrover1 343:6675661fa600 416 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
rgrover1 343:6675661fa600 417 __I uint32_t RESERVED0[3];
rgrover1 343:6675661fa600 418 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
rgrover1 343:6675661fa600 419 __I uint32_t RESERVED1[56];
rgrover1 343:6675661fa600 420 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
rgrover1 343:6675661fa600 421 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
rgrover1 343:6675661fa600 422 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
rgrover1 343:6675661fa600 423 __I uint32_t RESERVED2[4];
rgrover1 343:6675661fa600 424 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
rgrover1 343:6675661fa600 425 __I uint32_t RESERVED3;
rgrover1 343:6675661fa600 426 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
rgrover1 343:6675661fa600 427 __I uint32_t RESERVED4[7];
rgrover1 343:6675661fa600 428 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
rgrover1 343:6675661fa600 429 __I uint32_t RESERVED5[46];
rgrover1 343:6675661fa600 430 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
rgrover1 343:6675661fa600 431 __I uint32_t RESERVED6[64];
rgrover1 343:6675661fa600 432 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 433 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 434 __I uint32_t RESERVED7[93];
rgrover1 343:6675661fa600 435 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
rgrover1 343:6675661fa600 436 __I uint32_t RESERVED8[31];
rgrover1 343:6675661fa600 437 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
rgrover1 343:6675661fa600 438 __I uint32_t RESERVED9;
rgrover1 343:6675661fa600 439 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
rgrover1 343:6675661fa600 440 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
rgrover1 343:6675661fa600 441 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
rgrover1 343:6675661fa600 442 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
rgrover1 343:6675661fa600 443 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
rgrover1 343:6675661fa600 444 Once read the character is consumed. If read when no character
rgrover1 343:6675661fa600 445 available, the UART will stop working. */
rgrover1 343:6675661fa600 446 __O uint32_t TXD; /*!< TXD register. */
rgrover1 343:6675661fa600 447 __I uint32_t RESERVED10;
rgrover1 343:6675661fa600 448 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
rgrover1 343:6675661fa600 449 __I uint32_t RESERVED11[17];
rgrover1 343:6675661fa600 450 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
rgrover1 343:6675661fa600 451 __I uint32_t RESERVED12[675];
rgrover1 343:6675661fa600 452 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 453 } NRF_UART_Type;
rgrover1 343:6675661fa600 454
rgrover1 343:6675661fa600 455
rgrover1 343:6675661fa600 456 /* ================================================================================ */
rgrover1 343:6675661fa600 457 /* ================ SPI ================ */
rgrover1 343:6675661fa600 458 /* ================================================================================ */
rgrover1 343:6675661fa600 459
rgrover1 343:6675661fa600 460
rgrover1 343:6675661fa600 461 /**
rgrover1 343:6675661fa600 462 * @brief SPI master 0. (SPI)
rgrover1 343:6675661fa600 463 */
rgrover1 343:6675661fa600 464
rgrover1 343:6675661fa600 465 typedef struct { /*!< SPI Structure */
rgrover1 343:6675661fa600 466 __I uint32_t RESERVED0[66];
rgrover1 343:6675661fa600 467 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
rgrover1 343:6675661fa600 468 __I uint32_t RESERVED1[126];
rgrover1 343:6675661fa600 469 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 470 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 471 __I uint32_t RESERVED2[125];
rgrover1 343:6675661fa600 472 __IO uint32_t ENABLE; /*!< Enable SPI. */
rgrover1 343:6675661fa600 473 __I uint32_t RESERVED3;
rgrover1 343:6675661fa600 474 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 343:6675661fa600 475 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 343:6675661fa600 476 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 343:6675661fa600 477 __I uint32_t RESERVED4;
rgrover1 343:6675661fa600 478 __I uint32_t RXD; /*!< RX data. */
rgrover1 343:6675661fa600 479 __IO uint32_t TXD; /*!< TX data. */
rgrover1 343:6675661fa600 480 __I uint32_t RESERVED5;
rgrover1 343:6675661fa600 481 __IO uint32_t FREQUENCY; /*!< SPI frequency */
rgrover1 343:6675661fa600 482 __I uint32_t RESERVED6[11];
rgrover1 343:6675661fa600 483 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 343:6675661fa600 484 __I uint32_t RESERVED7[681];
rgrover1 343:6675661fa600 485 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 486 } NRF_SPI_Type;
rgrover1 343:6675661fa600 487
rgrover1 343:6675661fa600 488
rgrover1 343:6675661fa600 489 /* ================================================================================ */
rgrover1 343:6675661fa600 490 /* ================ TWI ================ */
rgrover1 343:6675661fa600 491 /* ================================================================================ */
rgrover1 343:6675661fa600 492
rgrover1 343:6675661fa600 493
rgrover1 343:6675661fa600 494 /**
rgrover1 343:6675661fa600 495 * @brief Two-wire interface master 0. (TWI)
rgrover1 343:6675661fa600 496 */
rgrover1 343:6675661fa600 497
rgrover1 343:6675661fa600 498 typedef struct { /*!< TWI Structure */
rgrover1 343:6675661fa600 499 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
rgrover1 343:6675661fa600 500 __I uint32_t RESERVED0;
rgrover1 343:6675661fa600 501 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
rgrover1 343:6675661fa600 502 __I uint32_t RESERVED1[2];
rgrover1 343:6675661fa600 503 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
rgrover1 343:6675661fa600 504 __I uint32_t RESERVED2;
rgrover1 343:6675661fa600 505 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
rgrover1 343:6675661fa600 506 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
rgrover1 343:6675661fa600 507 __I uint32_t RESERVED3[56];
rgrover1 343:6675661fa600 508 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
rgrover1 343:6675661fa600 509 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
rgrover1 343:6675661fa600 510 __I uint32_t RESERVED4[4];
rgrover1 343:6675661fa600 511 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
rgrover1 343:6675661fa600 512 __I uint32_t RESERVED5;
rgrover1 343:6675661fa600 513 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
rgrover1 343:6675661fa600 514 __I uint32_t RESERVED6[4];
rgrover1 343:6675661fa600 515 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
rgrover1 343:6675661fa600 516 __I uint32_t RESERVED7[3];
rgrover1 343:6675661fa600 517 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
rgrover1 343:6675661fa600 518 __I uint32_t RESERVED8[45];
rgrover1 343:6675661fa600 519 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
rgrover1 343:6675661fa600 520 __I uint32_t RESERVED9[64];
rgrover1 343:6675661fa600 521 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 522 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 523 __I uint32_t RESERVED10[110];
rgrover1 343:6675661fa600 524 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
rgrover1 343:6675661fa600 525 __I uint32_t RESERVED11[14];
rgrover1 343:6675661fa600 526 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
rgrover1 343:6675661fa600 527 __I uint32_t RESERVED12;
rgrover1 343:6675661fa600 528 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
rgrover1 343:6675661fa600 529 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
rgrover1 343:6675661fa600 530 __I uint32_t RESERVED13[2];
rgrover1 343:6675661fa600 531 __I uint32_t RXD; /*!< RX data register. */
rgrover1 343:6675661fa600 532 __IO uint32_t TXD; /*!< TX data register. */
rgrover1 343:6675661fa600 533 __I uint32_t RESERVED14;
rgrover1 343:6675661fa600 534 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
rgrover1 343:6675661fa600 535 __I uint32_t RESERVED15[24];
rgrover1 343:6675661fa600 536 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
rgrover1 343:6675661fa600 537 __I uint32_t RESERVED16[668];
rgrover1 343:6675661fa600 538 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 539 } NRF_TWI_Type;
rgrover1 343:6675661fa600 540
rgrover1 343:6675661fa600 541
rgrover1 343:6675661fa600 542 /* ================================================================================ */
rgrover1 343:6675661fa600 543 /* ================ SPIS ================ */
rgrover1 343:6675661fa600 544 /* ================================================================================ */
rgrover1 343:6675661fa600 545
rgrover1 343:6675661fa600 546
rgrover1 343:6675661fa600 547 /**
rgrover1 343:6675661fa600 548 * @brief SPI slave 1. (SPIS)
rgrover1 343:6675661fa600 549 */
rgrover1 343:6675661fa600 550
rgrover1 343:6675661fa600 551 typedef struct { /*!< SPIS Structure */
rgrover1 343:6675661fa600 552 __I uint32_t RESERVED0[9];
rgrover1 343:6675661fa600 553 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
rgrover1 343:6675661fa600 554 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
rgrover1 343:6675661fa600 555 __I uint32_t RESERVED1[54];
rgrover1 343:6675661fa600 556 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
rgrover1 343:6675661fa600 557 __I uint32_t RESERVED2[8];
rgrover1 343:6675661fa600 558 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
rgrover1 343:6675661fa600 559 __I uint32_t RESERVED3[53];
rgrover1 343:6675661fa600 560 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
rgrover1 343:6675661fa600 561 __I uint32_t RESERVED4[64];
rgrover1 343:6675661fa600 562 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 563 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 564 __I uint32_t RESERVED5[61];
rgrover1 343:6675661fa600 565 __I uint32_t SEMSTAT; /*!< Semaphore status. */
rgrover1 343:6675661fa600 566 __I uint32_t RESERVED6[15];
rgrover1 343:6675661fa600 567 __IO uint32_t STATUS; /*!< Status from last transaction. */
rgrover1 343:6675661fa600 568 __I uint32_t RESERVED7[47];
rgrover1 343:6675661fa600 569 __IO uint32_t ENABLE; /*!< Enable SPIS. */
rgrover1 343:6675661fa600 570 __I uint32_t RESERVED8;
rgrover1 343:6675661fa600 571 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 343:6675661fa600 572 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 343:6675661fa600 573 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 343:6675661fa600 574 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
rgrover1 343:6675661fa600 575 __I uint32_t RESERVED9[7];
rgrover1 343:6675661fa600 576 __IO uint32_t RXDPTR; /*!< RX data pointer. */
rgrover1 343:6675661fa600 577 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
rgrover1 343:6675661fa600 578 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
rgrover1 343:6675661fa600 579 __I uint32_t RESERVED10;
rgrover1 343:6675661fa600 580 __IO uint32_t TXDPTR; /*!< TX data pointer. */
rgrover1 343:6675661fa600 581 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
rgrover1 343:6675661fa600 582 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
rgrover1 343:6675661fa600 583 __I uint32_t RESERVED11;
rgrover1 343:6675661fa600 584 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 343:6675661fa600 585 __I uint32_t RESERVED12;
rgrover1 343:6675661fa600 586 __IO uint32_t DEF; /*!< Default character. */
rgrover1 343:6675661fa600 587 __I uint32_t RESERVED13[24];
rgrover1 343:6675661fa600 588 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 343:6675661fa600 589 __I uint32_t RESERVED14[654];
rgrover1 343:6675661fa600 590 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 591 } NRF_SPIS_Type;
rgrover1 343:6675661fa600 592
rgrover1 343:6675661fa600 593
rgrover1 343:6675661fa600 594 /* ================================================================================ */
rgrover1 343:6675661fa600 595 /* ================ SPIM ================ */
rgrover1 343:6675661fa600 596 /* ================================================================================ */
rgrover1 343:6675661fa600 597
rgrover1 343:6675661fa600 598
rgrover1 343:6675661fa600 599 /**
rgrover1 343:6675661fa600 600 * @brief SPI master with easyDMA 1. (SPIM)
rgrover1 343:6675661fa600 601 */
rgrover1 343:6675661fa600 602
rgrover1 343:6675661fa600 603 typedef struct { /*!< SPIM Structure */
rgrover1 343:6675661fa600 604 __I uint32_t RESERVED0[4];
rgrover1 343:6675661fa600 605 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
rgrover1 343:6675661fa600 606 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
rgrover1 343:6675661fa600 607 __I uint32_t RESERVED1;
rgrover1 343:6675661fa600 608 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
rgrover1 343:6675661fa600 609 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
rgrover1 343:6675661fa600 610 __I uint32_t RESERVED2[56];
rgrover1 343:6675661fa600 611 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
rgrover1 343:6675661fa600 612 __I uint32_t RESERVED3[2];
rgrover1 343:6675661fa600 613 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
rgrover1 343:6675661fa600 614 __I uint32_t RESERVED4;
rgrover1 343:6675661fa600 615 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
rgrover1 343:6675661fa600 616 __I uint32_t RESERVED5;
rgrover1 343:6675661fa600 617 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
rgrover1 343:6675661fa600 618 __I uint32_t RESERVED6[10];
rgrover1 343:6675661fa600 619 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
rgrover1 343:6675661fa600 620 __I uint32_t RESERVED7[44];
rgrover1 343:6675661fa600 621 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
rgrover1 343:6675661fa600 622 __I uint32_t RESERVED8[64];
rgrover1 343:6675661fa600 623 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 624 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 625 __I uint32_t RESERVED9[125];
rgrover1 343:6675661fa600 626 __IO uint32_t ENABLE; /*!< Enable SPIM. */
rgrover1 343:6675661fa600 627 __I uint32_t RESERVED10;
rgrover1 343:6675661fa600 628 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
rgrover1 343:6675661fa600 629 __I uint32_t RESERVED11;
rgrover1 343:6675661fa600 630 __I uint32_t RXDDATA; /*!< RXD register. */
rgrover1 343:6675661fa600 631 __IO uint32_t TXDDATA; /*!< TXD register. */
rgrover1 343:6675661fa600 632 __I uint32_t RESERVED12;
rgrover1 343:6675661fa600 633 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
rgrover1 343:6675661fa600 634 __I uint32_t RESERVED13[3];
rgrover1 343:6675661fa600 635 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
rgrover1 343:6675661fa600 636 __I uint32_t RESERVED14;
rgrover1 343:6675661fa600 637 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
rgrover1 343:6675661fa600 638 __I uint32_t RESERVED15;
rgrover1 343:6675661fa600 639 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 343:6675661fa600 640 __I uint32_t RESERVED16[26];
rgrover1 343:6675661fa600 641 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 343:6675661fa600 642 __I uint32_t RESERVED17[654];
rgrover1 343:6675661fa600 643 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 644 } NRF_SPIM_Type;
rgrover1 343:6675661fa600 645
rgrover1 343:6675661fa600 646
rgrover1 343:6675661fa600 647 /* ================================================================================ */
rgrover1 343:6675661fa600 648 /* ================ GPIOTE ================ */
rgrover1 343:6675661fa600 649 /* ================================================================================ */
rgrover1 343:6675661fa600 650
rgrover1 343:6675661fa600 651
rgrover1 343:6675661fa600 652 /**
rgrover1 343:6675661fa600 653 * @brief GPIO tasks and events. (GPIOTE)
rgrover1 343:6675661fa600 654 */
rgrover1 343:6675661fa600 655
rgrover1 343:6675661fa600 656 typedef struct { /*!< GPIOTE Structure */
rgrover1 343:6675661fa600 657 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 343:6675661fa600 658 __I uint32_t RESERVED0[60];
rgrover1 343:6675661fa600 659 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 343:6675661fa600 660 __I uint32_t RESERVED1[27];
rgrover1 343:6675661fa600 661 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
rgrover1 343:6675661fa600 662 __I uint32_t RESERVED2[97];
rgrover1 343:6675661fa600 663 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 664 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 665 __I uint32_t RESERVED3[129];
rgrover1 343:6675661fa600 666 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
rgrover1 343:6675661fa600 667 __I uint32_t RESERVED4[695];
rgrover1 343:6675661fa600 668 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 669 } NRF_GPIOTE_Type;
rgrover1 343:6675661fa600 670
rgrover1 343:6675661fa600 671
rgrover1 343:6675661fa600 672 /* ================================================================================ */
rgrover1 343:6675661fa600 673 /* ================ ADC ================ */
rgrover1 343:6675661fa600 674 /* ================================================================================ */
rgrover1 343:6675661fa600 675
rgrover1 343:6675661fa600 676
rgrover1 343:6675661fa600 677 /**
rgrover1 343:6675661fa600 678 * @brief Analog to digital converter. (ADC)
rgrover1 343:6675661fa600 679 */
rgrover1 343:6675661fa600 680
rgrover1 343:6675661fa600 681 typedef struct { /*!< ADC Structure */
rgrover1 343:6675661fa600 682 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
rgrover1 343:6675661fa600 683 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
rgrover1 343:6675661fa600 684 __I uint32_t RESERVED0[62];
rgrover1 343:6675661fa600 685 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
rgrover1 343:6675661fa600 686 __I uint32_t RESERVED1[128];
rgrover1 343:6675661fa600 687 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 688 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 689 __I uint32_t RESERVED2[61];
rgrover1 343:6675661fa600 690 __I uint32_t BUSY; /*!< ADC busy register. */
rgrover1 343:6675661fa600 691 __I uint32_t RESERVED3[63];
rgrover1 343:6675661fa600 692 __IO uint32_t ENABLE; /*!< ADC enable. */
rgrover1 343:6675661fa600 693 __IO uint32_t CONFIG; /*!< ADC configuration register. */
rgrover1 343:6675661fa600 694 __I uint32_t RESULT; /*!< Result of ADC conversion. */
rgrover1 343:6675661fa600 695 __I uint32_t RESERVED4[700];
rgrover1 343:6675661fa600 696 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 697 } NRF_ADC_Type;
rgrover1 343:6675661fa600 698
rgrover1 343:6675661fa600 699
rgrover1 343:6675661fa600 700 /* ================================================================================ */
rgrover1 343:6675661fa600 701 /* ================ TIMER ================ */
rgrover1 343:6675661fa600 702 /* ================================================================================ */
rgrover1 343:6675661fa600 703
rgrover1 343:6675661fa600 704
rgrover1 343:6675661fa600 705 /**
rgrover1 343:6675661fa600 706 * @brief Timer 0. (TIMER)
rgrover1 343:6675661fa600 707 */
rgrover1 343:6675661fa600 708
rgrover1 343:6675661fa600 709 typedef struct { /*!< TIMER Structure */
rgrover1 343:6675661fa600 710 __O uint32_t TASKS_START; /*!< Start Timer. */
rgrover1 343:6675661fa600 711 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
rgrover1 343:6675661fa600 712 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
rgrover1 343:6675661fa600 713 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
rgrover1 343:6675661fa600 714 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
rgrover1 343:6675661fa600 715 __I uint32_t RESERVED0[11];
rgrover1 343:6675661fa600 716 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
rgrover1 343:6675661fa600 717 __I uint32_t RESERVED1[60];
rgrover1 343:6675661fa600 718 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 343:6675661fa600 719 __I uint32_t RESERVED2[44];
rgrover1 343:6675661fa600 720 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
rgrover1 343:6675661fa600 721 __I uint32_t RESERVED3[64];
rgrover1 343:6675661fa600 722 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 723 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 724 __I uint32_t RESERVED4[126];
rgrover1 343:6675661fa600 725 __IO uint32_t MODE; /*!< Timer Mode selection. */
rgrover1 343:6675661fa600 726 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
rgrover1 343:6675661fa600 727 __I uint32_t RESERVED5;
rgrover1 343:6675661fa600 728 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
rgrover1 343:6675661fa600 729 clock frequency is divided by 2^SCALE. */
rgrover1 343:6675661fa600 730 __I uint32_t RESERVED6[11];
rgrover1 343:6675661fa600 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 343:6675661fa600 732 __I uint32_t RESERVED7[683];
rgrover1 343:6675661fa600 733 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 734 } NRF_TIMER_Type;
rgrover1 343:6675661fa600 735
rgrover1 343:6675661fa600 736
rgrover1 343:6675661fa600 737 /* ================================================================================ */
rgrover1 343:6675661fa600 738 /* ================ RTC ================ */
rgrover1 343:6675661fa600 739 /* ================================================================================ */
rgrover1 343:6675661fa600 740
rgrover1 343:6675661fa600 741
rgrover1 343:6675661fa600 742 /**
rgrover1 343:6675661fa600 743 * @brief Real time counter 0. (RTC)
rgrover1 343:6675661fa600 744 */
rgrover1 343:6675661fa600 745
rgrover1 343:6675661fa600 746 typedef struct { /*!< RTC Structure */
rgrover1 343:6675661fa600 747 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
rgrover1 343:6675661fa600 748 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
rgrover1 343:6675661fa600 749 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
rgrover1 343:6675661fa600 750 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
rgrover1 343:6675661fa600 751 __I uint32_t RESERVED0[60];
rgrover1 343:6675661fa600 752 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
rgrover1 343:6675661fa600 753 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
rgrover1 343:6675661fa600 754 __I uint32_t RESERVED1[14];
rgrover1 343:6675661fa600 755 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 343:6675661fa600 756 __I uint32_t RESERVED2[109];
rgrover1 343:6675661fa600 757 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 758 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 759 __I uint32_t RESERVED3[13];
rgrover1 343:6675661fa600 760 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
rgrover1 343:6675661fa600 761 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
rgrover1 343:6675661fa600 762 the value of EVTEN. */
rgrover1 343:6675661fa600 763 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
rgrover1 343:6675661fa600 764 gives the value of EVTEN. */
rgrover1 343:6675661fa600 765 __I uint32_t RESERVED4[110];
rgrover1 343:6675661fa600 766 __I uint32_t COUNTER; /*!< Current COUNTER value. */
rgrover1 343:6675661fa600 767 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
rgrover1 343:6675661fa600 768 Must be written when RTC is STOPed. */
rgrover1 343:6675661fa600 769 __I uint32_t RESERVED5[13];
rgrover1 343:6675661fa600 770 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 343:6675661fa600 771 __I uint32_t RESERVED6[683];
rgrover1 343:6675661fa600 772 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 773 } NRF_RTC_Type;
rgrover1 343:6675661fa600 774
rgrover1 343:6675661fa600 775
rgrover1 343:6675661fa600 776 /* ================================================================================ */
rgrover1 343:6675661fa600 777 /* ================ TEMP ================ */
rgrover1 343:6675661fa600 778 /* ================================================================================ */
rgrover1 343:6675661fa600 779
rgrover1 343:6675661fa600 780
rgrover1 343:6675661fa600 781 /**
rgrover1 343:6675661fa600 782 * @brief Temperature Sensor. (TEMP)
rgrover1 343:6675661fa600 783 */
rgrover1 343:6675661fa600 784
rgrover1 343:6675661fa600 785 typedef struct { /*!< TEMP Structure */
rgrover1 343:6675661fa600 786 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
rgrover1 343:6675661fa600 787 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
rgrover1 343:6675661fa600 788 __I uint32_t RESERVED0[62];
rgrover1 343:6675661fa600 789 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
rgrover1 343:6675661fa600 790 __I uint32_t RESERVED1[128];
rgrover1 343:6675661fa600 791 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 792 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 793 __I uint32_t RESERVED2[127];
rgrover1 343:6675661fa600 794 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
rgrover1 343:6675661fa600 795 __I uint32_t RESERVED3[700];
rgrover1 343:6675661fa600 796 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 797 } NRF_TEMP_Type;
rgrover1 343:6675661fa600 798
rgrover1 343:6675661fa600 799
rgrover1 343:6675661fa600 800 /* ================================================================================ */
rgrover1 343:6675661fa600 801 /* ================ RNG ================ */
rgrover1 343:6675661fa600 802 /* ================================================================================ */
rgrover1 343:6675661fa600 803
rgrover1 343:6675661fa600 804
rgrover1 343:6675661fa600 805 /**
rgrover1 343:6675661fa600 806 * @brief Random Number Generator. (RNG)
rgrover1 343:6675661fa600 807 */
rgrover1 343:6675661fa600 808
rgrover1 343:6675661fa600 809 typedef struct { /*!< RNG Structure */
rgrover1 343:6675661fa600 810 __O uint32_t TASKS_START; /*!< Start the random number generator. */
rgrover1 343:6675661fa600 811 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
rgrover1 343:6675661fa600 812 __I uint32_t RESERVED0[62];
rgrover1 343:6675661fa600 813 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
rgrover1 343:6675661fa600 814 __I uint32_t RESERVED1[63];
rgrover1 343:6675661fa600 815 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
rgrover1 343:6675661fa600 816 __I uint32_t RESERVED2[64];
rgrover1 343:6675661fa600 817 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
rgrover1 343:6675661fa600 818 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
rgrover1 343:6675661fa600 819 __I uint32_t RESERVED3[126];
rgrover1 343:6675661fa600 820 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 343:6675661fa600 821 __I uint32_t VALUE; /*!< RNG random number. */
rgrover1 343:6675661fa600 822 __I uint32_t RESERVED4[700];
rgrover1 343:6675661fa600 823 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 824 } NRF_RNG_Type;
rgrover1 343:6675661fa600 825
rgrover1 343:6675661fa600 826
rgrover1 343:6675661fa600 827 /* ================================================================================ */
rgrover1 343:6675661fa600 828 /* ================ ECB ================ */
rgrover1 343:6675661fa600 829 /* ================================================================================ */
rgrover1 343:6675661fa600 830
rgrover1 343:6675661fa600 831
rgrover1 343:6675661fa600 832 /**
rgrover1 343:6675661fa600 833 * @brief AES ECB Mode Encryption. (ECB)
rgrover1 343:6675661fa600 834 */
rgrover1 343:6675661fa600 835
rgrover1 343:6675661fa600 836 typedef struct { /*!< ECB Structure */
rgrover1 343:6675661fa600 837 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
rgrover1 343:6675661fa600 838 will not initiate a new encryption and the ERRORECB event will
rgrover1 343:6675661fa600 839 be triggered. */
rgrover1 343:6675661fa600 840 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
rgrover1 343:6675661fa600 841 this will will trigger the ERRORECB event. */
rgrover1 343:6675661fa600 842 __I uint32_t RESERVED0[62];
rgrover1 343:6675661fa600 843 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
rgrover1 343:6675661fa600 844 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
rgrover1 343:6675661fa600 845 error. */
rgrover1 343:6675661fa600 846 __I uint32_t RESERVED1[127];
rgrover1 343:6675661fa600 847 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 848 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 849 __I uint32_t RESERVED2[126];
rgrover1 343:6675661fa600 850 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
rgrover1 343:6675661fa600 851 __I uint32_t RESERVED3[701];
rgrover1 343:6675661fa600 852 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 853 } NRF_ECB_Type;
rgrover1 343:6675661fa600 854
rgrover1 343:6675661fa600 855
rgrover1 343:6675661fa600 856 /* ================================================================================ */
rgrover1 343:6675661fa600 857 /* ================ AAR ================ */
rgrover1 343:6675661fa600 858 /* ================================================================================ */
rgrover1 343:6675661fa600 859
rgrover1 343:6675661fa600 860
rgrover1 343:6675661fa600 861 /**
rgrover1 343:6675661fa600 862 * @brief Accelerated Address Resolver. (AAR)
rgrover1 343:6675661fa600 863 */
rgrover1 343:6675661fa600 864
rgrover1 343:6675661fa600 865 typedef struct { /*!< AAR Structure */
rgrover1 343:6675661fa600 866 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
rgrover1 343:6675661fa600 867 data structure. */
rgrover1 343:6675661fa600 868 __I uint32_t RESERVED0;
rgrover1 343:6675661fa600 869 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
rgrover1 343:6675661fa600 870 __I uint32_t RESERVED1[61];
rgrover1 343:6675661fa600 871 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
rgrover1 343:6675661fa600 872 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
rgrover1 343:6675661fa600 873 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
rgrover1 343:6675661fa600 874 __I uint32_t RESERVED2[126];
rgrover1 343:6675661fa600 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 877 __I uint32_t RESERVED3[61];
rgrover1 343:6675661fa600 878 __I uint32_t STATUS; /*!< Resolution status. */
rgrover1 343:6675661fa600 879 __I uint32_t RESERVED4[63];
rgrover1 343:6675661fa600 880 __IO uint32_t ENABLE; /*!< Enable AAR. */
rgrover1 343:6675661fa600 881 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
rgrover1 343:6675661fa600 882 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
rgrover1 343:6675661fa600 883 __I uint32_t RESERVED5;
rgrover1 343:6675661fa600 884 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
rgrover1 343:6675661fa600 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 343:6675661fa600 886 during resolution. A minimum of 3 bytes must be reserved. */
rgrover1 343:6675661fa600 887 __I uint32_t RESERVED6[697];
rgrover1 343:6675661fa600 888 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 889 } NRF_AAR_Type;
rgrover1 343:6675661fa600 890
rgrover1 343:6675661fa600 891
rgrover1 343:6675661fa600 892 /* ================================================================================ */
rgrover1 343:6675661fa600 893 /* ================ CCM ================ */
rgrover1 343:6675661fa600 894 /* ================================================================================ */
rgrover1 343:6675661fa600 895
rgrover1 343:6675661fa600 896
rgrover1 343:6675661fa600 897 /**
rgrover1 343:6675661fa600 898 * @brief AES CCM Mode Encryption. (CCM)
rgrover1 343:6675661fa600 899 */
rgrover1 343:6675661fa600 900
rgrover1 343:6675661fa600 901 typedef struct { /*!< CCM Structure */
rgrover1 343:6675661fa600 902 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
rgrover1 343:6675661fa600 903 itself when completed. */
rgrover1 343:6675661fa600 904 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
rgrover1 343:6675661fa600 905 completed. */
rgrover1 343:6675661fa600 906 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
rgrover1 343:6675661fa600 907 __I uint32_t RESERVED0[61];
rgrover1 343:6675661fa600 908 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
rgrover1 343:6675661fa600 909 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
rgrover1 343:6675661fa600 910 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
rgrover1 343:6675661fa600 911 __I uint32_t RESERVED1[61];
rgrover1 343:6675661fa600 912 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
rgrover1 343:6675661fa600 913 __I uint32_t RESERVED2[64];
rgrover1 343:6675661fa600 914 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 915 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 916 __I uint32_t RESERVED3[61];
rgrover1 343:6675661fa600 917 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
rgrover1 343:6675661fa600 918 __I uint32_t RESERVED4[63];
rgrover1 343:6675661fa600 919 __IO uint32_t ENABLE; /*!< CCM enable. */
rgrover1 343:6675661fa600 920 __IO uint32_t MODE; /*!< Operation mode. */
rgrover1 343:6675661fa600 921 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
rgrover1 343:6675661fa600 922 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
rgrover1 343:6675661fa600 923 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
rgrover1 343:6675661fa600 924 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 343:6675661fa600 925 during resolution. A minimum of 43 bytes must be reserved. */
rgrover1 343:6675661fa600 926 __I uint32_t RESERVED5[697];
rgrover1 343:6675661fa600 927 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 928 } NRF_CCM_Type;
rgrover1 343:6675661fa600 929
rgrover1 343:6675661fa600 930
rgrover1 343:6675661fa600 931 /* ================================================================================ */
rgrover1 343:6675661fa600 932 /* ================ WDT ================ */
rgrover1 343:6675661fa600 933 /* ================================================================================ */
rgrover1 343:6675661fa600 934
rgrover1 343:6675661fa600 935
rgrover1 343:6675661fa600 936 /**
rgrover1 343:6675661fa600 937 * @brief Watchdog Timer. (WDT)
rgrover1 343:6675661fa600 938 */
rgrover1 343:6675661fa600 939
rgrover1 343:6675661fa600 940 typedef struct { /*!< WDT Structure */
rgrover1 343:6675661fa600 941 __O uint32_t TASKS_START; /*!< Start the watchdog. */
rgrover1 343:6675661fa600 942 __I uint32_t RESERVED0[63];
rgrover1 343:6675661fa600 943 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
rgrover1 343:6675661fa600 944 __I uint32_t RESERVED1[128];
rgrover1 343:6675661fa600 945 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 946 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 947 __I uint32_t RESERVED2[61];
rgrover1 343:6675661fa600 948 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
rgrover1 343:6675661fa600 949 __I uint32_t REQSTATUS; /*!< Request status. */
rgrover1 343:6675661fa600 950 __I uint32_t RESERVED3[63];
rgrover1 343:6675661fa600 951 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
rgrover1 343:6675661fa600 952 __IO uint32_t RREN; /*!< Reload request enable. */
rgrover1 343:6675661fa600 953 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 343:6675661fa600 954 __I uint32_t RESERVED4[60];
rgrover1 343:6675661fa600 955 __O uint32_t RR[8]; /*!< Reload requests registers. */
rgrover1 343:6675661fa600 956 __I uint32_t RESERVED5[631];
rgrover1 343:6675661fa600 957 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 958 } NRF_WDT_Type;
rgrover1 343:6675661fa600 959
rgrover1 343:6675661fa600 960
rgrover1 343:6675661fa600 961 /* ================================================================================ */
rgrover1 343:6675661fa600 962 /* ================ QDEC ================ */
rgrover1 343:6675661fa600 963 /* ================================================================================ */
rgrover1 343:6675661fa600 964
rgrover1 343:6675661fa600 965
rgrover1 343:6675661fa600 966 /**
rgrover1 343:6675661fa600 967 * @brief Rotary decoder. (QDEC)
rgrover1 343:6675661fa600 968 */
rgrover1 343:6675661fa600 969
rgrover1 343:6675661fa600 970 typedef struct { /*!< QDEC Structure */
rgrover1 343:6675661fa600 971 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
rgrover1 343:6675661fa600 972 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
rgrover1 343:6675661fa600 973 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
rgrover1 343:6675661fa600 974 and clears the ACC registers. */
rgrover1 343:6675661fa600 975 __I uint32_t RESERVED0[61];
rgrover1 343:6675661fa600 976 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
rgrover1 343:6675661fa600 977 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
rgrover1 343:6675661fa600 978 ACC register different than zero. */
rgrover1 343:6675661fa600 979 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
rgrover1 343:6675661fa600 980 __I uint32_t RESERVED1[61];
rgrover1 343:6675661fa600 981 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
rgrover1 343:6675661fa600 982 __I uint32_t RESERVED2[64];
rgrover1 343:6675661fa600 983 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 984 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 985 __I uint32_t RESERVED3[125];
rgrover1 343:6675661fa600 986 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
rgrover1 343:6675661fa600 987 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
rgrover1 343:6675661fa600 988 __IO uint32_t SAMPLEPER; /*!< Sample period. */
rgrover1 343:6675661fa600 989 __I int32_t SAMPLE; /*!< Motion sample value. */
rgrover1 343:6675661fa600 990 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 343:6675661fa600 991 __I int32_t ACC; /*!< Accumulated valid transitions register. */
rgrover1 343:6675661fa600 992 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
rgrover1 343:6675661fa600 993 task. */
rgrover1 343:6675661fa600 994 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
rgrover1 343:6675661fa600 995 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
rgrover1 343:6675661fa600 996 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
rgrover1 343:6675661fa600 997 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
rgrover1 343:6675661fa600 998 __I uint32_t RESERVED4[5];
rgrover1 343:6675661fa600 999 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
rgrover1 343:6675661fa600 1000 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
rgrover1 343:6675661fa600 1001 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
rgrover1 343:6675661fa600 1002 task. */
rgrover1 343:6675661fa600 1003 __I uint32_t RESERVED5[684];
rgrover1 343:6675661fa600 1004 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 1005 } NRF_QDEC_Type;
rgrover1 343:6675661fa600 1006
rgrover1 343:6675661fa600 1007
rgrover1 343:6675661fa600 1008 /* ================================================================================ */
rgrover1 343:6675661fa600 1009 /* ================ LPCOMP ================ */
rgrover1 343:6675661fa600 1010 /* ================================================================================ */
rgrover1 343:6675661fa600 1011
rgrover1 343:6675661fa600 1012
rgrover1 343:6675661fa600 1013 /**
rgrover1 343:6675661fa600 1014 * @brief Low power comparator. (LPCOMP)
rgrover1 343:6675661fa600 1015 */
rgrover1 343:6675661fa600 1016
rgrover1 343:6675661fa600 1017 typedef struct { /*!< LPCOMP Structure */
rgrover1 343:6675661fa600 1018 __O uint32_t TASKS_START; /*!< Start the comparator. */
rgrover1 343:6675661fa600 1019 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
rgrover1 343:6675661fa600 1020 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
rgrover1 343:6675661fa600 1021 __I uint32_t RESERVED0[61];
rgrover1 343:6675661fa600 1022 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
rgrover1 343:6675661fa600 1023 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
rgrover1 343:6675661fa600 1024 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
rgrover1 343:6675661fa600 1025 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
rgrover1 343:6675661fa600 1026 __I uint32_t RESERVED1[60];
rgrover1 343:6675661fa600 1027 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
rgrover1 343:6675661fa600 1028 __I uint32_t RESERVED2[64];
rgrover1 343:6675661fa600 1029 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 343:6675661fa600 1030 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 343:6675661fa600 1031 __I uint32_t RESERVED3[61];
rgrover1 343:6675661fa600 1032 __I uint32_t RESULT; /*!< Result of last compare. */
rgrover1 343:6675661fa600 1033 __I uint32_t RESERVED4[63];
rgrover1 343:6675661fa600 1034 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
rgrover1 343:6675661fa600 1035 __IO uint32_t PSEL; /*!< Input pin select. */
rgrover1 343:6675661fa600 1036 __IO uint32_t REFSEL; /*!< Reference select. */
rgrover1 343:6675661fa600 1037 __IO uint32_t EXTREFSEL; /*!< External reference select. */
rgrover1 343:6675661fa600 1038 __I uint32_t RESERVED5[4];
rgrover1 343:6675661fa600 1039 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
rgrover1 343:6675661fa600 1040 __I uint32_t RESERVED6[694];
rgrover1 343:6675661fa600 1041 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 343:6675661fa600 1042 } NRF_LPCOMP_Type;
rgrover1 343:6675661fa600 1043
rgrover1 343:6675661fa600 1044
rgrover1 343:6675661fa600 1045 /* ================================================================================ */
rgrover1 343:6675661fa600 1046 /* ================ SWI ================ */
rgrover1 343:6675661fa600 1047 /* ================================================================================ */
rgrover1 343:6675661fa600 1048
rgrover1 343:6675661fa600 1049
rgrover1 343:6675661fa600 1050 /**
rgrover1 343:6675661fa600 1051 * @brief SW Interrupts. (SWI)
rgrover1 343:6675661fa600 1052 */
rgrover1 343:6675661fa600 1053
rgrover1 343:6675661fa600 1054 typedef struct { /*!< SWI Structure */
rgrover1 343:6675661fa600 1055 __I uint32_t UNUSED; /*!< Unused. */
rgrover1 343:6675661fa600 1056 } NRF_SWI_Type;
rgrover1 343:6675661fa600 1057
rgrover1 343:6675661fa600 1058
rgrover1 343:6675661fa600 1059 /* ================================================================================ */
rgrover1 343:6675661fa600 1060 /* ================ NVMC ================ */
rgrover1 343:6675661fa600 1061 /* ================================================================================ */
rgrover1 343:6675661fa600 1062
rgrover1 343:6675661fa600 1063
rgrover1 343:6675661fa600 1064 /**
rgrover1 343:6675661fa600 1065 * @brief Non Volatile Memory Controller. (NVMC)
rgrover1 343:6675661fa600 1066 */
rgrover1 343:6675661fa600 1067
rgrover1 343:6675661fa600 1068 typedef struct { /*!< NVMC Structure */
rgrover1 343:6675661fa600 1069 __I uint32_t RESERVED0[256];
rgrover1 343:6675661fa600 1070 __I uint32_t READY; /*!< Ready flag. */
rgrover1 343:6675661fa600 1071 __I uint32_t RESERVED1[64];
rgrover1 343:6675661fa600 1072 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 343:6675661fa600 1073 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 343:6675661fa600 1074 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
rgrover1 343:6675661fa600 1075 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
rgrover1 343:6675661fa600 1076 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
rgrover1 343:6675661fa600 1077 } NRF_NVMC_Type;
rgrover1 343:6675661fa600 1078
rgrover1 343:6675661fa600 1079
rgrover1 343:6675661fa600 1080 /* ================================================================================ */
rgrover1 343:6675661fa600 1081 /* ================ PPI ================ */
rgrover1 343:6675661fa600 1082 /* ================================================================================ */
rgrover1 343:6675661fa600 1083
rgrover1 343:6675661fa600 1084
rgrover1 343:6675661fa600 1085 /**
rgrover1 343:6675661fa600 1086 * @brief PPI controller. (PPI)
rgrover1 343:6675661fa600 1087 */
rgrover1 343:6675661fa600 1088
rgrover1 343:6675661fa600 1089 typedef struct { /*!< PPI Structure */
rgrover1 343:6675661fa600 1090 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
rgrover1 343:6675661fa600 1091 __I uint32_t RESERVED0[312];
rgrover1 343:6675661fa600 1092 __IO uint32_t CHEN; /*!< Channel enable. */
rgrover1 343:6675661fa600 1093 __IO uint32_t CHENSET; /*!< Channel enable set. */
rgrover1 343:6675661fa600 1094 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
rgrover1 343:6675661fa600 1095 __I uint32_t RESERVED1;
rgrover1 343:6675661fa600 1096 PPI_CH_Type CH[16]; /*!< PPI Channel. */
rgrover1 343:6675661fa600 1097 __I uint32_t RESERVED2[156];
rgrover1 343:6675661fa600 1098 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
rgrover1 343:6675661fa600 1099 } NRF_PPI_Type;
rgrover1 343:6675661fa600 1100
rgrover1 343:6675661fa600 1101
rgrover1 343:6675661fa600 1102 /* ================================================================================ */
rgrover1 343:6675661fa600 1103 /* ================ FICR ================ */
rgrover1 343:6675661fa600 1104 /* ================================================================================ */
rgrover1 343:6675661fa600 1105
rgrover1 343:6675661fa600 1106
rgrover1 343:6675661fa600 1107 /**
rgrover1 343:6675661fa600 1108 * @brief Factory Information Configuration. (FICR)
rgrover1 343:6675661fa600 1109 */
rgrover1 343:6675661fa600 1110
rgrover1 343:6675661fa600 1111 typedef struct { /*!< FICR Structure */
rgrover1 343:6675661fa600 1112 __I uint32_t RESERVED0[4];
rgrover1 343:6675661fa600 1113 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
rgrover1 343:6675661fa600 1114 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
rgrover1 343:6675661fa600 1115 __I uint32_t RESERVED1[4];
rgrover1 343:6675661fa600 1116 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
rgrover1 343:6675661fa600 1117 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
rgrover1 343:6675661fa600 1118 __I uint32_t RESERVED2;
rgrover1 343:6675661fa600 1119 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
rgrover1 343:6675661fa600 1120
rgrover1 343:6675661fa600 1121 union {
rgrover1 343:6675661fa600 1122 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
rgrover1 343:6675661fa600 1123 kept for backward compatinility purposes. Use SIZERAMBLOCKS
rgrover1 343:6675661fa600 1124 instead. */
rgrover1 343:6675661fa600 1125 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
rgrover1 343:6675661fa600 1126 };
rgrover1 343:6675661fa600 1127 __I uint32_t RESERVED3[5];
rgrover1 343:6675661fa600 1128 __I uint32_t CONFIGID; /*!< Configuration identifier. */
rgrover1 343:6675661fa600 1129 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
rgrover1 343:6675661fa600 1130 __I uint32_t RESERVED4[6];
rgrover1 343:6675661fa600 1131 __I uint32_t ER[4]; /*!< Encryption root. */
rgrover1 343:6675661fa600 1132 __I uint32_t IR[4]; /*!< Identity root. */
rgrover1 343:6675661fa600 1133 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
rgrover1 343:6675661fa600 1134 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
rgrover1 343:6675661fa600 1135 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
rgrover1 343:6675661fa600 1136 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
rgrover1 343:6675661fa600 1137 mode. */
rgrover1 343:6675661fa600 1138 __I uint32_t RESERVED5[10];
rgrover1 343:6675661fa600 1139 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
rgrover1 343:6675661fa600 1140 mode. */
rgrover1 343:6675661fa600 1141 FICR_INFO_Type INFO; /*!< Device info */
rgrover1 343:6675661fa600 1142 } NRF_FICR_Type;
rgrover1 343:6675661fa600 1143
rgrover1 343:6675661fa600 1144
rgrover1 343:6675661fa600 1145 /* ================================================================================ */
rgrover1 343:6675661fa600 1146 /* ================ UICR ================ */
rgrover1 343:6675661fa600 1147 /* ================================================================================ */
rgrover1 343:6675661fa600 1148
rgrover1 343:6675661fa600 1149
rgrover1 343:6675661fa600 1150 /**
rgrover1 343:6675661fa600 1151 * @brief User Information Configuration. (UICR)
rgrover1 343:6675661fa600 1152 */
rgrover1 343:6675661fa600 1153
rgrover1 343:6675661fa600 1154 typedef struct { /*!< UICR Structure */
rgrover1 343:6675661fa600 1155 __IO uint32_t CLENR0; /*!< Length of code region 0. */
rgrover1 343:6675661fa600 1156 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
rgrover1 343:6675661fa600 1157 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
rgrover1 343:6675661fa600 1158 __I uint32_t RESERVED0;
rgrover1 343:6675661fa600 1159 __I uint32_t FWID; /*!< Firmware ID. */
rgrover1 343:6675661fa600 1160 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
rgrover1 343:6675661fa600 1161 } NRF_UICR_Type;
rgrover1 343:6675661fa600 1162
rgrover1 343:6675661fa600 1163
rgrover1 343:6675661fa600 1164 /* ================================================================================ */
rgrover1 343:6675661fa600 1165 /* ================ GPIO ================ */
rgrover1 343:6675661fa600 1166 /* ================================================================================ */
rgrover1 343:6675661fa600 1167
rgrover1 343:6675661fa600 1168
rgrover1 343:6675661fa600 1169 /**
rgrover1 343:6675661fa600 1170 * @brief General purpose input and output. (GPIO)
rgrover1 343:6675661fa600 1171 */
rgrover1 343:6675661fa600 1172
rgrover1 343:6675661fa600 1173 typedef struct { /*!< GPIO Structure */
rgrover1 343:6675661fa600 1174 __I uint32_t RESERVED0[321];
rgrover1 343:6675661fa600 1175 __IO uint32_t OUT; /*!< Write GPIO port. */
rgrover1 343:6675661fa600 1176 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
rgrover1 343:6675661fa600 1177 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
rgrover1 343:6675661fa600 1178 __I uint32_t IN; /*!< Read GPIO port. */
rgrover1 343:6675661fa600 1179 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
rgrover1 343:6675661fa600 1180 __IO uint32_t DIRSET; /*!< DIR set register. */
rgrover1 343:6675661fa600 1181 __IO uint32_t DIRCLR; /*!< DIR clear register. */
rgrover1 343:6675661fa600 1182 __I uint32_t RESERVED1[120];
rgrover1 343:6675661fa600 1183 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
rgrover1 343:6675661fa600 1184 } NRF_GPIO_Type;
rgrover1 343:6675661fa600 1185
rgrover1 343:6675661fa600 1186
rgrover1 343:6675661fa600 1187 /* -------------------- End of section using anonymous unions ------------------- */
rgrover1 343:6675661fa600 1188 #if defined(__CC_ARM)
rgrover1 343:6675661fa600 1189 #pragma pop
rgrover1 343:6675661fa600 1190 #elif defined(__ICCARM__)
rgrover1 343:6675661fa600 1191 /* leave anonymous unions enabled */
rgrover1 343:6675661fa600 1192 #elif defined(__GNUC__)
rgrover1 343:6675661fa600 1193 /* anonymous unions are enabled by default */
rgrover1 343:6675661fa600 1194 #elif defined(__TMS470__)
rgrover1 343:6675661fa600 1195 /* anonymous unions are enabled by default */
rgrover1 343:6675661fa600 1196 #elif defined(__TASKING__)
rgrover1 343:6675661fa600 1197 #pragma warning restore
rgrover1 343:6675661fa600 1198 #else
rgrover1 343:6675661fa600 1199 #warning Not supported compiler type
rgrover1 343:6675661fa600 1200 #endif
rgrover1 343:6675661fa600 1201
rgrover1 343:6675661fa600 1202
rgrover1 343:6675661fa600 1203
rgrover1 343:6675661fa600 1204
rgrover1 343:6675661fa600 1205 /* ================================================================================ */
rgrover1 343:6675661fa600 1206 /* ================ Peripheral memory map ================ */
rgrover1 343:6675661fa600 1207 /* ================================================================================ */
rgrover1 343:6675661fa600 1208
rgrover1 343:6675661fa600 1209 #define NRF_POWER_BASE 0x40000000UL
rgrover1 343:6675661fa600 1210 #define NRF_CLOCK_BASE 0x40000000UL
rgrover1 343:6675661fa600 1211 #define NRF_MPU_BASE 0x40000000UL
rgrover1 343:6675661fa600 1212 #define NRF_PU_BASE 0x40000000UL
rgrover1 343:6675661fa600 1213 #define NRF_AMLI_BASE 0x40000000UL
rgrover1 343:6675661fa600 1214 #define NRF_RADIO_BASE 0x40001000UL
rgrover1 343:6675661fa600 1215 #define NRF_UART0_BASE 0x40002000UL
rgrover1 343:6675661fa600 1216 #define NRF_SPI0_BASE 0x40003000UL
rgrover1 343:6675661fa600 1217 #define NRF_TWI0_BASE 0x40003000UL
rgrover1 343:6675661fa600 1218 #define NRF_SPI1_BASE 0x40004000UL
rgrover1 343:6675661fa600 1219 #define NRF_TWI1_BASE 0x40004000UL
rgrover1 343:6675661fa600 1220 #define NRF_SPIS1_BASE 0x40004000UL
rgrover1 343:6675661fa600 1221 #define NRF_SPIM1_BASE 0x40004000UL
rgrover1 343:6675661fa600 1222 #define NRF_GPIOTE_BASE 0x40006000UL
rgrover1 343:6675661fa600 1223 #define NRF_ADC_BASE 0x40007000UL
rgrover1 343:6675661fa600 1224 #define NRF_TIMER0_BASE 0x40008000UL
rgrover1 343:6675661fa600 1225 #define NRF_TIMER1_BASE 0x40009000UL
rgrover1 343:6675661fa600 1226 #define NRF_TIMER2_BASE 0x4000A000UL
rgrover1 343:6675661fa600 1227 #define NRF_RTC0_BASE 0x4000B000UL
rgrover1 343:6675661fa600 1228 #define NRF_TEMP_BASE 0x4000C000UL
rgrover1 343:6675661fa600 1229 #define NRF_RNG_BASE 0x4000D000UL
rgrover1 343:6675661fa600 1230 #define NRF_ECB_BASE 0x4000E000UL
rgrover1 343:6675661fa600 1231 #define NRF_AAR_BASE 0x4000F000UL
rgrover1 343:6675661fa600 1232 #define NRF_CCM_BASE 0x4000F000UL
rgrover1 343:6675661fa600 1233 #define NRF_WDT_BASE 0x40010000UL
rgrover1 343:6675661fa600 1234 #define NRF_RTC1_BASE 0x40011000UL
rgrover1 343:6675661fa600 1235 #define NRF_QDEC_BASE 0x40012000UL
rgrover1 343:6675661fa600 1236 #define NRF_LPCOMP_BASE 0x40013000UL
rgrover1 343:6675661fa600 1237 #define NRF_SWI_BASE 0x40014000UL
rgrover1 343:6675661fa600 1238 #define NRF_NVMC_BASE 0x4001E000UL
rgrover1 343:6675661fa600 1239 #define NRF_PPI_BASE 0x4001F000UL
rgrover1 343:6675661fa600 1240 #define NRF_FICR_BASE 0x10000000UL
rgrover1 343:6675661fa600 1241 #define NRF_UICR_BASE 0x10001000UL
rgrover1 343:6675661fa600 1242 #define NRF_GPIO_BASE 0x50000000UL
rgrover1 343:6675661fa600 1243
rgrover1 343:6675661fa600 1244
rgrover1 343:6675661fa600 1245 /* ================================================================================ */
rgrover1 343:6675661fa600 1246 /* ================ Peripheral declaration ================ */
rgrover1 343:6675661fa600 1247 /* ================================================================================ */
rgrover1 343:6675661fa600 1248
rgrover1 343:6675661fa600 1249 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
rgrover1 343:6675661fa600 1250 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
rgrover1 343:6675661fa600 1251 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
rgrover1 343:6675661fa600 1252 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
rgrover1 343:6675661fa600 1253 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
rgrover1 343:6675661fa600 1254 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
rgrover1 343:6675661fa600 1255 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
rgrover1 343:6675661fa600 1256 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
rgrover1 343:6675661fa600 1257 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
rgrover1 343:6675661fa600 1258 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
rgrover1 343:6675661fa600 1259 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
rgrover1 343:6675661fa600 1260 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
rgrover1 343:6675661fa600 1261 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
rgrover1 343:6675661fa600 1262 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
rgrover1 343:6675661fa600 1263 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
rgrover1 343:6675661fa600 1264 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
rgrover1 343:6675661fa600 1265 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
rgrover1 343:6675661fa600 1266 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
rgrover1 343:6675661fa600 1267 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
rgrover1 343:6675661fa600 1268 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
rgrover1 343:6675661fa600 1269 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
rgrover1 343:6675661fa600 1270 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
rgrover1 343:6675661fa600 1271 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
rgrover1 343:6675661fa600 1272 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
rgrover1 343:6675661fa600 1273 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
rgrover1 343:6675661fa600 1274 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
rgrover1 343:6675661fa600 1275 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
rgrover1 343:6675661fa600 1276 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
rgrover1 343:6675661fa600 1277 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
rgrover1 343:6675661fa600 1278 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
rgrover1 343:6675661fa600 1279 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
rgrover1 343:6675661fa600 1280 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
rgrover1 343:6675661fa600 1281 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
rgrover1 343:6675661fa600 1282 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
rgrover1 343:6675661fa600 1283
rgrover1 343:6675661fa600 1284
rgrover1 343:6675661fa600 1285 /** @} */ /* End of group Device_Peripheral_Registers */
rgrover1 343:6675661fa600 1286 /** @} */ /* End of group nRF51 */
rgrover1 343:6675661fa600 1287 /** @} */ /* End of group Nordic Semiconductor */
rgrover1 343:6675661fa600 1288
rgrover1 343:6675661fa600 1289 #ifdef __cplusplus
rgrover1 343:6675661fa600 1290 }
rgrover1 343:6675661fa600 1291 #endif
rgrover1 343:6675661fa600 1292
rgrover1 343:6675661fa600 1293
rgrover1 343:6675661fa600 1294 #endif /* nRF51_H */