Rob Kluin / nRF51822

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Fork of nRF51822 by Nordic Semiconductor

source/nordic-sdk/components/device/nrf51.h@512:521c3578f13d, 2015-12-02 (annotated)

Committer:
rgrover1
Date:
Wed Dec 02 12:35:26 2015 +0000
Revision:
512:521c3578f13d
Parent:
504:2179e57ad950
Child:
551:ab7a8de3ff10
Synchronized with git rev 6825c511

Author: Rohit Grover

Release 2.1.0

=============



Upgrading to files from v8.1 of the Nordic SDK.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 504:2179e57ad950 1 /*
rgrover1 504:2179e57ad950 2 * Copyright (c) Nordic Semiconductor ASA
rgrover1 504:2179e57ad950 3 * All rights reserved.
rgrover1 504:2179e57ad950 4 *
rgrover1 504:2179e57ad950 5 * Redistribution and use in source and binary forms, with or without modification,
rgrover1 504:2179e57ad950 6 * are permitted provided that the following conditions are met:
rgrover1 504:2179e57ad950 7 *
rgrover1 504:2179e57ad950 8 * 1. Redistributions of source code must retain the above copyright notice, this
rgrover1 504:2179e57ad950 9 * list of conditions and the following disclaimer.
rgrover1 504:2179e57ad950 10 *
rgrover1 504:2179e57ad950 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
rgrover1 504:2179e57ad950 12 * list of conditions and the following disclaimer in the documentation and/or
rgrover1 504:2179e57ad950 13 * other materials provided with the distribution.
rgrover1 504:2179e57ad950 14 *
rgrover1 504:2179e57ad950 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
rgrover1 504:2179e57ad950 16 * contributors to this software may be used to endorse or promote products
rgrover1 504:2179e57ad950 17 * derived from this software without specific prior written permission.
rgrover1 504:2179e57ad950 18 *
rgrover1 504:2179e57ad950 19 *
rgrover1 504:2179e57ad950 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
rgrover1 504:2179e57ad950 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
rgrover1 504:2179e57ad950 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 504:2179e57ad950 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
rgrover1 504:2179e57ad950 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
rgrover1 504:2179e57ad950 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
rgrover1 504:2179e57ad950 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
rgrover1 504:2179e57ad950 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
rgrover1 504:2179e57ad950 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
rgrover1 504:2179e57ad950 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 504:2179e57ad950 30 *
rgrover1 504:2179e57ad950 31 */
rgrover1 504:2179e57ad950 32
rgrover1 504:2179e57ad950 33 #ifndef NRF51_H
rgrover1 504:2179e57ad950 34 #define NRF51_H
rgrover1 504:2179e57ad950 35
rgrover1 504:2179e57ad950 36 #ifdef __cplusplus
rgrover1 504:2179e57ad950 37 extern "C" {
rgrover1 504:2179e57ad950 38 #endif
rgrover1 504:2179e57ad950 39
rgrover1 504:2179e57ad950 40
rgrover1 504:2179e57ad950 41 /* ------------------------- Interrupt Number Definition ------------------------ */
rgrover1 504:2179e57ad950 42
rgrover1 504:2179e57ad950 43 typedef enum {
rgrover1 504:2179e57ad950 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
rgrover1 504:2179e57ad950 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
rgrover1 504:2179e57ad950 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
rgrover1 504:2179e57ad950 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
rgrover1 504:2179e57ad950 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
rgrover1 504:2179e57ad950 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
rgrover1 504:2179e57ad950 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
rgrover1 504:2179e57ad950 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
rgrover1 504:2179e57ad950 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
rgrover1 504:2179e57ad950 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
rgrover1 504:2179e57ad950 54 RADIO_IRQn = 1, /*!< 1 RADIO */
rgrover1 504:2179e57ad950 55 UART0_IRQn = 2, /*!< 2 UART0 */
rgrover1 504:2179e57ad950 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
rgrover1 504:2179e57ad950 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
rgrover1 504:2179e57ad950 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
rgrover1 504:2179e57ad950 59 ADC_IRQn = 7, /*!< 7 ADC */
rgrover1 504:2179e57ad950 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
rgrover1 504:2179e57ad950 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
rgrover1 504:2179e57ad950 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
rgrover1 504:2179e57ad950 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
rgrover1 504:2179e57ad950 64 TEMP_IRQn = 12, /*!< 12 TEMP */
rgrover1 504:2179e57ad950 65 RNG_IRQn = 13, /*!< 13 RNG */
rgrover1 504:2179e57ad950 66 ECB_IRQn = 14, /*!< 14 ECB */
rgrover1 504:2179e57ad950 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
rgrover1 504:2179e57ad950 68 WDT_IRQn = 16, /*!< 16 WDT */
rgrover1 504:2179e57ad950 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
rgrover1 504:2179e57ad950 70 QDEC_IRQn = 18, /*!< 18 QDEC */
rgrover1 504:2179e57ad950 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
rgrover1 504:2179e57ad950 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
rgrover1 504:2179e57ad950 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
rgrover1 504:2179e57ad950 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
rgrover1 504:2179e57ad950 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
rgrover1 504:2179e57ad950 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
rgrover1 504:2179e57ad950 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
rgrover1 504:2179e57ad950 78 } IRQn_Type;
rgrover1 504:2179e57ad950 79
rgrover1 504:2179e57ad950 80
rgrover1 504:2179e57ad950 81 /** @addtogroup Configuration_of_CMSIS
rgrover1 504:2179e57ad950 82 * @{
rgrover1 504:2179e57ad950 83 */
rgrover1 504:2179e57ad950 84
rgrover1 504:2179e57ad950 85
rgrover1 504:2179e57ad950 86 /* ================================================================================ */
rgrover1 504:2179e57ad950 87 /* ================ Processor and Core Peripheral Section ================ */
rgrover1 504:2179e57ad950 88 /* ================================================================================ */
rgrover1 504:2179e57ad950 89
rgrover1 504:2179e57ad950 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
rgrover1 504:2179e57ad950 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
rgrover1 504:2179e57ad950 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
rgrover1 504:2179e57ad950 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
rgrover1 504:2179e57ad950 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rgrover1 504:2179e57ad950 95 /** @} */ /* End of group Configuration_of_CMSIS */
rgrover1 504:2179e57ad950 96
rgrover1 504:2179e57ad950 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
rgrover1 504:2179e57ad950 98 #include "system_nrf51.h" /*!< nrf51 System */
rgrover1 504:2179e57ad950 99
rgrover1 504:2179e57ad950 100
rgrover1 504:2179e57ad950 101 /* ================================================================================ */
rgrover1 504:2179e57ad950 102 /* ================ Device Specific Peripheral Section ================ */
rgrover1 504:2179e57ad950 103 /* ================================================================================ */
rgrover1 504:2179e57ad950 104
rgrover1 504:2179e57ad950 105
rgrover1 504:2179e57ad950 106 /** @addtogroup Device_Peripheral_Registers
rgrover1 504:2179e57ad950 107 * @{
rgrover1 504:2179e57ad950 108 */
rgrover1 504:2179e57ad950 109
rgrover1 504:2179e57ad950 110
rgrover1 504:2179e57ad950 111 /* ------------------- Start of section using anonymous unions ------------------ */
rgrover1 504:2179e57ad950 112 #if defined(__CC_ARM)
rgrover1 504:2179e57ad950 113 #pragma push
rgrover1 504:2179e57ad950 114 #pragma anon_unions
rgrover1 504:2179e57ad950 115 #elif defined(__ICCARM__)
rgrover1 504:2179e57ad950 116 #pragma language=extended
rgrover1 504:2179e57ad950 117 #elif defined(__GNUC__)
rgrover1 504:2179e57ad950 118 /* anonymous unions are enabled by default */
rgrover1 504:2179e57ad950 119 #elif defined(__TMS470__)
rgrover1 504:2179e57ad950 120 /* anonymous unions are enabled by default */
rgrover1 504:2179e57ad950 121 #elif defined(__TASKING__)
rgrover1 504:2179e57ad950 122 #pragma warning 586
rgrover1 504:2179e57ad950 123 #else
rgrover1 504:2179e57ad950 124 #warning Not supported compiler type
rgrover1 504:2179e57ad950 125 #endif
rgrover1 504:2179e57ad950 126
rgrover1 504:2179e57ad950 127
rgrover1 504:2179e57ad950 128 typedef struct {
rgrover1 504:2179e57ad950 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
rgrover1 504:2179e57ad950 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
rgrover1 504:2179e57ad950 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
rgrover1 504:2179e57ad950 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
rgrover1 504:2179e57ad950 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
rgrover1 504:2179e57ad950 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
rgrover1 504:2179e57ad950 135 } AMLI_RAMPRI_Type;
rgrover1 504:2179e57ad950 136
rgrover1 504:2179e57ad950 137 typedef struct {
rgrover1 504:2179e57ad950 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
rgrover1 504:2179e57ad950 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
rgrover1 504:2179e57ad950 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
rgrover1 504:2179e57ad950 141 } SPIM_PSEL_Type;
rgrover1 504:2179e57ad950 142
rgrover1 504:2179e57ad950 143 typedef struct {
rgrover1 504:2179e57ad950 144 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 504:2179e57ad950 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
rgrover1 504:2179e57ad950 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
rgrover1 504:2179e57ad950 147 } SPIM_RXD_Type;
rgrover1 504:2179e57ad950 148
rgrover1 504:2179e57ad950 149 typedef struct {
rgrover1 504:2179e57ad950 150 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 504:2179e57ad950 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
rgrover1 504:2179e57ad950 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
rgrover1 504:2179e57ad950 153 } SPIM_TXD_Type;
rgrover1 504:2179e57ad950 154
rgrover1 504:2179e57ad950 155 typedef struct {
rgrover1 504:2179e57ad950 156 __O uint32_t EN; /*!< Enable channel group. */
rgrover1 504:2179e57ad950 157 __O uint32_t DIS; /*!< Disable channel group. */
rgrover1 504:2179e57ad950 158 } PPI_TASKS_CHG_Type;
rgrover1 504:2179e57ad950 159
rgrover1 504:2179e57ad950 160 typedef struct {
rgrover1 504:2179e57ad950 161 __IO uint32_t EEP; /*!< Channel event end-point. */
rgrover1 504:2179e57ad950 162 __IO uint32_t TEP; /*!< Channel task end-point. */
rgrover1 504:2179e57ad950 163 } PPI_CH_Type;
rgrover1 504:2179e57ad950 164
rgrover1 504:2179e57ad950 165
rgrover1 504:2179e57ad950 166 /* ================================================================================ */
rgrover1 504:2179e57ad950 167 /* ================ POWER ================ */
rgrover1 504:2179e57ad950 168 /* ================================================================================ */
rgrover1 504:2179e57ad950 169
rgrover1 504:2179e57ad950 170
rgrover1 504:2179e57ad950 171 /**
rgrover1 504:2179e57ad950 172 * @brief Power Control. (POWER)
rgrover1 504:2179e57ad950 173 */
rgrover1 504:2179e57ad950 174
rgrover1 504:2179e57ad950 175 typedef struct { /*!< POWER Structure */
rgrover1 504:2179e57ad950 176 __I uint32_t RESERVED0[30];
rgrover1 504:2179e57ad950 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
rgrover1 504:2179e57ad950 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
rgrover1 504:2179e57ad950 179 __I uint32_t RESERVED1[34];
rgrover1 504:2179e57ad950 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
rgrover1 504:2179e57ad950 181 __I uint32_t RESERVED2[126];
rgrover1 504:2179e57ad950 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 184 __I uint32_t RESERVED3[61];
rgrover1 504:2179e57ad950 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
rgrover1 504:2179e57ad950 186 __I uint32_t RESERVED4[9];
rgrover1 504:2179e57ad950 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
rgrover1 504:2179e57ad950 188 __I uint32_t RESERVED5[53];
rgrover1 504:2179e57ad950 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
rgrover1 504:2179e57ad950 190 __I uint32_t RESERVED6[3];
rgrover1 504:2179e57ad950 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
rgrover1 504:2179e57ad950 192 __I uint32_t RESERVED7[2];
rgrover1 504:2179e57ad950 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
rgrover1 504:2179e57ad950 194 register. */
rgrover1 504:2179e57ad950 195 __I uint32_t RESERVED8;
rgrover1 504:2179e57ad950 196 __IO uint32_t RAMON; /*!< Ram on/off. */
rgrover1 504:2179e57ad950 197 __I uint32_t RESERVED9[7];
rgrover1 504:2179e57ad950 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
rgrover1 504:2179e57ad950 199 is a retained register. */
rgrover1 504:2179e57ad950 200 __I uint32_t RESERVED10[3];
rgrover1 504:2179e57ad950 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
rgrover1 504:2179e57ad950 202 __I uint32_t RESERVED11[8];
rgrover1 504:2179e57ad950 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
rgrover1 504:2179e57ad950 204 __I uint32_t RESERVED12[291];
rgrover1 504:2179e57ad950 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
rgrover1 504:2179e57ad950 206 } NRF_POWER_Type;
rgrover1 504:2179e57ad950 207
rgrover1 504:2179e57ad950 208
rgrover1 504:2179e57ad950 209 /* ================================================================================ */
rgrover1 504:2179e57ad950 210 /* ================ CLOCK ================ */
rgrover1 504:2179e57ad950 211 /* ================================================================================ */
rgrover1 504:2179e57ad950 212
rgrover1 504:2179e57ad950 213
rgrover1 504:2179e57ad950 214 /**
rgrover1 504:2179e57ad950 215 * @brief Clock control. (CLOCK)
rgrover1 504:2179e57ad950 216 */
rgrover1 504:2179e57ad950 217
rgrover1 504:2179e57ad950 218 typedef struct { /*!< CLOCK Structure */
rgrover1 504:2179e57ad950 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
rgrover1 504:2179e57ad950 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
rgrover1 504:2179e57ad950 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
rgrover1 504:2179e57ad950 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
rgrover1 504:2179e57ad950 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
rgrover1 504:2179e57ad950 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
rgrover1 504:2179e57ad950 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
rgrover1 504:2179e57ad950 226 __I uint32_t RESERVED0[57];
rgrover1 504:2179e57ad950 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
rgrover1 504:2179e57ad950 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
rgrover1 504:2179e57ad950 229 __I uint32_t RESERVED1;
rgrover1 504:2179e57ad950 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
rgrover1 504:2179e57ad950 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
rgrover1 504:2179e57ad950 232 __I uint32_t RESERVED2[124];
rgrover1 504:2179e57ad950 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 235 __I uint32_t RESERVED3[63];
rgrover1 504:2179e57ad950 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
rgrover1 504:2179e57ad950 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
rgrover1 504:2179e57ad950 238 __I uint32_t RESERVED4;
rgrover1 504:2179e57ad950 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
rgrover1 504:2179e57ad950 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
rgrover1 504:2179e57ad950 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
rgrover1 504:2179e57ad950 242 triggered. */
rgrover1 504:2179e57ad950 243 __I uint32_t RESERVED5[62];
rgrover1 504:2179e57ad950 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
rgrover1 504:2179e57ad950 245 __I uint32_t RESERVED6[7];
rgrover1 504:2179e57ad950 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
rgrover1 504:2179e57ad950 247 __I uint32_t RESERVED7[5];
rgrover1 504:2179e57ad950 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
rgrover1 504:2179e57ad950 249 } NRF_CLOCK_Type;
rgrover1 504:2179e57ad950 250
rgrover1 504:2179e57ad950 251
rgrover1 504:2179e57ad950 252 /* ================================================================================ */
rgrover1 504:2179e57ad950 253 /* ================ MPU ================ */
rgrover1 504:2179e57ad950 254 /* ================================================================================ */
rgrover1 504:2179e57ad950 255
rgrover1 504:2179e57ad950 256
rgrover1 504:2179e57ad950 257 /**
rgrover1 504:2179e57ad950 258 * @brief Memory Protection Unit. (MPU)
rgrover1 504:2179e57ad950 259 */
rgrover1 504:2179e57ad950 260
rgrover1 504:2179e57ad950 261 typedef struct { /*!< MPU Structure */
rgrover1 504:2179e57ad950 262 __I uint32_t RESERVED0[330];
rgrover1 504:2179e57ad950 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
rgrover1 504:2179e57ad950 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
rgrover1 504:2179e57ad950 265 __I uint32_t RESERVED1[52];
rgrover1 504:2179e57ad950 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
rgrover1 504:2179e57ad950 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
rgrover1 504:2179e57ad950 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
rgrover1 504:2179e57ad950 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
rgrover1 504:2179e57ad950 270 } NRF_MPU_Type;
rgrover1 504:2179e57ad950 271
rgrover1 504:2179e57ad950 272
rgrover1 504:2179e57ad950 273 /* ================================================================================ */
rgrover1 504:2179e57ad950 274 /* ================ PU ================ */
rgrover1 504:2179e57ad950 275 /* ================================================================================ */
rgrover1 504:2179e57ad950 276
rgrover1 504:2179e57ad950 277
rgrover1 504:2179e57ad950 278 /**
rgrover1 504:2179e57ad950 279 * @brief Patch unit. (PU)
rgrover1 504:2179e57ad950 280 */
rgrover1 504:2179e57ad950 281
rgrover1 504:2179e57ad950 282 typedef struct { /*!< PU Structure */
rgrover1 504:2179e57ad950 283 __I uint32_t RESERVED0[448];
rgrover1 504:2179e57ad950 284 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
rgrover1 504:2179e57ad950 285 __I uint32_t RESERVED1[24];
rgrover1 504:2179e57ad950 286 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
rgrover1 504:2179e57ad950 287 __I uint32_t RESERVED2[24];
rgrover1 504:2179e57ad950 288 __IO uint32_t PATCHEN; /*!< Patch enable register. */
rgrover1 504:2179e57ad950 289 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
rgrover1 504:2179e57ad950 290 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
rgrover1 504:2179e57ad950 291 } NRF_PU_Type;
rgrover1 504:2179e57ad950 292
rgrover1 504:2179e57ad950 293
rgrover1 504:2179e57ad950 294 /* ================================================================================ */
rgrover1 504:2179e57ad950 295 /* ================ AMLI ================ */
rgrover1 504:2179e57ad950 296 /* ================================================================================ */
rgrover1 504:2179e57ad950 297
rgrover1 504:2179e57ad950 298
rgrover1 504:2179e57ad950 299 /**
rgrover1 504:2179e57ad950 300 * @brief AHB Multi-Layer Interface. (AMLI)
rgrover1 504:2179e57ad950 301 */
rgrover1 504:2179e57ad950 302
rgrover1 504:2179e57ad950 303 typedef struct { /*!< AMLI Structure */
rgrover1 504:2179e57ad950 304 __I uint32_t RESERVED0[896];
rgrover1 504:2179e57ad950 305 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
rgrover1 504:2179e57ad950 306 } NRF_AMLI_Type;
rgrover1 504:2179e57ad950 307
rgrover1 504:2179e57ad950 308
rgrover1 504:2179e57ad950 309 /* ================================================================================ */
rgrover1 504:2179e57ad950 310 /* ================ RADIO ================ */
rgrover1 504:2179e57ad950 311 /* ================================================================================ */
rgrover1 504:2179e57ad950 312
rgrover1 504:2179e57ad950 313
rgrover1 504:2179e57ad950 314 /**
rgrover1 504:2179e57ad950 315 * @brief The radio. (RADIO)
rgrover1 504:2179e57ad950 316 */
rgrover1 504:2179e57ad950 317
rgrover1 504:2179e57ad950 318 typedef struct { /*!< RADIO Structure */
rgrover1 504:2179e57ad950 319 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
rgrover1 504:2179e57ad950 320 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
rgrover1 504:2179e57ad950 321 __O uint32_t TASKS_START; /*!< Start radio. */
rgrover1 504:2179e57ad950 322 __O uint32_t TASKS_STOP; /*!< Stop radio. */
rgrover1 504:2179e57ad950 323 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
rgrover1 504:2179e57ad950 324 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
rgrover1 504:2179e57ad950 325 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
rgrover1 504:2179e57ad950 326 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
rgrover1 504:2179e57ad950 327 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
rgrover1 504:2179e57ad950 328 __I uint32_t RESERVED0[55];
rgrover1 504:2179e57ad950 329 __IO uint32_t EVENTS_READY; /*!< Ready event. */
rgrover1 504:2179e57ad950 330 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
rgrover1 504:2179e57ad950 331 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
rgrover1 504:2179e57ad950 332 __IO uint32_t EVENTS_END; /*!< End event. */
rgrover1 504:2179e57ad950 333 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
rgrover1 504:2179e57ad950 334 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
rgrover1 504:2179e57ad950 335 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
rgrover1 504:2179e57ad950 336 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
rgrover1 504:2179e57ad950 337 sample is ready for readout at the RSSISAMPLE register. */
rgrover1 504:2179e57ad950 338 __I uint32_t RESERVED1[2];
rgrover1 504:2179e57ad950 339 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
rgrover1 504:2179e57ad950 340 __I uint32_t RESERVED2[53];
rgrover1 504:2179e57ad950 341 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
rgrover1 504:2179e57ad950 342 __I uint32_t RESERVED3[64];
rgrover1 504:2179e57ad950 343 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 344 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 345 __I uint32_t RESERVED4[61];
rgrover1 504:2179e57ad950 346 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
rgrover1 504:2179e57ad950 347 __I uint32_t CD; /*!< Carrier detect. */
rgrover1 504:2179e57ad950 348 __I uint32_t RXMATCH; /*!< Received address. */
rgrover1 504:2179e57ad950 349 __I uint32_t RXCRC; /*!< Received CRC. */
rgrover1 504:2179e57ad950 350 __I uint32_t DAI; /*!< Device address match index. */
rgrover1 504:2179e57ad950 351 __I uint32_t RESERVED5[60];
rgrover1 504:2179e57ad950 352 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
rgrover1 504:2179e57ad950 353 __IO uint32_t FREQUENCY; /*!< Frequency. */
rgrover1 504:2179e57ad950 354 __IO uint32_t TXPOWER; /*!< Output power. */
rgrover1 504:2179e57ad950 355 __IO uint32_t MODE; /*!< Data rate and modulation. */
rgrover1 504:2179e57ad950 356 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
rgrover1 504:2179e57ad950 357 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
rgrover1 504:2179e57ad950 358 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
rgrover1 504:2179e57ad950 359 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
rgrover1 504:2179e57ad950 360 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
rgrover1 504:2179e57ad950 361 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
rgrover1 504:2179e57ad950 362 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
rgrover1 504:2179e57ad950 363 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
rgrover1 504:2179e57ad950 364 __IO uint32_t CRCCNF; /*!< CRC configuration. */
rgrover1 504:2179e57ad950 365 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
rgrover1 504:2179e57ad950 366 __IO uint32_t CRCINIT; /*!< CRC initial value. */
rgrover1 504:2179e57ad950 367 __IO uint32_t TEST; /*!< Test features enable register. */
rgrover1 504:2179e57ad950 368 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
rgrover1 504:2179e57ad950 369 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
rgrover1 504:2179e57ad950 370 __I uint32_t RESERVED6;
rgrover1 504:2179e57ad950 371 __I uint32_t STATE; /*!< Current radio state. */
rgrover1 504:2179e57ad950 372 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
rgrover1 504:2179e57ad950 373 __I uint32_t RESERVED7[2];
rgrover1 504:2179e57ad950 374 __IO uint32_t BCC; /*!< Bit counter compare. */
rgrover1 504:2179e57ad950 375 __I uint32_t RESERVED8[39];
rgrover1 504:2179e57ad950 376 __IO uint32_t DAB[8]; /*!< Device address base segment. */
rgrover1 504:2179e57ad950 377 __IO uint32_t DAP[8]; /*!< Device address prefix. */
rgrover1 504:2179e57ad950 378 __IO uint32_t DACNF; /*!< Device address match configuration. */
rgrover1 504:2179e57ad950 379 __I uint32_t RESERVED9[56];
rgrover1 504:2179e57ad950 380 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
rgrover1 504:2179e57ad950 381 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
rgrover1 504:2179e57ad950 382 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
rgrover1 504:2179e57ad950 383 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
rgrover1 504:2179e57ad950 384 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
rgrover1 504:2179e57ad950 385 __I uint32_t RESERVED10[561];
rgrover1 504:2179e57ad950 386 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 387 } NRF_RADIO_Type;
rgrover1 504:2179e57ad950 388
rgrover1 504:2179e57ad950 389
rgrover1 504:2179e57ad950 390 /* ================================================================================ */
rgrover1 504:2179e57ad950 391 /* ================ UART ================ */
rgrover1 504:2179e57ad950 392 /* ================================================================================ */
rgrover1 504:2179e57ad950 393
rgrover1 504:2179e57ad950 394
rgrover1 504:2179e57ad950 395 /**
rgrover1 504:2179e57ad950 396 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
rgrover1 504:2179e57ad950 397 */
rgrover1 504:2179e57ad950 398
rgrover1 504:2179e57ad950 399 typedef struct { /*!< UART Structure */
rgrover1 504:2179e57ad950 400 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
rgrover1 504:2179e57ad950 401 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
rgrover1 504:2179e57ad950 402 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
rgrover1 504:2179e57ad950 403 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
rgrover1 504:2179e57ad950 404 __I uint32_t RESERVED0[3];
rgrover1 504:2179e57ad950 405 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
rgrover1 504:2179e57ad950 406 __I uint32_t RESERVED1[56];
rgrover1 504:2179e57ad950 407 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
rgrover1 504:2179e57ad950 408 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
rgrover1 504:2179e57ad950 409 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
rgrover1 504:2179e57ad950 410 __I uint32_t RESERVED2[4];
rgrover1 504:2179e57ad950 411 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
rgrover1 504:2179e57ad950 412 __I uint32_t RESERVED3;
rgrover1 504:2179e57ad950 413 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
rgrover1 504:2179e57ad950 414 __I uint32_t RESERVED4[7];
rgrover1 504:2179e57ad950 415 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
rgrover1 504:2179e57ad950 416 __I uint32_t RESERVED5[111];
rgrover1 504:2179e57ad950 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 419 __I uint32_t RESERVED6[93];
rgrover1 504:2179e57ad950 420 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
rgrover1 504:2179e57ad950 421 __I uint32_t RESERVED7[31];
rgrover1 504:2179e57ad950 422 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
rgrover1 504:2179e57ad950 423 __I uint32_t RESERVED8;
rgrover1 504:2179e57ad950 424 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
rgrover1 504:2179e57ad950 425 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
rgrover1 504:2179e57ad950 426 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
rgrover1 504:2179e57ad950 427 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
rgrover1 504:2179e57ad950 428 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
rgrover1 504:2179e57ad950 429 Once read the character is consumed. If read when no character
rgrover1 504:2179e57ad950 430 available, the UART will stop working. */
rgrover1 504:2179e57ad950 431 __O uint32_t TXD; /*!< TXD register. */
rgrover1 504:2179e57ad950 432 __I uint32_t RESERVED9;
rgrover1 504:2179e57ad950 433 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
rgrover1 504:2179e57ad950 434 __I uint32_t RESERVED10[17];
rgrover1 504:2179e57ad950 435 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
rgrover1 504:2179e57ad950 436 __I uint32_t RESERVED11[675];
rgrover1 504:2179e57ad950 437 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 438 } NRF_UART_Type;
rgrover1 504:2179e57ad950 439
rgrover1 504:2179e57ad950 440
rgrover1 504:2179e57ad950 441 /* ================================================================================ */
rgrover1 504:2179e57ad950 442 /* ================ SPI ================ */
rgrover1 504:2179e57ad950 443 /* ================================================================================ */
rgrover1 504:2179e57ad950 444
rgrover1 504:2179e57ad950 445
rgrover1 504:2179e57ad950 446 /**
rgrover1 504:2179e57ad950 447 * @brief SPI master 0. (SPI)
rgrover1 504:2179e57ad950 448 */
rgrover1 504:2179e57ad950 449
rgrover1 504:2179e57ad950 450 typedef struct { /*!< SPI Structure */
rgrover1 504:2179e57ad950 451 __I uint32_t RESERVED0[66];
rgrover1 504:2179e57ad950 452 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
rgrover1 504:2179e57ad950 453 __I uint32_t RESERVED1[126];
rgrover1 504:2179e57ad950 454 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 455 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 456 __I uint32_t RESERVED2[125];
rgrover1 504:2179e57ad950 457 __IO uint32_t ENABLE; /*!< Enable SPI. */
rgrover1 504:2179e57ad950 458 __I uint32_t RESERVED3;
rgrover1 504:2179e57ad950 459 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 504:2179e57ad950 460 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 504:2179e57ad950 461 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 504:2179e57ad950 462 __I uint32_t RESERVED4;
rgrover1 504:2179e57ad950 463 __I uint32_t RXD; /*!< RX data. */
rgrover1 504:2179e57ad950 464 __IO uint32_t TXD; /*!< TX data. */
rgrover1 504:2179e57ad950 465 __I uint32_t RESERVED5;
rgrover1 504:2179e57ad950 466 __IO uint32_t FREQUENCY; /*!< SPI frequency */
rgrover1 504:2179e57ad950 467 __I uint32_t RESERVED6[11];
rgrover1 504:2179e57ad950 468 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 504:2179e57ad950 469 __I uint32_t RESERVED7[681];
rgrover1 504:2179e57ad950 470 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 471 } NRF_SPI_Type;
rgrover1 504:2179e57ad950 472
rgrover1 504:2179e57ad950 473
rgrover1 504:2179e57ad950 474 /* ================================================================================ */
rgrover1 504:2179e57ad950 475 /* ================ TWI ================ */
rgrover1 504:2179e57ad950 476 /* ================================================================================ */
rgrover1 504:2179e57ad950 477
rgrover1 504:2179e57ad950 478
rgrover1 504:2179e57ad950 479 /**
rgrover1 504:2179e57ad950 480 * @brief Two-wire interface master 0. (TWI)
rgrover1 504:2179e57ad950 481 */
rgrover1 504:2179e57ad950 482
rgrover1 504:2179e57ad950 483 typedef struct { /*!< TWI Structure */
rgrover1 504:2179e57ad950 484 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
rgrover1 504:2179e57ad950 485 __I uint32_t RESERVED0;
rgrover1 504:2179e57ad950 486 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
rgrover1 504:2179e57ad950 487 __I uint32_t RESERVED1[2];
rgrover1 504:2179e57ad950 488 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
rgrover1 504:2179e57ad950 489 __I uint32_t RESERVED2;
rgrover1 504:2179e57ad950 490 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
rgrover1 504:2179e57ad950 491 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
rgrover1 504:2179e57ad950 492 __I uint32_t RESERVED3[56];
rgrover1 504:2179e57ad950 493 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
rgrover1 504:2179e57ad950 494 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
rgrover1 504:2179e57ad950 495 __I uint32_t RESERVED4[4];
rgrover1 504:2179e57ad950 496 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
rgrover1 504:2179e57ad950 497 __I uint32_t RESERVED5;
rgrover1 504:2179e57ad950 498 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
rgrover1 504:2179e57ad950 499 __I uint32_t RESERVED6[4];
rgrover1 504:2179e57ad950 500 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
rgrover1 504:2179e57ad950 501 __I uint32_t RESERVED7[3];
rgrover1 504:2179e57ad950 502 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
rgrover1 504:2179e57ad950 503 __I uint32_t RESERVED8[45];
rgrover1 504:2179e57ad950 504 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
rgrover1 504:2179e57ad950 505 __I uint32_t RESERVED9[64];
rgrover1 504:2179e57ad950 506 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 507 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 508 __I uint32_t RESERVED10[110];
rgrover1 504:2179e57ad950 509 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
rgrover1 504:2179e57ad950 510 __I uint32_t RESERVED11[14];
rgrover1 504:2179e57ad950 511 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
rgrover1 504:2179e57ad950 512 __I uint32_t RESERVED12;
rgrover1 504:2179e57ad950 513 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
rgrover1 504:2179e57ad950 514 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
rgrover1 504:2179e57ad950 515 __I uint32_t RESERVED13[2];
rgrover1 504:2179e57ad950 516 __I uint32_t RXD; /*!< RX data register. */
rgrover1 504:2179e57ad950 517 __IO uint32_t TXD; /*!< TX data register. */
rgrover1 504:2179e57ad950 518 __I uint32_t RESERVED14;
rgrover1 504:2179e57ad950 519 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
rgrover1 504:2179e57ad950 520 __I uint32_t RESERVED15[24];
rgrover1 504:2179e57ad950 521 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
rgrover1 504:2179e57ad950 522 __I uint32_t RESERVED16[668];
rgrover1 504:2179e57ad950 523 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 524 } NRF_TWI_Type;
rgrover1 504:2179e57ad950 525
rgrover1 504:2179e57ad950 526
rgrover1 504:2179e57ad950 527 /* ================================================================================ */
rgrover1 504:2179e57ad950 528 /* ================ SPIS ================ */
rgrover1 504:2179e57ad950 529 /* ================================================================================ */
rgrover1 504:2179e57ad950 530
rgrover1 504:2179e57ad950 531
rgrover1 504:2179e57ad950 532 /**
rgrover1 504:2179e57ad950 533 * @brief SPI slave 1. (SPIS)
rgrover1 504:2179e57ad950 534 */
rgrover1 504:2179e57ad950 535
rgrover1 504:2179e57ad950 536 typedef struct { /*!< SPIS Structure */
rgrover1 504:2179e57ad950 537 __I uint32_t RESERVED0[9];
rgrover1 504:2179e57ad950 538 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
rgrover1 504:2179e57ad950 539 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
rgrover1 504:2179e57ad950 540 __I uint32_t RESERVED1[54];
rgrover1 504:2179e57ad950 541 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
rgrover1 504:2179e57ad950 542 __I uint32_t RESERVED2[8];
rgrover1 504:2179e57ad950 543 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
rgrover1 504:2179e57ad950 544 __I uint32_t RESERVED3[53];
rgrover1 504:2179e57ad950 545 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
rgrover1 504:2179e57ad950 546 __I uint32_t RESERVED4[64];
rgrover1 504:2179e57ad950 547 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 548 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 549 __I uint32_t RESERVED5[61];
rgrover1 504:2179e57ad950 550 __I uint32_t SEMSTAT; /*!< Semaphore status. */
rgrover1 504:2179e57ad950 551 __I uint32_t RESERVED6[15];
rgrover1 504:2179e57ad950 552 __IO uint32_t STATUS; /*!< Status from last transaction. */
rgrover1 504:2179e57ad950 553 __I uint32_t RESERVED7[47];
rgrover1 504:2179e57ad950 554 __IO uint32_t ENABLE; /*!< Enable SPIS. */
rgrover1 504:2179e57ad950 555 __I uint32_t RESERVED8;
rgrover1 504:2179e57ad950 556 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 504:2179e57ad950 557 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 504:2179e57ad950 558 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 504:2179e57ad950 559 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
rgrover1 504:2179e57ad950 560 __I uint32_t RESERVED9[7];
rgrover1 504:2179e57ad950 561 __IO uint32_t RXDPTR; /*!< RX data pointer. */
rgrover1 504:2179e57ad950 562 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
rgrover1 504:2179e57ad950 563 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
rgrover1 504:2179e57ad950 564 __I uint32_t RESERVED10;
rgrover1 504:2179e57ad950 565 __IO uint32_t TXDPTR; /*!< TX data pointer. */
rgrover1 504:2179e57ad950 566 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
rgrover1 504:2179e57ad950 567 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
rgrover1 504:2179e57ad950 568 __I uint32_t RESERVED11;
rgrover1 504:2179e57ad950 569 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 504:2179e57ad950 570 __I uint32_t RESERVED12;
rgrover1 504:2179e57ad950 571 __IO uint32_t DEF; /*!< Default character. */
rgrover1 504:2179e57ad950 572 __I uint32_t RESERVED13[24];
rgrover1 504:2179e57ad950 573 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 504:2179e57ad950 574 __I uint32_t RESERVED14[654];
rgrover1 504:2179e57ad950 575 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 576 } NRF_SPIS_Type;
rgrover1 504:2179e57ad950 577
rgrover1 504:2179e57ad950 578
rgrover1 504:2179e57ad950 579 /* ================================================================================ */
rgrover1 504:2179e57ad950 580 /* ================ SPIM ================ */
rgrover1 504:2179e57ad950 581 /* ================================================================================ */
rgrover1 504:2179e57ad950 582
rgrover1 504:2179e57ad950 583
rgrover1 504:2179e57ad950 584 /**
rgrover1 504:2179e57ad950 585 * @brief SPI master with easyDMA 1. (SPIM)
rgrover1 504:2179e57ad950 586 */
rgrover1 504:2179e57ad950 587
rgrover1 504:2179e57ad950 588 typedef struct { /*!< SPIM Structure */
rgrover1 504:2179e57ad950 589 __I uint32_t RESERVED0[4];
rgrover1 504:2179e57ad950 590 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
rgrover1 504:2179e57ad950 591 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
rgrover1 504:2179e57ad950 592 __I uint32_t RESERVED1;
rgrover1 504:2179e57ad950 593 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
rgrover1 504:2179e57ad950 594 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
rgrover1 504:2179e57ad950 595 __I uint32_t RESERVED2[56];
rgrover1 504:2179e57ad950 596 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
rgrover1 504:2179e57ad950 597 __I uint32_t RESERVED3[2];
rgrover1 504:2179e57ad950 598 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
rgrover1 504:2179e57ad950 599 __I uint32_t RESERVED4;
rgrover1 504:2179e57ad950 600 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
rgrover1 504:2179e57ad950 601 __I uint32_t RESERVED5;
rgrover1 504:2179e57ad950 602 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
rgrover1 504:2179e57ad950 603 __I uint32_t RESERVED6[10];
rgrover1 504:2179e57ad950 604 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
rgrover1 504:2179e57ad950 605 __I uint32_t RESERVED7[44];
rgrover1 504:2179e57ad950 606 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
rgrover1 504:2179e57ad950 607 __I uint32_t RESERVED8[64];
rgrover1 504:2179e57ad950 608 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 609 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 610 __I uint32_t RESERVED9[125];
rgrover1 504:2179e57ad950 611 __IO uint32_t ENABLE; /*!< Enable SPIM. */
rgrover1 504:2179e57ad950 612 __I uint32_t RESERVED10;
rgrover1 504:2179e57ad950 613 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
rgrover1 504:2179e57ad950 614 __I uint32_t RESERVED11[4];
rgrover1 504:2179e57ad950 615 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
rgrover1 504:2179e57ad950 616 __I uint32_t RESERVED12[3];
rgrover1 504:2179e57ad950 617 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
rgrover1 504:2179e57ad950 618 __I uint32_t RESERVED13;
rgrover1 504:2179e57ad950 619 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
rgrover1 504:2179e57ad950 620 __I uint32_t RESERVED14;
rgrover1 504:2179e57ad950 621 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 504:2179e57ad950 622 __I uint32_t RESERVED15[26];
rgrover1 504:2179e57ad950 623 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 504:2179e57ad950 624 __I uint32_t RESERVED16[654];
rgrover1 504:2179e57ad950 625 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 626 } NRF_SPIM_Type;
rgrover1 504:2179e57ad950 627
rgrover1 504:2179e57ad950 628
rgrover1 504:2179e57ad950 629 /* ================================================================================ */
rgrover1 504:2179e57ad950 630 /* ================ GPIOTE ================ */
rgrover1 504:2179e57ad950 631 /* ================================================================================ */
rgrover1 504:2179e57ad950 632
rgrover1 504:2179e57ad950 633
rgrover1 504:2179e57ad950 634 /**
rgrover1 504:2179e57ad950 635 * @brief GPIO tasks and events. (GPIOTE)
rgrover1 504:2179e57ad950 636 */
rgrover1 504:2179e57ad950 637
rgrover1 504:2179e57ad950 638 typedef struct { /*!< GPIOTE Structure */
rgrover1 504:2179e57ad950 639 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 504:2179e57ad950 640 __I uint32_t RESERVED0[60];
rgrover1 504:2179e57ad950 641 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 504:2179e57ad950 642 __I uint32_t RESERVED1[27];
rgrover1 504:2179e57ad950 643 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
rgrover1 504:2179e57ad950 644 __I uint32_t RESERVED2[97];
rgrover1 504:2179e57ad950 645 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 646 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 647 __I uint32_t RESERVED3[129];
rgrover1 504:2179e57ad950 648 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
rgrover1 504:2179e57ad950 649 __I uint32_t RESERVED4[695];
rgrover1 504:2179e57ad950 650 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 651 } NRF_GPIOTE_Type;
rgrover1 504:2179e57ad950 652
rgrover1 504:2179e57ad950 653
rgrover1 504:2179e57ad950 654 /* ================================================================================ */
rgrover1 504:2179e57ad950 655 /* ================ ADC ================ */
rgrover1 504:2179e57ad950 656 /* ================================================================================ */
rgrover1 504:2179e57ad950 657
rgrover1 504:2179e57ad950 658
rgrover1 504:2179e57ad950 659 /**
rgrover1 504:2179e57ad950 660 * @brief Analog to digital converter. (ADC)
rgrover1 504:2179e57ad950 661 */
rgrover1 504:2179e57ad950 662
rgrover1 504:2179e57ad950 663 typedef struct { /*!< ADC Structure */
rgrover1 504:2179e57ad950 664 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
rgrover1 504:2179e57ad950 665 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
rgrover1 504:2179e57ad950 666 __I uint32_t RESERVED0[62];
rgrover1 504:2179e57ad950 667 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
rgrover1 504:2179e57ad950 668 __I uint32_t RESERVED1[128];
rgrover1 504:2179e57ad950 669 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 670 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 671 __I uint32_t RESERVED2[61];
rgrover1 504:2179e57ad950 672 __I uint32_t BUSY; /*!< ADC busy register. */
rgrover1 504:2179e57ad950 673 __I uint32_t RESERVED3[63];
rgrover1 504:2179e57ad950 674 __IO uint32_t ENABLE; /*!< ADC enable. */
rgrover1 504:2179e57ad950 675 __IO uint32_t CONFIG; /*!< ADC configuration register. */
rgrover1 504:2179e57ad950 676 __I uint32_t RESULT; /*!< Result of ADC conversion. */
rgrover1 504:2179e57ad950 677 __I uint32_t RESERVED4[700];
rgrover1 504:2179e57ad950 678 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 679 } NRF_ADC_Type;
rgrover1 504:2179e57ad950 680
rgrover1 504:2179e57ad950 681
rgrover1 504:2179e57ad950 682 /* ================================================================================ */
rgrover1 504:2179e57ad950 683 /* ================ TIMER ================ */
rgrover1 504:2179e57ad950 684 /* ================================================================================ */
rgrover1 504:2179e57ad950 685
rgrover1 504:2179e57ad950 686
rgrover1 504:2179e57ad950 687 /**
rgrover1 504:2179e57ad950 688 * @brief Timer 0. (TIMER)
rgrover1 504:2179e57ad950 689 */
rgrover1 504:2179e57ad950 690
rgrover1 504:2179e57ad950 691 typedef struct { /*!< TIMER Structure */
rgrover1 504:2179e57ad950 692 __O uint32_t TASKS_START; /*!< Start Timer. */
rgrover1 504:2179e57ad950 693 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
rgrover1 504:2179e57ad950 694 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
rgrover1 504:2179e57ad950 695 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
rgrover1 504:2179e57ad950 696 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
rgrover1 504:2179e57ad950 697 __I uint32_t RESERVED0[11];
rgrover1 504:2179e57ad950 698 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
rgrover1 504:2179e57ad950 699 __I uint32_t RESERVED1[60];
rgrover1 504:2179e57ad950 700 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 504:2179e57ad950 701 __I uint32_t RESERVED2[44];
rgrover1 504:2179e57ad950 702 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
rgrover1 504:2179e57ad950 703 __I uint32_t RESERVED3[64];
rgrover1 504:2179e57ad950 704 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 705 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 706 __I uint32_t RESERVED4[126];
rgrover1 504:2179e57ad950 707 __IO uint32_t MODE; /*!< Timer Mode selection. */
rgrover1 504:2179e57ad950 708 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
rgrover1 504:2179e57ad950 709 __I uint32_t RESERVED5;
rgrover1 504:2179e57ad950 710 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
rgrover1 504:2179e57ad950 711 clock frequency is divided by 2^SCALE. */
rgrover1 504:2179e57ad950 712 __I uint32_t RESERVED6[11];
rgrover1 504:2179e57ad950 713 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 504:2179e57ad950 714 __I uint32_t RESERVED7[683];
rgrover1 504:2179e57ad950 715 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 716 } NRF_TIMER_Type;
rgrover1 504:2179e57ad950 717
rgrover1 504:2179e57ad950 718
rgrover1 504:2179e57ad950 719 /* ================================================================================ */
rgrover1 504:2179e57ad950 720 /* ================ RTC ================ */
rgrover1 504:2179e57ad950 721 /* ================================================================================ */
rgrover1 504:2179e57ad950 722
rgrover1 504:2179e57ad950 723
rgrover1 504:2179e57ad950 724 /**
rgrover1 504:2179e57ad950 725 * @brief Real time counter 0. (RTC)
rgrover1 504:2179e57ad950 726 */
rgrover1 504:2179e57ad950 727
rgrover1 504:2179e57ad950 728 typedef struct { /*!< RTC Structure */
rgrover1 504:2179e57ad950 729 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
rgrover1 504:2179e57ad950 730 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
rgrover1 504:2179e57ad950 731 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
rgrover1 504:2179e57ad950 732 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
rgrover1 504:2179e57ad950 733 __I uint32_t RESERVED0[60];
rgrover1 504:2179e57ad950 734 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
rgrover1 504:2179e57ad950 735 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
rgrover1 504:2179e57ad950 736 __I uint32_t RESERVED1[14];
rgrover1 504:2179e57ad950 737 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 504:2179e57ad950 738 __I uint32_t RESERVED2[109];
rgrover1 504:2179e57ad950 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 741 __I uint32_t RESERVED3[13];
rgrover1 504:2179e57ad950 742 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
rgrover1 504:2179e57ad950 743 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
rgrover1 504:2179e57ad950 744 the value of EVTEN. */
rgrover1 504:2179e57ad950 745 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
rgrover1 504:2179e57ad950 746 gives the value of EVTEN. */
rgrover1 504:2179e57ad950 747 __I uint32_t RESERVED4[110];
rgrover1 504:2179e57ad950 748 __I uint32_t COUNTER; /*!< Current COUNTER value. */
rgrover1 504:2179e57ad950 749 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
rgrover1 504:2179e57ad950 750 Must be written when RTC is STOPed. */
rgrover1 504:2179e57ad950 751 __I uint32_t RESERVED5[13];
rgrover1 504:2179e57ad950 752 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 504:2179e57ad950 753 __I uint32_t RESERVED6[683];
rgrover1 504:2179e57ad950 754 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 755 } NRF_RTC_Type;
rgrover1 504:2179e57ad950 756
rgrover1 504:2179e57ad950 757
rgrover1 504:2179e57ad950 758 /* ================================================================================ */
rgrover1 504:2179e57ad950 759 /* ================ TEMP ================ */
rgrover1 504:2179e57ad950 760 /* ================================================================================ */
rgrover1 504:2179e57ad950 761
rgrover1 504:2179e57ad950 762
rgrover1 504:2179e57ad950 763 /**
rgrover1 504:2179e57ad950 764 * @brief Temperature Sensor. (TEMP)
rgrover1 504:2179e57ad950 765 */
rgrover1 504:2179e57ad950 766
rgrover1 504:2179e57ad950 767 typedef struct { /*!< TEMP Structure */
rgrover1 504:2179e57ad950 768 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
rgrover1 504:2179e57ad950 769 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
rgrover1 504:2179e57ad950 770 __I uint32_t RESERVED0[62];
rgrover1 504:2179e57ad950 771 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
rgrover1 504:2179e57ad950 772 __I uint32_t RESERVED1[128];
rgrover1 504:2179e57ad950 773 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 774 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 775 __I uint32_t RESERVED2[127];
rgrover1 504:2179e57ad950 776 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
rgrover1 504:2179e57ad950 777 __I uint32_t RESERVED3[700];
rgrover1 504:2179e57ad950 778 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 779 } NRF_TEMP_Type;
rgrover1 504:2179e57ad950 780
rgrover1 504:2179e57ad950 781
rgrover1 504:2179e57ad950 782 /* ================================================================================ */
rgrover1 504:2179e57ad950 783 /* ================ RNG ================ */
rgrover1 504:2179e57ad950 784 /* ================================================================================ */
rgrover1 504:2179e57ad950 785
rgrover1 504:2179e57ad950 786
rgrover1 504:2179e57ad950 787 /**
rgrover1 504:2179e57ad950 788 * @brief Random Number Generator. (RNG)
rgrover1 504:2179e57ad950 789 */
rgrover1 504:2179e57ad950 790
rgrover1 504:2179e57ad950 791 typedef struct { /*!< RNG Structure */
rgrover1 504:2179e57ad950 792 __O uint32_t TASKS_START; /*!< Start the random number generator. */
rgrover1 504:2179e57ad950 793 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
rgrover1 504:2179e57ad950 794 __I uint32_t RESERVED0[62];
rgrover1 504:2179e57ad950 795 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
rgrover1 504:2179e57ad950 796 __I uint32_t RESERVED1[63];
rgrover1 504:2179e57ad950 797 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
rgrover1 504:2179e57ad950 798 __I uint32_t RESERVED2[64];
rgrover1 504:2179e57ad950 799 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
rgrover1 504:2179e57ad950 800 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
rgrover1 504:2179e57ad950 801 __I uint32_t RESERVED3[126];
rgrover1 504:2179e57ad950 802 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 504:2179e57ad950 803 __I uint32_t VALUE; /*!< RNG random number. */
rgrover1 504:2179e57ad950 804 __I uint32_t RESERVED4[700];
rgrover1 504:2179e57ad950 805 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 806 } NRF_RNG_Type;
rgrover1 504:2179e57ad950 807
rgrover1 504:2179e57ad950 808
rgrover1 504:2179e57ad950 809 /* ================================================================================ */
rgrover1 504:2179e57ad950 810 /* ================ ECB ================ */
rgrover1 504:2179e57ad950 811 /* ================================================================================ */
rgrover1 504:2179e57ad950 812
rgrover1 504:2179e57ad950 813
rgrover1 504:2179e57ad950 814 /**
rgrover1 504:2179e57ad950 815 * @brief AES ECB Mode Encryption. (ECB)
rgrover1 504:2179e57ad950 816 */
rgrover1 504:2179e57ad950 817
rgrover1 504:2179e57ad950 818 typedef struct { /*!< ECB Structure */
rgrover1 504:2179e57ad950 819 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
rgrover1 504:2179e57ad950 820 will not initiate a new encryption and the ERRORECB event will
rgrover1 504:2179e57ad950 821 be triggered. */
rgrover1 504:2179e57ad950 822 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
rgrover1 504:2179e57ad950 823 this will will trigger the ERRORECB event. */
rgrover1 504:2179e57ad950 824 __I uint32_t RESERVED0[62];
rgrover1 504:2179e57ad950 825 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
rgrover1 504:2179e57ad950 826 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
rgrover1 504:2179e57ad950 827 error. */
rgrover1 504:2179e57ad950 828 __I uint32_t RESERVED1[127];
rgrover1 504:2179e57ad950 829 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 830 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 831 __I uint32_t RESERVED2[126];
rgrover1 504:2179e57ad950 832 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
rgrover1 504:2179e57ad950 833 __I uint32_t RESERVED3[701];
rgrover1 504:2179e57ad950 834 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 835 } NRF_ECB_Type;
rgrover1 504:2179e57ad950 836
rgrover1 504:2179e57ad950 837
rgrover1 504:2179e57ad950 838 /* ================================================================================ */
rgrover1 504:2179e57ad950 839 /* ================ AAR ================ */
rgrover1 504:2179e57ad950 840 /* ================================================================================ */
rgrover1 504:2179e57ad950 841
rgrover1 504:2179e57ad950 842
rgrover1 504:2179e57ad950 843 /**
rgrover1 504:2179e57ad950 844 * @brief Accelerated Address Resolver. (AAR)
rgrover1 504:2179e57ad950 845 */
rgrover1 504:2179e57ad950 846
rgrover1 504:2179e57ad950 847 typedef struct { /*!< AAR Structure */
rgrover1 504:2179e57ad950 848 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
rgrover1 504:2179e57ad950 849 data structure. */
rgrover1 504:2179e57ad950 850 __I uint32_t RESERVED0;
rgrover1 504:2179e57ad950 851 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
rgrover1 504:2179e57ad950 852 __I uint32_t RESERVED1[61];
rgrover1 504:2179e57ad950 853 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
rgrover1 504:2179e57ad950 854 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
rgrover1 504:2179e57ad950 855 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
rgrover1 504:2179e57ad950 856 __I uint32_t RESERVED2[126];
rgrover1 504:2179e57ad950 857 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 858 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 859 __I uint32_t RESERVED3[61];
rgrover1 504:2179e57ad950 860 __I uint32_t STATUS; /*!< Resolution status. */
rgrover1 504:2179e57ad950 861 __I uint32_t RESERVED4[63];
rgrover1 504:2179e57ad950 862 __IO uint32_t ENABLE; /*!< Enable AAR. */
rgrover1 504:2179e57ad950 863 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
rgrover1 504:2179e57ad950 864 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
rgrover1 504:2179e57ad950 865 __I uint32_t RESERVED5;
rgrover1 504:2179e57ad950 866 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
rgrover1 504:2179e57ad950 867 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 504:2179e57ad950 868 during resolution. A minimum of 3 bytes must be reserved. */
rgrover1 504:2179e57ad950 869 __I uint32_t RESERVED6[697];
rgrover1 504:2179e57ad950 870 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 871 } NRF_AAR_Type;
rgrover1 504:2179e57ad950 872
rgrover1 504:2179e57ad950 873
rgrover1 504:2179e57ad950 874 /* ================================================================================ */
rgrover1 504:2179e57ad950 875 /* ================ CCM ================ */
rgrover1 504:2179e57ad950 876 /* ================================================================================ */
rgrover1 504:2179e57ad950 877
rgrover1 504:2179e57ad950 878
rgrover1 504:2179e57ad950 879 /**
rgrover1 504:2179e57ad950 880 * @brief AES CCM Mode Encryption. (CCM)
rgrover1 504:2179e57ad950 881 */
rgrover1 504:2179e57ad950 882
rgrover1 504:2179e57ad950 883 typedef struct { /*!< CCM Structure */
rgrover1 504:2179e57ad950 884 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
rgrover1 504:2179e57ad950 885 itself when completed. */
rgrover1 504:2179e57ad950 886 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
rgrover1 504:2179e57ad950 887 completed. */
rgrover1 504:2179e57ad950 888 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
rgrover1 504:2179e57ad950 889 __I uint32_t RESERVED0[61];
rgrover1 504:2179e57ad950 890 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
rgrover1 504:2179e57ad950 891 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
rgrover1 504:2179e57ad950 892 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
rgrover1 504:2179e57ad950 893 __I uint32_t RESERVED1[61];
rgrover1 504:2179e57ad950 894 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
rgrover1 504:2179e57ad950 895 __I uint32_t RESERVED2[64];
rgrover1 504:2179e57ad950 896 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 897 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 898 __I uint32_t RESERVED3[61];
rgrover1 504:2179e57ad950 899 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
rgrover1 504:2179e57ad950 900 __I uint32_t RESERVED4[63];
rgrover1 504:2179e57ad950 901 __IO uint32_t ENABLE; /*!< CCM enable. */
rgrover1 504:2179e57ad950 902 __IO uint32_t MODE; /*!< Operation mode. */
rgrover1 504:2179e57ad950 903 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
rgrover1 504:2179e57ad950 904 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
rgrover1 504:2179e57ad950 905 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
rgrover1 504:2179e57ad950 906 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 504:2179e57ad950 907 during resolution. A minimum of 43 bytes must be reserved. */
rgrover1 504:2179e57ad950 908 __I uint32_t RESERVED5[697];
rgrover1 504:2179e57ad950 909 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 910 } NRF_CCM_Type;
rgrover1 504:2179e57ad950 911
rgrover1 504:2179e57ad950 912
rgrover1 504:2179e57ad950 913 /* ================================================================================ */
rgrover1 504:2179e57ad950 914 /* ================ WDT ================ */
rgrover1 504:2179e57ad950 915 /* ================================================================================ */
rgrover1 504:2179e57ad950 916
rgrover1 504:2179e57ad950 917
rgrover1 504:2179e57ad950 918 /**
rgrover1 504:2179e57ad950 919 * @brief Watchdog Timer. (WDT)
rgrover1 504:2179e57ad950 920 */
rgrover1 504:2179e57ad950 921
rgrover1 504:2179e57ad950 922 typedef struct { /*!< WDT Structure */
rgrover1 504:2179e57ad950 923 __O uint32_t TASKS_START; /*!< Start the watchdog. */
rgrover1 504:2179e57ad950 924 __I uint32_t RESERVED0[63];
rgrover1 504:2179e57ad950 925 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
rgrover1 504:2179e57ad950 926 __I uint32_t RESERVED1[128];
rgrover1 504:2179e57ad950 927 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 928 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 929 __I uint32_t RESERVED2[61];
rgrover1 504:2179e57ad950 930 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
rgrover1 504:2179e57ad950 931 __I uint32_t REQSTATUS; /*!< Request status. */
rgrover1 504:2179e57ad950 932 __I uint32_t RESERVED3[63];
rgrover1 504:2179e57ad950 933 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
rgrover1 504:2179e57ad950 934 __IO uint32_t RREN; /*!< Reload request enable. */
rgrover1 504:2179e57ad950 935 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 504:2179e57ad950 936 __I uint32_t RESERVED4[60];
rgrover1 504:2179e57ad950 937 __O uint32_t RR[8]; /*!< Reload requests registers. */
rgrover1 504:2179e57ad950 938 __I uint32_t RESERVED5[631];
rgrover1 504:2179e57ad950 939 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 940 } NRF_WDT_Type;
rgrover1 504:2179e57ad950 941
rgrover1 504:2179e57ad950 942
rgrover1 504:2179e57ad950 943 /* ================================================================================ */
rgrover1 504:2179e57ad950 944 /* ================ QDEC ================ */
rgrover1 504:2179e57ad950 945 /* ================================================================================ */
rgrover1 504:2179e57ad950 946
rgrover1 504:2179e57ad950 947
rgrover1 504:2179e57ad950 948 /**
rgrover1 504:2179e57ad950 949 * @brief Rotary decoder. (QDEC)
rgrover1 504:2179e57ad950 950 */
rgrover1 504:2179e57ad950 951
rgrover1 504:2179e57ad950 952 typedef struct { /*!< QDEC Structure */
rgrover1 504:2179e57ad950 953 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
rgrover1 504:2179e57ad950 954 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
rgrover1 504:2179e57ad950 955 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
rgrover1 504:2179e57ad950 956 and clears the ACC registers. */
rgrover1 504:2179e57ad950 957 __I uint32_t RESERVED0[61];
rgrover1 504:2179e57ad950 958 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
rgrover1 504:2179e57ad950 959 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
rgrover1 504:2179e57ad950 960 ACC register different than zero. */
rgrover1 504:2179e57ad950 961 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
rgrover1 504:2179e57ad950 962 __I uint32_t RESERVED1[61];
rgrover1 504:2179e57ad950 963 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
rgrover1 504:2179e57ad950 964 __I uint32_t RESERVED2[64];
rgrover1 504:2179e57ad950 965 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 966 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 967 __I uint32_t RESERVED3[125];
rgrover1 504:2179e57ad950 968 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
rgrover1 504:2179e57ad950 969 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
rgrover1 504:2179e57ad950 970 __IO uint32_t SAMPLEPER; /*!< Sample period. */
rgrover1 504:2179e57ad950 971 __I int32_t SAMPLE; /*!< Motion sample value. */
rgrover1 504:2179e57ad950 972 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 504:2179e57ad950 973 __I int32_t ACC; /*!< Accumulated valid transitions register. */
rgrover1 504:2179e57ad950 974 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
rgrover1 504:2179e57ad950 975 task. */
rgrover1 504:2179e57ad950 976 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
rgrover1 504:2179e57ad950 977 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
rgrover1 504:2179e57ad950 978 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
rgrover1 504:2179e57ad950 979 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
rgrover1 504:2179e57ad950 980 __I uint32_t RESERVED4[5];
rgrover1 504:2179e57ad950 981 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
rgrover1 504:2179e57ad950 982 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
rgrover1 504:2179e57ad950 983 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
rgrover1 504:2179e57ad950 984 task. */
rgrover1 504:2179e57ad950 985 __I uint32_t RESERVED5[684];
rgrover1 504:2179e57ad950 986 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 987 } NRF_QDEC_Type;
rgrover1 504:2179e57ad950 988
rgrover1 504:2179e57ad950 989
rgrover1 504:2179e57ad950 990 /* ================================================================================ */
rgrover1 504:2179e57ad950 991 /* ================ LPCOMP ================ */
rgrover1 504:2179e57ad950 992 /* ================================================================================ */
rgrover1 504:2179e57ad950 993
rgrover1 504:2179e57ad950 994
rgrover1 504:2179e57ad950 995 /**
rgrover1 504:2179e57ad950 996 * @brief Low power comparator. (LPCOMP)
rgrover1 504:2179e57ad950 997 */
rgrover1 504:2179e57ad950 998
rgrover1 504:2179e57ad950 999 typedef struct { /*!< LPCOMP Structure */
rgrover1 504:2179e57ad950 1000 __O uint32_t TASKS_START; /*!< Start the comparator. */
rgrover1 504:2179e57ad950 1001 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
rgrover1 504:2179e57ad950 1002 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
rgrover1 504:2179e57ad950 1003 __I uint32_t RESERVED0[61];
rgrover1 504:2179e57ad950 1004 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
rgrover1 504:2179e57ad950 1005 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
rgrover1 504:2179e57ad950 1006 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
rgrover1 504:2179e57ad950 1007 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
rgrover1 504:2179e57ad950 1008 __I uint32_t RESERVED1[60];
rgrover1 504:2179e57ad950 1009 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
rgrover1 504:2179e57ad950 1010 __I uint32_t RESERVED2[64];
rgrover1 504:2179e57ad950 1011 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 504:2179e57ad950 1012 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 504:2179e57ad950 1013 __I uint32_t RESERVED3[61];
rgrover1 504:2179e57ad950 1014 __I uint32_t RESULT; /*!< Result of last compare. */
rgrover1 504:2179e57ad950 1015 __I uint32_t RESERVED4[63];
rgrover1 504:2179e57ad950 1016 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
rgrover1 504:2179e57ad950 1017 __IO uint32_t PSEL; /*!< Input pin select. */
rgrover1 504:2179e57ad950 1018 __IO uint32_t REFSEL; /*!< Reference select. */
rgrover1 504:2179e57ad950 1019 __IO uint32_t EXTREFSEL; /*!< External reference select. */
rgrover1 504:2179e57ad950 1020 __I uint32_t RESERVED5[4];
rgrover1 504:2179e57ad950 1021 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
rgrover1 504:2179e57ad950 1022 __I uint32_t RESERVED6[694];
rgrover1 504:2179e57ad950 1023 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 504:2179e57ad950 1024 } NRF_LPCOMP_Type;
rgrover1 504:2179e57ad950 1025
rgrover1 504:2179e57ad950 1026
rgrover1 504:2179e57ad950 1027 /* ================================================================================ */
rgrover1 504:2179e57ad950 1028 /* ================ SWI ================ */
rgrover1 504:2179e57ad950 1029 /* ================================================================================ */
rgrover1 504:2179e57ad950 1030
rgrover1 504:2179e57ad950 1031
rgrover1 504:2179e57ad950 1032 /**
rgrover1 504:2179e57ad950 1033 * @brief SW Interrupts. (SWI)
rgrover1 504:2179e57ad950 1034 */
rgrover1 504:2179e57ad950 1035
rgrover1 504:2179e57ad950 1036 typedef struct { /*!< SWI Structure */
rgrover1 504:2179e57ad950 1037 __I uint32_t UNUSED; /*!< Unused. */
rgrover1 504:2179e57ad950 1038 } NRF_SWI_Type;
rgrover1 504:2179e57ad950 1039
rgrover1 504:2179e57ad950 1040
rgrover1 504:2179e57ad950 1041 /* ================================================================================ */
rgrover1 504:2179e57ad950 1042 /* ================ NVMC ================ */
rgrover1 504:2179e57ad950 1043 /* ================================================================================ */
rgrover1 504:2179e57ad950 1044
rgrover1 504:2179e57ad950 1045
rgrover1 504:2179e57ad950 1046 /**
rgrover1 504:2179e57ad950 1047 * @brief Non Volatile Memory Controller. (NVMC)
rgrover1 504:2179e57ad950 1048 */
rgrover1 504:2179e57ad950 1049
rgrover1 504:2179e57ad950 1050 typedef struct { /*!< NVMC Structure */
rgrover1 504:2179e57ad950 1051 __I uint32_t RESERVED0[256];
rgrover1 504:2179e57ad950 1052 __I uint32_t READY; /*!< Ready flag. */
rgrover1 504:2179e57ad950 1053 __I uint32_t RESERVED1[64];
rgrover1 504:2179e57ad950 1054 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 504:2179e57ad950 1055
rgrover1 504:2179e57ad950 1056 union {
rgrover1 504:2179e57ad950 1057 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 504:2179e57ad950 1058 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 504:2179e57ad950 1059 };
rgrover1 504:2179e57ad950 1060 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
rgrover1 504:2179e57ad950 1061 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
rgrover1 504:2179e57ad950 1062 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
rgrover1 504:2179e57ad950 1063 } NRF_NVMC_Type;
rgrover1 504:2179e57ad950 1064
rgrover1 504:2179e57ad950 1065
rgrover1 504:2179e57ad950 1066 /* ================================================================================ */
rgrover1 504:2179e57ad950 1067 /* ================ PPI ================ */
rgrover1 504:2179e57ad950 1068 /* ================================================================================ */
rgrover1 504:2179e57ad950 1069
rgrover1 504:2179e57ad950 1070
rgrover1 504:2179e57ad950 1071 /**
rgrover1 504:2179e57ad950 1072 * @brief PPI controller. (PPI)
rgrover1 504:2179e57ad950 1073 */
rgrover1 504:2179e57ad950 1074
rgrover1 504:2179e57ad950 1075 typedef struct { /*!< PPI Structure */
rgrover1 504:2179e57ad950 1076 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
rgrover1 504:2179e57ad950 1077 __I uint32_t RESERVED0[312];
rgrover1 504:2179e57ad950 1078 __IO uint32_t CHEN; /*!< Channel enable. */
rgrover1 504:2179e57ad950 1079 __IO uint32_t CHENSET; /*!< Channel enable set. */
rgrover1 504:2179e57ad950 1080 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
rgrover1 504:2179e57ad950 1081 __I uint32_t RESERVED1;
rgrover1 504:2179e57ad950 1082 PPI_CH_Type CH[16]; /*!< PPI Channel. */
rgrover1 504:2179e57ad950 1083 __I uint32_t RESERVED2[156];
rgrover1 504:2179e57ad950 1084 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
rgrover1 504:2179e57ad950 1085 } NRF_PPI_Type;
rgrover1 504:2179e57ad950 1086
rgrover1 504:2179e57ad950 1087
rgrover1 504:2179e57ad950 1088 /* ================================================================================ */
rgrover1 504:2179e57ad950 1089 /* ================ FICR ================ */
rgrover1 504:2179e57ad950 1090 /* ================================================================================ */
rgrover1 504:2179e57ad950 1091
rgrover1 504:2179e57ad950 1092
rgrover1 504:2179e57ad950 1093 /**
rgrover1 504:2179e57ad950 1094 * @brief Factory Information Configuration. (FICR)
rgrover1 504:2179e57ad950 1095 */
rgrover1 504:2179e57ad950 1096
rgrover1 504:2179e57ad950 1097 typedef struct { /*!< FICR Structure */
rgrover1 504:2179e57ad950 1098 __I uint32_t RESERVED0[4];
rgrover1 504:2179e57ad950 1099 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
rgrover1 504:2179e57ad950 1100 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
rgrover1 504:2179e57ad950 1101 __I uint32_t RESERVED1[4];
rgrover1 504:2179e57ad950 1102 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
rgrover1 504:2179e57ad950 1103 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
rgrover1 504:2179e57ad950 1104 __I uint32_t RESERVED2;
rgrover1 504:2179e57ad950 1105 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
rgrover1 504:2179e57ad950 1106
rgrover1 504:2179e57ad950 1107 union {
rgrover1 504:2179e57ad950 1108 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
rgrover1 504:2179e57ad950 1109 kept for backward compatinility purposes. Use SIZERAMBLOCKS
rgrover1 504:2179e57ad950 1110 instead. */
rgrover1 504:2179e57ad950 1111 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
rgrover1 504:2179e57ad950 1112 };
rgrover1 504:2179e57ad950 1113 __I uint32_t RESERVED3[5];
rgrover1 504:2179e57ad950 1114 __I uint32_t CONFIGID; /*!< Configuration identifier. */
rgrover1 504:2179e57ad950 1115 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
rgrover1 504:2179e57ad950 1116 __I uint32_t RESERVED4[6];
rgrover1 504:2179e57ad950 1117 __I uint32_t ER[4]; /*!< Encryption root. */
rgrover1 504:2179e57ad950 1118 __I uint32_t IR[4]; /*!< Identity root. */
rgrover1 504:2179e57ad950 1119 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
rgrover1 504:2179e57ad950 1120 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
rgrover1 504:2179e57ad950 1121 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
rgrover1 504:2179e57ad950 1122 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
rgrover1 504:2179e57ad950 1123 mode. */
rgrover1 504:2179e57ad950 1124 __I uint32_t RESERVED5[10];
rgrover1 504:2179e57ad950 1125 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
rgrover1 504:2179e57ad950 1126 mode. */
rgrover1 504:2179e57ad950 1127 } NRF_FICR_Type;
rgrover1 504:2179e57ad950 1128
rgrover1 504:2179e57ad950 1129
rgrover1 504:2179e57ad950 1130 /* ================================================================================ */
rgrover1 504:2179e57ad950 1131 /* ================ UICR ================ */
rgrover1 504:2179e57ad950 1132 /* ================================================================================ */
rgrover1 504:2179e57ad950 1133
rgrover1 504:2179e57ad950 1134
rgrover1 504:2179e57ad950 1135 /**
rgrover1 504:2179e57ad950 1136 * @brief User Information Configuration. (UICR)
rgrover1 504:2179e57ad950 1137 */
rgrover1 504:2179e57ad950 1138
rgrover1 504:2179e57ad950 1139 typedef struct { /*!< UICR Structure */
rgrover1 504:2179e57ad950 1140 __IO uint32_t CLENR0; /*!< Length of code region 0. */
rgrover1 504:2179e57ad950 1141 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
rgrover1 504:2179e57ad950 1142 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
rgrover1 504:2179e57ad950 1143 __I uint32_t RESERVED0;
rgrover1 504:2179e57ad950 1144 __I uint32_t FWID; /*!< Firmware ID. */
rgrover1 504:2179e57ad950 1145
rgrover1 504:2179e57ad950 1146 union {
rgrover1 504:2179e57ad950 1147 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
rgrover1 504:2179e57ad950 1148 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
rgrover1 504:2179e57ad950 1149 };
rgrover1 504:2179e57ad950 1150 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
rgrover1 504:2179e57ad950 1151 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
rgrover1 504:2179e57ad950 1152 } NRF_UICR_Type;
rgrover1 504:2179e57ad950 1153
rgrover1 504:2179e57ad950 1154
rgrover1 504:2179e57ad950 1155 /* ================================================================================ */
rgrover1 504:2179e57ad950 1156 /* ================ GPIO ================ */
rgrover1 504:2179e57ad950 1157 /* ================================================================================ */
rgrover1 504:2179e57ad950 1158
rgrover1 504:2179e57ad950 1159
rgrover1 504:2179e57ad950 1160 /**
rgrover1 504:2179e57ad950 1161 * @brief General purpose input and output. (GPIO)
rgrover1 504:2179e57ad950 1162 */
rgrover1 504:2179e57ad950 1163
rgrover1 504:2179e57ad950 1164 typedef struct { /*!< GPIO Structure */
rgrover1 504:2179e57ad950 1165 __I uint32_t RESERVED0[321];
rgrover1 504:2179e57ad950 1166 __IO uint32_t OUT; /*!< Write GPIO port. */
rgrover1 504:2179e57ad950 1167 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
rgrover1 504:2179e57ad950 1168 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
rgrover1 504:2179e57ad950 1169 __I uint32_t IN; /*!< Read GPIO port. */
rgrover1 504:2179e57ad950 1170 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
rgrover1 504:2179e57ad950 1171 __IO uint32_t DIRSET; /*!< DIR set register. */
rgrover1 504:2179e57ad950 1172 __IO uint32_t DIRCLR; /*!< DIR clear register. */
rgrover1 504:2179e57ad950 1173 __I uint32_t RESERVED1[120];
rgrover1 504:2179e57ad950 1174 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
rgrover1 504:2179e57ad950 1175 } NRF_GPIO_Type;
rgrover1 504:2179e57ad950 1176
rgrover1 504:2179e57ad950 1177
rgrover1 504:2179e57ad950 1178 /* -------------------- End of section using anonymous unions ------------------- */
rgrover1 504:2179e57ad950 1179 #if defined(__CC_ARM)
rgrover1 504:2179e57ad950 1180 #pragma pop
rgrover1 504:2179e57ad950 1181 #elif defined(__ICCARM__)
rgrover1 504:2179e57ad950 1182 /* leave anonymous unions enabled */
rgrover1 504:2179e57ad950 1183 #elif defined(__GNUC__)
rgrover1 504:2179e57ad950 1184 /* anonymous unions are enabled by default */
rgrover1 504:2179e57ad950 1185 #elif defined(__TMS470__)
rgrover1 504:2179e57ad950 1186 /* anonymous unions are enabled by default */
rgrover1 504:2179e57ad950 1187 #elif defined(__TASKING__)
rgrover1 504:2179e57ad950 1188 #pragma warning restore
rgrover1 504:2179e57ad950 1189 #else
rgrover1 504:2179e57ad950 1190 #warning Not supported compiler type
rgrover1 504:2179e57ad950 1191 #endif
rgrover1 504:2179e57ad950 1192
rgrover1 504:2179e57ad950 1193
rgrover1 504:2179e57ad950 1194
rgrover1 504:2179e57ad950 1195
rgrover1 504:2179e57ad950 1196 /* ================================================================================ */
rgrover1 504:2179e57ad950 1197 /* ================ Peripheral memory map ================ */
rgrover1 504:2179e57ad950 1198 /* ================================================================================ */
rgrover1 504:2179e57ad950 1199
rgrover1 504:2179e57ad950 1200 #define NRF_POWER_BASE 0x40000000UL
rgrover1 504:2179e57ad950 1201 #define NRF_CLOCK_BASE 0x40000000UL
rgrover1 504:2179e57ad950 1202 #define NRF_MPU_BASE 0x40000000UL
rgrover1 504:2179e57ad950 1203 #define NRF_PU_BASE 0x40000000UL
rgrover1 504:2179e57ad950 1204 #define NRF_AMLI_BASE 0x40000000UL
rgrover1 504:2179e57ad950 1205 #define NRF_RADIO_BASE 0x40001000UL
rgrover1 504:2179e57ad950 1206 #define NRF_UART0_BASE 0x40002000UL
rgrover1 504:2179e57ad950 1207 #define NRF_SPI0_BASE 0x40003000UL
rgrover1 504:2179e57ad950 1208 #define NRF_TWI0_BASE 0x40003000UL
rgrover1 504:2179e57ad950 1209 #define NRF_SPI1_BASE 0x40004000UL
rgrover1 504:2179e57ad950 1210 #define NRF_TWI1_BASE 0x40004000UL
rgrover1 504:2179e57ad950 1211 #define NRF_SPIS1_BASE 0x40004000UL
rgrover1 504:2179e57ad950 1212 #define NRF_SPIM1_BASE 0x40004000UL
rgrover1 504:2179e57ad950 1213 #define NRF_GPIOTE_BASE 0x40006000UL
rgrover1 504:2179e57ad950 1214 #define NRF_ADC_BASE 0x40007000UL
rgrover1 504:2179e57ad950 1215 #define NRF_TIMER0_BASE 0x40008000UL
rgrover1 504:2179e57ad950 1216 #define NRF_TIMER1_BASE 0x40009000UL
rgrover1 504:2179e57ad950 1217 #define NRF_TIMER2_BASE 0x4000A000UL
rgrover1 504:2179e57ad950 1218 #define NRF_RTC0_BASE 0x4000B000UL
rgrover1 504:2179e57ad950 1219 #define NRF_TEMP_BASE 0x4000C000UL
rgrover1 504:2179e57ad950 1220 #define NRF_RNG_BASE 0x4000D000UL
rgrover1 504:2179e57ad950 1221 #define NRF_ECB_BASE 0x4000E000UL
rgrover1 504:2179e57ad950 1222 #define NRF_AAR_BASE 0x4000F000UL
rgrover1 504:2179e57ad950 1223 #define NRF_CCM_BASE 0x4000F000UL
rgrover1 504:2179e57ad950 1224 #define NRF_WDT_BASE 0x40010000UL
rgrover1 504:2179e57ad950 1225 #define NRF_RTC1_BASE 0x40011000UL
rgrover1 504:2179e57ad950 1226 #define NRF_QDEC_BASE 0x40012000UL
rgrover1 504:2179e57ad950 1227 #define NRF_LPCOMP_BASE 0x40013000UL
rgrover1 504:2179e57ad950 1228 #define NRF_SWI_BASE 0x40014000UL
rgrover1 504:2179e57ad950 1229 #define NRF_NVMC_BASE 0x4001E000UL
rgrover1 504:2179e57ad950 1230 #define NRF_PPI_BASE 0x4001F000UL
rgrover1 504:2179e57ad950 1231 #define NRF_FICR_BASE 0x10000000UL
rgrover1 504:2179e57ad950 1232 #define NRF_UICR_BASE 0x10001000UL
rgrover1 504:2179e57ad950 1233 #define NRF_GPIO_BASE 0x50000000UL
rgrover1 504:2179e57ad950 1234
rgrover1 504:2179e57ad950 1235
rgrover1 504:2179e57ad950 1236 /* ================================================================================ */
rgrover1 504:2179e57ad950 1237 /* ================ Peripheral declaration ================ */
rgrover1 504:2179e57ad950 1238 /* ================================================================================ */
rgrover1 504:2179e57ad950 1239
rgrover1 504:2179e57ad950 1240 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
rgrover1 504:2179e57ad950 1241 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
rgrover1 504:2179e57ad950 1242 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
rgrover1 504:2179e57ad950 1243 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
rgrover1 504:2179e57ad950 1244 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
rgrover1 504:2179e57ad950 1245 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
rgrover1 504:2179e57ad950 1246 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
rgrover1 504:2179e57ad950 1247 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
rgrover1 504:2179e57ad950 1248 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
rgrover1 504:2179e57ad950 1249 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
rgrover1 504:2179e57ad950 1250 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
rgrover1 504:2179e57ad950 1251 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
rgrover1 504:2179e57ad950 1252 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
rgrover1 504:2179e57ad950 1253 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
rgrover1 504:2179e57ad950 1254 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
rgrover1 504:2179e57ad950 1255 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
rgrover1 504:2179e57ad950 1256 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
rgrover1 504:2179e57ad950 1257 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
rgrover1 504:2179e57ad950 1258 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
rgrover1 504:2179e57ad950 1259 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
rgrover1 504:2179e57ad950 1260 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
rgrover1 504:2179e57ad950 1261 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
rgrover1 504:2179e57ad950 1262 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
rgrover1 504:2179e57ad950 1263 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
rgrover1 504:2179e57ad950 1264 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
rgrover1 504:2179e57ad950 1265 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
rgrover1 504:2179e57ad950 1266 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
rgrover1 504:2179e57ad950 1267 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
rgrover1 504:2179e57ad950 1268 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
rgrover1 504:2179e57ad950 1269 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
rgrover1 504:2179e57ad950 1270 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
rgrover1 504:2179e57ad950 1271 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
rgrover1 504:2179e57ad950 1272 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
rgrover1 504:2179e57ad950 1273 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
rgrover1 504:2179e57ad950 1274
rgrover1 504:2179e57ad950 1275
rgrover1 504:2179e57ad950 1276 /** @} */ /* End of group Device_Peripheral_Registers */
rgrover1 504:2179e57ad950 1277 /** @} */ /* End of group nrf51 */
rgrover1 504:2179e57ad950 1278 /** @} */ /* End of group Nordic Semiconductor */
rgrover1 504:2179e57ad950 1279
rgrover1 504:2179e57ad950 1280 #ifdef __cplusplus
rgrover1 504:2179e57ad950 1281 }
rgrover1 504:2179e57ad950 1282 #endif
rgrover1 504:2179e57ad950 1283
rgrover1 504:2179e57ad950 1284
rgrover1 504:2179e57ad950 1285 #endif /* nrf51_H */