STMPE610 touch sensor driver library
Dependents: TS_Eyes Tokei testUniGraphic_150217 AfficheurTFTAdafruit ... more
SPI_STMPE610.cpp@0:68779c92cffa, 2014-11-08 (annotated)
- Committer:
- Rhyme
- Date:
- Sat Nov 08 05:17:25 2014 +0000
- Revision:
- 0:68779c92cffa
- Child:
- 1:43990f1c0a8b
First commit;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Rhyme | 0:68779c92cffa | 1 | /* mbed SPI_STMPE610.cpp to test adafruit 2.8" TFT LCD shiled w Touchscreen |
Rhyme | 0:68779c92cffa | 2 | * Copyright (c) 2014 Motoo Tanaka @ Design Methodology Lab |
Rhyme | 0:68779c92cffa | 3 | * |
Rhyme | 0:68779c92cffa | 4 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
Rhyme | 0:68779c92cffa | 5 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
Rhyme | 0:68779c92cffa | 6 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
Rhyme | 0:68779c92cffa | 7 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
Rhyme | 0:68779c92cffa | 8 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
Rhyme | 0:68779c92cffa | 9 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
Rhyme | 0:68779c92cffa | 10 | * THE SOFTWARE. |
Rhyme | 0:68779c92cffa | 11 | */ |
Rhyme | 0:68779c92cffa | 12 | /* |
Rhyme | 0:68779c92cffa | 13 | * Note: Since the interrupt siganl of the shield was not connected |
Rhyme | 0:68779c92cffa | 14 | * to an interrupt pin on my frdm-kl25z, I just used polling mode. |
Rhyme | 0:68779c92cffa | 15 | */ |
Rhyme | 0:68779c92cffa | 16 | /* |
Rhyme | 0:68779c92cffa | 17 | * Note: To make this work with FRDM-K64F |
Rhyme | 0:68779c92cffa | 18 | * PTA0 must be disconnected from the swd clk by cutting J11. |
Rhyme | 0:68779c92cffa | 19 | * But to re-active SWD you need to put jumper header to J11 |
Rhyme | 0:68779c92cffa | 20 | * so that it can be re-connected by a jumper. |
Rhyme | 0:68779c92cffa | 21 | */ |
Rhyme | 0:68779c92cffa | 22 | #include "SPI_STMPE610.h" |
Rhyme | 0:68779c92cffa | 23 | |
Rhyme | 0:68779c92cffa | 24 | /* some definitions here */ |
Rhyme | 0:68779c92cffa | 25 | #define REG_CHIP_ID 0x00 |
Rhyme | 0:68779c92cffa | 26 | #define REG_CHIP_ID_MSB 0x00 |
Rhyme | 0:68779c92cffa | 27 | #define REG_CHIP_ID_LSB 0x01 |
Rhyme | 0:68779c92cffa | 28 | |
Rhyme | 0:68779c92cffa | 29 | #define REG_ID_VER 0x02 |
Rhyme | 0:68779c92cffa | 30 | #define REG_SYS_CTRL1 0x03 |
Rhyme | 0:68779c92cffa | 31 | #define REG_SYS_CTRL1_RESET 0x02 |
Rhyme | 0:68779c92cffa | 32 | |
Rhyme | 0:68779c92cffa | 33 | #define REG_SYS_CTRL2 0x04 |
Rhyme | 0:68779c92cffa | 34 | #define REG_SPI_CFG 0x08 |
Rhyme | 0:68779c92cffa | 35 | #define REG_INT_CTRL 0x09 |
Rhyme | 0:68779c92cffa | 36 | #define REG_INT_CTRL_POL_HIGH 0x04 |
Rhyme | 0:68779c92cffa | 37 | #define REG_INT_CTRL_POL_LOW 0x00 |
Rhyme | 0:68779c92cffa | 38 | #define REG_INT_CTRL_EDGE 0x02 |
Rhyme | 0:68779c92cffa | 39 | #define REG_INT_CTRL_LEVEL 0x00 |
Rhyme | 0:68779c92cffa | 40 | #define REG_INT_CTRL_ENABLE 0x01 |
Rhyme | 0:68779c92cffa | 41 | #define REG_INT_CTRL_DISABLE 0x00 |
Rhyme | 0:68779c92cffa | 42 | |
Rhyme | 0:68779c92cffa | 43 | #define REG_INT_EN 0x0A |
Rhyme | 0:68779c92cffa | 44 | #define REG_INT_EN_TOUCHDET 0x01 |
Rhyme | 0:68779c92cffa | 45 | #define REG_INT_EN_FIFOTH 0x02 |
Rhyme | 0:68779c92cffa | 46 | #define REG_INT_EN_FIFOOF 0x04 |
Rhyme | 0:68779c92cffa | 47 | #define REG_INT_EN_FIFOFULL 0x08 |
Rhyme | 0:68779c92cffa | 48 | #define REG_INT_EN_FIFOEMPTY 0x10 |
Rhyme | 0:68779c92cffa | 49 | #define REG_INT_EN_ADC 0x40 |
Rhyme | 0:68779c92cffa | 50 | |
Rhyme | 0:68779c92cffa | 51 | #define REG_INT_STA 0x0B |
Rhyme | 0:68779c92cffa | 52 | #define REG_INT_STA_TOUCHDET 0x01 |
Rhyme | 0:68779c92cffa | 53 | |
Rhyme | 0:68779c92cffa | 54 | #define REG_GPIO_EN 0x0C |
Rhyme | 0:68779c92cffa | 55 | #define REG_GPIO_INT_STA 0x0D |
Rhyme | 0:68779c92cffa | 56 | #define REG_ADC_INT_EN 0x0E |
Rhyme | 0:68779c92cffa | 57 | #define REG_ADC_INT_STA 0x0F |
Rhyme | 0:68779c92cffa | 58 | #define REG_GPIO_SET_PIN 0x10 |
Rhyme | 0:68779c92cffa | 59 | #define REG_GPIO_CLR_PIN 0x11 |
Rhyme | 0:68779c92cffa | 60 | #define REG_GPIO_MP_STA 0x12 |
Rhyme | 0:68779c92cffa | 61 | #define REG_GPIO_DIR 0x13 |
Rhyme | 0:68779c92cffa | 62 | #define REG_GPIO_ED 0x14 |
Rhyme | 0:68779c92cffa | 63 | #define REG_GPIO_RE 0x15 |
Rhyme | 0:68779c92cffa | 64 | #define REG_GPIO_FE 0x16 |
Rhyme | 0:68779c92cffa | 65 | #define REG_GPIO_AF 0x17 |
Rhyme | 0:68779c92cffa | 66 | #define REG_ADC_CTRL1 0x20 |
Rhyme | 0:68779c92cffa | 67 | #define REG_ADC_CTRL1_12BIT 0x08 |
Rhyme | 0:68779c92cffa | 68 | #define REG_ADC_CTRL1_10BIT 0x00 |
Rhyme | 0:68779c92cffa | 69 | |
Rhyme | 0:68779c92cffa | 70 | #define REG_ADC_CTRL2 0x21 |
Rhyme | 0:68779c92cffa | 71 | #define REG_ADC_CTRL2_1_625MHZ 0x00 |
Rhyme | 0:68779c92cffa | 72 | #define REG_ADC_CTRL2_3_25MHZ 0x01 |
Rhyme | 0:68779c92cffa | 73 | #define REG_ADC_CTRL2_6_5MHZ 0x02 |
Rhyme | 0:68779c92cffa | 74 | |
Rhyme | 0:68779c92cffa | 75 | #define REG_ADC_CAPT 0x22 |
Rhyme | 0:68779c92cffa | 76 | #define REG_ADC_DATA_CH0 0x30 |
Rhyme | 0:68779c92cffa | 77 | #define REG_ADC_DATA_CH1 0x32 |
Rhyme | 0:68779c92cffa | 78 | #define REG_ADC_DATA_CH4 0x38 |
Rhyme | 0:68779c92cffa | 79 | #define REG_ADC_DATA_CH5 0x3A |
Rhyme | 0:68779c92cffa | 80 | #define REG_ADC_DATA_CH6 0x3C |
Rhyme | 0:68779c92cffa | 81 | #define REG_ADC_DATA_CH7 0x3E |
Rhyme | 0:68779c92cffa | 82 | #define REG_TSC_CTRL 0x40 |
Rhyme | 0:68779c92cffa | 83 | #define REG_TSC_CTRL_EN 0x01 |
Rhyme | 0:68779c92cffa | 84 | #define REG_TSC_CTRL_XYZ 0x00 |
Rhyme | 0:68779c92cffa | 85 | #define REG_TSC_CTRL_XY 0x02 |
Rhyme | 0:68779c92cffa | 86 | |
Rhyme | 0:68779c92cffa | 87 | #define REG_TSC_CFG 0x41 |
Rhyme | 0:68779c92cffa | 88 | #define REG_TSC_CFG_1SAMPLE 0x00 |
Rhyme | 0:68779c92cffa | 89 | #define REG_TSC_CFG_2SAMPLE 0x40 |
Rhyme | 0:68779c92cffa | 90 | #define REG_TSC_CFG_4SAMPLE 0x80 |
Rhyme | 0:68779c92cffa | 91 | #define REG_TSC_CFG_8SAMPLE 0xC0 |
Rhyme | 0:68779c92cffa | 92 | #define REG_TSC_CFG_DELAY_10US 0x00 |
Rhyme | 0:68779c92cffa | 93 | #define REG_TSC_CFG_DELAY_50US 0x08 |
Rhyme | 0:68779c92cffa | 94 | #define REG_TSC_CFG_DELAY_100US 0x10 |
Rhyme | 0:68779c92cffa | 95 | #define REG_TSC_CFG_DELAY_500US 0x18 |
Rhyme | 0:68779c92cffa | 96 | #define REG_TSC_CFG_DELAY_1MS 0x20 |
Rhyme | 0:68779c92cffa | 97 | #define REG_TSC_CFG_DELAY_5MS 0x28 |
Rhyme | 0:68779c92cffa | 98 | #define REG_TSC_CFG_DELAY_10MS 0x30 |
Rhyme | 0:68779c92cffa | 99 | #define REG_TSC_CFG_DELAY_50MS 0x38 |
Rhyme | 0:68779c92cffa | 100 | #define REG_TSC_CFG_SETTLE_10US 0x00 |
Rhyme | 0:68779c92cffa | 101 | #define REG_TSC_CFG_SETTLE_100US 0x01 |
Rhyme | 0:68779c92cffa | 102 | #define REG_TSC_CFG_SETTLE_500US 0x02 |
Rhyme | 0:68779c92cffa | 103 | #define REG_TSC_CFG_SETTLE_1MS 0x03 |
Rhyme | 0:68779c92cffa | 104 | #define REG_TSC_CFG_SETTLE_5MS 0x04 |
Rhyme | 0:68779c92cffa | 105 | #define REG_TSC_CFG_SETTLE_10MS 0x05 |
Rhyme | 0:68779c92cffa | 106 | #define REG_TSC_CFG_SETTLE_50MS 0x06 |
Rhyme | 0:68779c92cffa | 107 | #define REG_TSC_CFG_SETTLE_100MS 0x07 |
Rhyme | 0:68779c92cffa | 108 | |
Rhyme | 0:68779c92cffa | 109 | #define REG_WDW_TR_X 0x42 |
Rhyme | 0:68779c92cffa | 110 | #define REG_WDW_TR_Y 0x44 |
Rhyme | 0:68779c92cffa | 111 | #define REG_WDW_BL_X 0x46 |
Rhyme | 0:68779c92cffa | 112 | #define REG_WDW_BL_Y 0x48 |
Rhyme | 0:68779c92cffa | 113 | #define REG_FIFO_TH 0x4A |
Rhyme | 0:68779c92cffa | 114 | #define REG_FIFO_STA 0x4B |
Rhyme | 0:68779c92cffa | 115 | #define REG_FIFO_SIZE 0x4C |
Rhyme | 0:68779c92cffa | 116 | #define REG_TSC_DATA_X 0x4D |
Rhyme | 0:68779c92cffa | 117 | #define REG_TSC_DATA_Y 0x4F |
Rhyme | 0:68779c92cffa | 118 | #define REG_TSC_DATA_Z 0x51 |
Rhyme | 0:68779c92cffa | 119 | #define REG_TSC_DATA_XYZ 0x52 |
Rhyme | 0:68779c92cffa | 120 | #define REG_TSC_FRACT_XYZ 0x56 |
Rhyme | 0:68779c92cffa | 121 | #define REG_TSC_DATA 0x57 |
Rhyme | 0:68779c92cffa | 122 | #define REG_TSC_I_DRIVE 0x58 |
Rhyme | 0:68779c92cffa | 123 | #define REG_TSC_SHIELD 0x59 |
Rhyme | 0:68779c92cffa | 124 | |
Rhyme | 0:68779c92cffa | 125 | SPI_STMPE610::SPI_STMPE610(PinName mosi, PinName miso, PinName sclk, PinName cs) : |
Rhyme | 0:68779c92cffa | 126 | m_spi(mosi, miso, sclk), m_cs(cs) { |
Rhyme | 0:68779c92cffa | 127 | // activate the peripheral |
Rhyme | 0:68779c92cffa | 128 | m_cs = 0 ; |
Rhyme | 0:68779c92cffa | 129 | _mode = 0 ; |
Rhyme | 0:68779c92cffa | 130 | m_spi.frequency(1000000) ; |
Rhyme | 0:68779c92cffa | 131 | m_spi.format(8, 0) ; |
Rhyme | 0:68779c92cffa | 132 | write8(REG_SYS_CTRL1, REG_SYS_CTRL1_RESET) ; |
Rhyme | 0:68779c92cffa | 133 | wait(0.1) ; |
Rhyme | 0:68779c92cffa | 134 | write8(REG_SYS_CTRL2, 0x00) ; // turn on clocks |
Rhyme | 0:68779c92cffa | 135 | write8(REG_TSC_CFG, |
Rhyme | 0:68779c92cffa | 136 | REG_TSC_CFG_4SAMPLE |
Rhyme | 0:68779c92cffa | 137 | | REG_TSC_CFG_DELAY_100US |
Rhyme | 0:68779c92cffa | 138 | | REG_TSC_CFG_SETTLE_1MS ) ; |
Rhyme | 0:68779c92cffa | 139 | |
Rhyme | 0:68779c92cffa | 140 | write8(REG_TSC_CTRL, REG_TSC_CTRL_XYZ | REG_TSC_CTRL_EN) ; |
Rhyme | 0:68779c92cffa | 141 | m_cs = 1 ; |
Rhyme | 0:68779c92cffa | 142 | } |
Rhyme | 0:68779c92cffa | 143 | |
Rhyme | 0:68779c92cffa | 144 | SPI_STMPE610::~SPI_STMPE610() { } |
Rhyme | 0:68779c92cffa | 145 | |
Rhyme | 0:68779c92cffa | 146 | void SPI_STMPE610::readRegs(int addr, uint8_t * data, int len) { |
Rhyme | 0:68779c92cffa | 147 | m_cs = 0 ; |
Rhyme | 0:68779c92cffa | 148 | |
Rhyme | 0:68779c92cffa | 149 | for (int i = 0 ; i < len ; i++ ) { |
Rhyme | 0:68779c92cffa | 150 | m_spi.write((addr+i)|0x80) ; // spacify address to read |
Rhyme | 0:68779c92cffa | 151 | data[i] = m_spi.write((addr+i)|0x80) ; |
Rhyme | 0:68779c92cffa | 152 | } |
Rhyme | 0:68779c92cffa | 153 | m_spi.write(0x00) ; // to terminate read mode |
Rhyme | 0:68779c92cffa | 154 | m_cs = 1 ; |
Rhyme | 0:68779c92cffa | 155 | } |
Rhyme | 0:68779c92cffa | 156 | |
Rhyme | 0:68779c92cffa | 157 | void SPI_STMPE610::writeRegs(uint8_t * data, int len) { |
Rhyme | 0:68779c92cffa | 158 | m_cs = 0 ; |
Rhyme | 0:68779c92cffa | 159 | for (int i = 0 ; i < len ; i++ ) { |
Rhyme | 0:68779c92cffa | 160 | m_spi.write(data[i]) ; |
Rhyme | 0:68779c92cffa | 161 | } |
Rhyme | 0:68779c92cffa | 162 | m_cs = 1 ; |
Rhyme | 0:68779c92cffa | 163 | } |
Rhyme | 0:68779c92cffa | 164 | |
Rhyme | 0:68779c92cffa | 165 | void SPI_STMPE610::write8(int addr, uint8_t data8) |
Rhyme | 0:68779c92cffa | 166 | { |
Rhyme | 0:68779c92cffa | 167 | uint8_t data[2] ; |
Rhyme | 0:68779c92cffa | 168 | data[0] = addr ; |
Rhyme | 0:68779c92cffa | 169 | data[1] = data8 ; |
Rhyme | 0:68779c92cffa | 170 | writeRegs(data, 2) ; |
Rhyme | 0:68779c92cffa | 171 | } |
Rhyme | 0:68779c92cffa | 172 | |
Rhyme | 0:68779c92cffa | 173 | uint8_t SPI_STMPE610::read8(int addr) |
Rhyme | 0:68779c92cffa | 174 | { |
Rhyme | 0:68779c92cffa | 175 | uint8_t data[1] ; |
Rhyme | 0:68779c92cffa | 176 | readRegs(addr, data, 1) ; |
Rhyme | 0:68779c92cffa | 177 | return( data[0] ) ; |
Rhyme | 0:68779c92cffa | 178 | } |
Rhyme | 0:68779c92cffa | 179 | |
Rhyme | 0:68779c92cffa | 180 | void SPI_STMPE610::write16(int addr, uint16_t data16) |
Rhyme | 0:68779c92cffa | 181 | { |
Rhyme | 0:68779c92cffa | 182 | uint8_t data[3] ; |
Rhyme | 0:68779c92cffa | 183 | data[0] = addr ; |
Rhyme | 0:68779c92cffa | 184 | data[1] = (data16 >> 8) & 0xFF ; |
Rhyme | 0:68779c92cffa | 185 | data[2] = data16 & 0xFF ; |
Rhyme | 0:68779c92cffa | 186 | writeRegs(data, 3) ; |
Rhyme | 0:68779c92cffa | 187 | } |
Rhyme | 0:68779c92cffa | 188 | |
Rhyme | 0:68779c92cffa | 189 | uint16_t SPI_STMPE610::read16(int addr) |
Rhyme | 0:68779c92cffa | 190 | { |
Rhyme | 0:68779c92cffa | 191 | uint8_t data[2] ; |
Rhyme | 0:68779c92cffa | 192 | uint16_t value = 0 ; |
Rhyme | 0:68779c92cffa | 193 | readRegs(addr, data, 2) ; |
Rhyme | 0:68779c92cffa | 194 | value = (data[0] << 8) | data[1] ; |
Rhyme | 0:68779c92cffa | 195 | return( value ) ; |
Rhyme | 0:68779c92cffa | 196 | } |
Rhyme | 0:68779c92cffa | 197 | |
Rhyme | 0:68779c92cffa | 198 | int SPI_STMPE610::getRAWPoint(uint16_t *x, uint16_t *y, uint16_t *z) |
Rhyme | 0:68779c92cffa | 199 | { |
Rhyme | 0:68779c92cffa | 200 | uint8_t data[8], touched = 0 ; |
Rhyme | 0:68779c92cffa | 201 | data[0] = REG_TSC_CTRL ; |
Rhyme | 0:68779c92cffa | 202 | data[1] = REG_TSC_CTRL_EN ; |
Rhyme | 0:68779c92cffa | 203 | writeRegs(data, 2) ; |
Rhyme | 0:68779c92cffa | 204 | wait(0.01) ; |
Rhyme | 0:68779c92cffa | 205 | |
Rhyme | 0:68779c92cffa | 206 | readRegs(REG_TSC_CTRL, data, 1) ; |
Rhyme | 0:68779c92cffa | 207 | touched = data[0] & 0x80 ; |
Rhyme | 0:68779c92cffa | 208 | if (touched) { //Touch Detected |
Rhyme | 0:68779c92cffa | 209 | readRegs(REG_TSC_DATA_X, data,5) ; |
Rhyme | 0:68779c92cffa | 210 | *x = (data[0] << 8) | data[1] ; |
Rhyme | 0:68779c92cffa | 211 | *y = (data[2] << 8) | data[3] ; |
Rhyme | 0:68779c92cffa | 212 | *z = data[4] ; |
Rhyme | 0:68779c92cffa | 213 | } else { |
Rhyme | 0:68779c92cffa | 214 | *x = 0 ; |
Rhyme | 0:68779c92cffa | 215 | *y = 0 ; |
Rhyme | 0:68779c92cffa | 216 | *z = 0 ; |
Rhyme | 0:68779c92cffa | 217 | } |
Rhyme | 0:68779c92cffa | 218 | |
Rhyme | 0:68779c92cffa | 219 | data[0] = 0x4B ; |
Rhyme | 0:68779c92cffa | 220 | data[1] = 0x01 ; |
Rhyme | 0:68779c92cffa | 221 | writeRegs(data, 2) ; // clear FIFO |
Rhyme | 0:68779c92cffa | 222 | |
Rhyme | 0:68779c92cffa | 223 | data[0] = REG_TSC_CTRL ; |
Rhyme | 0:68779c92cffa | 224 | data[1] = 0x00 ; // disable TSC |
Rhyme | 0:68779c92cffa | 225 | writeRegs(data, 2) ; |
Rhyme | 0:68779c92cffa | 226 | |
Rhyme | 0:68779c92cffa | 227 | return( touched & (*x || *y || *z)) ; |
Rhyme | 0:68779c92cffa | 228 | } |