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PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

Dependents:   YATTT sd_map_test cPong SnowDemo ... more

PokittoLib

Library for programming Pokitto hardware

How to Use

  1. Import this library to online compiler (see button "import" on the right hand side
  2. DO NOT import mbed-src anymore, a better version is now included inside PokittoLib
  3. Change My_settings.h according to your project
  4. Start coding!

POKITTO_HW/clock_11u6x.h@30:796f9611d2ac, 2018-01-30 (annotated)

Committer:
Pokitto
Date:
Tue Jan 30 10:41:12 2018 +0000
Revision:
30:796f9611d2ac
Child:
58:5f58a2846a20
Sound enhancements done

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pokitto 30:796f9611d2ac 1 /*
Pokitto 30:796f9611d2ac 2 * @brief LPC11U6X Clock control functions
Pokitto 30:796f9611d2ac 3 *
Pokitto 30:796f9611d2ac 4 * @note
Pokitto 30:796f9611d2ac 5 * Copyright(C) NXP Semiconductors, 2013
Pokitto 30:796f9611d2ac 6 * All rights reserved.
Pokitto 30:796f9611d2ac 7 *
Pokitto 30:796f9611d2ac 8 * @par
Pokitto 30:796f9611d2ac 9 * Software that is described herein is for illustrative purposes only
Pokitto 30:796f9611d2ac 10 * which provides customers with programming information regarding the
Pokitto 30:796f9611d2ac 11 * LPC products. This software is supplied "AS IS" without any warranties of
Pokitto 30:796f9611d2ac 12 * any kind, and NXP Semiconductors and its licensor disclaim any and
Pokitto 30:796f9611d2ac 13 * all warranties, express or implied, including all implied warranties of
Pokitto 30:796f9611d2ac 14 * merchantability, fitness for a particular purpose and non-infringement of
Pokitto 30:796f9611d2ac 15 * intellectual property rights. NXP Semiconductors assumes no responsibility
Pokitto 30:796f9611d2ac 16 * or liability for the use of the software, conveys no license or rights under any
Pokitto 30:796f9611d2ac 17 * patent, copyright, mask work right, or any other intellectual property rights in
Pokitto 30:796f9611d2ac 18 * or to any products. NXP Semiconductors reserves the right to make changes
Pokitto 30:796f9611d2ac 19 * in the software without notification. NXP Semiconductors also makes no
Pokitto 30:796f9611d2ac 20 * representation or warranty that such application will be suitable for the
Pokitto 30:796f9611d2ac 21 * specified use without further testing or modification.
Pokitto 30:796f9611d2ac 22 *
Pokitto 30:796f9611d2ac 23 * @par
Pokitto 30:796f9611d2ac 24 * Permission to use, copy, modify, and distribute this software and its
Pokitto 30:796f9611d2ac 25 * documentation is hereby granted, under NXP Semiconductors' and its
Pokitto 30:796f9611d2ac 26 * licensor's relevant copyrights in the software, without fee, provided that it
Pokitto 30:796f9611d2ac 27 * is used in conjunction with NXP Semiconductors microcontrollers. This
Pokitto 30:796f9611d2ac 28 * copyright, permission, and disclaimer notice must appear in all copies of
Pokitto 30:796f9611d2ac 29 * this code.
Pokitto 30:796f9611d2ac 30 */
Pokitto 30:796f9611d2ac 31
Pokitto 30:796f9611d2ac 32 #ifndef __CLOCK_11U6X_H_
Pokitto 30:796f9611d2ac 33 #define __CLOCK_11U6X_H_
Pokitto 30:796f9611d2ac 34
Pokitto 30:796f9611d2ac 35 #include "lpc_defs.h"
Pokitto 30:796f9611d2ac 36 #define STATIC static
Pokitto 30:796f9611d2ac 37 #define INLINE inline
Pokitto 30:796f9611d2ac 38 #define bool unsigned char
Pokitto 30:796f9611d2ac 39
Pokitto 30:796f9611d2ac 40 #ifdef __cplusplus
Pokitto 30:796f9611d2ac 41 extern "C" {
Pokitto 30:796f9611d2ac 42 #endif
Pokitto 30:796f9611d2ac 43
Pokitto 30:796f9611d2ac 44 /** @defgroup CLOCK_11U6X CHIP: LPC11u6x Clock Control block driver
Pokitto 30:796f9611d2ac 45 * @ingroup CHIP_11U6X_Drivers
Pokitto 30:796f9611d2ac 46 * @{
Pokitto 30:796f9611d2ac 47 */
Pokitto 30:796f9611d2ac 48
Pokitto 30:796f9611d2ac 49 /** Internal oscillator frequency */
Pokitto 30:796f9611d2ac 50 #define SYSCTL_IRC_FREQ (12000000)
Pokitto 30:796f9611d2ac 51
Pokitto 30:796f9611d2ac 52 /**
Pokitto 30:796f9611d2ac 53 * @brief Set System PLL divider values
Pokitto 30:796f9611d2ac 54 * @param msel : PLL feedback divider value. M = msel + 1.
Pokitto 30:796f9611d2ac 55 * @param psel : PLL post divider value. P = (1<<psel).
Pokitto 30:796f9611d2ac 56 * @return Nothing
Pokitto 30:796f9611d2ac 57 * @note See the user manual for how to setup the PLL.
Pokitto 30:796f9611d2ac 58 */
Pokitto 30:796f9611d2ac 59 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
Pokitto 30:796f9611d2ac 60 {
Pokitto 30:796f9611d2ac 61 LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
Pokitto 30:796f9611d2ac 62 }
Pokitto 30:796f9611d2ac 63
Pokitto 30:796f9611d2ac 64 /**
Pokitto 30:796f9611d2ac 65 * @brief Read System PLL lock status
Pokitto 30:796f9611d2ac 66 * @return true of the PLL is locked. false if not locked
Pokitto 30:796f9611d2ac 67 */
Pokitto 30:796f9611d2ac 68 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
Pokitto 30:796f9611d2ac 69 {
Pokitto 30:796f9611d2ac 70 return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
Pokitto 30:796f9611d2ac 71 }
Pokitto 30:796f9611d2ac 72
Pokitto 30:796f9611d2ac 73 /**
Pokitto 30:796f9611d2ac 74 * Clock sources for system PLL
Pokitto 30:796f9611d2ac 75 */
Pokitto 30:796f9611d2ac 76 typedef enum CHIP_SYSCTL_PLLCLKSRC {
Pokitto 30:796f9611d2ac 77 SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator in */
Pokitto 30:796f9611d2ac 78 SYSCTL_PLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
Pokitto 30:796f9611d2ac 79 SYSCTL_PLLCLKSRC_SYSOSC = SYSCTL_PLLCLKSRC_MAINOSC,
Pokitto 30:796f9611d2ac 80 SYSCTL_PLLCLKSRC_RESERVED1, /*!< Reserved */
Pokitto 30:796f9611d2ac 81 SYSCTL_PLLCLKSRC_RTC32K, /*!< RTC 32KHz clock */
Pokitto 30:796f9611d2ac 82 } CHIP_SYSCTL_PLLCLKSRC_T;
Pokitto 30:796f9611d2ac 83
Pokitto 30:796f9611d2ac 84 /**
Pokitto 30:796f9611d2ac 85 * @brief Set System PLL clock source
Pokitto 30:796f9611d2ac 86 * @param src : Clock source for system PLL
Pokitto 30:796f9611d2ac 87 * @return Nothing
Pokitto 30:796f9611d2ac 88 * @note This function will also toggle the clock source update register
Pokitto 30:796f9611d2ac 89 * to update the clock source.
Pokitto 30:796f9611d2ac 90 */
Pokitto 30:796f9611d2ac 91 void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
Pokitto 30:796f9611d2ac 92
Pokitto 30:796f9611d2ac 93 /**
Pokitto 30:796f9611d2ac 94 * @brief Set USB PLL divider values
Pokitto 30:796f9611d2ac 95 * @param msel : PLL feedback divider value. M = msel + 1.
Pokitto 30:796f9611d2ac 96 * @param psel : PLL post divider value. P = (1<<psel).
Pokitto 30:796f9611d2ac 97 * @return Nothing
Pokitto 30:796f9611d2ac 98 * @note See the user manual for how to setup the PLL.
Pokitto 30:796f9611d2ac 99 */
Pokitto 30:796f9611d2ac 100 STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
Pokitto 30:796f9611d2ac 101 {
Pokitto 30:796f9611d2ac 102 LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
Pokitto 30:796f9611d2ac 103 }
Pokitto 30:796f9611d2ac 104
Pokitto 30:796f9611d2ac 105 /**
Pokitto 30:796f9611d2ac 106 * @brief Read USB PLL lock status
Pokitto 30:796f9611d2ac 107 * @return true of the PLL is locked. false if not locked
Pokitto 30:796f9611d2ac 108 */
Pokitto 30:796f9611d2ac 109 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
Pokitto 30:796f9611d2ac 110 {
Pokitto 30:796f9611d2ac 111 return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
Pokitto 30:796f9611d2ac 112 }
Pokitto 30:796f9611d2ac 113
Pokitto 30:796f9611d2ac 114 /**
Pokitto 30:796f9611d2ac 115 * Clock sources for USB PLL
Pokitto 30:796f9611d2ac 116 */
Pokitto 30:796f9611d2ac 117 typedef enum CHIP_SYSCTL_USBPLLCLKSRC {
Pokitto 30:796f9611d2ac 118 SYSCTL_USBPLLCLKSRC_IRC = 0, /*!< Internal oscillator in */
Pokitto 30:796f9611d2ac 119 SYSCTL_USBPLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
Pokitto 30:796f9611d2ac 120 SYSCTL_USBPLLCLKSRC_SYSOSC = SYSCTL_USBPLLCLKSRC_MAINOSC,
Pokitto 30:796f9611d2ac 121 SYSCTL_USBPLLCLKSRC_RESERVED1, /*!< Reserved */
Pokitto 30:796f9611d2ac 122 SYSCTL_USBPLLCLKSRC_RESERVED2, /*!< Reserved */
Pokitto 30:796f9611d2ac 123 } CHIP_SYSCTL_USBPLLCLKSRC_T;
Pokitto 30:796f9611d2ac 124
Pokitto 30:796f9611d2ac 125 /**
Pokitto 30:796f9611d2ac 126 * @brief Set USB PLL clock source
Pokitto 30:796f9611d2ac 127 * @param src : Clock source for USB PLL
Pokitto 30:796f9611d2ac 128 * @return Nothing
Pokitto 30:796f9611d2ac 129 * @note This function will also toggle the clock source update register
Pokitto 30:796f9611d2ac 130 * to update the clock source.
Pokitto 30:796f9611d2ac 131 */
Pokitto 30:796f9611d2ac 132 void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_USBPLLCLKSRC_T src);
Pokitto 30:796f9611d2ac 133
Pokitto 30:796f9611d2ac 134 /**
Pokitto 30:796f9611d2ac 135 * @brief Bypass System Oscillator and set oscillator frequency range
Pokitto 30:796f9611d2ac 136 * @param bypass : Flag to bypass oscillator
Pokitto 30:796f9611d2ac 137 * @param highfr : Flag to set oscillator range from 15-25 MHz
Pokitto 30:796f9611d2ac 138 * @return Nothing
Pokitto 30:796f9611d2ac 139 * @note Sets the PLL input to bypass the oscillator. This would be
Pokitto 30:796f9611d2ac 140 * used if an external clock that is not an oscillator is attached
Pokitto 30:796f9611d2ac 141 * to the XTALIN pin.
Pokitto 30:796f9611d2ac 142 */
Pokitto 30:796f9611d2ac 143 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
Pokitto 30:796f9611d2ac 144
Pokitto 30:796f9611d2ac 145 /**
Pokitto 30:796f9611d2ac 146 * @brief Enable the RTC 32KHz output
Pokitto 30:796f9611d2ac 147 * @return Nothing
Pokitto 30:796f9611d2ac 148 * @note This clock can be used for the main clock directly, but
Pokitto 30:796f9611d2ac 149 * do not use this clock with the system PLL.
Pokitto 30:796f9611d2ac 150 */
Pokitto 30:796f9611d2ac 151 STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
Pokitto 30:796f9611d2ac 152 {
Pokitto 30:796f9611d2ac 153 LPC_SYSCTL->RTCOSCCTRL = 1;
Pokitto 30:796f9611d2ac 154 }
Pokitto 30:796f9611d2ac 155
Pokitto 30:796f9611d2ac 156 /**
Pokitto 30:796f9611d2ac 157 * @brief Disable the RTC 32KHz output
Pokitto 30:796f9611d2ac 158 * @return Nothing
Pokitto 30:796f9611d2ac 159 */
Pokitto 30:796f9611d2ac 160 STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
Pokitto 30:796f9611d2ac 161 {
Pokitto 30:796f9611d2ac 162 LPC_SYSCTL->RTCOSCCTRL = 0;
Pokitto 30:796f9611d2ac 163 }
Pokitto 30:796f9611d2ac 164
Pokitto 30:796f9611d2ac 165 /**
Pokitto 30:796f9611d2ac 166 * Watchdog and low frequency oscillator frequencies plus or minus 40%
Pokitto 30:796f9611d2ac 167 */
Pokitto 30:796f9611d2ac 168 typedef enum CHIP_WDTLFO_OSC {
Pokitto 30:796f9611d2ac 169 WDTLFO_OSC_ILLEGAL,
Pokitto 30:796f9611d2ac 170 WDTLFO_OSC_0_60, /*!< 0.6 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 171 WDTLFO_OSC_1_05, /*!< 1.05 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 172 WDTLFO_OSC_1_40, /*!< 1.4 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 173 WDTLFO_OSC_1_75, /*!< 1.75 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 174 WDTLFO_OSC_2_10, /*!< 2.1 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 175 WDTLFO_OSC_2_40, /*!< 2.4 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 176 WDTLFO_OSC_2_70, /*!< 2.7 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 177 WDTLFO_OSC_3_00, /*!< 3.0 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 178 WDTLFO_OSC_3_25, /*!< 3.25 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 179 WDTLFO_OSC_3_50, /*!< 3.5 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 180 WDTLFO_OSC_3_75, /*!< 3.75 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 181 WDTLFO_OSC_4_00, /*!< 4.0 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 182 WDTLFO_OSC_4_20, /*!< 4.2 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 183 WDTLFO_OSC_4_40, /*!< 4.4 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 184 WDTLFO_OSC_4_60 /*!< 4.6 MHz watchdog/LFO rate */
Pokitto 30:796f9611d2ac 185 } CHIP_WDTLFO_OSC_T;
Pokitto 30:796f9611d2ac 186
Pokitto 30:796f9611d2ac 187 /**
Pokitto 30:796f9611d2ac 188 * @brief Setup Watchdog oscillator rate and divider
Pokitto 30:796f9611d2ac 189 * @param wdtclk : Selected watchdog clock rate
Pokitto 30:796f9611d2ac 190 * @param div : Watchdog divider value, even value between 2 and 64
Pokitto 30:796f9611d2ac 191 * @return Nothing
Pokitto 30:796f9611d2ac 192 * @note Watchdog rate = selected rate divided by divider rate
Pokitto 30:796f9611d2ac 193 */
Pokitto 30:796f9611d2ac 194 STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
Pokitto 30:796f9611d2ac 195 {
Pokitto 30:796f9611d2ac 196 LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
Pokitto 30:796f9611d2ac 197 }
Pokitto 30:796f9611d2ac 198
Pokitto 30:796f9611d2ac 199 /**
Pokitto 30:796f9611d2ac 200 * Clock sources for main system clock
Pokitto 30:796f9611d2ac 201 */
Pokitto 30:796f9611d2ac 202 typedef enum CHIP_SYSCTL_MAINCLKSRC {
Pokitto 30:796f9611d2ac 203 SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
Pokitto 30:796f9611d2ac 204 SYSCTL_MAINCLKSRC_PLLIN, /*!< System PLL input */
Pokitto 30:796f9611d2ac 205 SYSCTL_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */
Pokitto 30:796f9611d2ac 206 SYSCTL_MAINCLKSRC_PLLOUT, /*!< System PLL output */
Pokitto 30:796f9611d2ac 207 } CHIP_SYSCTL_MAINCLKSRC_T;
Pokitto 30:796f9611d2ac 208
Pokitto 30:796f9611d2ac 209 /**
Pokitto 30:796f9611d2ac 210 * @brief Set main system clock source
Pokitto 30:796f9611d2ac 211 * @param src : Clock source for main system
Pokitto 30:796f9611d2ac 212 * @return Nothing
Pokitto 30:796f9611d2ac 213 * @note This function will also toggle the clock source update register
Pokitto 30:796f9611d2ac 214 * to update the clock source.
Pokitto 30:796f9611d2ac 215 */
Pokitto 30:796f9611d2ac 216 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
Pokitto 30:796f9611d2ac 217
Pokitto 30:796f9611d2ac 218 /**
Pokitto 30:796f9611d2ac 219 * @brief Returns the main clock source
Pokitto 30:796f9611d2ac 220 * @return Which clock is used for the core clock source?
Pokitto 30:796f9611d2ac 221 */
Pokitto 30:796f9611d2ac 222 STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
Pokitto 30:796f9611d2ac 223 {
Pokitto 30:796f9611d2ac 224 return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
Pokitto 30:796f9611d2ac 225 }
Pokitto 30:796f9611d2ac 226
Pokitto 30:796f9611d2ac 227 /**
Pokitto 30:796f9611d2ac 228 * @brief Set system clock divider
Pokitto 30:796f9611d2ac 229 * @param div : divider for system clock
Pokitto 30:796f9611d2ac 230 * @return Nothing
Pokitto 30:796f9611d2ac 231 * @note Use 0 to disable, or a divider value of 1 to 255. The system clock
Pokitto 30:796f9611d2ac 232 * rate is the main system clock divided by this value.
Pokitto 30:796f9611d2ac 233 */
Pokitto 30:796f9611d2ac 234 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
Pokitto 30:796f9611d2ac 235 {
Pokitto 30:796f9611d2ac 236 LPC_SYSCTL->SYSAHBCLKDIV = div;
Pokitto 30:796f9611d2ac 237 }
Pokitto 30:796f9611d2ac 238
Pokitto 30:796f9611d2ac 239 /**
Pokitto 30:796f9611d2ac 240 * System and peripheral clocks
Pokitto 30:796f9611d2ac 241 */
Pokitto 30:796f9611d2ac 242 typedef enum CHIP_SYSCTL_CLOCK {
Pokitto 30:796f9611d2ac 243 SYSCTL_CLOCK_SYS = 0, /*!< 0: System clock */
Pokitto 30:796f9611d2ac 244 SYSCTL_CLOCK_ROM, /*!< 1: ROM clock */
Pokitto 30:796f9611d2ac 245 SYSCTL_CLOCK_RAM0, /*!< 2: RAM0 clock */
Pokitto 30:796f9611d2ac 246 SYSCTL_CLOCK_FLASHREG, /*!< 3: FLASH register interface clock */
Pokitto 30:796f9611d2ac 247 SYSCTL_CLOCK_FLASHARRAY, /*!< 4: FLASH array access clock */
Pokitto 30:796f9611d2ac 248 SYSCTL_CLOCK_I2C0, /*!< 5: I2C0 clock */
Pokitto 30:796f9611d2ac 249 SYSCTL_CLOCK_GPIO, /*!< 6: GPIO clock */
Pokitto 30:796f9611d2ac 250 SYSCTL_CLOCK_CT16B0, /*!< 7: 16-bit Counter/timer 0 clock */
Pokitto 30:796f9611d2ac 251 SYSCTL_CLOCK_CT16B1, /*!< 8: 16-bit Counter/timer 1 clock */
Pokitto 30:796f9611d2ac 252 SYSCTL_CLOCK_CT32B0, /*!< 9: 32-bit Counter/timer 0 clock */
Pokitto 30:796f9611d2ac 253 SYSCTL_CLOCK_CT32B1, /*!< 10: 32-bit Counter/timer 1 clock */
Pokitto 30:796f9611d2ac 254 SYSCTL_CLOCK_SSP0, /*!< 11: SSP0 clock */
Pokitto 30:796f9611d2ac 255 SYSCTL_CLOCK_UART0, /*!< 12: UART0 clock */
Pokitto 30:796f9611d2ac 256 SYSCTL_CLOCK_ADC, /*!< 13: ADC clock */
Pokitto 30:796f9611d2ac 257 SYSCTL_CLOCK_USB, /*!< 14: USB clock */
Pokitto 30:796f9611d2ac 258 SYSCTL_CLOCK_WDT, /*!< 15: Watchdog timer clock */
Pokitto 30:796f9611d2ac 259 SYSCTL_CLOCK_IOCON, /*!< 16: IOCON block clock */
Pokitto 30:796f9611d2ac 260 SYSCTL_CLOCK_RESERVED17, /*!< 17: Reserved */
Pokitto 30:796f9611d2ac 261 SYSCTL_CLOCK_SSP1, /*!< 18: SSP1 clock */
Pokitto 30:796f9611d2ac 262 SYSCTL_CLOCK_PINT, /*!< 19: GPIO Pin int register interface clock */
Pokitto 30:796f9611d2ac 263 SYSCTL_CLOCK_USART1, /*!< 20: USART1 clock */
Pokitto 30:796f9611d2ac 264 SYSCTL_CLOCK_USART2, /*!< 21: USART2 clock */
Pokitto 30:796f9611d2ac 265 SYSCTL_CLOCK_USART3_4, /*!< 22: USART3_4 clock */
Pokitto 30:796f9611d2ac 266 SYSCTL_CLOCK_P0INT, /*!< 23: GPIO GROUP1 interrupt register clock */
Pokitto 30:796f9611d2ac 267 SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT,/*!< 23: GPIO GROUP0 interrupt register interface clock */
Pokitto 30:796f9611d2ac 268 SYSCTL_CLOCK_P1INT, /*!< 24: GPIO GROUP1 interrupt register clock */
Pokitto 30:796f9611d2ac 269 SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT,/*!< 24: GPIO GROUP1 interrupt register interface clock */
Pokitto 30:796f9611d2ac 270 SYSCTL_CLOCK_I2C1, /*!< 25: I2C1 clock */
Pokitto 30:796f9611d2ac 271 SYSCTL_CLOCK_RAM1, /*!< 26: SRAM block clock */
Pokitto 30:796f9611d2ac 272 SYSCTL_CLOCK_USBRAM, /*!< 27: USB SRAM block clock */
Pokitto 30:796f9611d2ac 273 SYSCTL_CLOCK_CRC, /*!< 25: CRC clock */
Pokitto 30:796f9611d2ac 274 SYSCTL_CLOCK_DMA, /*!< 25: DMA clock */
Pokitto 30:796f9611d2ac 275 SYSCTL_CLOCK_RTC, /*!< 25: RTC clock */
Pokitto 30:796f9611d2ac 276 SYSCTL_CLOCK_SCT0_1, /*!< 25: SCT 0/1 clock */
Pokitto 30:796f9611d2ac 277 } CHIP_SYSCTL_CLOCK_T;
Pokitto 30:796f9611d2ac 278
Pokitto 30:796f9611d2ac 279 /**
Pokitto 30:796f9611d2ac 280 * @brief Enable a system or peripheral clock
Pokitto 30:796f9611d2ac 281 * @param clk : Clock to enable
Pokitto 30:796f9611d2ac 282 * @return Nothing
Pokitto 30:796f9611d2ac 283 */
Pokitto 30:796f9611d2ac 284 STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
Pokitto 30:796f9611d2ac 285 {
Pokitto 30:796f9611d2ac 286 LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
Pokitto 30:796f9611d2ac 287 }
Pokitto 30:796f9611d2ac 288
Pokitto 30:796f9611d2ac 289 /**
Pokitto 30:796f9611d2ac 290 * @brief Disable a system or peripheral clock
Pokitto 30:796f9611d2ac 291 * @param clk : Clock to disable
Pokitto 30:796f9611d2ac 292 * @return Nothing
Pokitto 30:796f9611d2ac 293 */
Pokitto 30:796f9611d2ac 294 STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
Pokitto 30:796f9611d2ac 295 {
Pokitto 30:796f9611d2ac 296 LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
Pokitto 30:796f9611d2ac 297 }
Pokitto 30:796f9611d2ac 298
Pokitto 30:796f9611d2ac 299 /**
Pokitto 30:796f9611d2ac 300 * @brief Set SSP0 divider
Pokitto 30:796f9611d2ac 301 * @param div : divider for SSP0 clock
Pokitto 30:796f9611d2ac 302 * @return Nothing
Pokitto 30:796f9611d2ac 303 * @note Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
Pokitto 30:796f9611d2ac 304 * rate is the main system clock divided by this value.
Pokitto 30:796f9611d2ac 305 */
Pokitto 30:796f9611d2ac 306 STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
Pokitto 30:796f9611d2ac 307 {
Pokitto 30:796f9611d2ac 308 LPC_SYSCTL->SSP0CLKDIV = div;
Pokitto 30:796f9611d2ac 309 }
Pokitto 30:796f9611d2ac 310
Pokitto 30:796f9611d2ac 311 /**
Pokitto 30:796f9611d2ac 312 * @brief Return SSP0 divider
Pokitto 30:796f9611d2ac 313 * @return divider for SSP0 clock
Pokitto 30:796f9611d2ac 314 * @note A value of 0 means the clock is disabled.
Pokitto 30:796f9611d2ac 315 */
Pokitto 30:796f9611d2ac 316 STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
Pokitto 30:796f9611d2ac 317 {
Pokitto 30:796f9611d2ac 318 return LPC_SYSCTL->SSP0CLKDIV;
Pokitto 30:796f9611d2ac 319 }
Pokitto 30:796f9611d2ac 320
Pokitto 30:796f9611d2ac 321 /**
Pokitto 30:796f9611d2ac 322 * @brief Set USART0 divider clock
Pokitto 30:796f9611d2ac 323 * @param div : divider for UART clock
Pokitto 30:796f9611d2ac 324 * @return Nothing
Pokitto 30:796f9611d2ac 325 * @note Use 0 to disable, or a divider value of 1 to 255. The UART clock
Pokitto 30:796f9611d2ac 326 * rate is the main system clock divided by this value.
Pokitto 30:796f9611d2ac 327 */
Pokitto 30:796f9611d2ac 328 STATIC INLINE void Chip_Clock_SetUSART0ClockDiv(uint32_t div)
Pokitto 30:796f9611d2ac 329 {
Pokitto 30:796f9611d2ac 330 LPC_SYSCTL->USART0CLKDIV = div;
Pokitto 30:796f9611d2ac 331 }
Pokitto 30:796f9611d2ac 332
Pokitto 30:796f9611d2ac 333 /**
Pokitto 30:796f9611d2ac 334 * @brief Return USART0 divider
Pokitto 30:796f9611d2ac 335 * @return divider for UART clock
Pokitto 30:796f9611d2ac 336 * @note A value of 0 means the clock is disabled.
Pokitto 30:796f9611d2ac 337 */
Pokitto 30:796f9611d2ac 338 STATIC INLINE uint32_t Chip_Clock_GetUASRT0ClockDiv(void)
Pokitto 30:796f9611d2ac 339 {
Pokitto 30:796f9611d2ac 340 return LPC_SYSCTL->USART0CLKDIV;
Pokitto 30:796f9611d2ac 341 }
Pokitto 30:796f9611d2ac 342
Pokitto 30:796f9611d2ac 343 /**
Pokitto 30:796f9611d2ac 344 * @brief Set SSP1 divider clock
Pokitto 30:796f9611d2ac 345 * @param div : divider for SSP1 clock
Pokitto 30:796f9611d2ac 346 * @return Nothing
Pokitto 30:796f9611d2ac 347 * @note Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
Pokitto 30:796f9611d2ac 348 * rate is the main system clock divided by this value.
Pokitto 30:796f9611d2ac 349 */
Pokitto 30:796f9611d2ac 350 STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
Pokitto 30:796f9611d2ac 351 {
Pokitto 30:796f9611d2ac 352 LPC_SYSCTL->SSP1CLKDIV = div;
Pokitto 30:796f9611d2ac 353 }
Pokitto 30:796f9611d2ac 354
Pokitto 30:796f9611d2ac 355 /**
Pokitto 30:796f9611d2ac 356 * @brief Return SSP1 divider
Pokitto 30:796f9611d2ac 357 * @return divider for SSP1 clock
Pokitto 30:796f9611d2ac 358 * @note A value of 0 means the clock is disabled.
Pokitto 30:796f9611d2ac 359 */
Pokitto 30:796f9611d2ac 360 STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
Pokitto 30:796f9611d2ac 361 {
Pokitto 30:796f9611d2ac 362 return LPC_SYSCTL->SSP1CLKDIV;
Pokitto 30:796f9611d2ac 363 }
Pokitto 30:796f9611d2ac 364
Pokitto 30:796f9611d2ac 365 /**
Pokitto 30:796f9611d2ac 366 * @brief Set USART 1/2/3/4 UART base rate (up to main clock rate)
Pokitto 30:796f9611d2ac 367 * @param rate : Desired rate for fractional divider/multipler output
Pokitto 30:796f9611d2ac 368 * @param fEnable : true to use fractional clocking, false for integer clocking
Pokitto 30:796f9611d2ac 369 * @return Actual rate generated
Pokitto 30:796f9611d2ac 370 * @note USARTs 1 - 4 use the same base clock for their baud rate
Pokitto 30:796f9611d2ac 371 * basis. This function is used to generate that clock, while the
Pokitto 30:796f9611d2ac 372 * UART driver's SetBaud functions will attempt to get the closest
Pokitto 30:796f9611d2ac 373 * baud rate from this base clock without altering it. This needs
Pokitto 30:796f9611d2ac 374 * to be setup prior to individual UART setup.<br>
Pokitto 30:796f9611d2ac 375 * UARTs need a base clock 16x faster than the baud rate, so if you
Pokitto 30:796f9611d2ac 376 * need a 115.2Kbps baud rate, you will need a clock rate of at
Pokitto 30:796f9611d2ac 377 * least (115.2K * 16). The UART base clock is generated from the
Pokitto 30:796f9611d2ac 378 * main system clock, so fractional clocking may be the only
Pokitto 30:796f9611d2ac 379 * possible choice when using a low main system clock frequency.
Pokitto 30:796f9611d2ac 380 * Do not alter the FRGCLKDIV register after this call.
Pokitto 30:796f9611d2ac 381 */
Pokitto 30:796f9611d2ac 382 uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable);
Pokitto 30:796f9611d2ac 383
Pokitto 30:796f9611d2ac 384 /**
Pokitto 30:796f9611d2ac 385 * @brief Get USART 1/2/3/4 UART base rate
Pokitto 30:796f9611d2ac 386 * @return USART 1/2/3/4 UART base rate
Pokitto 30:796f9611d2ac 387 */
Pokitto 30:796f9611d2ac 388 uint32_t Chip_Clock_GetUSARTNBaseClockRate(void);
Pokitto 30:796f9611d2ac 389
Pokitto 30:796f9611d2ac 390 /**
Pokitto 30:796f9611d2ac 391 * @brief Set USART 1/2/3/4 fractional baud rate divider clock
Pokitto 30:796f9611d2ac 392 * @param div : divider for USART 1/2/3/4 fractional baud rate clock
Pokitto 30:796f9611d2ac 393 * @return Nothing
Pokitto 30:796f9611d2ac 394 * @note Use 0 to disable, or a divider value of 1 to 255.
Pokitto 30:796f9611d2ac 395 * This does not affect USART0.
Pokitto 30:796f9611d2ac 396 */
Pokitto 30:796f9611d2ac 397 STATIC INLINE void Chip_Clock_SetUSARTNBaseClockDiv(uint8_t div)
Pokitto 30:796f9611d2ac 398 {
Pokitto 30:796f9611d2ac 399 LPC_SYSCTL->FRGCLKDIV = (uint32_t) div;
Pokitto 30:796f9611d2ac 400 }
Pokitto 30:796f9611d2ac 401
Pokitto 30:796f9611d2ac 402 /**
Pokitto 30:796f9611d2ac 403 * @brief Return USART 1/2/3/4 fractional baud rate divider
Pokitto 30:796f9611d2ac 404 * @return divider for USART 1/2/3/4 fractional baud rate clock
Pokitto 30:796f9611d2ac 405 * @note A value of 0 means the clock is disabled.
Pokitto 30:796f9611d2ac 406 * This does not affect USART0.
Pokitto 30:796f9611d2ac 407 */
Pokitto 30:796f9611d2ac 408 STATIC INLINE uint32_t Chip_Clock_GetUSARTNBaseClockDiv(void)
Pokitto 30:796f9611d2ac 409 {
Pokitto 30:796f9611d2ac 410 return LPC_SYSCTL->FRGCLKDIV;
Pokitto 30:796f9611d2ac 411 }
Pokitto 30:796f9611d2ac 412
Pokitto 30:796f9611d2ac 413 /**
Pokitto 30:796f9611d2ac 414 * @brief Set The USART Fractional Generator Divider
Pokitto 30:796f9611d2ac 415 * @param div : Fractional Generator Divider value, should be 0xFF
Pokitto 30:796f9611d2ac 416 * @return Nothing
Pokitto 30:796f9611d2ac 417 */
Pokitto 30:796f9611d2ac 418 STATIC INLINE void Chip_Clock_SetUSARTNFRGDivider(uint8_t div)
Pokitto 30:796f9611d2ac 419 {
Pokitto 30:796f9611d2ac 420 LPC_SYSCTL->UARTFRGDIV = (uint32_t) div;
Pokitto 30:796f9611d2ac 421 }
Pokitto 30:796f9611d2ac 422
Pokitto 30:796f9611d2ac 423 /**
Pokitto 30:796f9611d2ac 424 * @brief Set The USART Fractional Generator Divider
Pokitto 30:796f9611d2ac 425 * @return Value of USART Fractional Generator Divider
Pokitto 30:796f9611d2ac 426 */
Pokitto 30:796f9611d2ac 427 STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGDivider(void)
Pokitto 30:796f9611d2ac 428 {
Pokitto 30:796f9611d2ac 429 return LPC_SYSCTL->UARTFRGDIV;
Pokitto 30:796f9611d2ac 430 }
Pokitto 30:796f9611d2ac 431
Pokitto 30:796f9611d2ac 432 /**
Pokitto 30:796f9611d2ac 433 * @brief Set The USART Fractional Generator Multiplier
Pokitto 30:796f9611d2ac 434 * @param mult : An 8-bit value (0-255) U_PCLK = UARTCLKDIV/(1 + MULT/256)
Pokitto 30:796f9611d2ac 435 * @return Nothing
Pokitto 30:796f9611d2ac 436 */
Pokitto 30:796f9611d2ac 437 STATIC INLINE void Chip_Clock_SetUSARTNFRGMultiplier(uint8_t mult)
Pokitto 30:796f9611d2ac 438 {
Pokitto 30:796f9611d2ac 439 LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult;
Pokitto 30:796f9611d2ac 440 }
Pokitto 30:796f9611d2ac 441
Pokitto 30:796f9611d2ac 442 /**
Pokitto 30:796f9611d2ac 443 * @brief Get The USART Fractional Generator Multiplier
Pokitto 30:796f9611d2ac 444 * @return Value of USART Fractional Generator Multiplier
Pokitto 30:796f9611d2ac 445 */
Pokitto 30:796f9611d2ac 446 STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGMultiplier(void)
Pokitto 30:796f9611d2ac 447 {
Pokitto 30:796f9611d2ac 448 return LPC_SYSCTL->UARTFRGMULT;
Pokitto 30:796f9611d2ac 449 }
Pokitto 30:796f9611d2ac 450
Pokitto 30:796f9611d2ac 451 /**
Pokitto 30:796f9611d2ac 452 * Clock sources for USB
Pokitto 30:796f9611d2ac 453 */
Pokitto 30:796f9611d2ac 454 typedef enum CHIP_SYSCTL_USBCLKSRC {
Pokitto 30:796f9611d2ac 455 SYSCTL_USBCLKSRC_PLLOUT = 0, /*!< USB PLL out */
Pokitto 30:796f9611d2ac 456 SYSCTL_USBCLKSRC_MAINSYSCLK, /*!< Main system clock */
Pokitto 30:796f9611d2ac 457 } CHIP_SYSCTL_USBCLKSRC_T;
Pokitto 30:796f9611d2ac 458
Pokitto 30:796f9611d2ac 459 /**
Pokitto 30:796f9611d2ac 460 * @brief Set USB clock source and divider
Pokitto 30:796f9611d2ac 461 * @param src : Clock source for USB
Pokitto 30:796f9611d2ac 462 * @param div : divider for USB clock
Pokitto 30:796f9611d2ac 463 * @return Nothing
Pokitto 30:796f9611d2ac 464 * @note Use 0 to disable, or a divider value of 1 to 255. The USB clock
Pokitto 30:796f9611d2ac 465 * rate is either the main system clock or USB PLL output clock divided
Pokitto 30:796f9611d2ac 466 * by this value. This function will also toggle the clock source
Pokitto 30:796f9611d2ac 467 * update register to update the clock source.
Pokitto 30:796f9611d2ac 468 */
Pokitto 30:796f9611d2ac 469 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
Pokitto 30:796f9611d2ac 470
Pokitto 30:796f9611d2ac 471 /**
Pokitto 30:796f9611d2ac 472 * Clock sources for CLKOUT
Pokitto 30:796f9611d2ac 473 */
Pokitto 30:796f9611d2ac 474 typedef enum CHIP_SYSCTL_CLKOUTSRC {
Pokitto 30:796f9611d2ac 475 SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
Pokitto 30:796f9611d2ac 476 SYSCTL_CLKOUTSRC_MAINOSC, /*!< Main oscillator for CLKOUT */
Pokitto 30:796f9611d2ac 477 SYSCTL_CLKOUTSRC_SYSOSC = SYSCTL_CLKOUTSRC_MAINOSC,
Pokitto 30:796f9611d2ac 478 SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
Pokitto 30:796f9611d2ac 479 SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main system clock for CLKOUT */
Pokitto 30:796f9611d2ac 480 } CHIP_SYSCTL_CLKOUTSRC_T;
Pokitto 30:796f9611d2ac 481
Pokitto 30:796f9611d2ac 482 /**
Pokitto 30:796f9611d2ac 483 * @brief Set CLKOUT clock source and divider
Pokitto 30:796f9611d2ac 484 * @param src : Clock source for CLKOUT
Pokitto 30:796f9611d2ac 485 * @param div : divider for CLKOUT clock
Pokitto 30:796f9611d2ac 486 * @return Nothing
Pokitto 30:796f9611d2ac 487 * @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
Pokitto 30:796f9611d2ac 488 * rate is the clock source divided by the divider. This function will
Pokitto 30:796f9611d2ac 489 * also toggle the clock source update register to update the clock
Pokitto 30:796f9611d2ac 490 * source.
Pokitto 30:796f9611d2ac 491 */
Pokitto 30:796f9611d2ac 492 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
Pokitto 30:796f9611d2ac 493
Pokitto 30:796f9611d2ac 494 /**
Pokitto 30:796f9611d2ac 495 * @brief Set IOCON glitch filter clock divider value
Pokitto 30:796f9611d2ac 496 * @param index : IOCON divider index (0 - 6) to set
Pokitto 30:796f9611d2ac 497 * @param div : value for IOCON filter divider value
Pokitto 30:796f9611d2ac 498 * @return Nothing
Pokitto 30:796f9611d2ac 499 * @note Use 0 to disable, or a divider value of 1 to 255.
Pokitto 30:796f9611d2ac 500 */
Pokitto 30:796f9611d2ac 501 STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv(int index, uint32_t div)
Pokitto 30:796f9611d2ac 502 {
Pokitto 30:796f9611d2ac 503 LPC_SYSCTL->IOCONCLKDIV[6 - index] = div;
Pokitto 30:796f9611d2ac 504 }
Pokitto 30:796f9611d2ac 505
Pokitto 30:796f9611d2ac 506 /**
Pokitto 30:796f9611d2ac 507 * @brief Return IOCON glitch filter clock divider value
Pokitto 30:796f9611d2ac 508 * @param index : IOCON divider index (0 - 6) to get
Pokitto 30:796f9611d2ac 509 * @return IOCON glitch filter clock divider value
Pokitto 30:796f9611d2ac 510 */
Pokitto 30:796f9611d2ac 511 STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv(int index)
Pokitto 30:796f9611d2ac 512 {
Pokitto 30:796f9611d2ac 513 return LPC_SYSCTL->IOCONCLKDIV[6 - index];
Pokitto 30:796f9611d2ac 514 }
Pokitto 30:796f9611d2ac 515
Pokitto 30:796f9611d2ac 516 /**
Pokitto 30:796f9611d2ac 517 * @brief Returns the main oscillator clock rate
Pokitto 30:796f9611d2ac 518 * @return main oscillator clock rate in Hz
Pokitto 30:796f9611d2ac 519 */
Pokitto 30:796f9611d2ac 520 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
Pokitto 30:796f9611d2ac 521 {
Pokitto 30:796f9611d2ac 522 return 12000000; //OscRateIn;
Pokitto 30:796f9611d2ac 523 }
Pokitto 30:796f9611d2ac 524
Pokitto 30:796f9611d2ac 525 /**
Pokitto 30:796f9611d2ac 526 * @brief Returns the internal oscillator (IRC) clock rate
Pokitto 30:796f9611d2ac 527 * @return internal oscillator (IRC) clock rate in Hz
Pokitto 30:796f9611d2ac 528 */
Pokitto 30:796f9611d2ac 529 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
Pokitto 30:796f9611d2ac 530 {
Pokitto 30:796f9611d2ac 531 return SYSCTL_IRC_FREQ;
Pokitto 30:796f9611d2ac 532 }
Pokitto 30:796f9611d2ac 533
Pokitto 30:796f9611d2ac 534 /**
Pokitto 30:796f9611d2ac 535 * @brief Returns the RTC clock rate
Pokitto 30:796f9611d2ac 536 * @return RTC oscillator clock rate in Hz
Pokitto 30:796f9611d2ac 537 */
Pokitto 30:796f9611d2ac 538 STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
Pokitto 30:796f9611d2ac 539 {
Pokitto 30:796f9611d2ac 540 return 32768;//RTCOscRateIn;
Pokitto 30:796f9611d2ac 541 }
Pokitto 30:796f9611d2ac 542
Pokitto 30:796f9611d2ac 543 /**
Pokitto 30:796f9611d2ac 544 * @brief Return estimated watchdog oscillator rate
Pokitto 30:796f9611d2ac 545 * @return Estimated watchdog oscillator rate
Pokitto 30:796f9611d2ac 546 * @note This rate is accurate to plus or minus 40%.
Pokitto 30:796f9611d2ac 547 */
Pokitto 30:796f9611d2ac 548 uint32_t Chip_Clock_GetWDTOSCRate(void);
Pokitto 30:796f9611d2ac 549
Pokitto 30:796f9611d2ac 550 /**
Pokitto 30:796f9611d2ac 551 * @brief Return System PLL input clock rate
Pokitto 30:796f9611d2ac 552 * @return System PLL input clock rate
Pokitto 30:796f9611d2ac 553 */
Pokitto 30:796f9611d2ac 554 uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
Pokitto 30:796f9611d2ac 555
Pokitto 30:796f9611d2ac 556 /**
Pokitto 30:796f9611d2ac 557 * @brief Return System PLL output clock rate
Pokitto 30:796f9611d2ac 558 * @return System PLL output clock rate
Pokitto 30:796f9611d2ac 559 */
Pokitto 30:796f9611d2ac 560 uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
Pokitto 30:796f9611d2ac 561
Pokitto 30:796f9611d2ac 562 /**
Pokitto 30:796f9611d2ac 563 * @brief Return USB PLL input clock rate
Pokitto 30:796f9611d2ac 564 * @return USB PLL input clock rate
Pokitto 30:796f9611d2ac 565 */
Pokitto 30:796f9611d2ac 566 uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
Pokitto 30:796f9611d2ac 567
Pokitto 30:796f9611d2ac 568 /**
Pokitto 30:796f9611d2ac 569 * @brief Return USB PLL output clock rate
Pokitto 30:796f9611d2ac 570 * @return USB PLL output clock rate
Pokitto 30:796f9611d2ac 571 */
Pokitto 30:796f9611d2ac 572 uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
Pokitto 30:796f9611d2ac 573
Pokitto 30:796f9611d2ac 574 /**
Pokitto 30:796f9611d2ac 575 * @brief Return main clock rate
Pokitto 30:796f9611d2ac 576 * @return main clock rate
Pokitto 30:796f9611d2ac 577 */
Pokitto 30:796f9611d2ac 578 uint32_t Chip_Clock_GetMainClockRate(void);
Pokitto 30:796f9611d2ac 579
Pokitto 30:796f9611d2ac 580 /**
Pokitto 30:796f9611d2ac 581 * @brief Return system clock rate
Pokitto 30:796f9611d2ac 582 * @return system clock rate
Pokitto 30:796f9611d2ac 583 */
Pokitto 30:796f9611d2ac 584 uint32_t Chip_Clock_GetSystemClockRate(void);
Pokitto 30:796f9611d2ac 585
Pokitto 30:796f9611d2ac 586 /**
Pokitto 30:796f9611d2ac 587 * @}
Pokitto 30:796f9611d2ac 588 */
Pokitto 30:796f9611d2ac 589
Pokitto 30:796f9611d2ac 590 #ifdef __cplusplus
Pokitto 30:796f9611d2ac 591 }
Pokitto 30:796f9611d2ac 592 #endif
Pokitto 30:796f9611d2ac 593
Pokitto 30:796f9611d2ac 594 #endif /* __CLOCK_11U6X_H_ */
Pokitto 30:796f9611d2ac 595