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PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

Dependents:   YATTT sd_map_test cPong SnowDemo ... more

PokittoLib

Library for programming Pokitto hardware

How to Use

  1. Import this library to online compiler (see button "import" on the right hand side
  2. DO NOT import mbed-src anymore, a better version is now included inside PokittoLib
  3. Change My_settings.h according to your project
  4. Start coding!

POKITTO_HW/dma_11u6x.h@30:796f9611d2ac, 2018-01-30 (annotated)

Committer:
Pokitto
Date:
Tue Jan 30 10:41:12 2018 +0000
Revision:
30:796f9611d2ac
Sound enhancements done

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pokitto 30:796f9611d2ac 1 /*
Pokitto 30:796f9611d2ac 2 * @brief LPC11u6x DMA chip driver
Pokitto 30:796f9611d2ac 3 *
Pokitto 30:796f9611d2ac 4 * @note
Pokitto 30:796f9611d2ac 5 * Copyright(C) NXP Semiconductors, 2013
Pokitto 30:796f9611d2ac 6 * All rights reserved.
Pokitto 30:796f9611d2ac 7 *
Pokitto 30:796f9611d2ac 8 * @par
Pokitto 30:796f9611d2ac 9 * Software that is described herein is for illustrative purposes only
Pokitto 30:796f9611d2ac 10 * which provides customers with programming information regarding the
Pokitto 30:796f9611d2ac 11 * LPC products. This software is supplied "AS IS" without any warranties of
Pokitto 30:796f9611d2ac 12 * any kind, and NXP Semiconductors and its licensor disclaim any and
Pokitto 30:796f9611d2ac 13 * all warranties, express or implied, including all implied warranties of
Pokitto 30:796f9611d2ac 14 * merchantability, fitness for a particular purpose and non-infringement of
Pokitto 30:796f9611d2ac 15 * intellectual property rights. NXP Semiconductors assumes no responsibility
Pokitto 30:796f9611d2ac 16 * or liability for the use of the software, conveys no license or rights under any
Pokitto 30:796f9611d2ac 17 * patent, copyright, mask work right, or any other intellectual property rights in
Pokitto 30:796f9611d2ac 18 * or to any products. NXP Semiconductors reserves the right to make changes
Pokitto 30:796f9611d2ac 19 * in the software without notification. NXP Semiconductors also makes no
Pokitto 30:796f9611d2ac 20 * representation or warranty that such application will be suitable for the
Pokitto 30:796f9611d2ac 21 * specified use without further testing or modification.
Pokitto 30:796f9611d2ac 22 *
Pokitto 30:796f9611d2ac 23 * @par
Pokitto 30:796f9611d2ac 24 * Permission to use, copy, modify, and distribute this software and its
Pokitto 30:796f9611d2ac 25 * documentation is hereby granted, under NXP Semiconductors' and its
Pokitto 30:796f9611d2ac 26 * licensor's relevant copyrights in the software, without fee, provided that it
Pokitto 30:796f9611d2ac 27 * is used in conjunction with NXP Semiconductors microcontrollers. This
Pokitto 30:796f9611d2ac 28 * copyright, permission, and disclaimer notice must appear in all copies of
Pokitto 30:796f9611d2ac 29 * this code.
Pokitto 30:796f9611d2ac 30 */
Pokitto 30:796f9611d2ac 31
Pokitto 30:796f9611d2ac 32 #ifndef __DMA_11U6X_H_
Pokitto 30:796f9611d2ac 33 #define __DMA_11U6X_H_
Pokitto 30:796f9611d2ac 34
Pokitto 30:796f9611d2ac 35 #include "lpc_types.h"
Pokitto 30:796f9611d2ac 36 #include "clock_11u6x.h"
Pokitto 30:796f9611d2ac 37
Pokitto 30:796f9611d2ac 38 #ifdef __cplusplus
Pokitto 30:796f9611d2ac 39 extern "C" {
Pokitto 30:796f9611d2ac 40 #endif
Pokitto 30:796f9611d2ac 41
Pokitto 30:796f9611d2ac 42 /** @defgroup DMA_11U6X CHIP: LPC11u6x DMA Controller driver
Pokitto 30:796f9611d2ac 43 * @ingroup CHIP_11U6X_Drivers
Pokitto 30:796f9611d2ac 44 * @{
Pokitto 30:796f9611d2ac 45 */
Pokitto 30:796f9611d2ac 46
Pokitto 30:796f9611d2ac 47 /**
Pokitto 30:796f9611d2ac 48 * @brief DMA Controller shared registers structure
Pokitto 30:796f9611d2ac 49 */
Pokitto 30:796f9611d2ac 50 typedef struct { /*!< DMA shared registers structure */
Pokitto 30:796f9611d2ac 51 __IO uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */
Pokitto 30:796f9611d2ac 52 __I uint32_t RESERVED0;
Pokitto 30:796f9611d2ac 53 __O uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */
Pokitto 30:796f9611d2ac 54 __I uint32_t RESERVED1;
Pokitto 30:796f9611d2ac 55 __I uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */
Pokitto 30:796f9611d2ac 56 __I uint32_t RESERVED2;
Pokitto 30:796f9611d2ac 57 __I uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */
Pokitto 30:796f9611d2ac 58 __I uint32_t RESERVED3;
Pokitto 30:796f9611d2ac 59 __IO uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */
Pokitto 30:796f9611d2ac 60 __I uint32_t RESERVED4;
Pokitto 30:796f9611d2ac 61 __IO uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */
Pokitto 30:796f9611d2ac 62 __I uint32_t RESERVED5;
Pokitto 30:796f9611d2ac 63 __O uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */
Pokitto 30:796f9611d2ac 64 __I uint32_t RESERVED6;
Pokitto 30:796f9611d2ac 65 __IO uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */
Pokitto 30:796f9611d2ac 66 __I uint32_t RESERVED7;
Pokitto 30:796f9611d2ac 67 __IO uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */
Pokitto 30:796f9611d2ac 68 __I uint32_t RESERVED8;
Pokitto 30:796f9611d2ac 69 __O uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */
Pokitto 30:796f9611d2ac 70 __I uint32_t RESERVED9;
Pokitto 30:796f9611d2ac 71 __O uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */
Pokitto 30:796f9611d2ac 72 __I uint32_t RESERVED10;
Pokitto 30:796f9611d2ac 73 __O uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */
Pokitto 30:796f9611d2ac 74 } LPC_DMA_COMMON_T;
Pokitto 30:796f9611d2ac 75
Pokitto 30:796f9611d2ac 76 /**
Pokitto 30:796f9611d2ac 77 * @brief DMA Controller shared registers structure
Pokitto 30:796f9611d2ac 78 */
Pokitto 30:796f9611d2ac 79 typedef struct { /*!< DMA channel register structure */
Pokitto 30:796f9611d2ac 80 __IO uint32_t CFG; /*!< DMA Configuration register */
Pokitto 30:796f9611d2ac 81 __I uint32_t CTLSTAT; /*!< DMA Control and status register */
Pokitto 30:796f9611d2ac 82 __IO uint32_t XFERCFG; /*!< DMA Transfer configuration register */
Pokitto 30:796f9611d2ac 83 __I uint32_t RESERVED;
Pokitto 30:796f9611d2ac 84 } LPC_DMA_CHANNEL_T;
Pokitto 30:796f9611d2ac 85
Pokitto 30:796f9611d2ac 86
Pokitto 30:796f9611d2ac 87 #define DMA_CH15 15
Pokitto 30:796f9611d2ac 88
Pokitto 30:796f9611d2ac 89 /* On LPC412x, Max DMA channel is 22 */
Pokitto 30:796f9611d2ac 90 #define MAX_DMA_CHANNEL (DMA_CH15 + 1)
Pokitto 30:796f9611d2ac 91
Pokitto 30:796f9611d2ac 92 /**
Pokitto 30:796f9611d2ac 93 * @brief DMA Controller register block structure
Pokitto 30:796f9611d2ac 94 */
Pokitto 30:796f9611d2ac 95 typedef struct { /*!< DMA Structure */
Pokitto 30:796f9611d2ac 96 __IO uint32_t CTRL; /*!< DMA control register */
Pokitto 30:796f9611d2ac 97 __I uint32_t INTSTAT; /*!< DMA Interrupt status register */
Pokitto 30:796f9611d2ac 98 __IO uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */
Pokitto 30:796f9611d2ac 99 __I uint32_t RESERVED2[5];
Pokitto 30:796f9611d2ac 100 LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */
Pokitto 30:796f9611d2ac 101 __I uint32_t RESERVED0[225];
Pokitto 30:796f9611d2ac 102 LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */
Pokitto 30:796f9611d2ac 103 } LPC_DMA_T;
Pokitto 30:796f9611d2ac 104
Pokitto 30:796f9611d2ac 105 /** @defgroup DMA_COMMONDRV_11U6X CHIP: LPC11u6x DMA Controller driver common functions
Pokitto 30:796f9611d2ac 106 * @{
Pokitto 30:796f9611d2ac 107 */
Pokitto 30:796f9611d2ac 108
Pokitto 30:796f9611d2ac 109 /**
Pokitto 30:796f9611d2ac 110 * @brief Initialize DMA controller
Pokitto 30:796f9611d2ac 111 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 112 * @return Nothing
Pokitto 30:796f9611d2ac 113 */
Pokitto 30:796f9611d2ac 114 STATIC INLINE void Chip_DMA_Init(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 115 {
Pokitto 30:796f9611d2ac 116 (void) pDMA;
Pokitto 30:796f9611d2ac 117 Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_DMA);
Pokitto 30:796f9611d2ac 118 }
Pokitto 30:796f9611d2ac 119
Pokitto 30:796f9611d2ac 120 /**
Pokitto 30:796f9611d2ac 121 * @brief De-Initialize DMA controller
Pokitto 30:796f9611d2ac 122 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 123 * @return Nothing
Pokitto 30:796f9611d2ac 124 */
Pokitto 30:796f9611d2ac 125 STATIC INLINE void Chip_DMA_DeInit(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 126 {
Pokitto 30:796f9611d2ac 127 (void) pDMA;
Pokitto 30:796f9611d2ac 128 Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_DMA);
Pokitto 30:796f9611d2ac 129 }
Pokitto 30:796f9611d2ac 130
Pokitto 30:796f9611d2ac 131 /**
Pokitto 30:796f9611d2ac 132 * @brief Enable DMA controller
Pokitto 30:796f9611d2ac 133 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 134 * @return Nothing
Pokitto 30:796f9611d2ac 135 */
Pokitto 30:796f9611d2ac 136 STATIC INLINE void Chip_DMA_Enable(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 137 {
Pokitto 30:796f9611d2ac 138 pDMA->CTRL = 1;
Pokitto 30:796f9611d2ac 139 }
Pokitto 30:796f9611d2ac 140
Pokitto 30:796f9611d2ac 141 /**
Pokitto 30:796f9611d2ac 142 * @brief Disable DMA controller
Pokitto 30:796f9611d2ac 143 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 144 * @return Nothing
Pokitto 30:796f9611d2ac 145 */
Pokitto 30:796f9611d2ac 146 STATIC INLINE void Chip_DMA_Disable(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 147 {
Pokitto 30:796f9611d2ac 148 pDMA->CTRL = 0;
Pokitto 30:796f9611d2ac 149 }
Pokitto 30:796f9611d2ac 150
Pokitto 30:796f9611d2ac 151 /* DMA interrupt status bits (common) */
Pokitto 30:796f9611d2ac 152 #define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */
Pokitto 30:796f9611d2ac 153 #define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */
Pokitto 30:796f9611d2ac 154
Pokitto 30:796f9611d2ac 155 /**
Pokitto 30:796f9611d2ac 156 * @brief Get pending interrupt or error interrupts
Pokitto 30:796f9611d2ac 157 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 158 * @return An Or'ed value of DMA_INTSTAT_* types
Pokitto 30:796f9611d2ac 159 * @note If any DMA channels have an active interrupt or error interrupt
Pokitto 30:796f9611d2ac 160 * pending, this functional will a common status that applies to all
Pokitto 30:796f9611d2ac 161 * channels.
Pokitto 30:796f9611d2ac 162 */
Pokitto 30:796f9611d2ac 163 STATIC INLINE uint32_t Chip_DMA_GetIntStatus(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 164 {
Pokitto 30:796f9611d2ac 165 return pDMA->INTSTAT;
Pokitto 30:796f9611d2ac 166 }
Pokitto 30:796f9611d2ac 167
Pokitto 30:796f9611d2ac 168
Pokitto 30:796f9611d2ac 169
Pokitto 30:796f9611d2ac 170 /* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
Pokitto 30:796f9611d2ac 171 function if a DMA SRAM table is needed. */
Pokitto 30:796f9611d2ac 172 extern DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
Pokitto 30:796f9611d2ac 173
Pokitto 30:796f9611d2ac 174 /**
Pokitto 30:796f9611d2ac 175 * @brief Set DMA controller SRAM base address
Pokitto 30:796f9611d2ac 176 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 177 * @param base : The base address where the DMA descriptors will be stored
Pokitto 30:796f9611d2ac 178 * @return Nothing
Pokitto 30:796f9611d2ac 179 * @note A 256 byte block of memory aligned on a 256 byte boundary must be
Pokitto 30:796f9611d2ac 180 * provided for this function. It sets the base address used for
Pokitto 30:796f9611d2ac 181 * DMA descriptor table (16 descriptors total that use 16 bytes each).<br>
Pokitto 30:796f9611d2ac 182 *
Pokitto 30:796f9611d2ac 183 * A pre-defined table with correct alignment can be used for this
Pokitto 30:796f9611d2ac 184 * function by calling Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table));
Pokitto 30:796f9611d2ac 185 */
Pokitto 30:796f9611d2ac 186 STATIC INLINE void Chip_DMA_SetSRAMBase(LPC_DMA_T *pDMA, uint32_t base)
Pokitto 30:796f9611d2ac 187 {
Pokitto 30:796f9611d2ac 188 pDMA->SRAMBASE = base;
Pokitto 30:796f9611d2ac 189 }
Pokitto 30:796f9611d2ac 190
Pokitto 30:796f9611d2ac 191 /**
Pokitto 30:796f9611d2ac 192 * @brief Returns DMA controller SRAM base address
Pokitto 30:796f9611d2ac 193 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 194 * @return The base address where the DMA descriptors are stored
Pokitto 30:796f9611d2ac 195 */
Pokitto 30:796f9611d2ac 196 STATIC INLINE uint32_t Chip_DMA_GetSRAMBase(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 197 {
Pokitto 30:796f9611d2ac 198 return pDMA->SRAMBASE;
Pokitto 30:796f9611d2ac 199 }
Pokitto 30:796f9611d2ac 200
Pokitto 30:796f9611d2ac 201 /**
Pokitto 30:796f9611d2ac 202 * @}
Pokitto 30:796f9611d2ac 203 */
Pokitto 30:796f9611d2ac 204
Pokitto 30:796f9611d2ac 205 /** @defgroup DMA_COMMON_11U6X CHIP: LPC11u6x DMA Controller driver common channel functions
Pokitto 30:796f9611d2ac 206 * @{
Pokitto 30:796f9611d2ac 207 */
Pokitto 30:796f9611d2ac 208
Pokitto 30:796f9611d2ac 209 /**
Pokitto 30:796f9611d2ac 210 * @brief Enables a single DMA channel
Pokitto 30:796f9611d2ac 211 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 212 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 213 * @return Nothing
Pokitto 30:796f9611d2ac 214 */
Pokitto 30:796f9611d2ac 215 STATIC INLINE void Chip_DMA_EnableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 216 {
Pokitto 30:796f9611d2ac 217 pDMA->DMACOMMON[0].ENABLESET = (1 << ch);
Pokitto 30:796f9611d2ac 218 }
Pokitto 30:796f9611d2ac 219
Pokitto 30:796f9611d2ac 220 /**
Pokitto 30:796f9611d2ac 221 * @brief Disables a single DMA channel
Pokitto 30:796f9611d2ac 222 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 223 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 224 * @return Nothing
Pokitto 30:796f9611d2ac 225 */
Pokitto 30:796f9611d2ac 226 STATIC INLINE void Chip_DMA_DisableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 227 {
Pokitto 30:796f9611d2ac 228 pDMA->DMACOMMON[0].ENABLECLR = (1 << ch);
Pokitto 30:796f9611d2ac 229 }
Pokitto 30:796f9611d2ac 230
Pokitto 30:796f9611d2ac 231 /**
Pokitto 30:796f9611d2ac 232 * @brief Returns all enabled DMA channels
Pokitto 30:796f9611d2ac 233 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 234 * @return An Or'ed value of all enabled DMA channels (0 - 15)
Pokitto 30:796f9611d2ac 235 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 236 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 237 * channel 1, etc.) is enabled. A low state is disabled.
Pokitto 30:796f9611d2ac 238 */
Pokitto 30:796f9611d2ac 239 STATIC INLINE uint32_t Chip_DMA_GetEnabledChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 240 {
Pokitto 30:796f9611d2ac 241 return pDMA->DMACOMMON[0].ENABLESET;
Pokitto 30:796f9611d2ac 242 }
Pokitto 30:796f9611d2ac 243
Pokitto 30:796f9611d2ac 244 /**
Pokitto 30:796f9611d2ac 245 * @brief Returns all active DMA channels
Pokitto 30:796f9611d2ac 246 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 247 * @return An Or'ed value of all active DMA channels (0 - 15)
Pokitto 30:796f9611d2ac 248 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 249 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 250 * channel 1, etc.) is active. A low state is inactive. A active
Pokitto 30:796f9611d2ac 251 * channel indicates that a DMA operation has been started but
Pokitto 30:796f9611d2ac 252 * not yet fully completed.
Pokitto 30:796f9611d2ac 253 */
Pokitto 30:796f9611d2ac 254 STATIC INLINE uint32_t Chip_DMA_GetActiveChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 255 {
Pokitto 30:796f9611d2ac 256 return pDMA->DMACOMMON[0].ACTIVE;
Pokitto 30:796f9611d2ac 257 }
Pokitto 30:796f9611d2ac 258
Pokitto 30:796f9611d2ac 259 /**
Pokitto 30:796f9611d2ac 260 * @brief Returns all busy DMA channels
Pokitto 30:796f9611d2ac 261 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 262 * @return An Or'ed value of all busy DMA channels (0 - 15)
Pokitto 30:796f9611d2ac 263 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 264 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 265 * channel 1, etc.) is busy. A low state is not busy. A DMA
Pokitto 30:796f9611d2ac 266 * channel is considered busy when there is any operation
Pokitto 30:796f9611d2ac 267 * related to that channel in the DMA controller�s internal
Pokitto 30:796f9611d2ac 268 * pipeline.
Pokitto 30:796f9611d2ac 269 */
Pokitto 30:796f9611d2ac 270 STATIC INLINE uint32_t Chip_DMA_GetBusyChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 271 {
Pokitto 30:796f9611d2ac 272 return pDMA->DMACOMMON[0].BUSY;
Pokitto 30:796f9611d2ac 273 }
Pokitto 30:796f9611d2ac 274
Pokitto 30:796f9611d2ac 275 /**
Pokitto 30:796f9611d2ac 276 * @brief Returns pending error interrupt status for all DMA channels
Pokitto 30:796f9611d2ac 277 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 278 * @return An Or'ed value of all channels (0 - 15) error interrupt status
Pokitto 30:796f9611d2ac 279 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 280 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 281 * channel 1, etc.) has a pending error interrupt. A low state
Pokitto 30:796f9611d2ac 282 * indicates no error interrupt.
Pokitto 30:796f9611d2ac 283 */
Pokitto 30:796f9611d2ac 284 STATIC INLINE uint32_t Chip_DMA_GetErrorIntChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 285 {
Pokitto 30:796f9611d2ac 286 return pDMA->DMACOMMON[0].ERRINT;
Pokitto 30:796f9611d2ac 287 }
Pokitto 30:796f9611d2ac 288
Pokitto 30:796f9611d2ac 289 /**
Pokitto 30:796f9611d2ac 290 * @brief Clears a pending error interrupt status for a single DMA channel
Pokitto 30:796f9611d2ac 291 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 292 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 293 * @return Nothing
Pokitto 30:796f9611d2ac 294 */
Pokitto 30:796f9611d2ac 295 STATIC INLINE void Chip_DMA_ClearErrorIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 296 {
Pokitto 30:796f9611d2ac 297 pDMA->DMACOMMON[0].ERRINT = (1 << ch);
Pokitto 30:796f9611d2ac 298 }
Pokitto 30:796f9611d2ac 299
Pokitto 30:796f9611d2ac 300 /**
Pokitto 30:796f9611d2ac 301 * @brief Enables a single DMA channel's interrupt used in common DMA interrupt
Pokitto 30:796f9611d2ac 302 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 303 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 304 * @return Nothing
Pokitto 30:796f9611d2ac 305 */
Pokitto 30:796f9611d2ac 306 STATIC INLINE void Chip_DMA_EnableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 307 {
Pokitto 30:796f9611d2ac 308 pDMA->DMACOMMON[0].INTENSET = (1 << ch);
Pokitto 30:796f9611d2ac 309 }
Pokitto 30:796f9611d2ac 310
Pokitto 30:796f9611d2ac 311 /**
Pokitto 30:796f9611d2ac 312 * @brief Disables a single DMA channel's interrupt used in common DMA interrupt
Pokitto 30:796f9611d2ac 313 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 314 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 315 * @return Nothing
Pokitto 30:796f9611d2ac 316 */
Pokitto 30:796f9611d2ac 317 STATIC INLINE void Chip_DMA_DisableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 318 {
Pokitto 30:796f9611d2ac 319 pDMA->DMACOMMON[0].INTENCLR = (1 << ch);
Pokitto 30:796f9611d2ac 320 }
Pokitto 30:796f9611d2ac 321
Pokitto 30:796f9611d2ac 322 /**
Pokitto 30:796f9611d2ac 323 * @brief Returns all enabled interrupt channels
Pokitto 30:796f9611d2ac 324 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 325 * @return Nothing
Pokitto 30:796f9611d2ac 326 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 327 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 328 * channel 1, etc.) has an enabled interrupt for the channel.
Pokitto 30:796f9611d2ac 329 * A low state indicates that the DMA channel will not contribute
Pokitto 30:796f9611d2ac 330 * to the common DMA interrupt status.
Pokitto 30:796f9611d2ac 331 */
Pokitto 30:796f9611d2ac 332 STATIC INLINE uint32_t Chip_DMA_GetEnableIntChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 333 {
Pokitto 30:796f9611d2ac 334 return pDMA->DMACOMMON[0].INTENSET;
Pokitto 30:796f9611d2ac 335 }
Pokitto 30:796f9611d2ac 336
Pokitto 30:796f9611d2ac 337 /**
Pokitto 30:796f9611d2ac 338 * @brief Returns active A interrupt status for all channels
Pokitto 30:796f9611d2ac 339 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 340 * @return Nothing
Pokitto 30:796f9611d2ac 341 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 342 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 343 * channel 1, etc.) has an active A interrupt for the channel.
Pokitto 30:796f9611d2ac 344 * A low state indicates that the A interrupt is not active.
Pokitto 30:796f9611d2ac 345 */
Pokitto 30:796f9611d2ac 346 STATIC INLINE uint32_t Chip_DMA_GetActiveIntAChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 347 {
Pokitto 30:796f9611d2ac 348 return pDMA->DMACOMMON[0].INTA;
Pokitto 30:796f9611d2ac 349 }
Pokitto 30:796f9611d2ac 350
Pokitto 30:796f9611d2ac 351 /**
Pokitto 30:796f9611d2ac 352 * @brief Clears active A interrupt status for a single channel
Pokitto 30:796f9611d2ac 353 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 354 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 355 * @return Nothing
Pokitto 30:796f9611d2ac 356 */
Pokitto 30:796f9611d2ac 357 STATIC INLINE void Chip_DMA_ClearActiveIntAChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 358 {
Pokitto 30:796f9611d2ac 359 pDMA->DMACOMMON[0].INTA = (1 << ch);
Pokitto 30:796f9611d2ac 360 }
Pokitto 30:796f9611d2ac 361
Pokitto 30:796f9611d2ac 362 /**
Pokitto 30:796f9611d2ac 363 * @brief Returns active B interrupt status for all channels
Pokitto 30:796f9611d2ac 364 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 365 * @return Nothing
Pokitto 30:796f9611d2ac 366 * @note A high values in bits 0 .. 15 in the return values indicates
Pokitto 30:796f9611d2ac 367 * that the channel for that bit (bit 0 = channel 0, bit 1 -
Pokitto 30:796f9611d2ac 368 * channel 1, etc.) has an active B interrupt for the channel.
Pokitto 30:796f9611d2ac 369 * A low state indicates that the B interrupt is not active.
Pokitto 30:796f9611d2ac 370 */
Pokitto 30:796f9611d2ac 371 STATIC INLINE uint32_t Chip_DMA_GetActiveIntBChannels(LPC_DMA_T *pDMA)
Pokitto 30:796f9611d2ac 372 {
Pokitto 30:796f9611d2ac 373 return pDMA->DMACOMMON[0].INTB;
Pokitto 30:796f9611d2ac 374 }
Pokitto 30:796f9611d2ac 375
Pokitto 30:796f9611d2ac 376 /**
Pokitto 30:796f9611d2ac 377 * @brief Clears active B interrupt status for a single channel
Pokitto 30:796f9611d2ac 378 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 379 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 380 * @return Nothing
Pokitto 30:796f9611d2ac 381 */
Pokitto 30:796f9611d2ac 382 STATIC INLINE void Chip_DMA_ClearActiveIntBChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 383 {
Pokitto 30:796f9611d2ac 384 pDMA->DMACOMMON[0].INTB = (1 << ch);
Pokitto 30:796f9611d2ac 385 }
Pokitto 30:796f9611d2ac 386
Pokitto 30:796f9611d2ac 387 /**
Pokitto 30:796f9611d2ac 388 * @brief Sets the VALIDPENDING control bit for a single channel
Pokitto 30:796f9611d2ac 389 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 390 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 391 * @return Nothing
Pokitto 30:796f9611d2ac 392 * @note See the User Manual for more information for what this bit does.
Pokitto 30:796f9611d2ac 393 *
Pokitto 30:796f9611d2ac 394 */
Pokitto 30:796f9611d2ac 395 STATIC INLINE void Chip_DMA_SetValidChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 396 {
Pokitto 30:796f9611d2ac 397 pDMA->DMACOMMON[0].SETVALID = (1 << ch);
Pokitto 30:796f9611d2ac 398 }
Pokitto 30:796f9611d2ac 399
Pokitto 30:796f9611d2ac 400 /**
Pokitto 30:796f9611d2ac 401 * @brief Sets the TRIG bit for a single channel
Pokitto 30:796f9611d2ac 402 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 403 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 404 * @return Nothing
Pokitto 30:796f9611d2ac 405 * @note See the User Manual for more information for what this bit does.
Pokitto 30:796f9611d2ac 406 */
Pokitto 30:796f9611d2ac 407 STATIC INLINE void Chip_DMA_SetTrigChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 408 {
Pokitto 30:796f9611d2ac 409 pDMA->DMACOMMON[0].SETTRIG = (1 << ch);
Pokitto 30:796f9611d2ac 410 }
Pokitto 30:796f9611d2ac 411
Pokitto 30:796f9611d2ac 412 /**
Pokitto 30:796f9611d2ac 413 * @brief Aborts a DMA operation for a single channel
Pokitto 30:796f9611d2ac 414 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 415 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 416 * @return Nothing
Pokitto 30:796f9611d2ac 417 * @note To abort a channel, the channel should first be disabled. Then wait
Pokitto 30:796f9611d2ac 418 * until the channel is no longer busy by checking the corresponding
Pokitto 30:796f9611d2ac 419 * bit in BUSY. Finally, abort the channel operation. This prevents the
Pokitto 30:796f9611d2ac 420 * channel from restarting an incomplete operation when it is enabled
Pokitto 30:796f9611d2ac 421 * again.
Pokitto 30:796f9611d2ac 422 */
Pokitto 30:796f9611d2ac 423 STATIC INLINE void Chip_DMA_AbortChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 424 {
Pokitto 30:796f9611d2ac 425 pDMA->DMACOMMON[0].ABORT = (1 << ch);
Pokitto 30:796f9611d2ac 426 }
Pokitto 30:796f9611d2ac 427
Pokitto 30:796f9611d2ac 428 /**
Pokitto 30:796f9611d2ac 429 * @}
Pokitto 30:796f9611d2ac 430 */
Pokitto 30:796f9611d2ac 431
Pokitto 30:796f9611d2ac 432 /** @defgroup DMATRIGMUX_11U6X CHIP: LPC11u6x DMA trigger selection driver
Pokitto 30:796f9611d2ac 433 * @ingroup CHIP_11U6X_Drivers
Pokitto 30:796f9611d2ac 434 * @{
Pokitto 30:796f9611d2ac 435 */
Pokitto 30:796f9611d2ac 436
Pokitto 30:796f9611d2ac 437 /**
Pokitto 30:796f9611d2ac 438 * @brief DMA trigger pin muxing structure
Pokitto 30:796f9611d2ac 439 */
Pokitto 30:796f9611d2ac 440 typedef struct { /*!< DMA trigger pin muxing register structure */
Pokitto 30:796f9611d2ac 441 __IO uint32_t DMA_ITRIG_INMUX[MAX_DMA_CHANNEL]; /*!< Trigger input select register for DMA channels */
Pokitto 30:796f9611d2ac 442 } LPC_DMATRIGMUX_T;
Pokitto 30:796f9611d2ac 443
Pokitto 30:796f9611d2ac 444 /* DMA triggers that can mapped to DMA channels */
Pokitto 30:796f9611d2ac 445 typedef enum {
Pokitto 30:796f9611d2ac 446 DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */
Pokitto 30:796f9611d2ac 447 DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */
Pokitto 30:796f9611d2ac 448 DMATRIG_CT16B0_MAT0, /*!< 16-bit counter/timer 0 interrupt as trigger */
Pokitto 30:796f9611d2ac 449 DMATRIG_CT16B1_MAT0, /*!< 16-bit counter/timer 1 interrupt as trigger */
Pokitto 30:796f9611d2ac 450 DMATRIG_CT32B0_MAT0, /*!< 32-bit counter/timer 0 interrupt as trigger */
Pokitto 30:796f9611d2ac 451 DMATRIG_CT32B1_MAT0, /*!< 32-bit counter/timer 1 interrupt as trigger */
Pokitto 30:796f9611d2ac 452 DMATRIG_PINT0, /*!< Pin interrupt 0 as trigger */
Pokitto 30:796f9611d2ac 453 DMATRIG_PINT1, /*!< Pin interrupt 1 as trigger */
Pokitto 30:796f9611d2ac 454 DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */
Pokitto 30:796f9611d2ac 455 DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */
Pokitto 30:796f9611d2ac 456 DMATRIG_SCT1_DMA0, /*!< SCT 0, DMA 0 as trigger */
Pokitto 30:796f9611d2ac 457 DMATRIG_SCT1_DMA1 /*!< SCT 1, DMA 1 as trigger */
Pokitto 30:796f9611d2ac 458 } DMA_TRIGSRC_T;
Pokitto 30:796f9611d2ac 459
Pokitto 30:796f9611d2ac 460 /**
Pokitto 30:796f9611d2ac 461 * @brief Select a trigger source for a DMA channel
Pokitto 30:796f9611d2ac 462 * @param pDMATRIG : The base of DMA trigger setup block on the chip
Pokitto 30:796f9611d2ac 463 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 464 * @param trig : Trigger source for the DMA channel
Pokitto 30:796f9611d2ac 465 * @return Nothing
Pokitto 30:796f9611d2ac 466 * @note A DMA trigger source only needs to be setup when the DMA is setup
Pokitto 30:796f9611d2ac 467 * for hardware trigger mode (when Chip_DMA_SetupChannelConfig() is
Pokitto 30:796f9611d2ac 468 * called with DMA_CFG_HWTRIGEN as OR'ed option).
Pokitto 30:796f9611d2ac 469 */
Pokitto 30:796f9611d2ac 470 STATIC INLINE void Chip_DMA_SetHWTrigger(LPC_DMATRIGMUX_T *pDMATRIG, DMA_CHID_T ch, DMA_TRIGSRC_T trig)
Pokitto 30:796f9611d2ac 471 {
Pokitto 30:796f9611d2ac 472 pDMATRIG->DMA_ITRIG_INMUX[ch] = (uint32_t) trig;
Pokitto 30:796f9611d2ac 473 }
Pokitto 30:796f9611d2ac 474
Pokitto 30:796f9611d2ac 475 /**
Pokitto 30:796f9611d2ac 476 * @}
Pokitto 30:796f9611d2ac 477 */
Pokitto 30:796f9611d2ac 478
Pokitto 30:796f9611d2ac 479 /** @defgroup DMA_CHANNEL_11U6X CHIP: LPC11u6x DMA Controller driver channel specific functions
Pokitto 30:796f9611d2ac 480 * @{
Pokitto 30:796f9611d2ac 481 */
Pokitto 30:796f9611d2ac 482
Pokitto 30:796f9611d2ac 483 /* Support macro for DMA_CHDESC_T */
Pokitto 30:796f9611d2ac 484 #define DMA_ADDR(addr) ((uint32_t) (addr))
Pokitto 30:796f9611d2ac 485
Pokitto 30:796f9611d2ac 486 /* Support definitions for setting the configuration of a DMA channel. You
Pokitto 30:796f9611d2ac 487 will need to get more information on these options from the User manual. */
Pokitto 30:796f9611d2ac 488 #define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */
Pokitto 30:796f9611d2ac 489 #define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */
Pokitto 30:796f9611d2ac 490 #define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */
Pokitto 30:796f9611d2ac 491 #define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */
Pokitto 30:796f9611d2ac 492 #define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */
Pokitto 30:796f9611d2ac 493 #define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */
Pokitto 30:796f9611d2ac 494 #define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */
Pokitto 30:796f9611d2ac 495 #define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */
Pokitto 30:796f9611d2ac 496 #define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */
Pokitto 30:796f9611d2ac 497 #define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */
Pokitto 30:796f9611d2ac 498 #define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */
Pokitto 30:796f9611d2ac 499 #define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */
Pokitto 30:796f9611d2ac 500 #define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */
Pokitto 30:796f9611d2ac 501 #define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */
Pokitto 30:796f9611d2ac 502 #define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */
Pokitto 30:796f9611d2ac 503 #define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */
Pokitto 30:796f9611d2ac 504 #define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */
Pokitto 30:796f9611d2ac 505 #define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */
Pokitto 30:796f9611d2ac 506 #define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */
Pokitto 30:796f9611d2ac 507 #define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */
Pokitto 30:796f9611d2ac 508 #define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */
Pokitto 30:796f9611d2ac 509 #define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */
Pokitto 30:796f9611d2ac 510 #define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */
Pokitto 30:796f9611d2ac 511
Pokitto 30:796f9611d2ac 512 /**
Pokitto 30:796f9611d2ac 513 * @brief Setup a DMA channel configuration
Pokitto 30:796f9611d2ac 514 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 515 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 516 * @param cfg : An Or'ed value of DMA_CFG_* values that define the channel's configuration
Pokitto 30:796f9611d2ac 517 * @return Nothing
Pokitto 30:796f9611d2ac 518 * @note This function sets up all configurable options for the DMA channel.
Pokitto 30:796f9611d2ac 519 * These options are usually set once for a channel and then unchanged.<br>
Pokitto 30:796f9611d2ac 520 *
Pokitto 30:796f9611d2ac 521 * The following example show how to configure the channel for peripheral
Pokitto 30:796f9611d2ac 522 * DMA requests, burst transfer size of 1 (in 'transfers', not bytes),
Pokitto 30:796f9611d2ac 523 * continuous reading of the same source address, incrementing destination
Pokitto 30:796f9611d2ac 524 * address, and highest channel priority.<br>
Pokitto 30:796f9611d2ac 525 * Example: Chip_DMA_SetupChannelConfig(pDMA, SSP0_RX_DMA,
Pokitto 30:796f9611d2ac 526 * (DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_1 |
Pokitto 30:796f9611d2ac 527 * DMA_CFG_SRCBURSTWRAP | DMA_CFG_CHPRIORITY(0)));<br>
Pokitto 30:796f9611d2ac 528 *
Pokitto 30:796f9611d2ac 529 * The following example show how to configure the channel for an external
Pokitto 30:796f9611d2ac 530 * trigger from the imput mux with low edge polarity, a burst transfer size of 8,
Pokitto 30:796f9611d2ac 531 * incrementing source and destination addresses, and lowest channel
Pokitto 30:796f9611d2ac 532 * priority.<br>
Pokitto 30:796f9611d2ac 533 * Example: Chip_DMA_SetupChannelConfig(pDMA, DMA_CH14,
Pokitto 30:796f9611d2ac 534 * (DMA_CFG_HWTRIGEN | DMA_CFG_TRIGPOL_LOW | DMA_CFG_TRIGTYPE_EDGE |
Pokitto 30:796f9611d2ac 535 * DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_8 |
Pokitto 30:796f9611d2ac 536 * DMA_CFG_CHPRIORITY(3)));<br>
Pokitto 30:796f9611d2ac 537 *
Pokitto 30:796f9611d2ac 538 * For non-peripheral DMA triggering (DMA_CFG_HWTRIGEN definition), use the
Pokitto 30:796f9611d2ac 539 * DMA input mux functions to configure the DMA trigger source for a DMA channel.
Pokitto 30:796f9611d2ac 540 */
Pokitto 30:796f9611d2ac 541 STATIC INLINE void Chip_DMA_SetupChannelConfig(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg)
Pokitto 30:796f9611d2ac 542 {
Pokitto 30:796f9611d2ac 543 pDMA->DMACH[ch].CFG = cfg;
Pokitto 30:796f9611d2ac 544 }
Pokitto 30:796f9611d2ac 545
Pokitto 30:796f9611d2ac 546 /* DMA channel control and status register definitions */
Pokitto 30:796f9611d2ac 547 #define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */
Pokitto 30:796f9611d2ac 548 #define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */
Pokitto 30:796f9611d2ac 549
Pokitto 30:796f9611d2ac 550 /**
Pokitto 30:796f9611d2ac 551 * @brief Returns channel specific status flags
Pokitto 30:796f9611d2ac 552 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 553 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 554 * @return AN Or'ed value of DMA_CTLSTAT_VALIDPENDING and DMA_CTLSTAT_TRIG
Pokitto 30:796f9611d2ac 555 */
Pokitto 30:796f9611d2ac 556 STATIC INLINE uint32_t Chip_DMA_GetChannelStatus(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 557 {
Pokitto 30:796f9611d2ac 558 return pDMA->DMACH[ch].XFERCFG;
Pokitto 30:796f9611d2ac 559 }
Pokitto 30:796f9611d2ac 560
Pokitto 30:796f9611d2ac 561 /* DMA channel transfer configuration registers definitions */
Pokitto 30:796f9611d2ac 562 #define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */
Pokitto 30:796f9611d2ac 563 #define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */
Pokitto 30:796f9611d2ac 564 #define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */
Pokitto 30:796f9611d2ac 565 #define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */
Pokitto 30:796f9611d2ac 566 #define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */
Pokitto 30:796f9611d2ac 567 #define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */
Pokitto 30:796f9611d2ac 568 #define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */
Pokitto 30:796f9611d2ac 569 #define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */
Pokitto 30:796f9611d2ac 570 #define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */
Pokitto 30:796f9611d2ac 571 #define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */
Pokitto 30:796f9611d2ac 572 #define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */
Pokitto 30:796f9611d2ac 573 #define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */
Pokitto 30:796f9611d2ac 574 #define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */
Pokitto 30:796f9611d2ac 575 #define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */
Pokitto 30:796f9611d2ac 576 #define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */
Pokitto 30:796f9611d2ac 577 #define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */
Pokitto 30:796f9611d2ac 578 #define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */
Pokitto 30:796f9611d2ac 579 #define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */
Pokitto 30:796f9611d2ac 580
Pokitto 30:796f9611d2ac 581 /**
Pokitto 30:796f9611d2ac 582 * @brief Setup a DMA channel transfer configuration
Pokitto 30:796f9611d2ac 583 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 584 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 585 * @param cfg : An Or'ed value of DMA_XFERCFG_* values that define the channel's transfer configuration
Pokitto 30:796f9611d2ac 586 * @return Nothing
Pokitto 30:796f9611d2ac 587 * @note This function sets up the transfer configuration for the DMA channel.<br>
Pokitto 30:796f9611d2ac 588 *
Pokitto 30:796f9611d2ac 589 * The following example show how to configure the channel's transfer for
Pokitto 30:796f9611d2ac 590 * multiple transfer descriptors (ie, ping-pong), interrupt 'A' trigger on
Pokitto 30:796f9611d2ac 591 * transfer descriptor completion, 128 byte size transfers, and source and
Pokitto 30:796f9611d2ac 592 * destination address increment.<br>
Pokitto 30:796f9611d2ac 593 * Example: Chip_DMA_SetupChannelTransfer(pDMA, SSP0_RX_DMA,
Pokitto 30:796f9611d2ac 594 * (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_RELOAD | DMA_XFERCFG_SETINTA |
Pokitto 30:796f9611d2ac 595 * DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 | DMA_XFERCFG_DSTINC_1 |
Pokitto 30:796f9611d2ac 596 * DMA_XFERCFG_XFERCOUNT(128)));<br>
Pokitto 30:796f9611d2ac 597 */
Pokitto 30:796f9611d2ac 598 STATIC INLINE void Chip_DMA_SetupChannelTransfer(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg)
Pokitto 30:796f9611d2ac 599 {
Pokitto 30:796f9611d2ac 600 pDMA->DMACH[ch].XFERCFG = cfg;
Pokitto 30:796f9611d2ac 601 }
Pokitto 30:796f9611d2ac 602
Pokitto 30:796f9611d2ac 603 /**
Pokitto 30:796f9611d2ac 604 * @brief Set DMA transfer register interrupt bits (safe)
Pokitto 30:796f9611d2ac 605 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 606 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 607 * @param mask : Bits to set
Pokitto 30:796f9611d2ac 608 * @return Nothing
Pokitto 30:796f9611d2ac 609 * @note This function safely sets bits in the DMA channel specific XFERCFG
Pokitto 30:796f9611d2ac 610 * register.
Pokitto 30:796f9611d2ac 611 */
Pokitto 30:796f9611d2ac 612 void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask);
Pokitto 30:796f9611d2ac 613
Pokitto 30:796f9611d2ac 614 /**
Pokitto 30:796f9611d2ac 615 * @brief Clear DMA transfer register interrupt bits (safe)
Pokitto 30:796f9611d2ac 616 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 617 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 618 * @param mask : Bits to clear
Pokitto 30:796f9611d2ac 619 * @return Nothing
Pokitto 30:796f9611d2ac 620 * @note This function safely clears bits in the DMA channel specific XFERCFG
Pokitto 30:796f9611d2ac 621 * register.
Pokitto 30:796f9611d2ac 622 */
Pokitto 30:796f9611d2ac 623 void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask);
Pokitto 30:796f9611d2ac 624
Pokitto 30:796f9611d2ac 625 /**
Pokitto 30:796f9611d2ac 626 * @brief Update the transfer size in an existing DMA channel transfer configuration
Pokitto 30:796f9611d2ac 627 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 628 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 629 * @param trans : Number of transfers to update the transfer configuration to (1 - 1023)
Pokitto 30:796f9611d2ac 630 * @return Nothing
Pokitto 30:796f9611d2ac 631 */
Pokitto 30:796f9611d2ac 632 void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans);
Pokitto 30:796f9611d2ac 633
Pokitto 30:796f9611d2ac 634 /**
Pokitto 30:796f9611d2ac 635 * @brief Sets a DMA channel configuration as valid
Pokitto 30:796f9611d2ac 636 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 637 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 638 * @return Nothing
Pokitto 30:796f9611d2ac 639 */
Pokitto 30:796f9611d2ac 640 STATIC INLINE void Chip_DMA_SetChannelValid(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 641 {
Pokitto 30:796f9611d2ac 642 Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID);
Pokitto 30:796f9611d2ac 643 }
Pokitto 30:796f9611d2ac 644
Pokitto 30:796f9611d2ac 645 /**
Pokitto 30:796f9611d2ac 646 * @brief Sets a DMA channel configuration as invalid
Pokitto 30:796f9611d2ac 647 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 648 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 649 * @return Nothing
Pokitto 30:796f9611d2ac 650 */
Pokitto 30:796f9611d2ac 651 STATIC INLINE void Chip_DMA_SetChannelInValid(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 652 {
Pokitto 30:796f9611d2ac 653 Chip_DMA_ClearTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID);
Pokitto 30:796f9611d2ac 654 }
Pokitto 30:796f9611d2ac 655
Pokitto 30:796f9611d2ac 656 /**
Pokitto 30:796f9611d2ac 657 * @brief Performs a software trigger of the DMA channel
Pokitto 30:796f9611d2ac 658 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 659 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 660 * @return Nothing
Pokitto 30:796f9611d2ac 661 */
Pokitto 30:796f9611d2ac 662 STATIC INLINE void Chip_DMA_SWTriggerChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
Pokitto 30:796f9611d2ac 663 {
Pokitto 30:796f9611d2ac 664 Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_SWTRIG);
Pokitto 30:796f9611d2ac 665 }
Pokitto 30:796f9611d2ac 666
Pokitto 30:796f9611d2ac 667 /**
Pokitto 30:796f9611d2ac 668 * @brief Sets up a DMA channel with the passed DMA transfer descriptor
Pokitto 30:796f9611d2ac 669 * @param pDMA : The base of DMA controller on the chip
Pokitto 30:796f9611d2ac 670 * @param ch : DMA channel ID
Pokitto 30:796f9611d2ac 671 * @param desc : Pointer to DMA transfer descriptor
Pokitto 30:796f9611d2ac 672 * @return false if the DMA channel was active, otherwise true
Pokitto 30:796f9611d2ac 673 * @note This function will set the DMA descriptor in the SRAM table to the
Pokitto 30:796f9611d2ac 674 * the passed descriptor. This function is only meant to be used when
Pokitto 30:796f9611d2ac 675 * the DMA channel is not active and can be used to setup the
Pokitto 30:796f9611d2ac 676 * initial transfer for a linked list or ping-pong buffer or just a
Pokitto 30:796f9611d2ac 677 * single transfer without a next descriptor.<br>
Pokitto 30:796f9611d2ac 678 *
Pokitto 30:796f9611d2ac 679 * If using this function to write the initial transfer descriptor in
Pokitto 30:796f9611d2ac 680 * a linked list or ping-pong buffer configuration, it should contain a
Pokitto 30:796f9611d2ac 681 * non-NULL 'next' field pointer.
Pokitto 30:796f9611d2ac 682 */
Pokitto 30:796f9611d2ac 683 bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc);
Pokitto 30:796f9611d2ac 684
Pokitto 30:796f9611d2ac 685 /**
Pokitto 30:796f9611d2ac 686 * @}
Pokitto 30:796f9611d2ac 687 */
Pokitto 30:796f9611d2ac 688
Pokitto 30:796f9611d2ac 689 /**
Pokitto 30:796f9611d2ac 690 * @}
Pokitto 30:796f9611d2ac 691 */
Pokitto 30:796f9611d2ac 692
Pokitto 30:796f9611d2ac 693 #ifdef __cplusplus
Pokitto 30:796f9611d2ac 694 }
Pokitto 30:796f9611d2ac 695 #endif
Pokitto 30:796f9611d2ac 696
Pokitto 30:796f9611d2ac 697 #endif /* __DMA_11U6X_H_ */
Pokitto 30:796f9611d2ac 698
Pokitto 30:796f9611d2ac 699