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source/EncoderCounter.cpp@27:df11ab63cda4, 2017-03-06 (annotated)

Committer:
cittecla
Date:
Mon Mar 06 15:10:24 2017 +0000
Revision:
27:df11ab63cda4
Implemented encoder counter

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cittecla 27:df11ab63cda4 1 /*
cittecla 27:df11ab63cda4 2 * EncoderCounter.cpp
cittecla 27:df11ab63cda4 3 * Copyright (c) 2016, ZHAW
cittecla 27:df11ab63cda4 4 * All rights reserved.
cittecla 27:df11ab63cda4 5 */
cittecla 27:df11ab63cda4 6
cittecla 27:df11ab63cda4 7 #include "EncoderCounter.h"
cittecla 27:df11ab63cda4 8
cittecla 27:df11ab63cda4 9 using namespace std;
cittecla 27:df11ab63cda4 10
cittecla 27:df11ab63cda4 11 /**
cittecla 27:df11ab63cda4 12 * Creates and initializes the driver to read the quadrature
cittecla 27:df11ab63cda4 13 * encoder counter of the STM32 microcontroller.
cittecla 27:df11ab63cda4 14 * @param a the input pin for the channel A.
cittecla 27:df11ab63cda4 15 * @param b the input pin for the channel B.
cittecla 27:df11ab63cda4 16 */
cittecla 27:df11ab63cda4 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
cittecla 27:df11ab63cda4 18
cittecla 27:df11ab63cda4 19 // check pins
cittecla 27:df11ab63cda4 20
cittecla 27:df11ab63cda4 21 if ((a == PA_6) && (b == PC_7)) {
cittecla 27:df11ab63cda4 22
cittecla 27:df11ab63cda4 23 // pinmap OK for TIM3 CH1 and CH2
cittecla 27:df11ab63cda4 24
cittecla 27:df11ab63cda4 25 TIM = TIM3;
cittecla 27:df11ab63cda4 26
cittecla 27:df11ab63cda4 27 // configure reset and clock control registers
cittecla 27:df11ab63cda4 28
cittecla 27:df11ab63cda4 29 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
cittecla 27:df11ab63cda4 30
cittecla 27:df11ab63cda4 31 // configure general purpose I/O registers
cittecla 27:df11ab63cda4 32
cittecla 27:df11ab63cda4 33 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
cittecla 27:df11ab63cda4 34 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
cittecla 27:df11ab63cda4 35 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
cittecla 27:df11ab63cda4 36 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
cittecla 27:df11ab63cda4 37 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
cittecla 27:df11ab63cda4 38 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
cittecla 27:df11ab63cda4 39
cittecla 27:df11ab63cda4 40 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
cittecla 27:df11ab63cda4 41 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
cittecla 27:df11ab63cda4 42 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
cittecla 27:df11ab63cda4 43 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
cittecla 27:df11ab63cda4 44 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
cittecla 27:df11ab63cda4 45 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
cittecla 27:df11ab63cda4 46
cittecla 27:df11ab63cda4 47 // configure reset and clock control registers
cittecla 27:df11ab63cda4 48
cittecla 27:df11ab63cda4 49 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
cittecla 27:df11ab63cda4 50 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
cittecla 27:df11ab63cda4 51
cittecla 27:df11ab63cda4 52 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
cittecla 27:df11ab63cda4 53
cittecla 27:df11ab63cda4 54 } else if ((a == PB_6) && (b == PB_7)) {
cittecla 27:df11ab63cda4 55
cittecla 27:df11ab63cda4 56 // pinmap OK for TIM4 CH1 and CH2
cittecla 27:df11ab63cda4 57
cittecla 27:df11ab63cda4 58 TIM = TIM4;
cittecla 27:df11ab63cda4 59
cittecla 27:df11ab63cda4 60 // configure reset and clock control registers
cittecla 27:df11ab63cda4 61
cittecla 27:df11ab63cda4 62 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
cittecla 27:df11ab63cda4 63
cittecla 27:df11ab63cda4 64 // configure general purpose I/O registers
cittecla 27:df11ab63cda4 65
cittecla 27:df11ab63cda4 66 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
cittecla 27:df11ab63cda4 67 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
cittecla 27:df11ab63cda4 68 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
cittecla 27:df11ab63cda4 69 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
cittecla 27:df11ab63cda4 70 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
cittecla 27:df11ab63cda4 71 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
cittecla 27:df11ab63cda4 72
cittecla 27:df11ab63cda4 73 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
cittecla 27:df11ab63cda4 74 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
cittecla 27:df11ab63cda4 75 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
cittecla 27:df11ab63cda4 76 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
cittecla 27:df11ab63cda4 77 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
cittecla 27:df11ab63cda4 78 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
cittecla 27:df11ab63cda4 79
cittecla 27:df11ab63cda4 80 // configure reset and clock control registers
cittecla 27:df11ab63cda4 81
cittecla 27:df11ab63cda4 82 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
cittecla 27:df11ab63cda4 83 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
cittecla 27:df11ab63cda4 84
cittecla 27:df11ab63cda4 85 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
cittecla 27:df11ab63cda4 86
cittecla 27:df11ab63cda4 87 } else {
cittecla 27:df11ab63cda4 88
cittecla 27:df11ab63cda4 89 printf("pinmap not found for peripheral\n");
cittecla 27:df11ab63cda4 90 }
cittecla 27:df11ab63cda4 91
cittecla 27:df11ab63cda4 92 // configure general purpose timer 3 or 4
cittecla 27:df11ab63cda4 93
cittecla 27:df11ab63cda4 94 TIM->CR1 = 0x0000; // counter disable
cittecla 27:df11ab63cda4 95 TIM->CR2 = 0x0000; // reset master mode selection
cittecla 27:df11ab63cda4 96 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
cittecla 27:df11ab63cda4 97 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
cittecla 27:df11ab63cda4 98 TIM->CCMR2 = 0x0000; // reset capture mode register 2
cittecla 27:df11ab63cda4 99 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
cittecla 27:df11ab63cda4 100 TIM->CNT = 0x0000; // reset counter value
cittecla 27:df11ab63cda4 101 TIM->ARR = 0xFFFF; // auto reload register
cittecla 27:df11ab63cda4 102 TIM->CR1 = TIM_CR1_CEN; // counter enable
cittecla 27:df11ab63cda4 103 }
cittecla 27:df11ab63cda4 104
cittecla 27:df11ab63cda4 105 EncoderCounter::~EncoderCounter() {}
cittecla 27:df11ab63cda4 106
cittecla 27:df11ab63cda4 107 /**
cittecla 27:df11ab63cda4 108 * Resets the counter value to zero.
cittecla 27:df11ab63cda4 109 */
cittecla 27:df11ab63cda4 110 void EncoderCounter::reset() {
cittecla 27:df11ab63cda4 111
cittecla 27:df11ab63cda4 112 TIM->CNT = 0x0000;
cittecla 27:df11ab63cda4 113 }
cittecla 27:df11ab63cda4 114
cittecla 27:df11ab63cda4 115 /**
cittecla 27:df11ab63cda4 116 * Resets the counter value to a given offset value.
cittecla 27:df11ab63cda4 117 * @param offset the offset value to reset the counter to.
cittecla 27:df11ab63cda4 118 */
cittecla 27:df11ab63cda4 119 void EncoderCounter::reset(short offset) {
cittecla 27:df11ab63cda4 120
cittecla 27:df11ab63cda4 121 TIM->CNT = -offset;
cittecla 27:df11ab63cda4 122 }
cittecla 27:df11ab63cda4 123
cittecla 27:df11ab63cda4 124 /**
cittecla 27:df11ab63cda4 125 * Reads the quadrature encoder counter value.
cittecla 27:df11ab63cda4 126 * @return the quadrature encoder counter as a signed 16-bit integer value.
cittecla 27:df11ab63cda4 127 */
cittecla 27:df11ab63cda4 128 short EncoderCounter::read() {
cittecla 27:df11ab63cda4 129
cittecla 27:df11ab63cda4 130 return (short)(-TIM->CNT);
cittecla 27:df11ab63cda4 131 }
cittecla 27:df11ab63cda4 132
cittecla 27:df11ab63cda4 133 /**
cittecla 27:df11ab63cda4 134 * The empty operator is a shorthand notation of the <code>read()</code> method.
cittecla 27:df11ab63cda4 135 */
cittecla 27:df11ab63cda4 136 EncoderCounter::operator short() {
cittecla 27:df11ab63cda4 137
cittecla 27:df11ab63cda4 138 return read();
cittecla 27:df11ab63cda4 139 }