Nirvana Jay / BSP_DISCO_F746NG_patch

patch for F746 demo

Dependents:   F7DISCO_Demo

Fork of BSP_DISCO_F746NG by ST

Components/stmpe811/stmpe811.h@1:e8fac4061a5b, 2015-11-02 (annotated)

Committer:
NirT
Date:
Mon Nov 02 23:35:17 2015 +0000
Revision:
1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.

Who changed what in which revision?

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NirT 1:e8fac4061a5b 1 /**
NirT 1:e8fac4061a5b 2 ******************************************************************************
NirT 1:e8fac4061a5b 3 * @file stmpe811.h
NirT 1:e8fac4061a5b 4 * @author MCD Application Team
NirT 1:e8fac4061a5b 5 * @version V2.0.0
NirT 1:e8fac4061a5b 6 * @date 15-December-2014
NirT 1:e8fac4061a5b 7 * @brief This file contains all the functions prototypes for the
NirT 1:e8fac4061a5b 8 * stmpe811.c IO expander driver.
NirT 1:e8fac4061a5b 9 ******************************************************************************
NirT 1:e8fac4061a5b 10 * @attention
NirT 1:e8fac4061a5b 11 *
NirT 1:e8fac4061a5b 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
NirT 1:e8fac4061a5b 13 *
NirT 1:e8fac4061a5b 14 * Redistribution and use in source and binary forms, with or without modification,
NirT 1:e8fac4061a5b 15 * are permitted provided that the following conditions are met:
NirT 1:e8fac4061a5b 16 * 1. Redistributions of source code must retain the above copyright notice,
NirT 1:e8fac4061a5b 17 * this list of conditions and the following disclaimer.
NirT 1:e8fac4061a5b 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
NirT 1:e8fac4061a5b 19 * this list of conditions and the following disclaimer in the documentation
NirT 1:e8fac4061a5b 20 * and/or other materials provided with the distribution.
NirT 1:e8fac4061a5b 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NirT 1:e8fac4061a5b 22 * may be used to endorse or promote products derived from this software
NirT 1:e8fac4061a5b 23 * without specific prior written permission.
NirT 1:e8fac4061a5b 24 *
NirT 1:e8fac4061a5b 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NirT 1:e8fac4061a5b 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NirT 1:e8fac4061a5b 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NirT 1:e8fac4061a5b 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NirT 1:e8fac4061a5b 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NirT 1:e8fac4061a5b 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NirT 1:e8fac4061a5b 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NirT 1:e8fac4061a5b 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NirT 1:e8fac4061a5b 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NirT 1:e8fac4061a5b 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NirT 1:e8fac4061a5b 35 *
NirT 1:e8fac4061a5b 36 ******************************************************************************
NirT 1:e8fac4061a5b 37 */
NirT 1:e8fac4061a5b 38
NirT 1:e8fac4061a5b 39 /* Define to prevent recursive inclusion -------------------------------------*/
NirT 1:e8fac4061a5b 40 #ifndef __STMPE811_H
NirT 1:e8fac4061a5b 41 #define __STMPE811_H
NirT 1:e8fac4061a5b 42
NirT 1:e8fac4061a5b 43 #ifdef __cplusplus
NirT 1:e8fac4061a5b 44 extern "C" {
NirT 1:e8fac4061a5b 45 #endif
NirT 1:e8fac4061a5b 46
NirT 1:e8fac4061a5b 47 /* Includes ------------------------------------------------------------------*/
NirT 1:e8fac4061a5b 48 #include "../Common/ts.h"
NirT 1:e8fac4061a5b 49 #include "../Common/io.h"
NirT 1:e8fac4061a5b 50
NirT 1:e8fac4061a5b 51 /** @addtogroup BSP
NirT 1:e8fac4061a5b 52 * @{
NirT 1:e8fac4061a5b 53 */
NirT 1:e8fac4061a5b 54
NirT 1:e8fac4061a5b 55 /** @addtogroup Components
NirT 1:e8fac4061a5b 56 * @{
NirT 1:e8fac4061a5b 57 */
NirT 1:e8fac4061a5b 58
NirT 1:e8fac4061a5b 59 /** @defgroup STMPE811
NirT 1:e8fac4061a5b 60 * @{
NirT 1:e8fac4061a5b 61 */
NirT 1:e8fac4061a5b 62
NirT 1:e8fac4061a5b 63 /** @defgroup STMPE811_Exported_Types
NirT 1:e8fac4061a5b 64 * @{
NirT 1:e8fac4061a5b 65 */
NirT 1:e8fac4061a5b 66 /**
NirT 1:e8fac4061a5b 67 * @}
NirT 1:e8fac4061a5b 68 */
NirT 1:e8fac4061a5b 69
NirT 1:e8fac4061a5b 70 /** @defgroup STMPE811_Exported_Constants
NirT 1:e8fac4061a5b 71 * @{
NirT 1:e8fac4061a5b 72 */
NirT 1:e8fac4061a5b 73
NirT 1:e8fac4061a5b 74 /* Chip IDs */
NirT 1:e8fac4061a5b 75 #define STMPE811_ID 0x0811
NirT 1:e8fac4061a5b 76
NirT 1:e8fac4061a5b 77 /* Identification registers & System Control */
NirT 1:e8fac4061a5b 78 #define STMPE811_REG_CHP_ID_LSB 0x00
NirT 1:e8fac4061a5b 79 #define STMPE811_REG_CHP_ID_MSB 0x01
NirT 1:e8fac4061a5b 80 #define STMPE811_REG_ID_VER 0x02
NirT 1:e8fac4061a5b 81
NirT 1:e8fac4061a5b 82 /* Global interrupt Enable bit */
NirT 1:e8fac4061a5b 83 #define STMPE811_GIT_EN 0x01
NirT 1:e8fac4061a5b 84
NirT 1:e8fac4061a5b 85 /* IO expander functionalities */
NirT 1:e8fac4061a5b 86 #define STMPE811_ADC_FCT 0x01
NirT 1:e8fac4061a5b 87 #define STMPE811_TS_FCT 0x02
NirT 1:e8fac4061a5b 88 #define STMPE811_IO_FCT 0x04
NirT 1:e8fac4061a5b 89 #define STMPE811_TEMPSENS_FCT 0x08
NirT 1:e8fac4061a5b 90
NirT 1:e8fac4061a5b 91 /* Global Interrupts definitions */
NirT 1:e8fac4061a5b 92 #define STMPE811_GIT_IO 0x80 /* IO interrupt */
NirT 1:e8fac4061a5b 93 #define STMPE811_GIT_ADC 0x40 /* ADC interrupt */
NirT 1:e8fac4061a5b 94 #define STMPE811_GIT_TEMP 0x20 /* Not implemented */
NirT 1:e8fac4061a5b 95 #define STMPE811_GIT_FE 0x10 /* FIFO empty interrupt */
NirT 1:e8fac4061a5b 96 #define STMPE811_GIT_FF 0x08 /* FIFO full interrupt */
NirT 1:e8fac4061a5b 97 #define STMPE811_GIT_FOV 0x04 /* FIFO overflowed interrupt */
NirT 1:e8fac4061a5b 98 #define STMPE811_GIT_FTH 0x02 /* FIFO above threshold interrupt */
NirT 1:e8fac4061a5b 99 #define STMPE811_GIT_TOUCH 0x01 /* Touch is detected interrupt */
NirT 1:e8fac4061a5b 100 #define STMPE811_ALL_GIT 0x1F /* All global interrupts */
NirT 1:e8fac4061a5b 101 #define STMPE811_TS_IT (STMPE811_GIT_TOUCH | STMPE811_GIT_FTH | STMPE811_GIT_FOV | STMPE811_GIT_FF | STMPE811_GIT_FE) /* Touch screen interrupts */
NirT 1:e8fac4061a5b 102
NirT 1:e8fac4061a5b 103 /* General Control Registers */
NirT 1:e8fac4061a5b 104 #define STMPE811_REG_SYS_CTRL1 0x03
NirT 1:e8fac4061a5b 105 #define STMPE811_REG_SYS_CTRL2 0x04
NirT 1:e8fac4061a5b 106 #define STMPE811_REG_SPI_CFG 0x08
NirT 1:e8fac4061a5b 107
NirT 1:e8fac4061a5b 108 /* Interrupt system Registers */
NirT 1:e8fac4061a5b 109 #define STMPE811_REG_INT_CTRL 0x09
NirT 1:e8fac4061a5b 110 #define STMPE811_REG_INT_EN 0x0A
NirT 1:e8fac4061a5b 111 #define STMPE811_REG_INT_STA 0x0B
NirT 1:e8fac4061a5b 112 #define STMPE811_REG_IO_INT_EN 0x0C
NirT 1:e8fac4061a5b 113 #define STMPE811_REG_IO_INT_STA 0x0D
NirT 1:e8fac4061a5b 114
NirT 1:e8fac4061a5b 115 /* IO Registers */
NirT 1:e8fac4061a5b 116 #define STMPE811_REG_IO_SET_PIN 0x10
NirT 1:e8fac4061a5b 117 #define STMPE811_REG_IO_CLR_PIN 0x11
NirT 1:e8fac4061a5b 118 #define STMPE811_REG_IO_MP_STA 0x12
NirT 1:e8fac4061a5b 119 #define STMPE811_REG_IO_DIR 0x13
NirT 1:e8fac4061a5b 120 #define STMPE811_REG_IO_ED 0x14
NirT 1:e8fac4061a5b 121 #define STMPE811_REG_IO_RE 0x15
NirT 1:e8fac4061a5b 122 #define STMPE811_REG_IO_FE 0x16
NirT 1:e8fac4061a5b 123 #define STMPE811_REG_IO_AF 0x17
NirT 1:e8fac4061a5b 124
NirT 1:e8fac4061a5b 125 /* ADC Registers */
NirT 1:e8fac4061a5b 126 #define STMPE811_REG_ADC_INT_EN 0x0E
NirT 1:e8fac4061a5b 127 #define STMPE811_REG_ADC_INT_STA 0x0F
NirT 1:e8fac4061a5b 128 #define STMPE811_REG_ADC_CTRL1 0x20
NirT 1:e8fac4061a5b 129 #define STMPE811_REG_ADC_CTRL2 0x21
NirT 1:e8fac4061a5b 130 #define STMPE811_REG_ADC_CAPT 0x22
NirT 1:e8fac4061a5b 131 #define STMPE811_REG_ADC_DATA_CH0 0x30
NirT 1:e8fac4061a5b 132 #define STMPE811_REG_ADC_DATA_CH1 0x32
NirT 1:e8fac4061a5b 133 #define STMPE811_REG_ADC_DATA_CH2 0x34
NirT 1:e8fac4061a5b 134 #define STMPE811_REG_ADC_DATA_CH3 0x36
NirT 1:e8fac4061a5b 135 #define STMPE811_REG_ADC_DATA_CH4 0x38
NirT 1:e8fac4061a5b 136 #define STMPE811_REG_ADC_DATA_CH5 0x3A
NirT 1:e8fac4061a5b 137 #define STMPE811_REG_ADC_DATA_CH6 0x3B
NirT 1:e8fac4061a5b 138 #define STMPE811_REG_ADC_DATA_CH7 0x3C
NirT 1:e8fac4061a5b 139
NirT 1:e8fac4061a5b 140 /* Touch Screen Registers */
NirT 1:e8fac4061a5b 141 #define STMPE811_REG_TSC_CTRL 0x40
NirT 1:e8fac4061a5b 142 #define STMPE811_REG_TSC_CFG 0x41
NirT 1:e8fac4061a5b 143 #define STMPE811_REG_WDM_TR_X 0x42
NirT 1:e8fac4061a5b 144 #define STMPE811_REG_WDM_TR_Y 0x44
NirT 1:e8fac4061a5b 145 #define STMPE811_REG_WDM_BL_X 0x46
NirT 1:e8fac4061a5b 146 #define STMPE811_REG_WDM_BL_Y 0x48
NirT 1:e8fac4061a5b 147 #define STMPE811_REG_FIFO_TH 0x4A
NirT 1:e8fac4061a5b 148 #define STMPE811_REG_FIFO_STA 0x4B
NirT 1:e8fac4061a5b 149 #define STMPE811_REG_FIFO_SIZE 0x4C
NirT 1:e8fac4061a5b 150 #define STMPE811_REG_TSC_DATA_X 0x4D
NirT 1:e8fac4061a5b 151 #define STMPE811_REG_TSC_DATA_Y 0x4F
NirT 1:e8fac4061a5b 152 #define STMPE811_REG_TSC_DATA_Z 0x51
NirT 1:e8fac4061a5b 153 #define STMPE811_REG_TSC_DATA_XYZ 0x52
NirT 1:e8fac4061a5b 154 #define STMPE811_REG_TSC_FRACT_XYZ 0x56
NirT 1:e8fac4061a5b 155 #define STMPE811_REG_TSC_DATA_INC 0x57
NirT 1:e8fac4061a5b 156 #define STMPE811_REG_TSC_DATA_NON_INC 0xD7
NirT 1:e8fac4061a5b 157 #define STMPE811_REG_TSC_I_DRIVE 0x58
NirT 1:e8fac4061a5b 158 #define STMPE811_REG_TSC_SHIELD 0x59
NirT 1:e8fac4061a5b 159
NirT 1:e8fac4061a5b 160 /* Touch Screen Pins definition */
NirT 1:e8fac4061a5b 161 #define STMPE811_TOUCH_YD STMPE811_PIN_7
NirT 1:e8fac4061a5b 162 #define STMPE811_TOUCH_XD STMPE811_PIN_6
NirT 1:e8fac4061a5b 163 #define STMPE811_TOUCH_YU STMPE811_PIN_5
NirT 1:e8fac4061a5b 164 #define STMPE811_TOUCH_XU STMPE811_PIN_4
NirT 1:e8fac4061a5b 165 #define STMPE811_TOUCH_IO_ALL (uint32_t)(STMPE811_TOUCH_YD | STMPE811_TOUCH_XD | STMPE811_TOUCH_YU | STMPE811_TOUCH_XU)
NirT 1:e8fac4061a5b 166
NirT 1:e8fac4061a5b 167 /* IO Pins definition */
NirT 1:e8fac4061a5b 168 #define STMPE811_PIN_0 0x01
NirT 1:e8fac4061a5b 169 #define STMPE811_PIN_1 0x02
NirT 1:e8fac4061a5b 170 #define STMPE811_PIN_2 0x04
NirT 1:e8fac4061a5b 171 #define STMPE811_PIN_3 0x08
NirT 1:e8fac4061a5b 172 #define STMPE811_PIN_4 0x10
NirT 1:e8fac4061a5b 173 #define STMPE811_PIN_5 0x20
NirT 1:e8fac4061a5b 174 #define STMPE811_PIN_6 0x40
NirT 1:e8fac4061a5b 175 #define STMPE811_PIN_7 0x80
NirT 1:e8fac4061a5b 176 #define STMPE811_PIN_ALL 0xFF
NirT 1:e8fac4061a5b 177
NirT 1:e8fac4061a5b 178 /* IO Pins directions */
NirT 1:e8fac4061a5b 179 #define STMPE811_DIRECTION_IN 0x00
NirT 1:e8fac4061a5b 180 #define STMPE811_DIRECTION_OUT 0x01
NirT 1:e8fac4061a5b 181
NirT 1:e8fac4061a5b 182 /* IO IT types */
NirT 1:e8fac4061a5b 183 #define STMPE811_TYPE_LEVEL 0x00
NirT 1:e8fac4061a5b 184 #define STMPE811_TYPE_EDGE 0x02
NirT 1:e8fac4061a5b 185
NirT 1:e8fac4061a5b 186 /* IO IT polarity */
NirT 1:e8fac4061a5b 187 #define STMPE811_POLARITY_LOW 0x00
NirT 1:e8fac4061a5b 188 #define STMPE811_POLARITY_HIGH 0x04
NirT 1:e8fac4061a5b 189
NirT 1:e8fac4061a5b 190 /* IO Pin IT edge modes */
NirT 1:e8fac4061a5b 191 #define STMPE811_EDGE_FALLING 0x01
NirT 1:e8fac4061a5b 192 #define STMPE811_EDGE_RISING 0x02
NirT 1:e8fac4061a5b 193
NirT 1:e8fac4061a5b 194 /* TS registers masks */
NirT 1:e8fac4061a5b 195 #define STMPE811_TS_CTRL_ENABLE 0x01
NirT 1:e8fac4061a5b 196 #define STMPE811_TS_CTRL_STATUS 0x80
NirT 1:e8fac4061a5b 197 /**
NirT 1:e8fac4061a5b 198 * @}
NirT 1:e8fac4061a5b 199 */
NirT 1:e8fac4061a5b 200
NirT 1:e8fac4061a5b 201 /** @defgroup STMPE811_Exported_Macros
NirT 1:e8fac4061a5b 202 * @{
NirT 1:e8fac4061a5b 203 */
NirT 1:e8fac4061a5b 204 /**
NirT 1:e8fac4061a5b 205 * @}
NirT 1:e8fac4061a5b 206 */
NirT 1:e8fac4061a5b 207
NirT 1:e8fac4061a5b 208 /** @defgroup STMPE811_Exported_Functions
NirT 1:e8fac4061a5b 209 * @{
NirT 1:e8fac4061a5b 210 */
NirT 1:e8fac4061a5b 211
NirT 1:e8fac4061a5b 212 /**
NirT 1:e8fac4061a5b 213 * @brief STMPE811 Control functions
NirT 1:e8fac4061a5b 214 */
NirT 1:e8fac4061a5b 215 void stmpe811_Init(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 216 void stmpe811_Reset(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 217 uint16_t stmpe811_ReadID(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 218 void stmpe811_EnableGlobalIT(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 219 void stmpe811_DisableGlobalIT(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 220 void stmpe811_EnableITSource(uint16_t DeviceAddr, uint8_t Source);
NirT 1:e8fac4061a5b 221 void stmpe811_DisableITSource(uint16_t DeviceAddr, uint8_t Source);
NirT 1:e8fac4061a5b 222 void stmpe811_SetITPolarity(uint16_t DeviceAddr, uint8_t Polarity);
NirT 1:e8fac4061a5b 223 void stmpe811_SetITType(uint16_t DeviceAddr, uint8_t Type);
NirT 1:e8fac4061a5b 224 uint8_t stmpe811_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source);
NirT 1:e8fac4061a5b 225 uint8_t stmpe811_ReadGITStatus(uint16_t DeviceAddr, uint8_t Source);
NirT 1:e8fac4061a5b 226 void stmpe811_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source);
NirT 1:e8fac4061a5b 227
NirT 1:e8fac4061a5b 228 /**
NirT 1:e8fac4061a5b 229 * @brief STMPE811 IO functionalities functions
NirT 1:e8fac4061a5b 230 */
NirT 1:e8fac4061a5b 231 void stmpe811_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 232 uint8_t stmpe811_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode);
NirT 1:e8fac4061a5b 233 void stmpe811_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction);
NirT 1:e8fac4061a5b 234 void stmpe811_IO_EnableAF(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 235 void stmpe811_IO_DisableAF(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 236 void stmpe811_IO_SetEdgeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Edge);
NirT 1:e8fac4061a5b 237 void stmpe811_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState);
NirT 1:e8fac4061a5b 238 uint32_t stmpe811_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 239 void stmpe811_IO_EnableIT(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 240 void stmpe811_IO_DisableIT(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 241 void stmpe811_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 242 void stmpe811_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 243 uint32_t stmpe811_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 244 void stmpe811_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin);
NirT 1:e8fac4061a5b 245
NirT 1:e8fac4061a5b 246 /**
NirT 1:e8fac4061a5b 247 * @brief STMPE811 Touch screen functionalities functions
NirT 1:e8fac4061a5b 248 */
NirT 1:e8fac4061a5b 249 void stmpe811_TS_Start(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 250 uint8_t stmpe811_TS_DetectTouch(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 251 void stmpe811_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y);
NirT 1:e8fac4061a5b 252 void stmpe811_TS_EnableIT(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 253 void stmpe811_TS_DisableIT(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 254 uint8_t stmpe811_TS_ITStatus (uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 255 void stmpe811_TS_ClearIT (uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 256
NirT 1:e8fac4061a5b 257 void IOE_Init(void);
NirT 1:e8fac4061a5b 258 void IOE_ITConfig (void);
NirT 1:e8fac4061a5b 259 void IOE_Delay(uint32_t delay);
NirT 1:e8fac4061a5b 260 void IOE_Write(uint8_t addr, uint8_t reg, uint8_t value);
NirT 1:e8fac4061a5b 261 uint8_t IOE_Read(uint8_t addr, uint8_t reg);
NirT 1:e8fac4061a5b 262 uint16_t IOE_ReadMultiple(uint8_t addr, uint8_t reg, uint8_t *buffer, uint16_t length);
NirT 1:e8fac4061a5b 263
NirT 1:e8fac4061a5b 264 /* Touch screen driver structure */
NirT 1:e8fac4061a5b 265 extern TS_DrvTypeDef stmpe811_ts_drv;
NirT 1:e8fac4061a5b 266
NirT 1:e8fac4061a5b 267 /* IO driver structure */
NirT 1:e8fac4061a5b 268 extern IO_DrvTypeDef stmpe811_io_drv;
NirT 1:e8fac4061a5b 269
NirT 1:e8fac4061a5b 270 #ifdef __cplusplus
NirT 1:e8fac4061a5b 271 }
NirT 1:e8fac4061a5b 272 #endif
NirT 1:e8fac4061a5b 273 #endif /* __STMPE811_H */
NirT 1:e8fac4061a5b 274
NirT 1:e8fac4061a5b 275 /**
NirT 1:e8fac4061a5b 276 * @}
NirT 1:e8fac4061a5b 277 */
NirT 1:e8fac4061a5b 278
NirT 1:e8fac4061a5b 279 /**
NirT 1:e8fac4061a5b 280 * @}
NirT 1:e8fac4061a5b 281 */
NirT 1:e8fac4061a5b 282
NirT 1:e8fac4061a5b 283 /**
NirT 1:e8fac4061a5b 284 * @}
NirT 1:e8fac4061a5b 285 */
NirT 1:e8fac4061a5b 286
NirT 1:e8fac4061a5b 287 /**
NirT 1:e8fac4061a5b 288 * @}
NirT 1:e8fac4061a5b 289 */
NirT 1:e8fac4061a5b 290
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