Nirvana Jay / BSP_DISCO_F746NG_patch

patch for F746 demo

Dependents:   F7DISCO_Demo

Fork of BSP_DISCO_F746NG by ST

Components/wm8994/wm8994.c@1:e8fac4061a5b, 2015-11-02 (annotated)

Committer:
NirT
Date:
Mon Nov 02 23:35:17 2015 +0000
Revision:
1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NirT 1:e8fac4061a5b 1 /**
NirT 1:e8fac4061a5b 2 ******************************************************************************
NirT 1:e8fac4061a5b 3 * @file wm8994.c
NirT 1:e8fac4061a5b 4 * @author MCD Application Team
NirT 1:e8fac4061a5b 5 * @version V2.0.0
NirT 1:e8fac4061a5b 6 * @date 24-June-2015
NirT 1:e8fac4061a5b 7 * @brief This file provides the WM8994 Audio Codec driver.
NirT 1:e8fac4061a5b 8 ******************************************************************************
NirT 1:e8fac4061a5b 9 * @attention
NirT 1:e8fac4061a5b 10 *
NirT 1:e8fac4061a5b 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
NirT 1:e8fac4061a5b 12 *
NirT 1:e8fac4061a5b 13 * Redistribution and use in source and binary forms, with or without modification,
NirT 1:e8fac4061a5b 14 * are permitted provided that the following conditions are met:
NirT 1:e8fac4061a5b 15 * 1. Redistributions of source code must retain the above copyright notice,
NirT 1:e8fac4061a5b 16 * this list of conditions and the following disclaimer.
NirT 1:e8fac4061a5b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NirT 1:e8fac4061a5b 18 * this list of conditions and the following disclaimer in the documentation
NirT 1:e8fac4061a5b 19 * and/or other materials provided with the distribution.
NirT 1:e8fac4061a5b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NirT 1:e8fac4061a5b 21 * may be used to endorse or promote products derived from this software
NirT 1:e8fac4061a5b 22 * without specific prior written permission.
NirT 1:e8fac4061a5b 23 *
NirT 1:e8fac4061a5b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NirT 1:e8fac4061a5b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NirT 1:e8fac4061a5b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NirT 1:e8fac4061a5b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NirT 1:e8fac4061a5b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NirT 1:e8fac4061a5b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NirT 1:e8fac4061a5b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NirT 1:e8fac4061a5b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NirT 1:e8fac4061a5b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NirT 1:e8fac4061a5b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NirT 1:e8fac4061a5b 34 *
NirT 1:e8fac4061a5b 35 ******************************************************************************
NirT 1:e8fac4061a5b 36 */
NirT 1:e8fac4061a5b 37
NirT 1:e8fac4061a5b 38 /* Includes ------------------------------------------------------------------*/
NirT 1:e8fac4061a5b 39 #include "wm8994.h"
NirT 1:e8fac4061a5b 40
NirT 1:e8fac4061a5b 41 /** @addtogroup BSP
NirT 1:e8fac4061a5b 42 * @{
NirT 1:e8fac4061a5b 43 */
NirT 1:e8fac4061a5b 44
NirT 1:e8fac4061a5b 45 /** @addtogroup Components
NirT 1:e8fac4061a5b 46 * @{
NirT 1:e8fac4061a5b 47 */
NirT 1:e8fac4061a5b 48
NirT 1:e8fac4061a5b 49 /** @addtogroup wm8994
NirT 1:e8fac4061a5b 50 * @brief This file provides a set of functions needed to drive the
NirT 1:e8fac4061a5b 51 * WM8994 audio codec.
NirT 1:e8fac4061a5b 52 * @{
NirT 1:e8fac4061a5b 53 */
NirT 1:e8fac4061a5b 54
NirT 1:e8fac4061a5b 55 /** @defgroup WM8994_Private_Types
NirT 1:e8fac4061a5b 56 * @{
NirT 1:e8fac4061a5b 57 */
NirT 1:e8fac4061a5b 58
NirT 1:e8fac4061a5b 59 /**
NirT 1:e8fac4061a5b 60 * @}
NirT 1:e8fac4061a5b 61 */
NirT 1:e8fac4061a5b 62
NirT 1:e8fac4061a5b 63 /** @defgroup WM8994_Private_Defines
NirT 1:e8fac4061a5b 64 * @{
NirT 1:e8fac4061a5b 65 */
NirT 1:e8fac4061a5b 66 /* Uncomment this line to enable verifying data sent to codec after each write
NirT 1:e8fac4061a5b 67 operation (for debug purpose) */
NirT 1:e8fac4061a5b 68 #if !defined (VERIFY_WRITTENDATA)
NirT 1:e8fac4061a5b 69 /* #define VERIFY_WRITTENDATA */
NirT 1:e8fac4061a5b 70 #endif /* VERIFY_WRITTENDATA */
NirT 1:e8fac4061a5b 71 /**
NirT 1:e8fac4061a5b 72 * @}
NirT 1:e8fac4061a5b 73 */
NirT 1:e8fac4061a5b 74
NirT 1:e8fac4061a5b 75 /** @defgroup WM8994_Private_Macros
NirT 1:e8fac4061a5b 76 * @{
NirT 1:e8fac4061a5b 77 */
NirT 1:e8fac4061a5b 78
NirT 1:e8fac4061a5b 79 /**
NirT 1:e8fac4061a5b 80 * @}
NirT 1:e8fac4061a5b 81 */
NirT 1:e8fac4061a5b 82
NirT 1:e8fac4061a5b 83 /** @defgroup WM8994_Private_Variables
NirT 1:e8fac4061a5b 84 * @{
NirT 1:e8fac4061a5b 85 */
NirT 1:e8fac4061a5b 86
NirT 1:e8fac4061a5b 87 /* Audio codec driver structure initialization */
NirT 1:e8fac4061a5b 88 AUDIO_DrvTypeDef wm8994_drv =
NirT 1:e8fac4061a5b 89 {
NirT 1:e8fac4061a5b 90 wm8994_Init,
NirT 1:e8fac4061a5b 91 wm8994_DeInit,
NirT 1:e8fac4061a5b 92 wm8994_ReadID,
NirT 1:e8fac4061a5b 93
NirT 1:e8fac4061a5b 94 wm8994_Play,
NirT 1:e8fac4061a5b 95 wm8994_Pause,
NirT 1:e8fac4061a5b 96 wm8994_Resume,
NirT 1:e8fac4061a5b 97 wm8994_Stop,
NirT 1:e8fac4061a5b 98
NirT 1:e8fac4061a5b 99 wm8994_SetFrequency,
NirT 1:e8fac4061a5b 100 wm8994_SetVolume,
NirT 1:e8fac4061a5b 101 wm8994_SetMute,
NirT 1:e8fac4061a5b 102 wm8994_SetOutputMode,
NirT 1:e8fac4061a5b 103
NirT 1:e8fac4061a5b 104 wm8994_Reset
NirT 1:e8fac4061a5b 105 };
NirT 1:e8fac4061a5b 106
NirT 1:e8fac4061a5b 107 static uint32_t outputEnabled = 0;
NirT 1:e8fac4061a5b 108 static uint32_t inputEnabled = 0;
NirT 1:e8fac4061a5b 109 /**
NirT 1:e8fac4061a5b 110 * @}
NirT 1:e8fac4061a5b 111 */
NirT 1:e8fac4061a5b 112
NirT 1:e8fac4061a5b 113 /** @defgroup WM8994_Function_Prototypes
NirT 1:e8fac4061a5b 114 * @{
NirT 1:e8fac4061a5b 115 */
NirT 1:e8fac4061a5b 116 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);
NirT 1:e8fac4061a5b 117 /**
NirT 1:e8fac4061a5b 118 * @}
NirT 1:e8fac4061a5b 119 */
NirT 1:e8fac4061a5b 120
NirT 1:e8fac4061a5b 121 /** @defgroup WM8994_Private_Functions
NirT 1:e8fac4061a5b 122 * @{
NirT 1:e8fac4061a5b 123 */
NirT 1:e8fac4061a5b 124
NirT 1:e8fac4061a5b 125 /**
NirT 1:e8fac4061a5b 126 * @brief Initializes the audio codec and the control interface.
NirT 1:e8fac4061a5b 127 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 128 * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
NirT 1:e8fac4061a5b 129 * OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1,
NirT 1:e8fac4061a5b 130 * INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2.
NirT 1:e8fac4061a5b 131 * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
NirT 1:e8fac4061a5b 132 * @param AudioFreq: Audio Frequency
NirT 1:e8fac4061a5b 133 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 134 */
NirT 1:e8fac4061a5b 135 uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq)
NirT 1:e8fac4061a5b 136 {
NirT 1:e8fac4061a5b 137 uint32_t counter = 0;
NirT 1:e8fac4061a5b 138 uint16_t output_device = OutputInputDevice & 0xFF;
NirT 1:e8fac4061a5b 139 uint16_t input_device = OutputInputDevice & 0xFF00;
NirT 1:e8fac4061a5b 140 uint16_t power_mgnt_reg_1 = 0;
NirT 1:e8fac4061a5b 141
NirT 1:e8fac4061a5b 142 /* Initialize the Control interface of the Audio Codec */
NirT 1:e8fac4061a5b 143 AUDIO_IO_Init();
NirT 1:e8fac4061a5b 144 /* wm8994 Errata Work-Arounds */
NirT 1:e8fac4061a5b 145 counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003);
NirT 1:e8fac4061a5b 146 counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000);
NirT 1:e8fac4061a5b 147 counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000);
NirT 1:e8fac4061a5b 148
NirT 1:e8fac4061a5b 149 /* Enable VMID soft start (fast), Start-up Bias Current Enabled */
NirT 1:e8fac4061a5b 150 counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C);
NirT 1:e8fac4061a5b 151
NirT 1:e8fac4061a5b 152 /* Enable bias generator, Enable VMID */
NirT 1:e8fac4061a5b 153 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003);
NirT 1:e8fac4061a5b 154
NirT 1:e8fac4061a5b 155 /* Add Delay */
NirT 1:e8fac4061a5b 156 AUDIO_IO_Delay(50);
NirT 1:e8fac4061a5b 157
NirT 1:e8fac4061a5b 158 /* Path Configurations for output */
NirT 1:e8fac4061a5b 159 if (output_device > 0)
NirT 1:e8fac4061a5b 160 {
NirT 1:e8fac4061a5b 161 outputEnabled = 1;
NirT 1:e8fac4061a5b 162 switch (output_device)
NirT 1:e8fac4061a5b 163 {
NirT 1:e8fac4061a5b 164 case OUTPUT_DEVICE_SPEAKER:
NirT 1:e8fac4061a5b 165 /* Enable DAC1 (Left), Enable DAC1 (Right),
NirT 1:e8fac4061a5b 166 Disable DAC2 (Left), Disable DAC2 (Right)*/
NirT 1:e8fac4061a5b 167 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
NirT 1:e8fac4061a5b 168
NirT 1:e8fac4061a5b 169 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 170 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
NirT 1:e8fac4061a5b 171
NirT 1:e8fac4061a5b 172 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 173 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
NirT 1:e8fac4061a5b 174
NirT 1:e8fac4061a5b 175 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 176 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
NirT 1:e8fac4061a5b 177
NirT 1:e8fac4061a5b 178 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 179 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
NirT 1:e8fac4061a5b 180 break;
NirT 1:e8fac4061a5b 181
NirT 1:e8fac4061a5b 182 case OUTPUT_DEVICE_HEADPHONE:
NirT 1:e8fac4061a5b 183 /* Disable DAC1 (Left), Disable DAC1 (Right),
NirT 1:e8fac4061a5b 184 Enable DAC2 (Left), Enable DAC2 (Right)*/
NirT 1:e8fac4061a5b 185 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
NirT 1:e8fac4061a5b 186
NirT 1:e8fac4061a5b 187 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 188 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
NirT 1:e8fac4061a5b 189
NirT 1:e8fac4061a5b 190 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 191 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
NirT 1:e8fac4061a5b 192
NirT 1:e8fac4061a5b 193 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 194 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
NirT 1:e8fac4061a5b 195
NirT 1:e8fac4061a5b 196 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 197 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
NirT 1:e8fac4061a5b 198 break;
NirT 1:e8fac4061a5b 199
NirT 1:e8fac4061a5b 200 case OUTPUT_DEVICE_BOTH:
NirT 1:e8fac4061a5b 201 /* Enable DAC1 (Left), Enable DAC1 (Right),
NirT 1:e8fac4061a5b 202 also Enable DAC2 (Left), Enable DAC2 (Right)*/
NirT 1:e8fac4061a5b 203 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
NirT 1:e8fac4061a5b 204
NirT 1:e8fac4061a5b 205 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 206 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
NirT 1:e8fac4061a5b 207
NirT 1:e8fac4061a5b 208 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 209 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
NirT 1:e8fac4061a5b 210
NirT 1:e8fac4061a5b 211 /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 212 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
NirT 1:e8fac4061a5b 213
NirT 1:e8fac4061a5b 214 /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 215 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
NirT 1:e8fac4061a5b 216 break;
NirT 1:e8fac4061a5b 217
NirT 1:e8fac4061a5b 218 case OUTPUT_DEVICE_AUTO :
NirT 1:e8fac4061a5b 219 default:
NirT 1:e8fac4061a5b 220 /* Disable DAC1 (Left), Disable DAC1 (Right),
NirT 1:e8fac4061a5b 221 Enable DAC2 (Left), Enable DAC2 (Right)*/
NirT 1:e8fac4061a5b 222 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
NirT 1:e8fac4061a5b 223
NirT 1:e8fac4061a5b 224 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 225 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
NirT 1:e8fac4061a5b 226
NirT 1:e8fac4061a5b 227 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 228 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
NirT 1:e8fac4061a5b 229
NirT 1:e8fac4061a5b 230 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 231 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
NirT 1:e8fac4061a5b 232
NirT 1:e8fac4061a5b 233 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 234 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
NirT 1:e8fac4061a5b 235 break;
NirT 1:e8fac4061a5b 236 }
NirT 1:e8fac4061a5b 237 }
NirT 1:e8fac4061a5b 238 else
NirT 1:e8fac4061a5b 239 {
NirT 1:e8fac4061a5b 240 outputEnabled = 0;
NirT 1:e8fac4061a5b 241 }
NirT 1:e8fac4061a5b 242
NirT 1:e8fac4061a5b 243 /* Path Configurations for input */
NirT 1:e8fac4061a5b 244 if (input_device > 0)
NirT 1:e8fac4061a5b 245 {
NirT 1:e8fac4061a5b 246 inputEnabled = 1;
NirT 1:e8fac4061a5b 247 switch (input_device)
NirT 1:e8fac4061a5b 248 {
NirT 1:e8fac4061a5b 249 case INPUT_DEVICE_DIGITAL_MICROPHONE_2 :
NirT 1:e8fac4061a5b 250 /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right)
NirT 1:e8fac4061a5b 251 * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right)
NirT 1:e8fac4061a5b 252 * Enable Left ADC, Enable Right ADC */
NirT 1:e8fac4061a5b 253 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30);
NirT 1:e8fac4061a5b 254
NirT 1:e8fac4061a5b 255 /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
NirT 1:e8fac4061a5b 256 counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
NirT 1:e8fac4061a5b 257
NirT 1:e8fac4061a5b 258 /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
NirT 1:e8fac4061a5b 259 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000);
NirT 1:e8fac4061a5b 260
NirT 1:e8fac4061a5b 261 /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
NirT 1:e8fac4061a5b 262 counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
NirT 1:e8fac4061a5b 263
NirT 1:e8fac4061a5b 264 /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
NirT 1:e8fac4061a5b 265 counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
NirT 1:e8fac4061a5b 266
NirT 1:e8fac4061a5b 267 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */
NirT 1:e8fac4061a5b 268 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E);
NirT 1:e8fac4061a5b 269 break;
NirT 1:e8fac4061a5b 270
NirT 1:e8fac4061a5b 271 case INPUT_DEVICE_INPUT_LINE_1 :
NirT 1:e8fac4061a5b 272 /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
NirT 1:e8fac4061a5b 273 * Enable Left ADC, Enable Right ADC */
NirT 1:e8fac4061a5b 274 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303);
NirT 1:e8fac4061a5b 275
NirT 1:e8fac4061a5b 276 /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
NirT 1:e8fac4061a5b 277 counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
NirT 1:e8fac4061a5b 278
NirT 1:e8fac4061a5b 279 /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */
NirT 1:e8fac4061a5b 280 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
NirT 1:e8fac4061a5b 281
NirT 1:e8fac4061a5b 282 /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */
NirT 1:e8fac4061a5b 283 counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
NirT 1:e8fac4061a5b 284
NirT 1:e8fac4061a5b 285 /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */
NirT 1:e8fac4061a5b 286 counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
NirT 1:e8fac4061a5b 287
NirT 1:e8fac4061a5b 288 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
NirT 1:e8fac4061a5b 289 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
NirT 1:e8fac4061a5b 290 break;
NirT 1:e8fac4061a5b 291
NirT 1:e8fac4061a5b 292 case INPUT_DEVICE_DIGITAL_MICROPHONE_1 :
NirT 1:e8fac4061a5b 293 case INPUT_DEVICE_INPUT_LINE_2 :
NirT 1:e8fac4061a5b 294 default:
NirT 1:e8fac4061a5b 295 /* Actually, no other input devices supported */
NirT 1:e8fac4061a5b 296 counter++;
NirT 1:e8fac4061a5b 297 break;
NirT 1:e8fac4061a5b 298 }
NirT 1:e8fac4061a5b 299 }
NirT 1:e8fac4061a5b 300 else
NirT 1:e8fac4061a5b 301 {
NirT 1:e8fac4061a5b 302 inputEnabled = 0;
NirT 1:e8fac4061a5b 303 }
NirT 1:e8fac4061a5b 304
NirT 1:e8fac4061a5b 305 /* Clock Configurations */
NirT 1:e8fac4061a5b 306 switch (AudioFreq)
NirT 1:e8fac4061a5b 307 {
NirT 1:e8fac4061a5b 308 case AUDIO_FREQUENCY_8K:
NirT 1:e8fac4061a5b 309 /* AIF1 Sample Rate = 8 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 310 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
NirT 1:e8fac4061a5b 311 break;
NirT 1:e8fac4061a5b 312
NirT 1:e8fac4061a5b 313 case AUDIO_FREQUENCY_16K:
NirT 1:e8fac4061a5b 314 /* AIF1 Sample Rate = 16 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 315 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
NirT 1:e8fac4061a5b 316 break;
NirT 1:e8fac4061a5b 317
NirT 1:e8fac4061a5b 318 case AUDIO_FREQUENCY_48K:
NirT 1:e8fac4061a5b 319 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 320 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
NirT 1:e8fac4061a5b 321 break;
NirT 1:e8fac4061a5b 322
NirT 1:e8fac4061a5b 323 case AUDIO_FREQUENCY_96K:
NirT 1:e8fac4061a5b 324 /* AIF1 Sample Rate = 96 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 325 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
NirT 1:e8fac4061a5b 326 break;
NirT 1:e8fac4061a5b 327
NirT 1:e8fac4061a5b 328 case AUDIO_FREQUENCY_11K:
NirT 1:e8fac4061a5b 329 /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 330 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
NirT 1:e8fac4061a5b 331 break;
NirT 1:e8fac4061a5b 332
NirT 1:e8fac4061a5b 333 case AUDIO_FREQUENCY_22K:
NirT 1:e8fac4061a5b 334 /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 335 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
NirT 1:e8fac4061a5b 336 break;
NirT 1:e8fac4061a5b 337
NirT 1:e8fac4061a5b 338 case AUDIO_FREQUENCY_44K:
NirT 1:e8fac4061a5b 339 /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 340 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
NirT 1:e8fac4061a5b 341 break;
NirT 1:e8fac4061a5b 342
NirT 1:e8fac4061a5b 343 default:
NirT 1:e8fac4061a5b 344 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 345 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
NirT 1:e8fac4061a5b 346 break;
NirT 1:e8fac4061a5b 347 }
NirT 1:e8fac4061a5b 348 /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
NirT 1:e8fac4061a5b 349 counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010);
NirT 1:e8fac4061a5b 350
NirT 1:e8fac4061a5b 351 /* slave mode */
NirT 1:e8fac4061a5b 352 counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000);
NirT 1:e8fac4061a5b 353
NirT 1:e8fac4061a5b 354 /* Enable the DSP processing clock for AIF1, Enable the core clock */
NirT 1:e8fac4061a5b 355 counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A);
NirT 1:e8fac4061a5b 356
NirT 1:e8fac4061a5b 357 /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
NirT 1:e8fac4061a5b 358 counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001);
NirT 1:e8fac4061a5b 359
NirT 1:e8fac4061a5b 360 if (output_device > 0) /* Audio output selected */
NirT 1:e8fac4061a5b 361 {
NirT 1:e8fac4061a5b 362 /* Analog Output Configuration */
NirT 1:e8fac4061a5b 363
NirT 1:e8fac4061a5b 364 /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
NirT 1:e8fac4061a5b 365 counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300);
NirT 1:e8fac4061a5b 366
NirT 1:e8fac4061a5b 367 /* Left Speaker Mixer Volume = 0dB */
NirT 1:e8fac4061a5b 368 counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000);
NirT 1:e8fac4061a5b 369
NirT 1:e8fac4061a5b 370 /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/
NirT 1:e8fac4061a5b 371 counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000);
NirT 1:e8fac4061a5b 372
NirT 1:e8fac4061a5b 373 /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
NirT 1:e8fac4061a5b 374 Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */
NirT 1:e8fac4061a5b 375 counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300);
NirT 1:e8fac4061a5b 376
NirT 1:e8fac4061a5b 377 /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
NirT 1:e8fac4061a5b 378 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003);
NirT 1:e8fac4061a5b 379
NirT 1:e8fac4061a5b 380 /* Headphone/Speaker Enable */
NirT 1:e8fac4061a5b 381
NirT 1:e8fac4061a5b 382 /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
NirT 1:e8fac4061a5b 383 counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005);
NirT 1:e8fac4061a5b 384
NirT 1:e8fac4061a5b 385 /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */
NirT 1:e8fac4061a5b 386 /* idem for Speaker */
NirT 1:e8fac4061a5b 387 power_mgnt_reg_1 |= 0x0303 | 0x3003;
NirT 1:e8fac4061a5b 388 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
NirT 1:e8fac4061a5b 389
NirT 1:e8fac4061a5b 390 /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
NirT 1:e8fac4061a5b 391 counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022);
NirT 1:e8fac4061a5b 392
NirT 1:e8fac4061a5b 393 /* Enable Charge Pump */
NirT 1:e8fac4061a5b 394 counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25);
NirT 1:e8fac4061a5b 395
NirT 1:e8fac4061a5b 396 /* Add Delay */
NirT 1:e8fac4061a5b 397 AUDIO_IO_Delay(15);
NirT 1:e8fac4061a5b 398
NirT 1:e8fac4061a5b 399 /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
NirT 1:e8fac4061a5b 400 counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001);
NirT 1:e8fac4061a5b 401
NirT 1:e8fac4061a5b 402 /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
NirT 1:e8fac4061a5b 403 counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001);
NirT 1:e8fac4061a5b 404
NirT 1:e8fac4061a5b 405 /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */
NirT 1:e8fac4061a5b 406 /* idem for SPKOUTL and SPKOUTR */
NirT 1:e8fac4061a5b 407 counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300);
NirT 1:e8fac4061a5b 408
NirT 1:e8fac4061a5b 409 /* Enable DC Servo and trigger start-up mode on left and right channels */
NirT 1:e8fac4061a5b 410 counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033);
NirT 1:e8fac4061a5b 411
NirT 1:e8fac4061a5b 412 /* Add Delay */
NirT 1:e8fac4061a5b 413 AUDIO_IO_Delay(250);
NirT 1:e8fac4061a5b 414
NirT 1:e8fac4061a5b 415 /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */
NirT 1:e8fac4061a5b 416 counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE);
NirT 1:e8fac4061a5b 417
NirT 1:e8fac4061a5b 418 /* Unmutes */
NirT 1:e8fac4061a5b 419
NirT 1:e8fac4061a5b 420 /* Unmute DAC 1 (Left) */
NirT 1:e8fac4061a5b 421 counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0);
NirT 1:e8fac4061a5b 422
NirT 1:e8fac4061a5b 423 /* Unmute DAC 1 (Right) */
NirT 1:e8fac4061a5b 424 counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0);
NirT 1:e8fac4061a5b 425
NirT 1:e8fac4061a5b 426 /* Unmute the AIF1 Timeslot 0 DAC path */
NirT 1:e8fac4061a5b 427 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
NirT 1:e8fac4061a5b 428
NirT 1:e8fac4061a5b 429 /* Unmute DAC 2 (Left) */
NirT 1:e8fac4061a5b 430 counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0);
NirT 1:e8fac4061a5b 431
NirT 1:e8fac4061a5b 432 /* Unmute DAC 2 (Right) */
NirT 1:e8fac4061a5b 433 counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0);
NirT 1:e8fac4061a5b 434
NirT 1:e8fac4061a5b 435 /* Unmute the AIF1 Timeslot 1 DAC2 path */
NirT 1:e8fac4061a5b 436 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
NirT 1:e8fac4061a5b 437
NirT 1:e8fac4061a5b 438 /* Volume Control */
NirT 1:e8fac4061a5b 439 wm8994_SetVolume(DeviceAddr, Volume);
NirT 1:e8fac4061a5b 440 }
NirT 1:e8fac4061a5b 441
NirT 1:e8fac4061a5b 442 if (input_device > 0) /* Audio input selected */
NirT 1:e8fac4061a5b 443 {
NirT 1:e8fac4061a5b 444 if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2))
NirT 1:e8fac4061a5b 445 {
NirT 1:e8fac4061a5b 446 /* Enable Microphone bias 1 generator, Enable VMID */
NirT 1:e8fac4061a5b 447 power_mgnt_reg_1 |= 0x0013;
NirT 1:e8fac4061a5b 448 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
NirT 1:e8fac4061a5b 449
NirT 1:e8fac4061a5b 450 /* ADC oversample enable */
NirT 1:e8fac4061a5b 451 counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
NirT 1:e8fac4061a5b 452
NirT 1:e8fac4061a5b 453 /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
NirT 1:e8fac4061a5b 454 counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800);
NirT 1:e8fac4061a5b 455 }
NirT 1:e8fac4061a5b 456 else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2))
NirT 1:e8fac4061a5b 457 {
NirT 1:e8fac4061a5b 458 /* Enable normal bias generator, Enable VMID */
NirT 1:e8fac4061a5b 459 power_mgnt_reg_1 |= 0x0003;
NirT 1:e8fac4061a5b 460 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
NirT 1:e8fac4061a5b 461
NirT 1:e8fac4061a5b 462 /* Disable mute on IN1L, IN1L Volume = +0dB */
NirT 1:e8fac4061a5b 463 counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B);
NirT 1:e8fac4061a5b 464
NirT 1:e8fac4061a5b 465 /* Disable mute on IN1R, IN1R Volume = +0dB */
NirT 1:e8fac4061a5b 466 counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B);
NirT 1:e8fac4061a5b 467
NirT 1:e8fac4061a5b 468 /* Disable mute on IN1L_TO_MIXINL, Gain = +0dB */
NirT 1:e8fac4061a5b 469 counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0025);
NirT 1:e8fac4061a5b 470
NirT 1:e8fac4061a5b 471 /* Disable mute on IN1R_TO_MIXINL, Gain = +0dB */
NirT 1:e8fac4061a5b 472 counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0025);
NirT 1:e8fac4061a5b 473
NirT 1:e8fac4061a5b 474 /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */
NirT 1:e8fac4061a5b 475 counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011);
NirT 1:e8fac4061a5b 476
NirT 1:e8fac4061a5b 477 /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */
NirT 1:e8fac4061a5b 478 counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
NirT 1:e8fac4061a5b 479 }
NirT 1:e8fac4061a5b 480 /* Volume Control */
NirT 1:e8fac4061a5b 481 wm8994_SetVolume(DeviceAddr, Volume);
NirT 1:e8fac4061a5b 482 }
NirT 1:e8fac4061a5b 483 /* Return communication control value */
NirT 1:e8fac4061a5b 484 return counter;
NirT 1:e8fac4061a5b 485 }
NirT 1:e8fac4061a5b 486
NirT 1:e8fac4061a5b 487 /**
NirT 1:e8fac4061a5b 488 * @brief Deinitializes the audio codec.
NirT 1:e8fac4061a5b 489 * @param None
NirT 1:e8fac4061a5b 490 * @retval None
NirT 1:e8fac4061a5b 491 */
NirT 1:e8fac4061a5b 492 void wm8994_DeInit(void)
NirT 1:e8fac4061a5b 493 {
NirT 1:e8fac4061a5b 494 /* Deinitialize Audio Codec interface */
NirT 1:e8fac4061a5b 495 AUDIO_IO_DeInit();
NirT 1:e8fac4061a5b 496 }
NirT 1:e8fac4061a5b 497
NirT 1:e8fac4061a5b 498 /**
NirT 1:e8fac4061a5b 499 * @brief Get the WM8994 ID.
NirT 1:e8fac4061a5b 500 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 501 * @retval The WM8994 ID
NirT 1:e8fac4061a5b 502 */
NirT 1:e8fac4061a5b 503 uint32_t wm8994_ReadID(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 504 {
NirT 1:e8fac4061a5b 505 /* Initialize the Control interface of the Audio Codec */
NirT 1:e8fac4061a5b 506 AUDIO_IO_Init();
NirT 1:e8fac4061a5b 507
NirT 1:e8fac4061a5b 508 return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR));
NirT 1:e8fac4061a5b 509 }
NirT 1:e8fac4061a5b 510
NirT 1:e8fac4061a5b 511 /**
NirT 1:e8fac4061a5b 512 * @brief Start the audio Codec play feature.
NirT 1:e8fac4061a5b 513 * @note For this codec no Play options are required.
NirT 1:e8fac4061a5b 514 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 515 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 516 */
NirT 1:e8fac4061a5b 517 uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
NirT 1:e8fac4061a5b 518 {
NirT 1:e8fac4061a5b 519 uint32_t counter = 0;
NirT 1:e8fac4061a5b 520
NirT 1:e8fac4061a5b 521 /* Resumes the audio file playing */
NirT 1:e8fac4061a5b 522 /* Unmute the output first */
NirT 1:e8fac4061a5b 523 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
NirT 1:e8fac4061a5b 524
NirT 1:e8fac4061a5b 525 return counter;
NirT 1:e8fac4061a5b 526 }
NirT 1:e8fac4061a5b 527
NirT 1:e8fac4061a5b 528 /**
NirT 1:e8fac4061a5b 529 * @brief Pauses playing on the audio codec.
NirT 1:e8fac4061a5b 530 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 531 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 532 */
NirT 1:e8fac4061a5b 533 uint32_t wm8994_Pause(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 534 {
NirT 1:e8fac4061a5b 535 uint32_t counter = 0;
NirT 1:e8fac4061a5b 536
NirT 1:e8fac4061a5b 537 /* Pause the audio file playing */
NirT 1:e8fac4061a5b 538 /* Mute the output first */
NirT 1:e8fac4061a5b 539 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
NirT 1:e8fac4061a5b 540
NirT 1:e8fac4061a5b 541 /* Put the Codec in Power save mode */
NirT 1:e8fac4061a5b 542 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01);
NirT 1:e8fac4061a5b 543
NirT 1:e8fac4061a5b 544 return counter;
NirT 1:e8fac4061a5b 545 }
NirT 1:e8fac4061a5b 546
NirT 1:e8fac4061a5b 547 /**
NirT 1:e8fac4061a5b 548 * @brief Resumes playing on the audio codec.
NirT 1:e8fac4061a5b 549 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 550 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 551 */
NirT 1:e8fac4061a5b 552 uint32_t wm8994_Resume(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 553 {
NirT 1:e8fac4061a5b 554 uint32_t counter = 0;
NirT 1:e8fac4061a5b 555
NirT 1:e8fac4061a5b 556 /* Resumes the audio file playing */
NirT 1:e8fac4061a5b 557 /* Unmute the output first */
NirT 1:e8fac4061a5b 558 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
NirT 1:e8fac4061a5b 559
NirT 1:e8fac4061a5b 560 return counter;
NirT 1:e8fac4061a5b 561 }
NirT 1:e8fac4061a5b 562
NirT 1:e8fac4061a5b 563 /**
NirT 1:e8fac4061a5b 564 * @brief Stops audio Codec playing. It powers down the codec.
NirT 1:e8fac4061a5b 565 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 566 * @param CodecPdwnMode: selects the power down mode.
NirT 1:e8fac4061a5b 567 * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this
NirT 1:e8fac4061a5b 568 * mode the codec keeps the previous initialization
NirT 1:e8fac4061a5b 569 * (no need to re-Initialize the codec registers).
NirT 1:e8fac4061a5b 570 * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
NirT 1:e8fac4061a5b 571 * mode, the codec is set to default configuration
NirT 1:e8fac4061a5b 572 * (user should re-Initialize the codec in order to
NirT 1:e8fac4061a5b 573 * play again the audio stream).
NirT 1:e8fac4061a5b 574 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 575 */
NirT 1:e8fac4061a5b 576 uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
NirT 1:e8fac4061a5b 577 {
NirT 1:e8fac4061a5b 578 uint32_t counter = 0;
NirT 1:e8fac4061a5b 579
NirT 1:e8fac4061a5b 580 if (outputEnabled != 0)
NirT 1:e8fac4061a5b 581 {
NirT 1:e8fac4061a5b 582 /* Mute the output first */
NirT 1:e8fac4061a5b 583 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
NirT 1:e8fac4061a5b 584
NirT 1:e8fac4061a5b 585 if (CodecPdwnMode == CODEC_PDWN_SW)
NirT 1:e8fac4061a5b 586 {
NirT 1:e8fac4061a5b 587 /* Only output mute required*/
NirT 1:e8fac4061a5b 588 }
NirT 1:e8fac4061a5b 589 else /* CODEC_PDWN_HW */
NirT 1:e8fac4061a5b 590 {
NirT 1:e8fac4061a5b 591 /* Mute the AIF1 Timeslot 0 DAC1 path */
NirT 1:e8fac4061a5b 592 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
NirT 1:e8fac4061a5b 593
NirT 1:e8fac4061a5b 594 /* Mute the AIF1 Timeslot 1 DAC2 path */
NirT 1:e8fac4061a5b 595 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
NirT 1:e8fac4061a5b 596
NirT 1:e8fac4061a5b 597 /* Disable DAC1L_TO_HPOUT1L */
NirT 1:e8fac4061a5b 598 counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000);
NirT 1:e8fac4061a5b 599
NirT 1:e8fac4061a5b 600 /* Disable DAC1R_TO_HPOUT1R */
NirT 1:e8fac4061a5b 601 counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000);
NirT 1:e8fac4061a5b 602
NirT 1:e8fac4061a5b 603 /* Disable DAC1 and DAC2 */
NirT 1:e8fac4061a5b 604 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000);
NirT 1:e8fac4061a5b 605
NirT 1:e8fac4061a5b 606 /* Reset Codec by writing in 0x0000 address register */
NirT 1:e8fac4061a5b 607 counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
NirT 1:e8fac4061a5b 608
NirT 1:e8fac4061a5b 609 outputEnabled = 0;
NirT 1:e8fac4061a5b 610 }
NirT 1:e8fac4061a5b 611 }
NirT 1:e8fac4061a5b 612 return counter;
NirT 1:e8fac4061a5b 613 }
NirT 1:e8fac4061a5b 614
NirT 1:e8fac4061a5b 615 /**
NirT 1:e8fac4061a5b 616 * @brief Sets higher or lower the codec volume level.
NirT 1:e8fac4061a5b 617 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 618 * @param Volume: a byte value from 0 to 255 (refer to codec registers
NirT 1:e8fac4061a5b 619 * description for more details).
NirT 1:e8fac4061a5b 620 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 621 */
NirT 1:e8fac4061a5b 622 uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
NirT 1:e8fac4061a5b 623 {
NirT 1:e8fac4061a5b 624 uint32_t counter = 0;
NirT 1:e8fac4061a5b 625 uint8_t convertedvol = VOLUME_CONVERT(Volume);
NirT 1:e8fac4061a5b 626
NirT 1:e8fac4061a5b 627 /* Output volume */
NirT 1:e8fac4061a5b 628 if (outputEnabled != 0)
NirT 1:e8fac4061a5b 629 {
NirT 1:e8fac4061a5b 630 if(convertedvol > 0x3E)
NirT 1:e8fac4061a5b 631 {
NirT 1:e8fac4061a5b 632 /* Unmute audio codec */
NirT 1:e8fac4061a5b 633 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
NirT 1:e8fac4061a5b 634
NirT 1:e8fac4061a5b 635 /* Left Headphone Volume */
NirT 1:e8fac4061a5b 636 counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140);
NirT 1:e8fac4061a5b 637
NirT 1:e8fac4061a5b 638 /* Right Headphone Volume */
NirT 1:e8fac4061a5b 639 counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140);
NirT 1:e8fac4061a5b 640
NirT 1:e8fac4061a5b 641 /* Left Speaker Volume */
NirT 1:e8fac4061a5b 642 counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140);
NirT 1:e8fac4061a5b 643
NirT 1:e8fac4061a5b 644 /* Right Speaker Volume */
NirT 1:e8fac4061a5b 645 counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140);
NirT 1:e8fac4061a5b 646 }
NirT 1:e8fac4061a5b 647 else if (Volume == 0)
NirT 1:e8fac4061a5b 648 {
NirT 1:e8fac4061a5b 649 /* Mute audio codec */
NirT 1:e8fac4061a5b 650 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
NirT 1:e8fac4061a5b 651 }
NirT 1:e8fac4061a5b 652 else
NirT 1:e8fac4061a5b 653 {
NirT 1:e8fac4061a5b 654 /* Unmute audio codec */
NirT 1:e8fac4061a5b 655 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
NirT 1:e8fac4061a5b 656
NirT 1:e8fac4061a5b 657 /* Left Headphone Volume */
NirT 1:e8fac4061a5b 658 counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140);
NirT 1:e8fac4061a5b 659
NirT 1:e8fac4061a5b 660 /* Right Headphone Volume */
NirT 1:e8fac4061a5b 661 counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140);
NirT 1:e8fac4061a5b 662
NirT 1:e8fac4061a5b 663 /* Left Speaker Volume */
NirT 1:e8fac4061a5b 664 counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140);
NirT 1:e8fac4061a5b 665
NirT 1:e8fac4061a5b 666 /* Right Speaker Volume */
NirT 1:e8fac4061a5b 667 counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140);
NirT 1:e8fac4061a5b 668 }
NirT 1:e8fac4061a5b 669 }
NirT 1:e8fac4061a5b 670
NirT 1:e8fac4061a5b 671 /* Input volume */
NirT 1:e8fac4061a5b 672 if (inputEnabled != 0)
NirT 1:e8fac4061a5b 673 {
NirT 1:e8fac4061a5b 674 convertedvol = VOLUME_IN_CONVERT(Volume);
NirT 1:e8fac4061a5b 675
NirT 1:e8fac4061a5b 676 /* Left AIF1 ADC1 volume */
NirT 1:e8fac4061a5b 677 counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100);
NirT 1:e8fac4061a5b 678
NirT 1:e8fac4061a5b 679 /* Right AIF1 ADC1 volume */
NirT 1:e8fac4061a5b 680 counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100);
NirT 1:e8fac4061a5b 681
NirT 1:e8fac4061a5b 682 /* Left AIF1 ADC2 volume */
NirT 1:e8fac4061a5b 683 counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100);
NirT 1:e8fac4061a5b 684
NirT 1:e8fac4061a5b 685 /* Right AIF1 ADC2 volume */
NirT 1:e8fac4061a5b 686 counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100);
NirT 1:e8fac4061a5b 687 }
NirT 1:e8fac4061a5b 688 return counter;
NirT 1:e8fac4061a5b 689 }
NirT 1:e8fac4061a5b 690
NirT 1:e8fac4061a5b 691 /**
NirT 1:e8fac4061a5b 692 * @brief Enables or disables the mute feature on the audio codec.
NirT 1:e8fac4061a5b 693 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 694 * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
NirT 1:e8fac4061a5b 695 * mute mode.
NirT 1:e8fac4061a5b 696 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 697 */
NirT 1:e8fac4061a5b 698 uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
NirT 1:e8fac4061a5b 699 {
NirT 1:e8fac4061a5b 700 uint32_t counter = 0;
NirT 1:e8fac4061a5b 701
NirT 1:e8fac4061a5b 702 if (outputEnabled != 0)
NirT 1:e8fac4061a5b 703 {
NirT 1:e8fac4061a5b 704 /* Set the Mute mode */
NirT 1:e8fac4061a5b 705 if(Cmd == AUDIO_MUTE_ON)
NirT 1:e8fac4061a5b 706 {
NirT 1:e8fac4061a5b 707 /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */
NirT 1:e8fac4061a5b 708 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
NirT 1:e8fac4061a5b 709
NirT 1:e8fac4061a5b 710 /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */
NirT 1:e8fac4061a5b 711 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
NirT 1:e8fac4061a5b 712 }
NirT 1:e8fac4061a5b 713 else /* AUDIO_MUTE_OFF Disable the Mute */
NirT 1:e8fac4061a5b 714 {
NirT 1:e8fac4061a5b 715 /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */
NirT 1:e8fac4061a5b 716 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
NirT 1:e8fac4061a5b 717
NirT 1:e8fac4061a5b 718 /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
NirT 1:e8fac4061a5b 719 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
NirT 1:e8fac4061a5b 720 }
NirT 1:e8fac4061a5b 721 }
NirT 1:e8fac4061a5b 722 return counter;
NirT 1:e8fac4061a5b 723 }
NirT 1:e8fac4061a5b 724
NirT 1:e8fac4061a5b 725 /**
NirT 1:e8fac4061a5b 726 * @brief Switch dynamically (while audio file is played) the output target
NirT 1:e8fac4061a5b 727 * (speaker or headphone).
NirT 1:e8fac4061a5b 728 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 729 * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
NirT 1:e8fac4061a5b 730 * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO
NirT 1:e8fac4061a5b 731 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 732 */
NirT 1:e8fac4061a5b 733 uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
NirT 1:e8fac4061a5b 734 {
NirT 1:e8fac4061a5b 735 uint32_t counter = 0;
NirT 1:e8fac4061a5b 736
NirT 1:e8fac4061a5b 737 switch (Output)
NirT 1:e8fac4061a5b 738 {
NirT 1:e8fac4061a5b 739 case OUTPUT_DEVICE_SPEAKER:
NirT 1:e8fac4061a5b 740 /* Enable DAC1 (Left), Enable DAC1 (Right),
NirT 1:e8fac4061a5b 741 Disable DAC2 (Left), Disable DAC2 (Right)*/
NirT 1:e8fac4061a5b 742 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
NirT 1:e8fac4061a5b 743
NirT 1:e8fac4061a5b 744 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 745 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
NirT 1:e8fac4061a5b 746
NirT 1:e8fac4061a5b 747 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 748 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
NirT 1:e8fac4061a5b 749
NirT 1:e8fac4061a5b 750 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 751 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
NirT 1:e8fac4061a5b 752
NirT 1:e8fac4061a5b 753 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 754 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
NirT 1:e8fac4061a5b 755 break;
NirT 1:e8fac4061a5b 756
NirT 1:e8fac4061a5b 757 case OUTPUT_DEVICE_HEADPHONE:
NirT 1:e8fac4061a5b 758 /* Disable DAC1 (Left), Disable DAC1 (Right),
NirT 1:e8fac4061a5b 759 Enable DAC2 (Left), Enable DAC2 (Right)*/
NirT 1:e8fac4061a5b 760 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
NirT 1:e8fac4061a5b 761
NirT 1:e8fac4061a5b 762 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 763 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
NirT 1:e8fac4061a5b 764
NirT 1:e8fac4061a5b 765 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 766 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
NirT 1:e8fac4061a5b 767
NirT 1:e8fac4061a5b 768 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 769 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
NirT 1:e8fac4061a5b 770
NirT 1:e8fac4061a5b 771 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 772 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
NirT 1:e8fac4061a5b 773 break;
NirT 1:e8fac4061a5b 774
NirT 1:e8fac4061a5b 775 case OUTPUT_DEVICE_BOTH:
NirT 1:e8fac4061a5b 776 /* Enable DAC1 (Left), Enable DAC1 (Right),
NirT 1:e8fac4061a5b 777 also Enable DAC2 (Left), Enable DAC2 (Right)*/
NirT 1:e8fac4061a5b 778 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
NirT 1:e8fac4061a5b 779
NirT 1:e8fac4061a5b 780 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 781 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
NirT 1:e8fac4061a5b 782
NirT 1:e8fac4061a5b 783 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 784 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
NirT 1:e8fac4061a5b 785
NirT 1:e8fac4061a5b 786 /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 787 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
NirT 1:e8fac4061a5b 788
NirT 1:e8fac4061a5b 789 /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 790 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
NirT 1:e8fac4061a5b 791 break;
NirT 1:e8fac4061a5b 792
NirT 1:e8fac4061a5b 793 default:
NirT 1:e8fac4061a5b 794 /* Disable DAC1 (Left), Disable DAC1 (Right),
NirT 1:e8fac4061a5b 795 Enable DAC2 (Left), Enable DAC2 (Right)*/
NirT 1:e8fac4061a5b 796 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
NirT 1:e8fac4061a5b 797
NirT 1:e8fac4061a5b 798 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
NirT 1:e8fac4061a5b 799 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
NirT 1:e8fac4061a5b 800
NirT 1:e8fac4061a5b 801 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
NirT 1:e8fac4061a5b 802 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
NirT 1:e8fac4061a5b 803
NirT 1:e8fac4061a5b 804 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
NirT 1:e8fac4061a5b 805 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
NirT 1:e8fac4061a5b 806
NirT 1:e8fac4061a5b 807 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
NirT 1:e8fac4061a5b 808 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
NirT 1:e8fac4061a5b 809 break;
NirT 1:e8fac4061a5b 810 }
NirT 1:e8fac4061a5b 811 return counter;
NirT 1:e8fac4061a5b 812 }
NirT 1:e8fac4061a5b 813
NirT 1:e8fac4061a5b 814 /**
NirT 1:e8fac4061a5b 815 * @brief Sets new frequency.
NirT 1:e8fac4061a5b 816 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 817 * @param AudioFreq: Audio frequency used to play the audio stream.
NirT 1:e8fac4061a5b 818 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 819 */
NirT 1:e8fac4061a5b 820 uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
NirT 1:e8fac4061a5b 821 {
NirT 1:e8fac4061a5b 822 uint32_t counter = 0;
NirT 1:e8fac4061a5b 823
NirT 1:e8fac4061a5b 824 /* Clock Configurations */
NirT 1:e8fac4061a5b 825 switch (AudioFreq)
NirT 1:e8fac4061a5b 826 {
NirT 1:e8fac4061a5b 827 case AUDIO_FREQUENCY_8K:
NirT 1:e8fac4061a5b 828 /* AIF1 Sample Rate = 8 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 829 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
NirT 1:e8fac4061a5b 830 break;
NirT 1:e8fac4061a5b 831
NirT 1:e8fac4061a5b 832 case AUDIO_FREQUENCY_16K:
NirT 1:e8fac4061a5b 833 /* AIF1 Sample Rate = 16 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 834 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
NirT 1:e8fac4061a5b 835 break;
NirT 1:e8fac4061a5b 836
NirT 1:e8fac4061a5b 837 case AUDIO_FREQUENCY_48K:
NirT 1:e8fac4061a5b 838 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 839 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
NirT 1:e8fac4061a5b 840 break;
NirT 1:e8fac4061a5b 841
NirT 1:e8fac4061a5b 842 case AUDIO_FREQUENCY_96K:
NirT 1:e8fac4061a5b 843 /* AIF1 Sample Rate = 96 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 844 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
NirT 1:e8fac4061a5b 845 break;
NirT 1:e8fac4061a5b 846
NirT 1:e8fac4061a5b 847 case AUDIO_FREQUENCY_11K:
NirT 1:e8fac4061a5b 848 /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 849 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
NirT 1:e8fac4061a5b 850 break;
NirT 1:e8fac4061a5b 851
NirT 1:e8fac4061a5b 852 case AUDIO_FREQUENCY_22K:
NirT 1:e8fac4061a5b 853 /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 854 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
NirT 1:e8fac4061a5b 855 break;
NirT 1:e8fac4061a5b 856
NirT 1:e8fac4061a5b 857 case AUDIO_FREQUENCY_44K:
NirT 1:e8fac4061a5b 858 /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 859 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
NirT 1:e8fac4061a5b 860 break;
NirT 1:e8fac4061a5b 861
NirT 1:e8fac4061a5b 862 default:
NirT 1:e8fac4061a5b 863 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
NirT 1:e8fac4061a5b 864 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
NirT 1:e8fac4061a5b 865 break;
NirT 1:e8fac4061a5b 866 }
NirT 1:e8fac4061a5b 867 return counter;
NirT 1:e8fac4061a5b 868 }
NirT 1:e8fac4061a5b 869
NirT 1:e8fac4061a5b 870 /**
NirT 1:e8fac4061a5b 871 * @brief Resets wm8994 registers.
NirT 1:e8fac4061a5b 872 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 873 * @retval 0 if correct communication, else wrong communication
NirT 1:e8fac4061a5b 874 */
NirT 1:e8fac4061a5b 875 uint32_t wm8994_Reset(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 876 {
NirT 1:e8fac4061a5b 877 uint32_t counter = 0;
NirT 1:e8fac4061a5b 878
NirT 1:e8fac4061a5b 879 /* Reset Codec by writing in 0x0000 address register */
NirT 1:e8fac4061a5b 880 counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
NirT 1:e8fac4061a5b 881 outputEnabled = 0;
NirT 1:e8fac4061a5b 882 inputEnabled=0;
NirT 1:e8fac4061a5b 883
NirT 1:e8fac4061a5b 884 return counter;
NirT 1:e8fac4061a5b 885 }
NirT 1:e8fac4061a5b 886
NirT 1:e8fac4061a5b 887 /**
NirT 1:e8fac4061a5b 888 * @brief Writes/Read a single data.
NirT 1:e8fac4061a5b 889 * @param Addr: I2C address
NirT 1:e8fac4061a5b 890 * @param Reg: Reg address
NirT 1:e8fac4061a5b 891 * @param Value: Data to be written
NirT 1:e8fac4061a5b 892 * @retval None
NirT 1:e8fac4061a5b 893 */
NirT 1:e8fac4061a5b 894 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)
NirT 1:e8fac4061a5b 895 {
NirT 1:e8fac4061a5b 896 uint32_t result = 0;
NirT 1:e8fac4061a5b 897
NirT 1:e8fac4061a5b 898 AUDIO_IO_Write(Addr, Reg, Value);
NirT 1:e8fac4061a5b 899
NirT 1:e8fac4061a5b 900 #ifdef VERIFY_WRITTENDATA
NirT 1:e8fac4061a5b 901 /* Verify that the data has been correctly written */
NirT 1:e8fac4061a5b 902 result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
NirT 1:e8fac4061a5b 903 #endif /* VERIFY_WRITTENDATA */
NirT 1:e8fac4061a5b 904
NirT 1:e8fac4061a5b 905 return result;
NirT 1:e8fac4061a5b 906 }
NirT 1:e8fac4061a5b 907
NirT 1:e8fac4061a5b 908 /**
NirT 1:e8fac4061a5b 909 * @}
NirT 1:e8fac4061a5b 910 */
NirT 1:e8fac4061a5b 911
NirT 1:e8fac4061a5b 912 /**
NirT 1:e8fac4061a5b 913 * @}
NirT 1:e8fac4061a5b 914 */
NirT 1:e8fac4061a5b 915
NirT 1:e8fac4061a5b 916 /**
NirT 1:e8fac4061a5b 917 * @}
NirT 1:e8fac4061a5b 918 */
NirT 1:e8fac4061a5b 919
NirT 1:e8fac4061a5b 920 /**
NirT 1:e8fac4061a5b 921 * @}
NirT 1:e8fac4061a5b 922 */
NirT 1:e8fac4061a5b 923
NirT 1:e8fac4061a5b 924 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/