Nirvana Jay / BSP_DISCO_F746NG_patch

patch for F746 demo

Dependents:   F7DISCO_Demo

Fork of BSP_DISCO_F746NG by ST

Components/n25q128a/n25q128a.h@1:e8fac4061a5b, 2015-11-02 (annotated)

Committer:
NirT
Date:
Mon Nov 02 23:35:17 2015 +0000
Revision:
1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.

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NirT 1:e8fac4061a5b 1 /**
NirT 1:e8fac4061a5b 2 ******************************************************************************
NirT 1:e8fac4061a5b 3 * @file n25q128a.h
NirT 1:e8fac4061a5b 4 * @author MCD Application Team
NirT 1:e8fac4061a5b 5 * @version V1.0.0
NirT 1:e8fac4061a5b 6 * @date 29-May-2015
NirT 1:e8fac4061a5b 7 * @brief This file contains all the description of the N25Q128A QSPI memory.
NirT 1:e8fac4061a5b 8 ******************************************************************************
NirT 1:e8fac4061a5b 9 * @attention
NirT 1:e8fac4061a5b 10 *
NirT 1:e8fac4061a5b 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
NirT 1:e8fac4061a5b 12 *
NirT 1:e8fac4061a5b 13 * Redistribution and use in source and binary forms, with or without modification,
NirT 1:e8fac4061a5b 14 * are permitted provided that the following conditions are met:
NirT 1:e8fac4061a5b 15 * 1. Redistributions of source code must retain the above copyright notice,
NirT 1:e8fac4061a5b 16 * this list of conditions and the following disclaimer.
NirT 1:e8fac4061a5b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NirT 1:e8fac4061a5b 18 * this list of conditions and the following disclaimer in the documentation
NirT 1:e8fac4061a5b 19 * and/or other materials provided with the distribution.
NirT 1:e8fac4061a5b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NirT 1:e8fac4061a5b 21 * may be used to endorse or promote products derived from this software
NirT 1:e8fac4061a5b 22 * without specific prior written permission.
NirT 1:e8fac4061a5b 23 *
NirT 1:e8fac4061a5b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NirT 1:e8fac4061a5b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NirT 1:e8fac4061a5b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NirT 1:e8fac4061a5b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NirT 1:e8fac4061a5b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NirT 1:e8fac4061a5b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NirT 1:e8fac4061a5b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NirT 1:e8fac4061a5b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NirT 1:e8fac4061a5b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NirT 1:e8fac4061a5b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NirT 1:e8fac4061a5b 34 *
NirT 1:e8fac4061a5b 35 ******************************************************************************
NirT 1:e8fac4061a5b 36 */
NirT 1:e8fac4061a5b 37
NirT 1:e8fac4061a5b 38 /* Define to prevent recursive inclusion -------------------------------------*/
NirT 1:e8fac4061a5b 39 #ifndef __N25Q128A_H
NirT 1:e8fac4061a5b 40 #define __N25Q128A_H
NirT 1:e8fac4061a5b 41
NirT 1:e8fac4061a5b 42 #ifdef __cplusplus
NirT 1:e8fac4061a5b 43 extern "C" {
NirT 1:e8fac4061a5b 44 #endif
NirT 1:e8fac4061a5b 45
NirT 1:e8fac4061a5b 46 /* Includes ------------------------------------------------------------------*/
NirT 1:e8fac4061a5b 47
NirT 1:e8fac4061a5b 48 /** @addtogroup BSP
NirT 1:e8fac4061a5b 49 * @{
NirT 1:e8fac4061a5b 50 */
NirT 1:e8fac4061a5b 51
NirT 1:e8fac4061a5b 52 /** @addtogroup Components
NirT 1:e8fac4061a5b 53 * @{
NirT 1:e8fac4061a5b 54 */
NirT 1:e8fac4061a5b 55
NirT 1:e8fac4061a5b 56 /** @addtogroup n25q128a
NirT 1:e8fac4061a5b 57 * @{
NirT 1:e8fac4061a5b 58 */
NirT 1:e8fac4061a5b 59
NirT 1:e8fac4061a5b 60 /** @defgroup N25Q128A_Exported_Types
NirT 1:e8fac4061a5b 61 * @{
NirT 1:e8fac4061a5b 62 */
NirT 1:e8fac4061a5b 63
NirT 1:e8fac4061a5b 64 /**
NirT 1:e8fac4061a5b 65 * @}
NirT 1:e8fac4061a5b 66 */
NirT 1:e8fac4061a5b 67
NirT 1:e8fac4061a5b 68 /** @defgroup N25Q128A_Exported_Constants
NirT 1:e8fac4061a5b 69 * @{
NirT 1:e8fac4061a5b 70 */
NirT 1:e8fac4061a5b 71
NirT 1:e8fac4061a5b 72 /**
NirT 1:e8fac4061a5b 73 * @brief N25Q128A Configuration
NirT 1:e8fac4061a5b 74 */
NirT 1:e8fac4061a5b 75 #define N25Q128A_FLASH_SIZE 0x1000000 /* 128 MBits => 16MBytes */
NirT 1:e8fac4061a5b 76 #define N25Q128A_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */
NirT 1:e8fac4061a5b 77 #define N25Q128A_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */
NirT 1:e8fac4061a5b 78 #define N25Q128A_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */
NirT 1:e8fac4061a5b 79
NirT 1:e8fac4061a5b 80 #define N25Q128A_DUMMY_CYCLES_READ 8
NirT 1:e8fac4061a5b 81 #define N25Q128A_DUMMY_CYCLES_READ_QUAD 10
NirT 1:e8fac4061a5b 82
NirT 1:e8fac4061a5b 83 #define N25Q128A_BULK_ERASE_MAX_TIME 250000
NirT 1:e8fac4061a5b 84 #define N25Q128A_SECTOR_ERASE_MAX_TIME 3000
NirT 1:e8fac4061a5b 85 #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME 800
NirT 1:e8fac4061a5b 86
NirT 1:e8fac4061a5b 87 /**
NirT 1:e8fac4061a5b 88 * @brief N25Q128A Commands
NirT 1:e8fac4061a5b 89 */
NirT 1:e8fac4061a5b 90 /* Reset Operations */
NirT 1:e8fac4061a5b 91 #define RESET_ENABLE_CMD 0x66
NirT 1:e8fac4061a5b 92 #define RESET_MEMORY_CMD 0x99
NirT 1:e8fac4061a5b 93
NirT 1:e8fac4061a5b 94 /* Identification Operations */
NirT 1:e8fac4061a5b 95 #define READ_ID_CMD 0x9E
NirT 1:e8fac4061a5b 96 #define READ_ID_CMD2 0x9F
NirT 1:e8fac4061a5b 97 #define MULTIPLE_IO_READ_ID_CMD 0xAF
NirT 1:e8fac4061a5b 98 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
NirT 1:e8fac4061a5b 99
NirT 1:e8fac4061a5b 100 /* Read Operations */
NirT 1:e8fac4061a5b 101 #define READ_CMD 0x03
NirT 1:e8fac4061a5b 102 #define FAST_READ_CMD 0x0B
NirT 1:e8fac4061a5b 103 #define DUAL_OUT_FAST_READ_CMD 0x3B
NirT 1:e8fac4061a5b 104 #define DUAL_INOUT_FAST_READ_CMD 0xBB
NirT 1:e8fac4061a5b 105 #define QUAD_OUT_FAST_READ_CMD 0x6B
NirT 1:e8fac4061a5b 106 #define QUAD_INOUT_FAST_READ_CMD 0xEB
NirT 1:e8fac4061a5b 107
NirT 1:e8fac4061a5b 108 /* Write Operations */
NirT 1:e8fac4061a5b 109 #define WRITE_ENABLE_CMD 0x06
NirT 1:e8fac4061a5b 110 #define WRITE_DISABLE_CMD 0x04
NirT 1:e8fac4061a5b 111
NirT 1:e8fac4061a5b 112 /* Register Operations */
NirT 1:e8fac4061a5b 113 #define READ_STATUS_REG_CMD 0x05
NirT 1:e8fac4061a5b 114 #define WRITE_STATUS_REG_CMD 0x01
NirT 1:e8fac4061a5b 115
NirT 1:e8fac4061a5b 116 #define READ_LOCK_REG_CMD 0xE8
NirT 1:e8fac4061a5b 117 #define WRITE_LOCK_REG_CMD 0xE5
NirT 1:e8fac4061a5b 118
NirT 1:e8fac4061a5b 119 #define READ_FLAG_STATUS_REG_CMD 0x70
NirT 1:e8fac4061a5b 120 #define CLEAR_FLAG_STATUS_REG_CMD 0x50
NirT 1:e8fac4061a5b 121
NirT 1:e8fac4061a5b 122 #define READ_NONVOL_CFG_REG_CMD 0xB5
NirT 1:e8fac4061a5b 123 #define WRITE_NONVOL_CFG_REG_CMD 0xB1
NirT 1:e8fac4061a5b 124
NirT 1:e8fac4061a5b 125 #define READ_VOL_CFG_REG_CMD 0x85
NirT 1:e8fac4061a5b 126 #define WRITE_VOL_CFG_REG_CMD 0x81
NirT 1:e8fac4061a5b 127
NirT 1:e8fac4061a5b 128 #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65
NirT 1:e8fac4061a5b 129 #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61
NirT 1:e8fac4061a5b 130
NirT 1:e8fac4061a5b 131 /* Program Operations */
NirT 1:e8fac4061a5b 132 #define PAGE_PROG_CMD 0x02
NirT 1:e8fac4061a5b 133 #define DUAL_IN_FAST_PROG_CMD 0xA2
NirT 1:e8fac4061a5b 134 #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2
NirT 1:e8fac4061a5b 135 #define QUAD_IN_FAST_PROG_CMD 0x32
NirT 1:e8fac4061a5b 136 #define EXT_QUAD_IN_FAST_PROG_CMD 0x12
NirT 1:e8fac4061a5b 137
NirT 1:e8fac4061a5b 138 /* Erase Operations */
NirT 1:e8fac4061a5b 139 #define SUBSECTOR_ERASE_CMD 0x20
NirT 1:e8fac4061a5b 140 #define SECTOR_ERASE_CMD 0xD8
NirT 1:e8fac4061a5b 141 #define BULK_ERASE_CMD 0xC7
NirT 1:e8fac4061a5b 142
NirT 1:e8fac4061a5b 143 #define PROG_ERASE_RESUME_CMD 0x7A
NirT 1:e8fac4061a5b 144 #define PROG_ERASE_SUSPEND_CMD 0x75
NirT 1:e8fac4061a5b 145
NirT 1:e8fac4061a5b 146 /* One-Time Programmable Operations */
NirT 1:e8fac4061a5b 147 #define READ_OTP_ARRAY_CMD 0x4B
NirT 1:e8fac4061a5b 148 #define PROG_OTP_ARRAY_CMD 0x42
NirT 1:e8fac4061a5b 149
NirT 1:e8fac4061a5b 150 /**
NirT 1:e8fac4061a5b 151 * @brief N25Q128A Registers
NirT 1:e8fac4061a5b 152 */
NirT 1:e8fac4061a5b 153 /* Status Register */
NirT 1:e8fac4061a5b 154 #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */
NirT 1:e8fac4061a5b 155 #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */
NirT 1:e8fac4061a5b 156 #define N25Q128A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */
NirT 1:e8fac4061a5b 157 #define N25Q128A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
NirT 1:e8fac4061a5b 158 #define N25Q128A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */
NirT 1:e8fac4061a5b 159
NirT 1:e8fac4061a5b 160 /* Nonvolatile Configuration Register */
NirT 1:e8fac4061a5b 161 #define N25Q128A_NVCR_LOCK ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */
NirT 1:e8fac4061a5b 162 #define N25Q128A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */
NirT 1:e8fac4061a5b 163 #define N25Q128A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */
NirT 1:e8fac4061a5b 164 #define N25Q128A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */
NirT 1:e8fac4061a5b 165 #define N25Q128A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */
NirT 1:e8fac4061a5b 166 #define N25Q128A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
NirT 1:e8fac4061a5b 167 #define N25Q128A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
NirT 1:e8fac4061a5b 168
NirT 1:e8fac4061a5b 169 /* Volatile Configuration Register */
NirT 1:e8fac4061a5b 170 #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */
NirT 1:e8fac4061a5b 171 #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */
NirT 1:e8fac4061a5b 172 #define N25Q128A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */
NirT 1:e8fac4061a5b 173
NirT 1:e8fac4061a5b 174 /* Enhanced Volatile Configuration Register */
NirT 1:e8fac4061a5b 175 #define N25Q128A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */
NirT 1:e8fac4061a5b 176 #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */
NirT 1:e8fac4061a5b 177 #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */
NirT 1:e8fac4061a5b 178 #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */
NirT 1:e8fac4061a5b 179 #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */
NirT 1:e8fac4061a5b 180
NirT 1:e8fac4061a5b 181 /* Flag Status Register */
NirT 1:e8fac4061a5b 182 #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */
NirT 1:e8fac4061a5b 183 #define N25Q128A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */
NirT 1:e8fac4061a5b 184 #define N25Q128A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */
NirT 1:e8fac4061a5b 185 #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */
NirT 1:e8fac4061a5b 186 #define N25Q128A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */
NirT 1:e8fac4061a5b 187 #define N25Q128A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */
NirT 1:e8fac4061a5b 188 #define N25Q128A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */
NirT 1:e8fac4061a5b 189
NirT 1:e8fac4061a5b 190 /**
NirT 1:e8fac4061a5b 191 * @}
NirT 1:e8fac4061a5b 192 */
NirT 1:e8fac4061a5b 193
NirT 1:e8fac4061a5b 194 /** @defgroup N25Q128A_Exported_Functions
NirT 1:e8fac4061a5b 195 * @{
NirT 1:e8fac4061a5b 196 */
NirT 1:e8fac4061a5b 197 /**
NirT 1:e8fac4061a5b 198 * @}
NirT 1:e8fac4061a5b 199 */
NirT 1:e8fac4061a5b 200
NirT 1:e8fac4061a5b 201 /**
NirT 1:e8fac4061a5b 202 * @}
NirT 1:e8fac4061a5b 203 */
NirT 1:e8fac4061a5b 204
NirT 1:e8fac4061a5b 205 /**
NirT 1:e8fac4061a5b 206 * @}
NirT 1:e8fac4061a5b 207 */
NirT 1:e8fac4061a5b 208
NirT 1:e8fac4061a5b 209 /**
NirT 1:e8fac4061a5b 210 * @}
NirT 1:e8fac4061a5b 211 */
NirT 1:e8fac4061a5b 212
NirT 1:e8fac4061a5b 213 #ifdef __cplusplus
NirT 1:e8fac4061a5b 214 }
NirT 1:e8fac4061a5b 215 #endif
NirT 1:e8fac4061a5b 216
NirT 1:e8fac4061a5b 217 #endif /* __N25Q128A_H */
NirT 1:e8fac4061a5b 218
NirT 1:e8fac4061a5b 219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/