Nirvana Jay / BSP_DISCO_F746NG_patch

patch for F746 demo

Dependents:   F7DISCO_Demo

Fork of BSP_DISCO_F746NG by ST

Components/Common/io.h@1:e8fac4061a5b, 2015-11-02 (annotated)

Committer:
NirT
Date:
Mon Nov 02 23:35:17 2015 +0000
Revision:
1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NirT 1:e8fac4061a5b 1 /**
NirT 1:e8fac4061a5b 2 ******************************************************************************
NirT 1:e8fac4061a5b 3 * @file io.h
NirT 1:e8fac4061a5b 4 * @author MCD Application Team
NirT 1:e8fac4061a5b 5 * @version V4.0.1
NirT 1:e8fac4061a5b 6 * @date 21-July-2015
NirT 1:e8fac4061a5b 7 * @brief This file contains all the functions prototypes for the IO driver.
NirT 1:e8fac4061a5b 8 ******************************************************************************
NirT 1:e8fac4061a5b 9 * @attention
NirT 1:e8fac4061a5b 10 *
NirT 1:e8fac4061a5b 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
NirT 1:e8fac4061a5b 12 *
NirT 1:e8fac4061a5b 13 * Redistribution and use in source and binary forms, with or without modification,
NirT 1:e8fac4061a5b 14 * are permitted provided that the following conditions are met:
NirT 1:e8fac4061a5b 15 * 1. Redistributions of source code must retain the above copyright notice,
NirT 1:e8fac4061a5b 16 * this list of conditions and the following disclaimer.
NirT 1:e8fac4061a5b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NirT 1:e8fac4061a5b 18 * this list of conditions and the following disclaimer in the documentation
NirT 1:e8fac4061a5b 19 * and/or other materials provided with the distribution.
NirT 1:e8fac4061a5b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NirT 1:e8fac4061a5b 21 * may be used to endorse or promote products derived from this software
NirT 1:e8fac4061a5b 22 * without specific prior written permission.
NirT 1:e8fac4061a5b 23 *
NirT 1:e8fac4061a5b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NirT 1:e8fac4061a5b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NirT 1:e8fac4061a5b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NirT 1:e8fac4061a5b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NirT 1:e8fac4061a5b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NirT 1:e8fac4061a5b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NirT 1:e8fac4061a5b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NirT 1:e8fac4061a5b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NirT 1:e8fac4061a5b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NirT 1:e8fac4061a5b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NirT 1:e8fac4061a5b 34 *
NirT 1:e8fac4061a5b 35 ******************************************************************************
NirT 1:e8fac4061a5b 36 */
NirT 1:e8fac4061a5b 37
NirT 1:e8fac4061a5b 38 /* Define to prevent recursive inclusion -------------------------------------*/
NirT 1:e8fac4061a5b 39 #ifndef __IO_H
NirT 1:e8fac4061a5b 40 #define __IO_H
NirT 1:e8fac4061a5b 41
NirT 1:e8fac4061a5b 42 #ifdef __cplusplus
NirT 1:e8fac4061a5b 43 extern "C" {
NirT 1:e8fac4061a5b 44 #endif
NirT 1:e8fac4061a5b 45
NirT 1:e8fac4061a5b 46 /* Includes ------------------------------------------------------------------*/
NirT 1:e8fac4061a5b 47 #include <stdint.h>
NirT 1:e8fac4061a5b 48
NirT 1:e8fac4061a5b 49 /** @addtogroup BSP
NirT 1:e8fac4061a5b 50 * @{
NirT 1:e8fac4061a5b 51 */
NirT 1:e8fac4061a5b 52
NirT 1:e8fac4061a5b 53 /** @addtogroup Components
NirT 1:e8fac4061a5b 54 * @{
NirT 1:e8fac4061a5b 55 */
NirT 1:e8fac4061a5b 56
NirT 1:e8fac4061a5b 57 /** @addtogroup IO
NirT 1:e8fac4061a5b 58 * @{
NirT 1:e8fac4061a5b 59 */
NirT 1:e8fac4061a5b 60
NirT 1:e8fac4061a5b 61 /** @defgroup IO_Exported_Types
NirT 1:e8fac4061a5b 62 * @{
NirT 1:e8fac4061a5b 63 */
NirT 1:e8fac4061a5b 64
NirT 1:e8fac4061a5b 65 /**
NirT 1:e8fac4061a5b 66 * @brief IO Bit SET and Bit RESET enumeration
NirT 1:e8fac4061a5b 67 */
NirT 1:e8fac4061a5b 68 typedef enum
NirT 1:e8fac4061a5b 69 {
NirT 1:e8fac4061a5b 70 IO_PIN_RESET = 0,
NirT 1:e8fac4061a5b 71 IO_PIN_SET
NirT 1:e8fac4061a5b 72 }IO_PinState;
NirT 1:e8fac4061a5b 73
NirT 1:e8fac4061a5b 74 typedef enum
NirT 1:e8fac4061a5b 75 {
NirT 1:e8fac4061a5b 76 IO_MODE_INPUT = 0, /* input floating */
NirT 1:e8fac4061a5b 77 IO_MODE_OUTPUT, /* output Push Pull */
NirT 1:e8fac4061a5b 78 IO_MODE_IT_RISING_EDGE, /* float input - irq detect on rising edge */
NirT 1:e8fac4061a5b 79 IO_MODE_IT_FALLING_EDGE, /* float input - irq detect on falling edge */
NirT 1:e8fac4061a5b 80 IO_MODE_IT_LOW_LEVEL, /* float input - irq detect on low level */
NirT 1:e8fac4061a5b 81 IO_MODE_IT_HIGH_LEVEL, /* float input - irq detect on high level */
NirT 1:e8fac4061a5b 82 /* following modes only available on MFX*/
NirT 1:e8fac4061a5b 83 IO_MODE_ANALOG, /* analog mode */
NirT 1:e8fac4061a5b 84 IO_MODE_OFF, /* when pin isn't used*/
NirT 1:e8fac4061a5b 85 IO_MODE_INPUT_PU, /* input with internal pull up resistor */
NirT 1:e8fac4061a5b 86 IO_MODE_INPUT_PD, /* input with internal pull down resistor */
NirT 1:e8fac4061a5b 87 IO_MODE_OUTPUT_OD, /* Open Drain output without internal resistor */
NirT 1:e8fac4061a5b 88 IO_MODE_OUTPUT_OD_PU, /* Open Drain output with internal pullup resistor */
NirT 1:e8fac4061a5b 89 IO_MODE_OUTPUT_OD_PD, /* Open Drain output with internal pulldown resistor */
NirT 1:e8fac4061a5b 90 IO_MODE_OUTPUT_PP, /* PushPull output without internal resistor */
NirT 1:e8fac4061a5b 91 IO_MODE_OUTPUT_PP_PU, /* PushPull output with internal pullup resistor */
NirT 1:e8fac4061a5b 92 IO_MODE_OUTPUT_PP_PD, /* PushPull output with internal pulldown resistor */
NirT 1:e8fac4061a5b 93 IO_MODE_IT_RISING_EDGE_PU, /* push up resistor input - irq on rising edge */
NirT 1:e8fac4061a5b 94 IO_MODE_IT_RISING_EDGE_PD, /* push dw resistor input - irq on rising edge */
NirT 1:e8fac4061a5b 95 IO_MODE_IT_FALLING_EDGE_PU, /* push up resistor input - irq on falling edge */
NirT 1:e8fac4061a5b 96 IO_MODE_IT_FALLING_EDGE_PD, /* push dw resistor input - irq on falling edge */
NirT 1:e8fac4061a5b 97 IO_MODE_IT_LOW_LEVEL_PU, /* push up resistor input - irq detect on low level */
NirT 1:e8fac4061a5b 98 IO_MODE_IT_LOW_LEVEL_PD, /* push dw resistor input - irq detect on low level */
NirT 1:e8fac4061a5b 99 IO_MODE_IT_HIGH_LEVEL_PU, /* push up resistor input - irq detect on high level */
NirT 1:e8fac4061a5b 100 IO_MODE_IT_HIGH_LEVEL_PD, /* push dw resistor input - irq detect on high level */
NirT 1:e8fac4061a5b 101
NirT 1:e8fac4061a5b 102 }IO_ModeTypedef;
NirT 1:e8fac4061a5b 103
NirT 1:e8fac4061a5b 104 /** @defgroup IO_Driver_structure IO Driver structure
NirT 1:e8fac4061a5b 105 * @{
NirT 1:e8fac4061a5b 106 */
NirT 1:e8fac4061a5b 107 typedef struct
NirT 1:e8fac4061a5b 108 {
NirT 1:e8fac4061a5b 109 void (*Init)(uint16_t);
NirT 1:e8fac4061a5b 110 uint16_t (*ReadID)(uint16_t);
NirT 1:e8fac4061a5b 111 void (*Reset)(uint16_t);
NirT 1:e8fac4061a5b 112
NirT 1:e8fac4061a5b 113 void (*Start)(uint16_t, uint32_t);
NirT 1:e8fac4061a5b 114 uint8_t (*Config)(uint16_t, uint32_t, IO_ModeTypedef);
NirT 1:e8fac4061a5b 115 void (*WritePin)(uint16_t, uint32_t, uint8_t);
NirT 1:e8fac4061a5b 116 uint32_t (*ReadPin)(uint16_t, uint32_t);
NirT 1:e8fac4061a5b 117
NirT 1:e8fac4061a5b 118 void (*EnableIT)(uint16_t);
NirT 1:e8fac4061a5b 119 void (*DisableIT)(uint16_t);
NirT 1:e8fac4061a5b 120 uint32_t (*ITStatus)(uint16_t, uint32_t);
NirT 1:e8fac4061a5b 121 void (*ClearIT)(uint16_t, uint32_t);
NirT 1:e8fac4061a5b 122
NirT 1:e8fac4061a5b 123 }IO_DrvTypeDef;
NirT 1:e8fac4061a5b 124 /**
NirT 1:e8fac4061a5b 125 * @}
NirT 1:e8fac4061a5b 126 */
NirT 1:e8fac4061a5b 127
NirT 1:e8fac4061a5b 128 /**
NirT 1:e8fac4061a5b 129 * @}
NirT 1:e8fac4061a5b 130 */
NirT 1:e8fac4061a5b 131
NirT 1:e8fac4061a5b 132 /**
NirT 1:e8fac4061a5b 133 * @}
NirT 1:e8fac4061a5b 134 */
NirT 1:e8fac4061a5b 135
NirT 1:e8fac4061a5b 136 /**
NirT 1:e8fac4061a5b 137 * @}
NirT 1:e8fac4061a5b 138 */
NirT 1:e8fac4061a5b 139
NirT 1:e8fac4061a5b 140 /**
NirT 1:e8fac4061a5b 141 * @}
NirT 1:e8fac4061a5b 142 */
NirT 1:e8fac4061a5b 143
NirT 1:e8fac4061a5b 144 #ifdef __cplusplus
NirT 1:e8fac4061a5b 145 }
NirT 1:e8fac4061a5b 146 #endif
NirT 1:e8fac4061a5b 147
NirT 1:e8fac4061a5b 148 #endif /* __IO_H */
NirT 1:e8fac4061a5b 149
NirT 1:e8fac4061a5b 150 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/