Nick Ryder / AD5384

AD5384 DAC.

Fork of AD5384 by wimbeaumont Project

AD5384.cpp@1:d2d6341d3e97, 2014-10-05 (annotated)

Committer:
wbeaumont
Date:
Sun Oct 05 17:10:03 2014 +0000
Revision:
1:d2d6341d3e97
Parent:
0:33bb5081488a
Child:
2:fc250e37a028
Child:
3:0d930c475e72
init functions added, ctr function added . version class added

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wbeaumont 0:33bb5081488a 1 #include "AD5384.h"
wbeaumont 0:33bb5081488a 2 #include "mbed.h"
wbeaumont 0:33bb5081488a 3
wbeaumont 0:33bb5081488a 4 #define nrch 40 // nr channels
wbeaumont 0:33bb5081488a 5 #define p2_14 16384
wbeaumont 0:33bb5081488a 6 #define p2_13 8192
wbeaumont 0:33bb5081488a 7
wbeaumont 0:33bb5081488a 8 #define C_ACTIVE 1
wbeaumont 0:33bb5081488a 9 #define C_DEACTIVE 0
wbeaumont 0:33bb5081488a 10
wbeaumont 0:33bb5081488a 11 // spi mode has to be set for each transmission as spi bus can be shared
wbeaumont 0:33bb5081488a 12
wbeaumont 1:d2d6341d3e97 13 /*****
wbeaumont 1:d2d6341d3e97 14 * version history
wbeaumont 1:d2d6341d3e97 15 * v1.10 initial release version
wbeaumont 1:d2d6341d3e97 16 * v1.11 added init 1 and init 2 function an ctrlreg defs
wbeaumont 1:d2d6341d3e97 17 * v1.12
wbeaumont 1:d2d6341d3e97 18 */
wbeaumont 1:d2d6341d3e97 19
wbeaumont 1:d2d6341d3e97 20 #define AD5384_SRC_VERSION "1.12"
wbeaumont 0:33bb5081488a 21
wbeaumont 0:33bb5081488a 22 #define M_DATA_R 0x3
wbeaumont 0:33bb5081488a 23 #define M_OFFS_R 0x2
wbeaumont 0:33bb5081488a 24 #define M_GAIN_R 0x1
wbeaumont 0:33bb5081488a 25 #define M_SPEC_R 0x0
wbeaumont 0:33bb5081488a 26
wbeaumont 0:33bb5081488a 27 #define NOP_INST 0x0
wbeaumont 0:33bb5081488a 28
wbeaumont 1:d2d6341d3e97 29
wbeaumont 1:d2d6341d3e97 30 // control register bits
wbeaumont 1:d2d6341d3e97 31 #define CTRL_REG_ADDR 0x0C
wbeaumont 1:d2d6341d3e97 32 #define OUT_PWD_STAT_HIMP 0x2000
wbeaumont 1:d2d6341d3e97 33 //0b10 0000 0000 0000
wbeaumont 1:d2d6341d3e97 34 #define OUT_PWD_STAT_100K 0x1FFF
wbeaumont 1:d2d6341d3e97 35 //0b01 1111 1111 1111
wbeaumont 1:d2d6341d3e97 36 #define INT_REF_2500 0X1000
wbeaumont 1:d2d6341d3e97 37 //0b01000000000000
wbeaumont 1:d2d6341d3e97 38 #define INT_REF_1250 0x2FFF
wbeaumont 1:d2d6341d3e97 39 //0b10111111111111
wbeaumont 1:d2d6341d3e97 40 #define I_BOOST_ON 0x0800
wbeaumont 1:d2d6341d3e97 41 //0b00100000000000
wbeaumont 1:d2d6341d3e97 42 #define I_BOOST_OFF 0x37FF
wbeaumont 1:d2d6341d3e97 43 //0b11011111111111
wbeaumont 1:d2d6341d3e97 44 #define REF_SRC_INT 0x0400
wbeaumont 1:d2d6341d3e97 45 //0b00010000000000
wbeaumont 1:d2d6341d3e97 46 #define REF_SRC_EXT 0x3BFF
wbeaumont 1:d2d6341d3e97 47 //0b11 1011 1111 1111
wbeaumont 1:d2d6341d3e97 48 #define MONITOR_MODE_EN 0x0200
wbeaumont 1:d2d6341d3e97 49 //0b00001000000000
wbeaumont 1:d2d6341d3e97 50 #define MONITOR_MODE_DIS 0x3DFF
wbeaumont 1:d2d6341d3e97 51 //0b11 1101 1111 1111
wbeaumont 1:d2d6341d3e97 52 #define TEMP_MONITOR_EN 0x0100
wbeaumont 1:d2d6341d3e97 53 //0b00000100000000
wbeaumont 1:d2d6341d3e97 54 #define TEMP_MONITOR_DIS 0x3EFF
wbeaumont 1:d2d6341d3e97 55 //0b11 1110 1111 1111
wbeaumont 1:d2d6341d3e97 56 #define TOGGLE_DISABLE 0x3F83
wbeaumont 1:d2d6341d3e97 57 //0b11 1111 1000 0011
wbeaumont 1:d2d6341d3e97 58
wbeaumont 1:d2d6341d3e97 59
wbeaumont 1:d2d6341d3e97 60
wbeaumont 1:d2d6341d3e97 61
wbeaumont 1:d2d6341d3e97 62 AD5384::AD5384(SWSPI *spiinterface ,DigitalOut* chipselect):getVersion( VERSION_AD5384_HDR,AD5384_SRC_VERSION, __TIME__, __DATE__) {
wbeaumont 0:33bb5081488a 63 vref=2.5;
wbeaumont 0:33bb5081488a 64 spi=spiinterface;
wbeaumont 0:33bb5081488a 65 cs=chipselect;
wbeaumont 0:33bb5081488a 66 for ( int nc=0 ; nc < nrch; nc++){
wbeaumont 0:33bb5081488a 67 gain[nc]=0x3FFE;
wbeaumont 0:33bb5081488a 68 offset[nc]=0x2000;
wbeaumont 0:33bb5081488a 69 }
wbeaumont 0:33bb5081488a 70 };
wbeaumont 0:33bb5081488a 71
wbeaumont 0:33bb5081488a 72 u16 AD5384::calculate_dac_setting(u8 nr, float vout ) {
wbeaumont 0:33bb5081488a 73 //Vout = 2 * Vref * x2 / 2^n => x2 = Vout * 2^14 /(2 * Vref)
wbeaumont 0:33bb5081488a 74 // x2 is loaded to the DAC string
wbeaumont 0:33bb5081488a 75 // x1 is the 14 bit DAC wordt written to the DAC input register
wbeaumont 0:33bb5081488a 76 if( nr >39 ) return 0;
wbeaumont 0:33bb5081488a 77 float x2= vout * p2_14 /(2 *vref);
wbeaumont 0:33bb5081488a 78 // x2 = [(gain+2)/2^n * x1] + offset-2^13
wbeaumont 0:33bb5081488a 79 // x1 = 2^14/(gain+2) * [ x2 - offset+2^13 ]
wbeaumont 0:33bb5081488a 80 u16 x1 = p2_14/(gain[nr]+1) *( x2- offset[nr]+p2_13);
wbeaumont 1:d2d6341d3e97 81 x1= 0x3FFF & x1;
wbeaumont 0:33bb5081488a 82 dac[nr]=x1 ;
wbeaumont 0:33bb5081488a 83 return x1;
wbeaumont 0:33bb5081488a 84 };
wbeaumont 0:33bb5081488a 85
wbeaumont 0:33bb5081488a 86
wbeaumont 0:33bb5081488a 87 u32 AD5384::format_word(u8 mode,u8 ch,u8 rw,u16 data) {
wbeaumont 0:33bb5081488a 88 // not clear what is the MSB bit ,set it to zero
wbeaumont 0:33bb5081488a 89 u32 shift = (u32) rw&1;
wbeaumont 0:33bb5081488a 90 u32 word= shift << 22;
wbeaumont 0:33bb5081488a 91
wbeaumont 0:33bb5081488a 92 shift= (u32)(ch &0x1F);
wbeaumont 0:33bb5081488a 93 shift = shift << 16;
wbeaumont 0:33bb5081488a 94 word = word | shift;
wbeaumont 0:33bb5081488a 95
wbeaumont 0:33bb5081488a 96 shift= (u32)(mode & 0x3);
wbeaumont 0:33bb5081488a 97 shift = shift << 14;
wbeaumont 0:33bb5081488a 98 word = word | shift;
wbeaumont 0:33bb5081488a 99
wbeaumont 0:33bb5081488a 100 word = word | (data & 0x3FFF);
wbeaumont 0:33bb5081488a 101
wbeaumont 0:33bb5081488a 102 return word;
wbeaumont 0:33bb5081488a 103 }
wbeaumont 0:33bb5081488a 104
wbeaumont 0:33bb5081488a 105 void AD5384::set_spi_mode(){
wbeaumont 0:33bb5081488a 106 spi->format(24,1);
wbeaumont 0:33bb5081488a 107 spi->frequency(10000000);
wbeaumont 0:33bb5081488a 108 }
wbeaumont 0:33bb5081488a 109
wbeaumont 0:33bb5081488a 110 u16 AD5384::set_volt(u8 ch, float vout ){
wbeaumont 0:33bb5081488a 111 volt[ch]=vout;
wbeaumont 0:33bb5081488a 112 u16 dacin=calculate_dac_setting(ch, vout );
wbeaumont 0:33bb5081488a 113 set_spi_mode();
wbeaumont 0:33bb5081488a 114 u32 data=format_word(M_DATA_R,ch,0,dacin);
wbeaumont 0:33bb5081488a 115 cs->write(C_ACTIVE);
wbeaumont 0:33bb5081488a 116 spi->write(data);
wbeaumont 0:33bb5081488a 117 cs->write(C_DEACTIVE);
wbeaumont 0:33bb5081488a 118 return dacin;
wbeaumont 0:33bb5081488a 119 }
wbeaumont 0:33bb5081488a 120
wbeaumont 1:d2d6341d3e97 121 void AD5384::init1(){
wbeaumont 1:d2d6341d3e97 122 u16 ctrlreg=0;
wbeaumont 1:d2d6341d3e97 123 ctrlreg = (INT_REF_2500 | REF_SRC_INT ) & TOGGLE_DISABLE;
wbeaumont 1:d2d6341d3e97 124 set_reg(M_SPEC_R,CTRL_REG_ADDR,ctrlreg);
wbeaumont 1:d2d6341d3e97 125
wbeaumont 1:d2d6341d3e97 126 }
wbeaumont 1:d2d6341d3e97 127
wbeaumont 1:d2d6341d3e97 128 void AD5384::init2(){
wbeaumont 1:d2d6341d3e97 129 u16 ctrlreg=0;
wbeaumont 1:d2d6341d3e97 130 // implecite INT_REF_1250
wbeaumont 1:d2d6341d3e97 131 ctrlreg = REF_SRC_INT & TOGGLE_DISABLE;
wbeaumont 1:d2d6341d3e97 132 set_reg(M_SPEC_R,CTRL_REG_ADDR,ctrlreg);
wbeaumont 1:d2d6341d3e97 133
wbeaumont 1:d2d6341d3e97 134 }
wbeaumont 1:d2d6341d3e97 135
wbeaumont 0:33bb5081488a 136
wbeaumont 0:33bb5081488a 137
wbeaumont 0:33bb5081488a 138 u32 AD5384::soft_clr(){
wbeaumont 0:33bb5081488a 139 return set_reg(M_SPEC_R,0x02,0x2000);
wbeaumont 0:33bb5081488a 140 }
wbeaumont 0:33bb5081488a 141
wbeaumont 0:33bb5081488a 142
wbeaumont 0:33bb5081488a 143 u32 AD5384::soft_rst(){
wbeaumont 0:33bb5081488a 144 return set_reg(M_SPEC_R,0x0F,0x211F);
wbeaumont 0:33bb5081488a 145 }
wbeaumont 0:33bb5081488a 146
wbeaumont 0:33bb5081488a 147
wbeaumont 0:33bb5081488a 148 u32 AD5384::clear_code(){
wbeaumont 0:33bb5081488a 149 return set_reg(M_SPEC_R,0x01,0x2000);
wbeaumont 0:33bb5081488a 150 }
wbeaumont 0:33bb5081488a 151
wbeaumont 0:33bb5081488a 152 u16 AD5384::set_gain(u8 ch, u16 gain ){
wbeaumont 0:33bb5081488a 153 set_reg(M_GAIN_R,ch,gain);
wbeaumont 0:33bb5081488a 154 return gain;
wbeaumont 0:33bb5081488a 155 }
wbeaumont 0:33bb5081488a 156
wbeaumont 0:33bb5081488a 157 u16 AD5384::set_offset(u8 ch, u16 gain ){
wbeaumont 0:33bb5081488a 158 set_reg(M_OFFS_R,ch,gain);
wbeaumont 0:33bb5081488a 159 return gain;
wbeaumont 0:33bb5081488a 160 }
wbeaumont 0:33bb5081488a 161
wbeaumont 0:33bb5081488a 162
wbeaumont 0:33bb5081488a 163 u16 AD5384::set_dac(u8 ch, u16 dac ){
wbeaumont 0:33bb5081488a 164 set_reg(M_DATA_R,ch,dac);
wbeaumont 0:33bb5081488a 165 return dac;
wbeaumont 0:33bb5081488a 166 }
wbeaumont 0:33bb5081488a 167
wbeaumont 1:d2d6341d3e97 168
wbeaumont 1:d2d6341d3e97 169
wbeaumont 1:d2d6341d3e97 170
wbeaumont 0:33bb5081488a 171
wbeaumont 0:33bb5081488a 172 u32 AD5384::set_reg(u8 mode,u8 ch, u16 value ){
wbeaumont 0:33bb5081488a 173 set_spi_mode();
wbeaumont 0:33bb5081488a 174 value=value & 0x3FFF;
wbeaumont 0:33bb5081488a 175 u32 data=format_word(mode,ch,0,value);
wbeaumont 0:33bb5081488a 176 cs->write(C_ACTIVE);
wbeaumont 0:33bb5081488a 177 spi->write(data);
wbeaumont 0:33bb5081488a 178 cs->write(C_DEACTIVE);
wbeaumont 0:33bb5081488a 179 return data;
wbeaumont 0:33bb5081488a 180 }
wbeaumont 0:33bb5081488a 181
wbeaumont 0:33bb5081488a 182 u16 AD5384::get_reg(u8 mode, u8 ch ){
wbeaumont 0:33bb5081488a 183 set_spi_mode();
wbeaumont 0:33bb5081488a 184 u32 data=format_word(mode,ch,1,0);
wbeaumont 0:33bb5081488a 185 cs->write(C_ACTIVE);
wbeaumont 0:33bb5081488a 186 spi->write(data);
wbeaumont 0:33bb5081488a 187 cs->write(C_DEACTIVE);
wbeaumont 0:33bb5081488a 188 wait( .00001);
wbeaumont 0:33bb5081488a 189 cs->write(C_ACTIVE);
wbeaumont 0:33bb5081488a 190 data=spi->write(NOP_INST);
wbeaumont 0:33bb5081488a 191 cs->write(C_DEACTIVE);
wbeaumont 0:33bb5081488a 192 return (u16) data;
wbeaumont 0:33bb5081488a 193 }
wbeaumont 0:33bb5081488a 194
wbeaumont 0:33bb5081488a 195 u16 AD5384::get_gain(u8 ch ){
wbeaumont 0:33bb5081488a 196 return get_reg(M_GAIN_R,ch);
wbeaumont 0:33bb5081488a 197
wbeaumont 0:33bb5081488a 198 }
wbeaumont 0:33bb5081488a 199
wbeaumont 0:33bb5081488a 200 u16 AD5384::get_dac(u8 ch){
wbeaumont 0:33bb5081488a 201 return get_reg(M_DATA_R,ch);
wbeaumont 0:33bb5081488a 202
wbeaumont 0:33bb5081488a 203 }
wbeaumont 0:33bb5081488a 204
wbeaumont 0:33bb5081488a 205
wbeaumont 0:33bb5081488a 206
wbeaumont 0:33bb5081488a 207
wbeaumont 0:33bb5081488a 208 u16 AD5384::get_offset(u8 ch ){
wbeaumont 0:33bb5081488a 209 return get_reg(M_OFFS_R,ch);
wbeaumont 0:33bb5081488a 210
wbeaumont 0:33bb5081488a 211 }
wbeaumont 0:33bb5081488a 212
wbeaumont 0:33bb5081488a 213 u32 AD5384::get_ctrl(){
wbeaumont 1:d2d6341d3e97 214
wbeaumont 0:33bb5081488a 215 return get_reg(M_SPEC_R, 0x0C);
wbeaumont 0:33bb5081488a 216 }
wbeaumont 0:33bb5081488a 217
wbeaumont 0:33bb5081488a 218
wbeaumont 0:33bb5081488a 219
wbeaumont 0:33bb5081488a 220
wbeaumont 0:33bb5081488a 221 u16 AD5384::get_ch_out_reg(u8 ch) {
wbeaumont 0:33bb5081488a 222 u32 data=format_word(M_DATA_R,ch,1,0);
wbeaumont 0:33bb5081488a 223 cs->write(C_ACTIVE);
wbeaumont 0:33bb5081488a 224 spi->write(data);
wbeaumont 0:33bb5081488a 225 cs->write(C_DEACTIVE);
wbeaumont 0:33bb5081488a 226 wait( .00001);
wbeaumont 0:33bb5081488a 227 cs->write(C_ACTIVE);
wbeaumont 0:33bb5081488a 228 data=spi->write(NOP_INST);
wbeaumont 0:33bb5081488a 229 cs->write(C_DEACTIVE);
wbeaumont 0:33bb5081488a 230 return (u16) data;
wbeaumont 1:d2d6341d3e97 231 }
wbeaumont 1:d2d6341d3e97 232
wbeaumont 1:d2d6341d3e97 233
wbeaumont 1:d2d6341d3e97 234
wbeaumont 1:d2d6341d3e97 235
wbeaumont 1:d2d6341d3e97 236
wbeaumont 1:d2d6341d3e97 237 #include "sscm_comm.h"
wbeaumont 1:d2d6341d3e97 238 /*
wbeaumont 1:d2d6341d3e97 239
wbeaumont 1:d2d6341d3e97 240 u16 AD5384::get_src_version_nr(){
wbeaumont 1:d2d6341d3e97 241 return sscm_comm::get_hex_version_nr(VERSION_AD5384_SRC);
wbeaumont 1:d2d6341d3e97 242 }
wbeaumont 1:d2d6341d3e97 243
wbeaumont 1:d2d6341d3e97 244 // returns the version number of hdr of this module
wbeaumont 1:d2d6341d3e97 245 u16 AD5384::get_hdr_version_nr(){
wbeaumont 1:d2d6341d3e97 246 return sscm_comm::get_hex_version_nr(VERSION_AD5384_HDR);
wbeaumont 1:d2d6341d3e97 247
wbeaumont 1:d2d6341d3e97 248 }
wbeaumont 1:d2d6341d3e97 249
wbeaumont 1:d2d6341d3e97 250 */