Li Menglu
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nRF51822
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Dependents: BLE_Acceleration_Statejudging
Fork of
nRF51822
by 
Nordic Semiconductor
source/nordic-sdk/components/device/nrf51_deprecated.h@551:ab7a8de3ff10, 2016-01-11 (annotated)
- Committer:
- vcoubard
- Date:
- Mon Jan 11 10:19:10 2016 +0000
- Revision:
- 551:ab7a8de3ff10
- Parent:
- 504:2179e57ad950
Synchronized with git rev 6825c511
Author: Rohit Grover
Release 2.1.0
=============
Upgrading to files from v8.1 of the Nordic SDK.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| vcoubard | 551:ab7a8de3ff10 | 1 | /* |
| vcoubard | 551:ab7a8de3ff10 | 2 | * Copyright (c) Nordic Semiconductor ASA |
| vcoubard | 551:ab7a8de3ff10 | 3 | * All rights reserved. |
| vcoubard | 551:ab7a8de3ff10 | 4 | * |
| vcoubard | 551:ab7a8de3ff10 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| vcoubard | 551:ab7a8de3ff10 | 6 | * are permitted provided that the following conditions are met: |
| vcoubard | 551:ab7a8de3ff10 | 7 | * |
| vcoubard | 551:ab7a8de3ff10 | 8 | * 1. Redistributions of source code must retain the above copyright notice, this |
| vcoubard | 551:ab7a8de3ff10 | 9 | * list of conditions and the following disclaimer. |
| vcoubard | 551:ab7a8de3ff10 | 10 | * |
| vcoubard | 551:ab7a8de3ff10 | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, this |
| vcoubard | 551:ab7a8de3ff10 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| vcoubard | 551:ab7a8de3ff10 | 13 | * other materials provided with the distribution. |
| vcoubard | 551:ab7a8de3ff10 | 14 | * |
| vcoubard | 551:ab7a8de3ff10 | 15 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of other |
| vcoubard | 551:ab7a8de3ff10 | 16 | * contributors to this software may be used to endorse or promote products |
| vcoubard | 551:ab7a8de3ff10 | 17 | * derived from this software without specific prior written permission. |
| vcoubard | 551:ab7a8de3ff10 | 18 | * |
| vcoubard | 551:ab7a8de3ff10 | 19 | * |
| vcoubard | 551:ab7a8de3ff10 | 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| vcoubard | 551:ab7a8de3ff10 | 21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| vcoubard | 551:ab7a8de3ff10 | 22 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| vcoubard | 551:ab7a8de3ff10 | 23 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| vcoubard | 551:ab7a8de3ff10 | 24 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| vcoubard | 551:ab7a8de3ff10 | 25 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| vcoubard | 551:ab7a8de3ff10 | 26 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| vcoubard | 551:ab7a8de3ff10 | 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| vcoubard | 551:ab7a8de3ff10 | 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| vcoubard | 551:ab7a8de3ff10 | 29 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| vcoubard | 551:ab7a8de3ff10 | 30 | * |
| vcoubard | 551:ab7a8de3ff10 | 31 | */ |
| vcoubard | 551:ab7a8de3ff10 | 32 | #ifndef NRF51_DEPRECATED_H |
| vcoubard | 551:ab7a8de3ff10 | 33 | #define NRF51_DEPRECATED_H |
| vcoubard | 551:ab7a8de3ff10 | 34 | |
| vcoubard | 551:ab7a8de3ff10 | 35 | /*lint ++flb "Enter library region */ |
| vcoubard | 551:ab7a8de3ff10 | 36 | |
| vcoubard | 551:ab7a8de3ff10 | 37 | /* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and |
| vcoubard | 551:ab7a8de3ff10 | 38 | * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these |
| vcoubard | 551:ab7a8de3ff10 | 39 | * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. |
| vcoubard | 551:ab7a8de3ff10 | 40 | */ |
| vcoubard | 551:ab7a8de3ff10 | 41 | |
| vcoubard | 551:ab7a8de3ff10 | 42 | /* NVMC */ |
| vcoubard | 551:ab7a8de3ff10 | 43 | /* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ |
| vcoubard | 551:ab7a8de3ff10 | 44 | #define ERASEPCR0 ERASEPROTECTEDPAGE |
| vcoubard | 551:ab7a8de3ff10 | 45 | /* The register ERASEPAGE is also called ERASEPCR1 in the documentation. */ |
| vcoubard | 551:ab7a8de3ff10 | 46 | #define ERASEPCR1 ERASEPAGE |
| vcoubard | 551:ab7a8de3ff10 | 47 | |
| vcoubard | 551:ab7a8de3ff10 | 48 | /* LPCOMP */ |
| vcoubard | 551:ab7a8de3ff10 | 49 | /* The interrupt ISR was renamed. Adding old name to the macros. */ |
| vcoubard | 551:ab7a8de3ff10 | 50 | #define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler |
| vcoubard | 551:ab7a8de3ff10 | 51 | |
| vcoubard | 551:ab7a8de3ff10 | 52 | |
| vcoubard | 551:ab7a8de3ff10 | 53 | /* MPU */ |
| vcoubard | 551:ab7a8de3ff10 | 54 | /* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ |
| vcoubard | 551:ab7a8de3ff10 | 55 | #define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos |
| vcoubard | 551:ab7a8de3ff10 | 56 | #define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk |
| vcoubard | 551:ab7a8de3ff10 | 57 | #define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 |
| vcoubard | 551:ab7a8de3ff10 | 58 | #define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 |
| vcoubard | 551:ab7a8de3ff10 | 59 | |
| vcoubard | 551:ab7a8de3ff10 | 60 | |
| vcoubard | 551:ab7a8de3ff10 | 61 | /* POWER */ |
| vcoubard | 551:ab7a8de3ff10 | 62 | /* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ |
| vcoubard | 551:ab7a8de3ff10 | 63 | #define POWER_RAMON_OFFRAM3_Pos (19UL) |
| vcoubard | 551:ab7a8de3ff10 | 64 | #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) |
| vcoubard | 551:ab7a8de3ff10 | 65 | #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) |
| vcoubard | 551:ab7a8de3ff10 | 66 | #define POWER_RAMON_OFFRAM3_RAM3On (1UL) |
| vcoubard | 551:ab7a8de3ff10 | 67 | /* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ |
| vcoubard | 551:ab7a8de3ff10 | 68 | #define POWER_RAMON_OFFRAM2_Pos (18UL) |
| vcoubard | 551:ab7a8de3ff10 | 69 | #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) |
| vcoubard | 551:ab7a8de3ff10 | 70 | #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) |
| vcoubard | 551:ab7a8de3ff10 | 71 | #define POWER_RAMON_OFFRAM2_RAM2On (1UL) |
| vcoubard | 551:ab7a8de3ff10 | 72 | /* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ |
| vcoubard | 551:ab7a8de3ff10 | 73 | #define POWER_RAMON_ONRAM3_Pos (3UL) |
| vcoubard | 551:ab7a8de3ff10 | 74 | #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) |
| vcoubard | 551:ab7a8de3ff10 | 75 | #define POWER_RAMON_ONRAM3_RAM3Off (0UL) |
| vcoubard | 551:ab7a8de3ff10 | 76 | #define POWER_RAMON_ONRAM3_RAM3On (1UL) |
| vcoubard | 551:ab7a8de3ff10 | 77 | /* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ |
| vcoubard | 551:ab7a8de3ff10 | 78 | #define POWER_RAMON_ONRAM2_Pos (2UL) |
| vcoubard | 551:ab7a8de3ff10 | 79 | #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) |
| vcoubard | 551:ab7a8de3ff10 | 80 | #define POWER_RAMON_ONRAM2_RAM2Off (0UL) |
| vcoubard | 551:ab7a8de3ff10 | 81 | #define POWER_RAMON_ONRAM2_RAM2On (1UL) |
| vcoubard | 551:ab7a8de3ff10 | 82 | |
| vcoubard | 551:ab7a8de3ff10 | 83 | |
| vcoubard | 551:ab7a8de3ff10 | 84 | /* RADIO */ |
| vcoubard | 551:ab7a8de3ff10 | 85 | /* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ |
| vcoubard | 551:ab7a8de3ff10 | 86 | #define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm |
| vcoubard | 551:ab7a8de3ff10 | 87 | /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ |
| vcoubard | 551:ab7a8de3ff10 | 88 | #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos |
| vcoubard | 551:ab7a8de3ff10 | 89 | #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk |
| vcoubard | 551:ab7a8de3ff10 | 90 | #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include |
| vcoubard | 551:ab7a8de3ff10 | 91 | #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip |
| vcoubard | 551:ab7a8de3ff10 | 92 | /* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ |
| vcoubard | 551:ab7a8de3ff10 | 93 | #define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos |
| vcoubard | 551:ab7a8de3ff10 | 94 | #define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk |
| vcoubard | 551:ab7a8de3ff10 | 95 | #define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled |
| vcoubard | 551:ab7a8de3ff10 | 96 | #define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled |
| vcoubard | 551:ab7a8de3ff10 | 97 | /* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ |
| vcoubard | 551:ab7a8de3ff10 | 98 | #define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos |
| vcoubard | 551:ab7a8de3ff10 | 99 | #define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk |
| vcoubard | 551:ab7a8de3ff10 | 100 | #define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled |
| vcoubard | 551:ab7a8de3ff10 | 101 | #define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled |
| vcoubard | 551:ab7a8de3ff10 | 102 | |
| vcoubard | 551:ab7a8de3ff10 | 103 | |
| vcoubard | 551:ab7a8de3ff10 | 104 | /* FICR */ |
| vcoubard | 551:ab7a8de3ff10 | 105 | /* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ |
| vcoubard | 551:ab7a8de3ff10 | 106 | #define SIZERAMBLOCK0 SIZERAMBLOCKS |
| vcoubard | 551:ab7a8de3ff10 | 107 | #define SIZERAMBLOCK1 SIZERAMBLOCKS |
| vcoubard | 551:ab7a8de3ff10 | 108 | #define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ |
| vcoubard | 551:ab7a8de3ff10 | 109 | #define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ |
| vcoubard | 551:ab7a8de3ff10 | 110 | /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ |
| vcoubard | 551:ab7a8de3ff10 | 111 | #define DEVICEID0 DEVICEID[0] |
| vcoubard | 551:ab7a8de3ff10 | 112 | #define DEVICEID1 DEVICEID[1] |
| vcoubard | 551:ab7a8de3ff10 | 113 | /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ |
| vcoubard | 551:ab7a8de3ff10 | 114 | #define ER0 ER[0] |
| vcoubard | 551:ab7a8de3ff10 | 115 | #define ER1 ER[1] |
| vcoubard | 551:ab7a8de3ff10 | 116 | #define ER2 ER[2] |
| vcoubard | 551:ab7a8de3ff10 | 117 | #define ER3 ER[3] |
| vcoubard | 551:ab7a8de3ff10 | 118 | /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ |
| vcoubard | 551:ab7a8de3ff10 | 119 | #define IR0 IR[0] |
| vcoubard | 551:ab7a8de3ff10 | 120 | #define IR1 IR[1] |
| vcoubard | 551:ab7a8de3ff10 | 121 | #define IR2 IR[2] |
| vcoubard | 551:ab7a8de3ff10 | 122 | #define IR3 IR[3] |
| vcoubard | 551:ab7a8de3ff10 | 123 | /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ |
| vcoubard | 551:ab7a8de3ff10 | 124 | #define DEVICEADDR0 DEVICEADDR[0] |
| vcoubard | 551:ab7a8de3ff10 | 125 | #define DEVICEADDR1 DEVICEADDR[1] |
| vcoubard | 551:ab7a8de3ff10 | 126 | |
| vcoubard | 551:ab7a8de3ff10 | 127 | |
| vcoubard | 551:ab7a8de3ff10 | 128 | /* PPI */ |
| vcoubard | 551:ab7a8de3ff10 | 129 | /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ |
| vcoubard | 551:ab7a8de3ff10 | 130 | #define TASKS_CHG0EN TASKS_CHG[0].EN |
| vcoubard | 551:ab7a8de3ff10 | 131 | #define TASKS_CHG0DIS TASKS_CHG[0].DIS |
| vcoubard | 551:ab7a8de3ff10 | 132 | #define TASKS_CHG1EN TASKS_CHG[1].EN |
| vcoubard | 551:ab7a8de3ff10 | 133 | #define TASKS_CHG1DIS TASKS_CHG[1].DIS |
| vcoubard | 551:ab7a8de3ff10 | 134 | #define TASKS_CHG2EN TASKS_CHG[2].EN |
| vcoubard | 551:ab7a8de3ff10 | 135 | #define TASKS_CHG2DIS TASKS_CHG[2].DIS |
| vcoubard | 551:ab7a8de3ff10 | 136 | #define TASKS_CHG3EN TASKS_CHG[3].EN |
| vcoubard | 551:ab7a8de3ff10 | 137 | #define TASKS_CHG3DIS TASKS_CHG[3].DIS |
| vcoubard | 551:ab7a8de3ff10 | 138 | /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ |
| vcoubard | 551:ab7a8de3ff10 | 139 | #define CH0_EEP CH[0].EEP |
| vcoubard | 551:ab7a8de3ff10 | 140 | #define CH0_TEP CH[0].TEP |
| vcoubard | 551:ab7a8de3ff10 | 141 | #define CH1_EEP CH[1].EEP |
| vcoubard | 551:ab7a8de3ff10 | 142 | #define CH1_TEP CH[1].TEP |
| vcoubard | 551:ab7a8de3ff10 | 143 | #define CH2_EEP CH[2].EEP |
| vcoubard | 551:ab7a8de3ff10 | 144 | #define CH2_TEP CH[2].TEP |
| vcoubard | 551:ab7a8de3ff10 | 145 | #define CH3_EEP CH[3].EEP |
| vcoubard | 551:ab7a8de3ff10 | 146 | #define CH3_TEP CH[3].TEP |
| vcoubard | 551:ab7a8de3ff10 | 147 | #define CH4_EEP CH[4].EEP |
| vcoubard | 551:ab7a8de3ff10 | 148 | #define CH4_TEP CH[4].TEP |
| vcoubard | 551:ab7a8de3ff10 | 149 | #define CH5_EEP CH[5].EEP |
| vcoubard | 551:ab7a8de3ff10 | 150 | #define CH5_TEP CH[5].TEP |
| vcoubard | 551:ab7a8de3ff10 | 151 | #define CH6_EEP CH[6].EEP |
| vcoubard | 551:ab7a8de3ff10 | 152 | #define CH6_TEP CH[6].TEP |
| vcoubard | 551:ab7a8de3ff10 | 153 | #define CH7_EEP CH[7].EEP |
| vcoubard | 551:ab7a8de3ff10 | 154 | #define CH7_TEP CH[7].TEP |
| vcoubard | 551:ab7a8de3ff10 | 155 | #define CH8_EEP CH[8].EEP |
| vcoubard | 551:ab7a8de3ff10 | 156 | #define CH8_TEP CH[8].TEP |
| vcoubard | 551:ab7a8de3ff10 | 157 | #define CH9_EEP CH[9].EEP |
| vcoubard | 551:ab7a8de3ff10 | 158 | #define CH9_TEP CH[9].TEP |
| vcoubard | 551:ab7a8de3ff10 | 159 | #define CH10_EEP CH[10].EEP |
| vcoubard | 551:ab7a8de3ff10 | 160 | #define CH10_TEP CH[10].TEP |
| vcoubard | 551:ab7a8de3ff10 | 161 | #define CH11_EEP CH[11].EEP |
| vcoubard | 551:ab7a8de3ff10 | 162 | #define CH11_TEP CH[11].TEP |
| vcoubard | 551:ab7a8de3ff10 | 163 | #define CH12_EEP CH[12].EEP |
| vcoubard | 551:ab7a8de3ff10 | 164 | #define CH12_TEP CH[12].TEP |
| vcoubard | 551:ab7a8de3ff10 | 165 | #define CH13_EEP CH[13].EEP |
| vcoubard | 551:ab7a8de3ff10 | 166 | #define CH13_TEP CH[13].TEP |
| vcoubard | 551:ab7a8de3ff10 | 167 | #define CH14_EEP CH[14].EEP |
| vcoubard | 551:ab7a8de3ff10 | 168 | #define CH14_TEP CH[14].TEP |
| vcoubard | 551:ab7a8de3ff10 | 169 | #define CH15_EEP CH[15].EEP |
| vcoubard | 551:ab7a8de3ff10 | 170 | #define CH15_TEP CH[15].TEP |
| vcoubard | 551:ab7a8de3ff10 | 171 | /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ |
| vcoubard | 551:ab7a8de3ff10 | 172 | #define CHG0 CHG[0] |
| vcoubard | 551:ab7a8de3ff10 | 173 | #define CHG1 CHG[1] |
| vcoubard | 551:ab7a8de3ff10 | 174 | #define CHG2 CHG[2] |
| vcoubard | 551:ab7a8de3ff10 | 175 | #define CHG3 CHG[3] |
| vcoubard | 551:ab7a8de3ff10 | 176 | /* All bitfield macros for the CHGx registers therefore changed name. */ |
| vcoubard | 551:ab7a8de3ff10 | 177 | #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos |
| vcoubard | 551:ab7a8de3ff10 | 178 | #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk |
| vcoubard | 551:ab7a8de3ff10 | 179 | #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 180 | #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included |
| vcoubard | 551:ab7a8de3ff10 | 181 | #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos |
| vcoubard | 551:ab7a8de3ff10 | 182 | #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk |
| vcoubard | 551:ab7a8de3ff10 | 183 | #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 184 | #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included |
| vcoubard | 551:ab7a8de3ff10 | 185 | #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos |
| vcoubard | 551:ab7a8de3ff10 | 186 | #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk |
| vcoubard | 551:ab7a8de3ff10 | 187 | #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 188 | #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included |
| vcoubard | 551:ab7a8de3ff10 | 189 | #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos |
| vcoubard | 551:ab7a8de3ff10 | 190 | #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk |
| vcoubard | 551:ab7a8de3ff10 | 191 | #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 192 | #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included |
| vcoubard | 551:ab7a8de3ff10 | 193 | #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos |
| vcoubard | 551:ab7a8de3ff10 | 194 | #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk |
| vcoubard | 551:ab7a8de3ff10 | 195 | #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 196 | #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included |
| vcoubard | 551:ab7a8de3ff10 | 197 | #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos |
| vcoubard | 551:ab7a8de3ff10 | 198 | #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk |
| vcoubard | 551:ab7a8de3ff10 | 199 | #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 200 | #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included |
| vcoubard | 551:ab7a8de3ff10 | 201 | #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos |
| vcoubard | 551:ab7a8de3ff10 | 202 | #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk |
| vcoubard | 551:ab7a8de3ff10 | 203 | #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 204 | #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included |
| vcoubard | 551:ab7a8de3ff10 | 205 | #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos |
| vcoubard | 551:ab7a8de3ff10 | 206 | #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk |
| vcoubard | 551:ab7a8de3ff10 | 207 | #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 208 | #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included |
| vcoubard | 551:ab7a8de3ff10 | 209 | #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos |
| vcoubard | 551:ab7a8de3ff10 | 210 | #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk |
| vcoubard | 551:ab7a8de3ff10 | 211 | #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 212 | #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included |
| vcoubard | 551:ab7a8de3ff10 | 213 | #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos |
| vcoubard | 551:ab7a8de3ff10 | 214 | #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk |
| vcoubard | 551:ab7a8de3ff10 | 215 | #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 216 | #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included |
| vcoubard | 551:ab7a8de3ff10 | 217 | #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos |
| vcoubard | 551:ab7a8de3ff10 | 218 | #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk |
| vcoubard | 551:ab7a8de3ff10 | 219 | #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 220 | #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included |
| vcoubard | 551:ab7a8de3ff10 | 221 | #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos |
| vcoubard | 551:ab7a8de3ff10 | 222 | #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk |
| vcoubard | 551:ab7a8de3ff10 | 223 | #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 224 | #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included |
| vcoubard | 551:ab7a8de3ff10 | 225 | #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos |
| vcoubard | 551:ab7a8de3ff10 | 226 | #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk |
| vcoubard | 551:ab7a8de3ff10 | 227 | #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 228 | #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included |
| vcoubard | 551:ab7a8de3ff10 | 229 | #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos |
| vcoubard | 551:ab7a8de3ff10 | 230 | #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk |
| vcoubard | 551:ab7a8de3ff10 | 231 | #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 232 | #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included |
| vcoubard | 551:ab7a8de3ff10 | 233 | #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos |
| vcoubard | 551:ab7a8de3ff10 | 234 | #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk |
| vcoubard | 551:ab7a8de3ff10 | 235 | #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 236 | #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included |
| vcoubard | 551:ab7a8de3ff10 | 237 | #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos |
| vcoubard | 551:ab7a8de3ff10 | 238 | #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk |
| vcoubard | 551:ab7a8de3ff10 | 239 | #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 240 | #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included |
| vcoubard | 551:ab7a8de3ff10 | 241 | #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos |
| vcoubard | 551:ab7a8de3ff10 | 242 | #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk |
| vcoubard | 551:ab7a8de3ff10 | 243 | #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 244 | #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included |
| vcoubard | 551:ab7a8de3ff10 | 245 | #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos |
| vcoubard | 551:ab7a8de3ff10 | 246 | #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk |
| vcoubard | 551:ab7a8de3ff10 | 247 | #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 248 | #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included |
| vcoubard | 551:ab7a8de3ff10 | 249 | #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos |
| vcoubard | 551:ab7a8de3ff10 | 250 | #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk |
| vcoubard | 551:ab7a8de3ff10 | 251 | #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 252 | #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included |
| vcoubard | 551:ab7a8de3ff10 | 253 | #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos |
| vcoubard | 551:ab7a8de3ff10 | 254 | #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk |
| vcoubard | 551:ab7a8de3ff10 | 255 | #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 256 | #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included |
| vcoubard | 551:ab7a8de3ff10 | 257 | #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos |
| vcoubard | 551:ab7a8de3ff10 | 258 | #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk |
| vcoubard | 551:ab7a8de3ff10 | 259 | #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 260 | #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included |
| vcoubard | 551:ab7a8de3ff10 | 261 | #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos |
| vcoubard | 551:ab7a8de3ff10 | 262 | #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk |
| vcoubard | 551:ab7a8de3ff10 | 263 | #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 264 | #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included |
| vcoubard | 551:ab7a8de3ff10 | 265 | #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos |
| vcoubard | 551:ab7a8de3ff10 | 266 | #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk |
| vcoubard | 551:ab7a8de3ff10 | 267 | #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 268 | #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included |
| vcoubard | 551:ab7a8de3ff10 | 269 | #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos |
| vcoubard | 551:ab7a8de3ff10 | 270 | #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk |
| vcoubard | 551:ab7a8de3ff10 | 271 | #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 272 | #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included |
| vcoubard | 551:ab7a8de3ff10 | 273 | #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos |
| vcoubard | 551:ab7a8de3ff10 | 274 | #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk |
| vcoubard | 551:ab7a8de3ff10 | 275 | #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 276 | #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included |
| vcoubard | 551:ab7a8de3ff10 | 277 | #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos |
| vcoubard | 551:ab7a8de3ff10 | 278 | #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk |
| vcoubard | 551:ab7a8de3ff10 | 279 | #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 280 | #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included |
| vcoubard | 551:ab7a8de3ff10 | 281 | #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos |
| vcoubard | 551:ab7a8de3ff10 | 282 | #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk |
| vcoubard | 551:ab7a8de3ff10 | 283 | #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 284 | #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included |
| vcoubard | 551:ab7a8de3ff10 | 285 | #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos |
| vcoubard | 551:ab7a8de3ff10 | 286 | #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk |
| vcoubard | 551:ab7a8de3ff10 | 287 | #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 288 | #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included |
| vcoubard | 551:ab7a8de3ff10 | 289 | #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos |
| vcoubard | 551:ab7a8de3ff10 | 290 | #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk |
| vcoubard | 551:ab7a8de3ff10 | 291 | #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 292 | #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included |
| vcoubard | 551:ab7a8de3ff10 | 293 | #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos |
| vcoubard | 551:ab7a8de3ff10 | 294 | #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk |
| vcoubard | 551:ab7a8de3ff10 | 295 | #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 296 | #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included |
| vcoubard | 551:ab7a8de3ff10 | 297 | #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos |
| vcoubard | 551:ab7a8de3ff10 | 298 | #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk |
| vcoubard | 551:ab7a8de3ff10 | 299 | #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 300 | #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included |
| vcoubard | 551:ab7a8de3ff10 | 301 | #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos |
| vcoubard | 551:ab7a8de3ff10 | 302 | #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk |
| vcoubard | 551:ab7a8de3ff10 | 303 | #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 304 | #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included |
| vcoubard | 551:ab7a8de3ff10 | 305 | #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos |
| vcoubard | 551:ab7a8de3ff10 | 306 | #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk |
| vcoubard | 551:ab7a8de3ff10 | 307 | #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 308 | #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included |
| vcoubard | 551:ab7a8de3ff10 | 309 | #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos |
| vcoubard | 551:ab7a8de3ff10 | 310 | #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk |
| vcoubard | 551:ab7a8de3ff10 | 311 | #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 312 | #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included |
| vcoubard | 551:ab7a8de3ff10 | 313 | #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos |
| vcoubard | 551:ab7a8de3ff10 | 314 | #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk |
| vcoubard | 551:ab7a8de3ff10 | 315 | #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 316 | #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included |
| vcoubard | 551:ab7a8de3ff10 | 317 | #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos |
| vcoubard | 551:ab7a8de3ff10 | 318 | #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk |
| vcoubard | 551:ab7a8de3ff10 | 319 | #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 320 | #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included |
| vcoubard | 551:ab7a8de3ff10 | 321 | #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos |
| vcoubard | 551:ab7a8de3ff10 | 322 | #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk |
| vcoubard | 551:ab7a8de3ff10 | 323 | #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 324 | #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included |
| vcoubard | 551:ab7a8de3ff10 | 325 | #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos |
| vcoubard | 551:ab7a8de3ff10 | 326 | #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk |
| vcoubard | 551:ab7a8de3ff10 | 327 | #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 328 | #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included |
| vcoubard | 551:ab7a8de3ff10 | 329 | #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos |
| vcoubard | 551:ab7a8de3ff10 | 330 | #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk |
| vcoubard | 551:ab7a8de3ff10 | 331 | #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 332 | #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included |
| vcoubard | 551:ab7a8de3ff10 | 333 | #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos |
| vcoubard | 551:ab7a8de3ff10 | 334 | #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk |
| vcoubard | 551:ab7a8de3ff10 | 335 | #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 336 | #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included |
| vcoubard | 551:ab7a8de3ff10 | 337 | #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos |
| vcoubard | 551:ab7a8de3ff10 | 338 | #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk |
| vcoubard | 551:ab7a8de3ff10 | 339 | #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 340 | #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included |
| vcoubard | 551:ab7a8de3ff10 | 341 | #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos |
| vcoubard | 551:ab7a8de3ff10 | 342 | #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk |
| vcoubard | 551:ab7a8de3ff10 | 343 | #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 344 | #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included |
| vcoubard | 551:ab7a8de3ff10 | 345 | #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos |
| vcoubard | 551:ab7a8de3ff10 | 346 | #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk |
| vcoubard | 551:ab7a8de3ff10 | 347 | #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 348 | #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included |
| vcoubard | 551:ab7a8de3ff10 | 349 | #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos |
| vcoubard | 551:ab7a8de3ff10 | 350 | #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk |
| vcoubard | 551:ab7a8de3ff10 | 351 | #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 352 | #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included |
| vcoubard | 551:ab7a8de3ff10 | 353 | #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos |
| vcoubard | 551:ab7a8de3ff10 | 354 | #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk |
| vcoubard | 551:ab7a8de3ff10 | 355 | #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 356 | #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included |
| vcoubard | 551:ab7a8de3ff10 | 357 | #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos |
| vcoubard | 551:ab7a8de3ff10 | 358 | #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk |
| vcoubard | 551:ab7a8de3ff10 | 359 | #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 360 | #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included |
| vcoubard | 551:ab7a8de3ff10 | 361 | #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos |
| vcoubard | 551:ab7a8de3ff10 | 362 | #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk |
| vcoubard | 551:ab7a8de3ff10 | 363 | #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 364 | #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included |
| vcoubard | 551:ab7a8de3ff10 | 365 | #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos |
| vcoubard | 551:ab7a8de3ff10 | 366 | #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk |
| vcoubard | 551:ab7a8de3ff10 | 367 | #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 368 | #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included |
| vcoubard | 551:ab7a8de3ff10 | 369 | #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos |
| vcoubard | 551:ab7a8de3ff10 | 370 | #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk |
| vcoubard | 551:ab7a8de3ff10 | 371 | #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 372 | #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included |
| vcoubard | 551:ab7a8de3ff10 | 373 | #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos |
| vcoubard | 551:ab7a8de3ff10 | 374 | #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk |
| vcoubard | 551:ab7a8de3ff10 | 375 | #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 376 | #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included |
| vcoubard | 551:ab7a8de3ff10 | 377 | #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos |
| vcoubard | 551:ab7a8de3ff10 | 378 | #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk |
| vcoubard | 551:ab7a8de3ff10 | 379 | #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 380 | #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included |
| vcoubard | 551:ab7a8de3ff10 | 381 | #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos |
| vcoubard | 551:ab7a8de3ff10 | 382 | #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk |
| vcoubard | 551:ab7a8de3ff10 | 383 | #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 384 | #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included |
| vcoubard | 551:ab7a8de3ff10 | 385 | #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos |
| vcoubard | 551:ab7a8de3ff10 | 386 | #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk |
| vcoubard | 551:ab7a8de3ff10 | 387 | #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 388 | #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included |
| vcoubard | 551:ab7a8de3ff10 | 389 | #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos |
| vcoubard | 551:ab7a8de3ff10 | 390 | #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk |
| vcoubard | 551:ab7a8de3ff10 | 391 | #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 392 | #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included |
| vcoubard | 551:ab7a8de3ff10 | 393 | #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos |
| vcoubard | 551:ab7a8de3ff10 | 394 | #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk |
| vcoubard | 551:ab7a8de3ff10 | 395 | #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 396 | #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included |
| vcoubard | 551:ab7a8de3ff10 | 397 | #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos |
| vcoubard | 551:ab7a8de3ff10 | 398 | #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk |
| vcoubard | 551:ab7a8de3ff10 | 399 | #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 400 | #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included |
| vcoubard | 551:ab7a8de3ff10 | 401 | #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos |
| vcoubard | 551:ab7a8de3ff10 | 402 | #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk |
| vcoubard | 551:ab7a8de3ff10 | 403 | #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 404 | #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included |
| vcoubard | 551:ab7a8de3ff10 | 405 | #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos |
| vcoubard | 551:ab7a8de3ff10 | 406 | #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk |
| vcoubard | 551:ab7a8de3ff10 | 407 | #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 408 | #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included |
| vcoubard | 551:ab7a8de3ff10 | 409 | #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos |
| vcoubard | 551:ab7a8de3ff10 | 410 | #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk |
| vcoubard | 551:ab7a8de3ff10 | 411 | #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 412 | #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included |
| vcoubard | 551:ab7a8de3ff10 | 413 | #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos |
| vcoubard | 551:ab7a8de3ff10 | 414 | #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk |
| vcoubard | 551:ab7a8de3ff10 | 415 | #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 416 | #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included |
| vcoubard | 551:ab7a8de3ff10 | 417 | #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos |
| vcoubard | 551:ab7a8de3ff10 | 418 | #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk |
| vcoubard | 551:ab7a8de3ff10 | 419 | #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 420 | #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included |
| vcoubard | 551:ab7a8de3ff10 | 421 | #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos |
| vcoubard | 551:ab7a8de3ff10 | 422 | #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk |
| vcoubard | 551:ab7a8de3ff10 | 423 | #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 424 | #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included |
| vcoubard | 551:ab7a8de3ff10 | 425 | #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos |
| vcoubard | 551:ab7a8de3ff10 | 426 | #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk |
| vcoubard | 551:ab7a8de3ff10 | 427 | #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 428 | #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included |
| vcoubard | 551:ab7a8de3ff10 | 429 | #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos |
| vcoubard | 551:ab7a8de3ff10 | 430 | #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk |
| vcoubard | 551:ab7a8de3ff10 | 431 | #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded |
| vcoubard | 551:ab7a8de3ff10 | 432 | #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included |
| vcoubard | 551:ab7a8de3ff10 | 433 | |
| vcoubard | 551:ab7a8de3ff10 | 434 | |
| vcoubard | 551:ab7a8de3ff10 | 435 | |
| vcoubard | 551:ab7a8de3ff10 | 436 | /*lint --flb "Leave library region" */ |
| vcoubard | 551:ab7a8de3ff10 | 437 | |
| vcoubard | 551:ab7a8de3ff10 | 438 | #endif /* NRF51_DEPRECATED_H */ |