Egor Rumjantsev
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Diff: TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h
- Revision:
- 92:4fc01daae5a5
- Parent:
- 86:04dd9b1680ae
--- a/TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h Wed Oct 29 11:02:04 2014 +0000
+++ b/TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h Thu Nov 27 13:33:22 2014 +0000
@@ -2,9 +2,9 @@
******************************************************************************
* @file stm32f3xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.0.1
- * @date 18-June-2014
- * @brief Header file of RCC HAL Extension module.
+ * @version V1.1.0
+ * @date 12-Sept-2014
+ * @brief Header file of RCC HAL Extended module.
******************************************************************************
* @attention
*
@@ -50,12 +50,118 @@
* @{
*/
-/** @addtogroup RCC
+/** @addtogroup RCCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
+
+ uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
+ This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
+
+}RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+}RCC_OscInitTypeDef;
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< PLLState: The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
+
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
+
+}RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
+ This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+
+}RCC_OscInitTypeDef;
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+
/**
* @brief RCC extended clocks structure definition
*/
@@ -253,6 +359,210 @@
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F303xC */
+#if defined(STM32F302xE)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t Tim20ClockSelection; /*!< TIM20 clock source
+ This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
+
+ uint32_t USBClockSelection; /*!< USB clock source
+ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F303xE */
+
+#if defined(STM32F398xx)
+typedef struct
+{
+ uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+
+ uint32_t Usart2ClockSelection; /*!< USART2 clock source
+ This parameter can be a value of @ref RCC_USART2_Clock_Source */
+
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCC_USART3_Clock_Source */
+
+ uint32_t Uart4ClockSelection; /*!< UART4 clock source
+ This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
+
+ uint32_t Uart5ClockSelection; /*!< UART5 clock source
+ This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
+
+ uint32_t I2c1ClockSelection; /*!< I2C1 clock source
+ This parameter can be a value of @ref RCC_I2C1_Clock_Source */
+
+ uint32_t I2c2ClockSelection; /*!< I2C2 clock source
+ This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
+
+ uint32_t I2c3ClockSelection; /*!< I2C3 clock source
+ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
+
+ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
+ This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
+
+ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
+ This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
+
+ uint32_t I2sClockSelection; /*!< I2S clock source
+ This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
+
+ uint32_t Tim1ClockSelection; /*!< TIM1 clock source
+ This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
+
+ uint32_t Tim2ClockSelection; /*!< TIM2 clock source
+ This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
+
+ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
+ This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
+
+ uint32_t Tim8ClockSelection; /*!< TIM8 clock source
+ This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
+
+ uint32_t Tim15ClockSelection; /*!< TIM15 clock source
+ This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
+
+ uint32_t Tim16ClockSelection; /*!< TIM16 clock source
+ This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
+
+ uint32_t Tim17ClockSelection; /*!< TIM17 clock source
+ This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
+
+ uint32_t Tim20ClockSelection; /*!< TIM20 clock source
+ This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
+
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F398xx */
+
#if defined(STM32F358xx)
typedef struct
{
@@ -310,7 +620,7 @@
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< USART2 clock source
@@ -340,7 +650,7 @@
uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
This parameter can be a value of @ref RCC_RTC_Clock_Source */
- uint32_t Usart1ClockSelection; /*!< USART1 clock source
+ uint32_t Usart1ClockSelection; /*!< USART1 clock source
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< USART2 clock source
@@ -374,7 +684,7 @@
This parameter can be a value of @ref RCC_RTC_Clock_Source */
uint32_t Usart1ClockSelection; /*!< USART1 clock source
- This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
+ This parameter can be a value of @ref RCC_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< USART2 clock source
This parameter can be a value of @ref RCC_USART2_Clock_Source */
@@ -469,12 +779,172 @@
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F378xx */
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants
+/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
+ * @{
+ */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F334x8) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
+ * @{
+ */
+#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
+#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
+#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
+
+#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F334x8 */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
+ * @{
+ */
+#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
+#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
+#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
+
+#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+ /* STM32F303x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
* @{
*/
-
-/** @defgroup RCCEx_Periph_Clock_Selection
+#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
+ ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
+ ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
+ ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
+ ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
+ ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
+ ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
+ ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
+ * @{
+ */
+
+#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
+#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
+#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
+#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
+#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
+#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
+#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
+#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
+#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
+#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
+#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
+#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
+#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
+#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
+#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
+#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
+
+#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
+ ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
* @{
*/
#if defined(STM32F301x8) || defined(STM32F318xx)
@@ -572,6 +1042,106 @@
RCC_PERIPHCLK_USB))
#endif /* STM32F303xC */
+#if defined(STM32F302xE)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
+ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17))
+#endif /* STM32F302xE */
+
+#if defined(STM32F303xE)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
+ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
+ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
+ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
+#endif /* STM32F303xE */
+
+#if defined(STM32F398xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
+#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
+#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
+#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
+#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
+#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
+#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
+#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
+#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
+#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
+#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
+ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
+ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
+ RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
+ RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
+ RCC_PERIPHCLK_TIM20))
+#endif /* STM32F398xx */
+
#if defined(STM32F358xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
@@ -680,7 +1250,7 @@
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup RCCEx_USART1_Clock_Source
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
@@ -696,7 +1266,7 @@
* @}
*/
-/** @defgroup RCCEx_I2C2_Clock_Source
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
* @{
*/
#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
@@ -708,7 +1278,7 @@
* @}
*/
-/** @defgroup RCCEx_I2C3_Clock_Source
+/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
* @{
*/
#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
@@ -720,7 +1290,7 @@
* @}
*/
-/** @defgroup RCCEx_ADC1_Clock_Source
+/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
* @{
*/
#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
@@ -748,7 +1318,7 @@
* @}
*/
-/** @defgroup RCCEx_I2S_Clock_Source
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
@@ -760,7 +1330,7 @@
* @}
*/
-/** @defgroup RCCEx_TIM1_Clock_Source
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
* @{
*/
#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
@@ -772,7 +1342,7 @@
* @}
*/
-/** @defgroup RCCEx_TIM15_Clock_Source
+/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
* @{
*/
#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
@@ -784,7 +1354,7 @@
* @}
*/
-/** @defgroup RCCEx_TIM16_Clock_Source
+/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
* @{
*/
#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
@@ -796,7 +1366,7 @@
* @}
*/
-/** @defgroup RCCEx_TIM17_Clock_Source
+/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
* @{
*/
#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
@@ -812,7 +1382,7 @@
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-/** @defgroup RCCEx_USART1_Clock_Source
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
@@ -828,7 +1398,7 @@
* @}
*/
-/** @defgroup RCCEx_I2C2_Clock_Source
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
* @{
*/
#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
@@ -840,7 +1410,7 @@
* @}
*/
-/** @defgroup RCCEx_ADC12_Clock_Source
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
* @{
*/
@@ -870,7 +1440,7 @@
* @}
*/
-/** @defgroup RCCEx_I2S_Clock_Source
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
@@ -881,7 +1451,7 @@
/**
* @}
*/
-/** @defgroup RCCEx_TIM1_Clock_Source
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
* @{
*/
#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
@@ -893,7 +1463,7 @@
* @}
*/
-/** @defgroup RCCEx_UART4_Clock_Source
+/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
* @{
*/
#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
@@ -909,7 +1479,7 @@
* @}
*/
-/** @defgroup RCCEx_UART5_Clock_Source
+/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
* @{
*/
#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
@@ -927,9 +1497,9 @@
#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-#if defined(STM32F303xC) || defined(STM32F358xx)
-
-/** @defgroup RCCEx_USART1_Clock_Source
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
@@ -945,7 +1515,196 @@
* @}
*/
-/** @defgroup RCCEx_ADC34_Clock_Source
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
+ * @{
+ */
+#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
+#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
+
+#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
+ * @{
+ */
+#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
+#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
+
+#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
+ * @{
+ */
+
+/* ADC1 & ADC2 */
+#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
+#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
+#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
+#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
+#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
+#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
+#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
+#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
+#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
+#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
+#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
+#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
+#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
+
+#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
+ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
+ * @{
+ */
+#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
+#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
+
+#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
+ * @{
+ */
+#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
+#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
+
+#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM1CLK_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
+ * @{
+ */
+#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
+#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
+
+#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM2CLK_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
+ * @{
+ */
+#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
+#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
+
+#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM34CLK_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
+ * @{
+ */
+#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
+#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
+
+#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM15CLK_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
+ * @{
+ */
+#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
+#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
+
+#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM16CLK_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
+ * @{
+ */
+#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
+#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
+
+#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM17CLK_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
+ * @{
+ */
+#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
+#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
+#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
+#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
+
+#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
+ * @{
+ */
+#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
+#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
+#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
+#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
+
+#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
+ * @{
+ */
+#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
+#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
+
+#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
+ ((SOURCE) == RCC_TIM20CLK_PLLCLK))
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
* @{
*/
@@ -975,7 +1734,7 @@
* @}
*/
-/** @defgroup RCCEx_TIM8_Clock_Source
+/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
* @{
*/
#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
@@ -987,11 +1746,11 @@
* @}
*/
-#endif /* STM32F303xC || STM32F358xx */
+#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-/** @defgroup RCCEx_USART1_Clock_Source
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
@@ -1007,7 +1766,7 @@
* @}
*/
-/** @defgroup RCCEx_ADC12_Clock_Source
+/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
* @{
*/
/* ADC1 & ADC2 */
@@ -1036,7 +1795,7 @@
* @}
*/
-/** @defgroup RCCEx_TIM1_Clock_Source
+/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
* @{
*/
#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
@@ -1052,7 +1811,7 @@
#if defined(STM32F334x8)
-/** @defgroup RCCEx_HRTIM1_Clock_Source
+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
* @{
*/
#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
@@ -1068,7 +1827,7 @@
#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup RCCEx_USART1_Clock_Source
+/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
@@ -1084,7 +1843,7 @@
* @}
*/
-/** @defgroup RCCEx_I2C2_Clock_Source
+/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
* @{
*/
#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
@@ -1096,7 +1855,7 @@
* @}
*/
-/** @defgroup RCCEx_ADC1_Clock_Source
+/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
* @{
*/
@@ -1112,7 +1871,7 @@
* @}
*/
-/** @defgroup RCCEx_CEC_Clock_Source
+/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
* @{
*/
#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
@@ -1124,7 +1883,7 @@
* @}
*/
-/** @defgroup RCCEx_SDADC_Clock_Prescaler
+/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
* @{
*/
#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
@@ -1160,8 +1919,11 @@
#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
-/** @defgroup RCCEx_USB_Clock_Source
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
* @{
*/
#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
@@ -1173,11 +1935,14 @@
* @}
*/
-#endif /* STM32F302x8 || STM32F302xC || STM32F303xC || STM32F373xC */
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup RCCEx_MCOx_Clock_Prescaler
+/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
* @{
*/
#define RCC_MCO_NODIV ((uint32_t)0x00000000)
@@ -1186,13 +1951,14 @@
/**
* @}
*/
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
- /* STM32F373xC || STM32F378xx */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F373xC || STM32F378xx */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
-/** @defgroup RCCEx_MCOx_Clock_Prescaler
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
* @{
*/
#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
@@ -1212,18 +1978,100 @@
* @}
*/
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F303x8 || STM32F334x8 || STM32F328xx */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Enable or disable the AHB peripheral clock.
+/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
+ * @{
+ */
+
+/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+/** @brief Macro to configure the PLL clock source, multiplication and division factors.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
+ * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
+ do { \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
+ } while(0)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/** @brief Macro to configure the PLL clock source and multiplication factor.
+ * @note This macro must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+/**
+ * @}
+ */
+
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
+ * @note Predivision factor can not be changed if PLL is used as system clock
+ * In this case, you have to select another source of the system clock, disable the PLL and
+ * then change the HSE predivision factor.
+ * @param __HSEPredivValue__: specifies the division value applied to HSE.
+ * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
+ */
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
+/**
+ * @}
+ */
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+ /* STM32F373xC || STM32F378xx */
+
+/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
+ * @brief Enable or disable the AHB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define __ADC1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC1EN))
@@ -1231,7 +2079,8 @@
#define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
#define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
@@ -1245,13 +2094,16 @@
/* Aliases for STM32 F3 compatibility */
#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
#define __ADC34_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC34EN))
#define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
-#endif /* STM32F303xC || STM32F358xx */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
@@ -1273,10 +2125,25 @@
#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
#endif /* STM32F373xC || STM32F378xx */
-/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __FMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FMCEN))
+#define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN))
+#define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN))
+
+#define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
+#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
+#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
+ * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
@@ -1290,7 +2157,8 @@
#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
#define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
@@ -1306,7 +2174,8 @@
#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
@@ -1344,20 +2213,29 @@
#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F334x8) || defined(STM32F328xx) || \
- defined(STM32F373xC) || defined(STM32F378xx)
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F373xC) || defined(STM32F378xx)
#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#endif /* STM32F303x8 || STM32F303xC || STM32F358xx || STM32F334x8 || STM32F328xx || STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302x8) || defined(STM32F302xC) || \
- defined(STM32F303xC) || defined(STM32F373xC)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F302x8 || STM32F302xC || STM32F303xC|| STM32F373xC */
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
#if !defined(STM32F301x8)
#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
@@ -1365,22 +2243,37 @@
#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
#endif /* STM32F301x8*/
-/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
+
+#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
+ * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
#define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#endif /* STM32F303xC || STM32F358xx */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
@@ -1410,17 +2303,37 @@
#define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
-
-/** @brief Force or release AHB peripheral reset.
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
+
+#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __TIM20_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM20EN))
+
+#define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
+#endif /* STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
+ * @brief Force or release AHB peripheral reset.
+ * @{
*/
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define __ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
@@ -1428,7 +2341,8 @@
#define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
#define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
/* Aliases for STM32 F3 compatibility */
@@ -1440,13 +2354,16 @@
/* Aliases for STM32 F3 compatibility */
#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
#define __ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
#define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
-#endif /* STM32F303xC || STM32F358xx */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
@@ -1466,7 +2383,22 @@
#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
#endif /* STM32F373xC || STM32F378xx */
-/** @brief Force or release APB1 peripheral reset.
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
+#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
+#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
+
+#define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
+#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
+#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
+ * @brief Force or release APB1 peripheral reset.
+ * @{
*/
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -1480,7 +2412,8 @@
#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -1496,7 +2429,8 @@
#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
@@ -1534,20 +2468,29 @@
#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F303x8) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F334x8) || defined(STM32F328xx) || \
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#endif /* STM32F303x8 || STM32F303xC || STM32F358xx || STM32F334x8 || STM32F328xx || STM32F373xC || STM32F378xx */
-
-#if defined(STM32F302x8) || defined(STM32F302xC) || \
- defined(STM32F303xC) || defined(STM32F373xC)
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F302x8 || STM32F302xC || STM32F303xC|| STM32F373xC */
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
#if !defined(STM32F301x8)
#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
@@ -1555,19 +2498,34 @@
#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
#endif /* STM32F301x8*/
-/** @brief Force or release APB2 peripheral reset.
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+/**
+ * @}
*/
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
+ * @brief Force or release APB2 peripheral reset.
+ * @{
+ */
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
#define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#endif /* STM32F303xC || STM32F358xx */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
@@ -1597,17 +2555,38 @@
#define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+#define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+
+#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define __TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
+
+#define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
+#endif /* STM32F303xE || STM32F398xx */
+
+/**
+ * @}
+ */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
* @param __I2C2CLKSource__: specifies the I2C2 clock source.
@@ -1641,6 +2620,13 @@
*/
#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
/** @brief Macro to configure the TIM1 clock (TIM1CLK).
* @param __TIM1CLKSource__: specifies the TIM1 clock source.
* This parameter can be one of the following values:
@@ -1709,6 +2695,13 @@
*/
#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
+ * @{
+ */
/** @brief Macro to configure the I2S clock source (I2SCLK).
* @note This function must be called before enabling the I2S APB clock.
* @param __I2SCLKSource__: specifies the I2S clock source.
@@ -1727,6 +2720,13 @@
* used as I2S clock source
*/
#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
/** @brief Macro to configure the ADC1 clock (ADC1CLK).
* @param __ADC1CLKSource__: specifies the ADC1 clock source.
@@ -1765,10 +2765,17 @@
* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
*/
#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
+/**
+ * @}
+ */
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
* @param __I2C2CLKSource__: specifies the I2C2 clock source.
@@ -1785,6 +2792,13 @@
* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
*/
#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
@@ -1823,6 +2837,13 @@
* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
*/
#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
/** @brief Macro to configure the TIM1 clock (TIM1CLK).
* @param __TIM1CLKSource__: specifies the TIM1 clock source.
@@ -1840,6 +2861,13 @@
* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
*/
#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
+ * @{
+ */
/** @brief Macro to configure the I2S clock source (I2SCLK).
* @note This function must be called before enabling the I2S APB clock.
@@ -1859,6 +2887,13 @@
* used as I2S clock source
*/
#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
+ * @{
+ */
/** @brief Macro to configure the UART4 clock (UART4CLK).
* @param __UART4CLKSource__: specifies the UART4 clock source.
@@ -1899,10 +2934,17 @@
* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
*/
#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
-
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
-
-#if defined(STM32F303xC) || defined(STM32F358xx)
+/**
+ * @}
+ */
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F302xC || STM32F303xC || STM32F358xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
* @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
@@ -1941,6 +2983,13 @@
* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
*/
#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
/** @brief Macro to configure the TIM8 clock (TIM8CLK).
* @param __TIM8CLKSource__: specifies the TIM8 clock source.
@@ -1959,9 +3008,16 @@
*/
#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
-#endif /* STM32F303xC || STM32F358xx */
+/**
+ * @}
+ */
+#endif /* STM32F303xE || STM32F398xx || */
+ /* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
@@ -2000,7 +3056,13 @@
* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
*/
#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
-
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
/** @brief Macro to configure the TIM1 clock (TIM1CLK).
* @param __TIM1CLKSource__: specifies the TIM1 clock source.
* This parameter can be one of the following values:
@@ -2017,11 +3079,15 @@
* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
*/
#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
-
+/**
+ * @}
+ */
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
#if defined(STM32F334x8)
-
+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
+ * @{
+ */
/** @brief Macro to configure the HRTIM1 clock.
* @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
* This parameter can be one of the following values:
@@ -2037,11 +3103,15 @@
* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
*/
#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
-
+/**
+ * @}
+ */
#endif /* STM32F334x8 */
#if defined(STM32F373xC) || defined(STM32F378xx)
-
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
* @param __I2C2CLKSource__: specifies the I2C2 clock source.
* This parameter can be one of the following values:
@@ -2057,7 +3127,13 @@
* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
*/
#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
-
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
+ * @{
+ */
/** @brief Macro to configure the ADC1 clock (ADC1CLK).
* @param __ADC1CLKSource__: specifies the ADC1 clock source.
* This parameter can be one of the following values:
@@ -2077,7 +3153,13 @@
* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
*/
#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
-
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
+ * @{
+ */
/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
* @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
* This parameter can be one of the following values:
@@ -2123,7 +3205,13 @@
* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
*/
#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
-
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
+ * @{
+ */
/** @brief Macro to configure the CEC clock.
* @param __CECCLKSource__: specifies the CEC clock source.
* This parameter can be one of the following values:
@@ -2139,11 +3227,20 @@
* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
*/
#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
+/**
+ * @}
+ */
#endif /* STM32F373xC || STM32F378xx */
-#if defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F373xC)
-
+#if defined(STM32F302xE) || defined(STM32F303xE) || \
+ defined(STM32F302xC) || defined(STM32F303xC) || \
+ defined(STM32F302x8) || \
+ defined(STM32F373xC)
+
+/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
+ * @{
+ */
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
* This parameter can be one of the following values:
@@ -2159,12 +3256,22 @@
* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
-
-#endif /* STM32F302x8 || STM32F302xC || STM32F303xC || STM32F373xC */
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || */
+ /* STM32F302xC || STM32F303xC || */
+ /* STM32F302x8 || */
+ /* STM32F373xC */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
+ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
/** @brief macro to configure the MCO clock.
* @param __MCOCLKSource__: specifies the MCO clock source.
* This parameter can be one of the following values:
@@ -2180,20 +3287,186 @@
*/
#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
+/**
+ * @}
+ */
#else
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+ * @{
+ */
#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
-
-#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || STM32F303x8 || STM32F334x8 || STM32F328xx */
+/**
+ * @}
+ */
+
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
+ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F301x8 || STM32F302x8 || STM32F318xx */
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+
+/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the I2C3 clock (I2C3CLK).
+ * @param __I2C3CLKSource__: specifies the I2C3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
+
+/** @brief Macro to get the I2C3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
+ * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+ */
+#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM2 clock (TIM2CLK).
+ * @param __TIM2CLKSource__: specifies the TIM2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
+ * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
+ */
+#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
+
+/** @brief Macro to get the TIM2 clock (TIM2CLK).
+ * @retval The clock source can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
+ * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
+ */
+#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
+
+/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
+ * @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
+ * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
+ */
+#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
+
+/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
+ * @retval The clock source can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
+ * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
+ */
+#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
+
+/** @brief Macro to configure the TIM15 clock (TIM15CLK).
+ * @param __TIM15CLKSource__: specifies the TIM15 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
+ * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
+
+/** @brief Macro to get the TIM15 clock (TIM15CLK).
+ * @retval The clock source can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
+ * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
+ */
+#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
+
+/** @brief Macro to configure the TIM16 clock (TIM16CLK).
+ * @param __TIM16CLKSource__: specifies the TIM16 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
+ * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
+
+/** @brief Macro to get the TIM16 clock (TIM16CLK).
+ * @retval The clock source can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
+ * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
+ */
+#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
+
+/** @brief Macro to configure the TIM17 clock (TIM17CLK).
+ * @param __TIM17CLKSource__: specifies the TIM17 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
+ * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
+
+/** @brief Macro to get the TIM17 clock (TIM17CLK).
+ * @retval The clock source can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
+ * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
+ */
+#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
+
+/**
+ * @}
+ */
+
+#endif /* STM32f302xE || STM32f303xE || STM32F398xx */
+
+#if defined(STM32F303xE) || defined(STM32F398xx)
+/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
+ * @{
+ */
+/** @brief Macro to configure the TIM20 clock (TIM20CLK).
+ * @param __TIM20CLKSource__: specifies the TIM20 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
+ * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
+ */
+#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
+
+/** @brief Macro to get the TIM20 clock (TIM20CLK).
+ * @retval The clock source can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
+ * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
+ */
+#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
+
+/**
+ * @}
+ */
+#endif /* STM32f303xE || STM32F398xx */
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+/**
+ * @}
+ */
/**
* @}
@@ -2203,6 +3476,9 @@
* @}
*/
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif