Class library for internal ADC and DAC connected by SPI. This library support clock generator using TIM3 for switched-capacitor filter to smooth output signal of DAC. This library includes derivative class to support interrupt occured in end of AD conversion. Validated for ST Nucleo F401RE, F411RE. 内蔵 ADC と,SPI 接続の DAC のためのクラスライブラリ.DAC の出力信号を平滑化するためのスイッチトキャパシタフィルタ用のクロックは TIM3 を使用.ST Nucleo F401RE,F411RE で動作を確認.
Dependents: UITDSP_ADDA_Example UIT2_MovingAv_Intr UIT2_VariableFIR UIT2_VowelSynthesizer ... more
ADC_Interrupt.hpp
- Committer:
- MikamiUitOpen
- Date:
- 2015-04-19
- Revision:
- 7:14cdca8b48f8
- Parent:
- 4:03c4518de836
File content as of revision 7:14cdca8b48f8:
//------------------------------------------------------ // Derived class of ADC_Base for use interrupt // // 2015/04/19, Copyright (c) 2015 MIKAMI, Naoki //------------------------------------------------------ #ifndef ADC_INTERRUPT_HPP #define ADC_INTERRUPT_HPP #include "ADC_BuiltIn.hpp" namespace Mikami { class ADC_Intr : public ADC_BuiltIn { private: // for inhibition of copy constructor ADC_Intr(const ADC_Intr&); // for inhibition of substitute operator ADC_Intr& operator=(const ADC_Intr&); public: ADC_Intr(PinName pin1, int frequency, PinName pin2 = NC, PinName pin3 = NC) : ADC_BuiltIn(pin1, frequency, pin2, pin3) { myAdc_->CR1 |= ADC_CR1_EOCIE; } // Interrupt enable // Set interrupt vector and enable IRQ of ADC void SetIntrVec(void (*Func)()) { NVIC_SetVector(ADC_IRQn, (uint32_t)Func); // See "cmsis_nvic.h" NVIC_EnableIRQ(ADC_IRQn); // See "core_cm4.h" } // Read ADC, range: [0, 0x0FFF] virtual uint16_t Read_u16() { return myAdc_->DR; } // Read ADC, range: [0, 0x0FFF] virtual uint16_t ReadWait_u16() { WaitDone(); return myAdc_->DR; } // Read ADC, range: [-1.0f, 1.0f] virtual float Read() { return AMP_*((int16_t)myAdc_->DR - 2048); } // Clear pending IRQ and enable IRQ void ClearPending_EnableIRQ() { NVIC_ClearPendingIRQ(ADC_IRQn); NVIC_EnableIRQ(ADC_IRQn); } // Software start with disable IRQ void SoftStart() { NVIC_DisableIRQ(ADC_IRQn); myAdc_->CR2 |= ADC_CR2_SWSTART; } }; } #endif // ADC_INTERRUPT_HPP