Martin Johnson
/
STM32F3-Discovery
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Dependents: Space_Invaders_Demo neopixels gpio_test_stm32f3_discovery gpio_test_systimer ... more
Embed:
(wiki syntax)
Show/hide line numbers
stm32f30x_spi.c
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_spi.c 00004 * @author MCD Application Team 00005 * @version V1.2.3 00006 * @date 10-July-2015 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the Serial peripheral interface (SPI): 00009 * + Initialization and Configuration 00010 * + Data transfers functions 00011 * + Hardware CRC Calculation 00012 * + DMA transfers management 00013 * + Interrupts and flags management 00014 * 00015 * @verbatim 00016 00017 00018 =============================================================================== 00019 ##### How to use this driver ##### 00020 =============================================================================== 00021 [..] 00022 (#) Enable peripheral clock using RCC_APBPeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) 00023 function for SPI1 or using RCC_APBPeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) 00024 function for SPI2. 00025 (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd() 00026 function. 00027 (#) Peripherals alternate function: 00028 (++) Connect the pin to the desired peripherals' Alternate 00029 Function (AF) using GPIO_PinAFConfig() function. 00030 (++) Configure the desired pin in alternate function by: 00031 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF. 00032 (++) Select the type, pull-up/pull-down and output speed via 00033 GPIO_PuPd, GPIO_OType and GPIO_Speed members. 00034 (++) Call GPIO_Init() function. 00035 (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 00036 Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() 00037 function in SPI mode. In I2S mode, program the Mode, Standard, Data Format, 00038 MCLK Output, Audio frequency and Polarity using I2S_Init() function. 00039 (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select 00040 at which threshold the RXNE event is generated. 00041 (#) Enable the NVIC and the corresponding interrupt using the function 00042 SPI_I2S_ITConfig() if you need to use interrupt mode. 00043 (#) When using the DMA mode 00044 (++) Configure the DMA using DMA_Init() function. 00045 (++) Active the needed channel Request using SPI_I2S_DMACmd() function. 00046 (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using 00047 I2S_Cmd(). 00048 (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 00049 (#) Optionally you can enable/configure the following parameters without 00050 re-initialization (i.e there is no need to call again SPI_Init() function): 00051 (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) 00052 is programmed as Data direction parameter using the SPI_Init() function 00053 it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx 00054 using the SPI_BiDirectionalLineConfig() function. 00055 (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 00056 using the SPI_Init() function it can be possible to manage the 00057 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. 00058 (++) Reconfigure the data size using the SPI_DataSizeConfig() function. 00059 (++) Enable or disable the SS output using the SPI_SSOutputCmd() function. 00060 (#) To use the CRC Hardware calculation feature refer to the Peripheral 00061 CRC hardware Calculation subsection. 00062 [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI 00063 peripheral is able to manage sending and receiving data simultaneously 00064 using two data lines. Each SPI peripheral has an extended block called I2Sxext 00065 (ie. I2S2ext for SPI2 and I2S3ext for SPI3). 00066 The extension block is not a full SPI IP, it is used only as I2S slave to 00067 implement full duplex mode. The extension block uses the same clock sources 00068 as its master. 00069 To configure I2S full duplex you have to: 00070 (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. 00071 (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to 00072 I2S_Init() function. 00073 (#) Call I2S_Cmd() for SPIx then for its extended block. 00074 (#) Configure interrupts or DMA requests and to get/clear flag status, 00075 use I2Sxext instance for the extension block. 00076 [..] Functions that can be called with I2Sxext instances are: 00077 I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData16(), SPI_I2S_SendData16(), 00078 SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), 00079 SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). 00080 [..] Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): 00081 [..] RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); 00082 I2S_StructInit(&I2SInitStruct); 00083 I2SInitStruct.Mode = I2S_Mode_MasterTx; 00084 I2S_Init(SPI3, &I2SInitStruct); 00085 I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) 00086 I2S_Cmd(SPI3, ENABLE); 00087 I2S_Cmd(SPI3ext, ENABLE); 00088 ... 00089 while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) 00090 {} 00091 SPI_I2S_SendData16(SPI3, txdata[i]); 00092 ... 00093 while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) 00094 {} 00095 rxdata[i] = SPI_I2S_ReceiveData16(I2S3ext); 00096 ... 00097 [..] 00098 (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() 00099 just after calling the function SPI_Init(). 00100 00101 @endverbatim 00102 ****************************************************************************** 00103 * @attention 00104 * 00105 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 00106 * 00107 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00108 * You may not use this file except in compliance with the License. 00109 * You may obtain a copy of the License at: 00110 * 00111 * http://www.st.com/software_license_agreement_liberty_v2 00112 * 00113 * Unless required by applicable law or agreed to in writing, software 00114 * distributed under the License is distributed on an "AS IS" BASIS, 00115 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00116 * See the License for the specific language governing permissions and 00117 * limitations under the License. 00118 * 00119 ****************************************************************************** 00120 */ 00121 00122 /* Includes ------------------------------------------------------------------*/ 00123 #include "stm32f30x_spi.h" 00124 #include "stm32f30x_rcc.h" 00125 00126 /** @addtogroup STM32F30x_StdPeriph_Driver 00127 * @{ 00128 */ 00129 00130 /** @defgroup SPI 00131 * @brief SPI driver modules 00132 * @{ 00133 */ 00134 00135 /* Private typedef -----------------------------------------------------------*/ 00136 /* Private define ------------------------------------------------------------*/ 00137 /* SPI registers Masks */ 00138 #define CR1_CLEAR_MASK ((uint16_t)0x3040) 00139 #define CR2_LDMA_MASK ((uint16_t)0x9FFF) 00140 00141 #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) 00142 00143 /* Private macro -------------------------------------------------------------*/ 00144 /* Private variables ---------------------------------------------------------*/ 00145 /* Private function prototypes -----------------------------------------------*/ 00146 /* Private functions ---------------------------------------------------------*/ 00147 00148 /** @defgroup SPI_Private_Functions 00149 * @{ 00150 */ 00151 00152 /** @defgroup SPI_Group1 Initialization and Configuration functions 00153 * @brief Initialization and Configuration functions 00154 * 00155 @verbatim 00156 =============================================================================== 00157 ##### Initialization and Configuration functions ##### 00158 =============================================================================== 00159 [..] This section provides a set of functions allowing to initialize the SPI Direction, 00160 SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud 00161 Rate Prescaler, SPI First Bit and SPI CRC Polynomial. 00162 [..] The SPI_Init() function follows the SPI configuration procedures for Master mode 00163 and Slave mode (details for these procedures are available in reference manual). 00164 [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected, 00165 use the following function to manage the NSS bit: 00166 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 00167 [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard) 00168 is selected, use the following function to enable the NSS output feature. 00169 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00170 [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the 00171 following function: void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00172 And it can be managed by software in the SPI Motorola mode using this function: 00173 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00174 [..] This section provides also functions to initialize the I2S Mode, Standard, 00175 Data Format, MCLK Output, Audio frequency and Polarity. 00176 [..] The I2S_Init() function follows the I2S configuration procedures for Master mode 00177 and Slave mode. 00178 00179 @endverbatim 00180 * @{ 00181 */ 00182 00183 /** 00184 * @brief Deinitializes the SPIx peripheral registers to their default 00185 * reset values. 00186 * @param SPIx: To select the SPIx peripheral, where x can be: 1, 2 or 3 00187 * in SPI mode. 00188 * @retval None 00189 */ 00190 void SPI_I2S_DeInit(SPI_TypeDef* SPIx) 00191 { 00192 /* Check the parameters */ 00193 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00194 00195 if (SPIx == SPI1) 00196 { 00197 /* Enable SPI1 reset state */ 00198 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); 00199 /* Release SPI1 from reset state */ 00200 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); 00201 } 00202 else if (SPIx == SPI2) 00203 { 00204 /* Enable SPI2 reset state */ 00205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); 00206 /* Release SPI2 from reset state */ 00207 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); 00208 } 00209 else if (SPIx == SPI3) 00210 { 00211 /* Enable SPI3 reset state */ 00212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); 00213 /* Release SPI3 from reset state */ 00214 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); 00215 } 00216 else 00217 { 00218 if (SPIx == SPI4) 00219 { 00220 /* Enable SPI4 reset state */ 00221 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); 00222 /* Release SPI4 from reset state */ 00223 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); 00224 } 00225 } 00226 } 00227 00228 /** 00229 * @brief Fills each SPI_InitStruct member with its default value. 00230 * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. 00231 * @retval None 00232 */ 00233 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) 00234 { 00235 /*--------------- Reset SPI init structure parameters values -----------------*/ 00236 /* Initialize the SPI_Direction member */ 00237 SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; 00238 /* Initialize the SPI_Mode member */ 00239 SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; 00240 /* Initialize the SPI_DataSize member */ 00241 SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; 00242 /* Initialize the SPI_CPOL member */ 00243 SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; 00244 /* Initialize the SPI_CPHA member */ 00245 SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; 00246 /* Initialize the SPI_NSS member */ 00247 SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; 00248 /* Initialize the SPI_BaudRatePrescaler member */ 00249 SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; 00250 /* Initialize the SPI_FirstBit member */ 00251 SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; 00252 /* Initialize the SPI_CRCPolynomial member */ 00253 SPI_InitStruct->SPI_CRCPolynomial = 7; 00254 } 00255 00256 /** 00257 * @brief Initializes the SPIx peripheral according to the specified 00258 * parameters in the SPI_InitStruct. 00259 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00260 * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that 00261 * contains the configuration information for the specified SPI peripheral. 00262 * @retval None 00263 */ 00264 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) 00265 { 00266 uint16_t tmpreg = 0; 00267 00268 /* check the parameters */ 00269 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00270 00271 /* Check the SPI parameters */ 00272 assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); 00273 assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); 00274 assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); 00275 assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); 00276 assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); 00277 assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); 00278 assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); 00279 assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); 00280 assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); 00281 00282 /* Configuring the SPI in master mode */ 00283 if(SPI_InitStruct->SPI_Mode == SPI_Mode_Master) 00284 { 00285 /*---------------------------- SPIx CR1 Configuration ------------------------*/ 00286 /* Get the SPIx CR1 value */ 00287 tmpreg = SPIx->CR1; 00288 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ 00289 tmpreg &= CR1_CLEAR_MASK; 00290 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler 00291 master/slave mode, CPOL and CPHA */ 00292 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ 00293 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ 00294 /* Set LSBFirst bit according to SPI_FirstBit value */ 00295 /* Set BR bits according to SPI_BaudRatePrescaler value */ 00296 /* Set CPOL bit according to SPI_CPOL value */ 00297 /* Set CPHA bit according to SPI_CPHA value */ 00298 tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) | 00299 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) | 00300 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) | 00301 SPI_InitStruct->SPI_FirstBit))); 00302 /* Write to SPIx CR1 */ 00303 SPIx->CR1 = tmpreg; 00304 /*-------------------------Data Size Configuration -----------------------*/ 00305 /* Get the SPIx CR2 value */ 00306 tmpreg = SPIx->CR2; 00307 /* Clear DS[3:0] bits */ 00308 tmpreg &= (uint16_t)~SPI_CR2_DS; 00309 /* Configure SPIx: Data Size */ 00310 tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); 00311 /* Write to SPIx CR2 */ 00312 SPIx->CR2 = tmpreg; 00313 } 00314 /* Configuring the SPI in slave mode */ 00315 else 00316 { 00317 /*---------------------------- Data size Configuration -----------------------*/ 00318 /* Get the SPIx CR2 value */ 00319 tmpreg = SPIx->CR2; 00320 /* Clear DS[3:0] bits */ 00321 tmpreg &= (uint16_t)~SPI_CR2_DS; 00322 /* Configure SPIx: Data Size */ 00323 tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); 00324 /* Write to SPIx CR2 */ 00325 SPIx->CR2 = tmpreg; 00326 /*---------------------------- SPIx CR1 Configuration ------------------------*/ 00327 /* Get the SPIx CR1 value */ 00328 tmpreg = SPIx->CR1; 00329 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ 00330 tmpreg &= CR1_CLEAR_MASK; 00331 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler 00332 master/salve mode, CPOL and CPHA */ 00333 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ 00334 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ 00335 /* Set LSBFirst bit according to SPI_FirstBit value */ 00336 /* Set BR bits according to SPI_BaudRatePrescaler value */ 00337 /* Set CPOL bit according to SPI_CPOL value */ 00338 /* Set CPHA bit according to SPI_CPHA value */ 00339 tmpreg |= (uint16_t)((uint16_t)(SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode) | 00340 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA) | 00341 (uint16_t)((uint16_t)(SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler) | 00342 SPI_InitStruct->SPI_FirstBit))); 00343 00344 /* Write to SPIx CR1 */ 00345 SPIx->CR1 = tmpreg; 00346 } 00347 00348 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ 00349 SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); 00350 00351 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ 00352 /* Write to SPIx CRCPOLY */ 00353 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; 00354 } 00355 00356 /** 00357 * @brief Fills each I2S_InitStruct member with its default value. 00358 * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. 00359 * @retval None 00360 */ 00361 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) 00362 { 00363 /*--------------- Reset I2S init structure parameters values -----------------*/ 00364 /* Initialize the I2S_Mode member */ 00365 I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; 00366 00367 /* Initialize the I2S_Standard member */ 00368 I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; 00369 00370 /* Initialize the I2S_DataFormat member */ 00371 I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; 00372 00373 /* Initialize the I2S_MCLKOutput member */ 00374 I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; 00375 00376 /* Initialize the I2S_AudioFreq member */ 00377 I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; 00378 00379 /* Initialize the I2S_CPOL member */ 00380 I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; 00381 } 00382 00383 /** 00384 * @brief Initializes the SPIx peripheral according to the specified 00385 * parameters in the I2S_InitStruct. 00386 * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 00387 * in I2S mode. 00388 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that 00389 * contains the configuration information for the specified SPI peripheral 00390 * configured in I2S mode. 00391 * @note 00392 * The function calculates the optimal prescaler needed to obtain the most 00393 * accurate audio frequency (depending on the I2S clock source, the PLL values 00394 * and the product configuration). But in case the prescaler value is greater 00395 * than 511, the default value (0x02) will be configured instead. 00396 * @retval None 00397 */ 00398 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) 00399 { 00400 uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; 00401 uint32_t tmp = 0; 00402 RCC_ClocksTypeDef RCC_Clocks; 00403 uint32_t sourceclock = 0; 00404 00405 /* Check the I2S parameters */ 00406 assert_param(IS_SPI_23_PERIPH(SPIx)); 00407 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); 00408 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); 00409 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); 00410 assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); 00411 assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); 00412 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); 00413 00414 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ 00415 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ 00416 SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; 00417 SPIx->I2SPR = 0x0002; 00418 00419 /* Get the I2SCFGR register value */ 00420 tmpreg = SPIx->I2SCFGR; 00421 00422 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ 00423 if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) 00424 { 00425 i2sodd = (uint16_t)0; 00426 i2sdiv = (uint16_t)2; 00427 } 00428 /* If the requested audio frequency is not the default, compute the prescaler */ 00429 else 00430 { 00431 /* Check the frame length (For the Prescaler computing) */ 00432 if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) 00433 { 00434 /* Packet length is 16 bits */ 00435 packetlength = 1; 00436 } 00437 else 00438 { 00439 /* Packet length is 32 bits */ 00440 packetlength = 2; 00441 } 00442 00443 /* I2S Clock source is System clock: Get System Clock frequency */ 00444 RCC_GetClocksFreq(&RCC_Clocks); 00445 00446 /* Get the source clock value: based on System Clock value */ 00447 sourceclock = RCC_Clocks.SYSCLK_Frequency; 00448 00449 /* Compute the Real divider depending on the MCLK output state with a floating point */ 00450 if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) 00451 { 00452 /* MCLK output is enabled */ 00453 tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); 00454 } 00455 else 00456 { 00457 /* MCLK output is disabled */ 00458 tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); 00459 } 00460 00461 /* Remove the floating point */ 00462 tmp = tmp / 10; 00463 00464 /* Check the parity of the divider */ 00465 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); 00466 00467 /* Compute the i2sdiv prescaler */ 00468 i2sdiv = (uint16_t)((tmp - i2sodd) / 2); 00469 00470 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ 00471 i2sodd = (uint16_t) (i2sodd << 8); 00472 } 00473 00474 /* Test if the divider is 1 or 0 or greater than 0xFF */ 00475 if ((i2sdiv < 2) || (i2sdiv > 0xFF)) 00476 { 00477 /* Set the default values */ 00478 i2sdiv = 2; 00479 i2sodd = 0; 00480 } 00481 00482 /* Write to SPIx I2SPR register the computed value */ 00483 SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); 00484 00485 /* Configure the I2S with the SPI_InitStruct values */ 00486 tmpreg |= (uint16_t)((uint16_t)(SPI_I2SCFGR_I2SMOD | I2S_InitStruct->I2S_Mode) | \ 00487 (uint16_t)((uint16_t)((uint16_t)(I2S_InitStruct->I2S_Standard |I2S_InitStruct->I2S_DataFormat) |\ 00488 I2S_InitStruct->I2S_CPOL))); 00489 00490 /* Write to SPIx I2SCFGR */ 00491 SPIx->I2SCFGR = tmpreg; 00492 } 00493 00494 /** 00495 * @brief Enables or disables the specified SPI peripheral. 00496 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00497 * @param NewState: new state of the SPIx peripheral. 00498 * This parameter can be: ENABLE or DISABLE. 00499 * @retval None 00500 */ 00501 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) 00502 { 00503 /* Check the parameters */ 00504 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00505 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00506 00507 if (NewState != DISABLE) 00508 { 00509 /* Enable the selected SPI peripheral */ 00510 SPIx->CR1 |= SPI_CR1_SPE; 00511 } 00512 else 00513 { 00514 /* Disable the selected SPI peripheral */ 00515 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); 00516 } 00517 } 00518 00519 /** 00520 * @brief Enables or disables the TI Mode. 00521 * @note This function can be called only after the SPI_Init() function has 00522 * been called. 00523 * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 00524 * are not taken into consideration and are configured by hardware 00525 * respectively to the TI mode requirements. 00526 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00527 * @param NewState: new state of the selected SPI TI communication mode. 00528 * This parameter can be: ENABLE or DISABLE. 00529 * @retval None 00530 */ 00531 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) 00532 { 00533 /* Check the parameters */ 00534 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00535 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00536 00537 if (NewState != DISABLE) 00538 { 00539 /* Enable the TI mode for the selected SPI peripheral */ 00540 SPIx->CR2 |= SPI_CR2_FRF; 00541 } 00542 else 00543 { 00544 /* Disable the TI mode for the selected SPI peripheral */ 00545 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); 00546 } 00547 } 00548 00549 /** 00550 * @brief Enables or disables the specified SPI peripheral (in I2S mode). 00551 * @param SPIx:To select the SPIx peripheral, where x can be: 2 or 3 in 00552 * I2S mode or I2Sxext for I2S full duplex mode. 00553 * @param NewState: new state of the SPIx peripheral. 00554 * This parameter can be: ENABLE or DISABLE. 00555 * @retval None 00556 */ 00557 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) 00558 { 00559 /* Check the parameters */ 00560 assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); 00561 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00562 if (NewState != DISABLE) 00563 { 00564 /* Enable the selected SPI peripheral in I2S mode */ 00565 SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; 00566 } 00567 else 00568 { 00569 /* Disable the selected SPI peripheral in I2S mode */ 00570 SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); 00571 } 00572 } 00573 00574 /** 00575 * @brief Configures the data size for the selected SPI. 00576 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00577 * @param SPI_DataSize: specifies the SPI data size. 00578 * For the SPIx peripheral this parameter can be one of the following values: 00579 * @arg SPI_DataSize_4b: Set data size to 4 bits 00580 * @arg SPI_DataSize_5b: Set data size to 5 bits 00581 * @arg SPI_DataSize_6b: Set data size to 6 bits 00582 * @arg SPI_DataSize_7b: Set data size to 7 bits 00583 * @arg SPI_DataSize_8b: Set data size to 8 bits 00584 * @arg SPI_DataSize_9b: Set data size to 9 bits 00585 * @arg SPI_DataSize_10b: Set data size to 10 bits 00586 * @arg SPI_DataSize_11b: Set data size to 11 bits 00587 * @arg SPI_DataSize_12b: Set data size to 12 bits 00588 * @arg SPI_DataSize_13b: Set data size to 13 bits 00589 * @arg SPI_DataSize_14b: Set data size to 14 bits 00590 * @arg SPI_DataSize_15b: Set data size to 15 bits 00591 * @arg SPI_DataSize_16b: Set data size to 16 bits 00592 * @retval None 00593 */ 00594 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) 00595 { 00596 uint16_t tmpreg = 0; 00597 00598 /* Check the parameters */ 00599 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00600 assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); 00601 /* Read the CR2 register */ 00602 tmpreg = SPIx->CR2; 00603 /* Clear DS[3:0] bits */ 00604 tmpreg &= (uint16_t)~SPI_CR2_DS; 00605 /* Set new DS[3:0] bits value */ 00606 tmpreg |= SPI_DataSize; 00607 SPIx->CR2 = tmpreg; 00608 } 00609 00610 /** 00611 * @brief Configures the FIFO reception threshold for the selected SPI. 00612 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00613 * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. 00614 * This parameter can be one of the following values: 00615 * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO 00616 * level is greater or equal to 1/2. 00617 * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO 00618 * level is greater or equal to 1/4. 00619 * @retval None 00620 */ 00621 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) 00622 { 00623 /* Check the parameters */ 00624 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00625 assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); 00626 00627 /* Clear FRXTH bit */ 00628 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); 00629 00630 /* Set new FRXTH bit value */ 00631 SPIx->CR2 |= SPI_RxFIFOThreshold; 00632 } 00633 00634 /** 00635 * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. 00636 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00637 * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. 00638 * This parameter can be one of the following values: 00639 * @arg SPI_Direction_Tx: Selects Tx transmission direction 00640 * @arg SPI_Direction_Rx: Selects Rx receive direction 00641 * @retval None 00642 */ 00643 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) 00644 { 00645 /* Check the parameters */ 00646 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00647 assert_param(IS_SPI_DIRECTION(SPI_Direction)); 00648 if (SPI_Direction == SPI_Direction_Tx) 00649 { 00650 /* Set the Tx only mode */ 00651 SPIx->CR1 |= SPI_Direction_Tx; 00652 } 00653 else 00654 { 00655 /* Set the Rx only mode */ 00656 SPIx->CR1 &= SPI_Direction_Rx; 00657 } 00658 } 00659 00660 /** 00661 * @brief Configures internally by software the NSS pin for the selected SPI. 00662 * @note This function can be called only after the SPI_Init() function has 00663 * been called. 00664 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00665 * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. 00666 * This parameter can be one of the following values: 00667 * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally 00668 * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally 00669 * @retval None 00670 */ 00671 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) 00672 { 00673 /* Check the parameters */ 00674 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00675 assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); 00676 00677 if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) 00678 { 00679 /* Set NSS pin internally by software */ 00680 SPIx->CR1 |= SPI_NSSInternalSoft_Set; 00681 } 00682 else 00683 { 00684 /* Reset NSS pin internally by software */ 00685 SPIx->CR1 &= SPI_NSSInternalSoft_Reset; 00686 } 00687 } 00688 00689 /** 00690 * @brief Configures the full duplex mode for the I2Sx peripheral using its 00691 * extension I2Sxext according to the specified parameters in the 00692 * I2S_InitStruct. 00693 * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. 00694 * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that 00695 * contains the configuration information for the specified I2S peripheral 00696 * extension. 00697 * 00698 * @note The structure pointed by I2S_InitStruct parameter should be the same 00699 * used for the master I2S peripheral. In this case, if the master is 00700 * configured as transmitter, the slave will be receiver and vice versa. 00701 * Or you can force a different mode by modifying the field I2S_Mode to the 00702 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration. 00703 * 00704 * @note The I2S full duplex extension can be configured in slave mode only. 00705 * 00706 * @retval None 00707 */ 00708 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) 00709 { 00710 uint16_t tmpreg = 0, tmp = 0; 00711 00712 /* Check the I2S parameters */ 00713 assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); 00714 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); 00715 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); 00716 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); 00717 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); 00718 00719 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ 00720 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ 00721 I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; 00722 I2Sxext->I2SPR = 0x0002; 00723 00724 /* Get the I2SCFGR register value */ 00725 tmpreg = I2Sxext->I2SCFGR; 00726 00727 /* Get the mode to be configured for the extended I2S */ 00728 if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) 00729 { 00730 tmp = I2S_Mode_SlaveRx; 00731 } 00732 else 00733 { 00734 if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) 00735 { 00736 tmp = I2S_Mode_SlaveTx; 00737 } 00738 } 00739 00740 00741 /* Configure the I2S with the SPI_InitStruct values */ 00742 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ 00743 (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ 00744 (uint16_t)I2S_InitStruct->I2S_CPOL)))); 00745 00746 /* Write to SPIx I2SCFGR */ 00747 I2Sxext->I2SCFGR = tmpreg; 00748 } 00749 00750 /** 00751 * @brief Enables or disables the SS output for the selected SPI. 00752 * @note This function can be called only after the SPI_Init() function has 00753 * been called and the NSS hardware management mode is selected. 00754 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00755 * @param NewState: new state of the SPIx SS output. 00756 * This parameter can be: ENABLE or DISABLE. 00757 * @retval None 00758 */ 00759 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) 00760 { 00761 /* Check the parameters */ 00762 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00763 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00764 if (NewState != DISABLE) 00765 { 00766 /* Enable the selected SPI SS output */ 00767 SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; 00768 } 00769 else 00770 { 00771 /* Disable the selected SPI SS output */ 00772 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); 00773 } 00774 } 00775 00776 /** 00777 * @brief Enables or disables the NSS pulse management mode. 00778 * @note This function can be called only after the SPI_Init() function has 00779 * been called. 00780 * @note When TI mode is selected, the control bits NSSP is not taken into 00781 * consideration and are configured by hardware respectively to the 00782 * TI mode requirements. 00783 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00784 * @param NewState: new state of the NSS pulse management mode. 00785 * This parameter can be: ENABLE or DISABLE. 00786 * @retval None 00787 */ 00788 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) 00789 { 00790 /* Check the parameters */ 00791 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00792 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00793 00794 if (NewState != DISABLE) 00795 { 00796 /* Enable the NSS pulse management mode */ 00797 SPIx->CR2 |= SPI_CR2_NSSP; 00798 } 00799 else 00800 { 00801 /* Disable the NSS pulse management mode */ 00802 SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); 00803 } 00804 } 00805 00806 /** 00807 * @} 00808 */ 00809 00810 /** @defgroup SPI_Group2 Data transfers functions 00811 * @brief Data transfers functions 00812 * 00813 @verbatim 00814 =============================================================================== 00815 ##### Data transfers functions ##### 00816 =============================================================================== 00817 [..] This section provides a set of functions allowing to manage the SPI or I2S 00818 data transfers. 00819 [..] In reception, data are received and then stored into an internal Rx buffer while 00820 In transmission, data are first stored into an internal Tx buffer before being 00821 transmitted. 00822 [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() 00823 function and returns the Rx buffered value. Whereas a write access to the SPI_DR 00824 can be done using SPI_I2S_SendData() function and stores the written data into 00825 Tx buffer. 00826 00827 @endverbatim 00828 * @{ 00829 */ 00830 00831 /** 00832 * @brief Transmits a Data through the SPIx peripheral. 00833 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00834 * @param Data: Data to be transmitted. 00835 * @retval None 00836 */ 00837 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) 00838 { 00839 uint32_t spixbase = 0x00; 00840 00841 /* Check the parameters */ 00842 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00843 00844 spixbase = (uint32_t)SPIx; 00845 spixbase += 0x0C; 00846 00847 *(__IO uint8_t *) spixbase = Data; 00848 } 00849 00850 /** 00851 * @brief Transmits a Data through the SPIx/I2Sx peripheral. 00852 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 00853 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 00854 * @param Data: Data to be transmitted. 00855 * @retval None 00856 */ 00857 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data) 00858 { 00859 /* Check the parameters */ 00860 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 00861 00862 SPIx->DR = (uint16_t)Data; 00863 } 00864 00865 /** 00866 * @brief Returns the most recent received data by the SPIx peripheral. 00867 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00868 * @retval The value of the received data. 00869 */ 00870 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) 00871 { 00872 uint32_t spixbase = 0x00; 00873 00874 /* Check the parameters */ 00875 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 00876 00877 spixbase = (uint32_t)SPIx; 00878 spixbase += 0x0C; 00879 00880 return *(__IO uint8_t *) spixbase; 00881 } 00882 00883 /** 00884 * @brief Returns the most recent received data by the SPIx peripheral. 00885 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4 00886 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 00887 * @retval The value of the received data. 00888 */ 00889 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx) 00890 { 00891 /* Check the parameters */ 00892 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 00893 00894 return SPIx->DR; 00895 } 00896 /** 00897 * @} 00898 */ 00899 00900 /** @defgroup SPI_Group3 Hardware CRC Calculation functions 00901 * @brief Hardware CRC Calculation functions 00902 * 00903 @verbatim 00904 =============================================================================== 00905 ##### Hardware CRC Calculation functions ##### 00906 =============================================================================== 00907 [..] This section provides a set of functions allowing to manage the SPI CRC hardware 00908 calculation. 00909 [..] SPI communication using CRC is possible through the following procedure: 00910 (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 00911 Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() 00912 function. 00913 (#) Enable the CRC calculation using the SPI_CalculateCRC() function. 00914 (#) Enable the SPI using the SPI_Cmd() function 00915 (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 00916 SPI_TransmitCRC() function to indicate that after transmission of the last 00917 data, the CRC should be transmitted. 00918 (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT 00919 bit is reset. The CRC is also received and compared against the SPI_RXCRCR 00920 value. 00921 If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt 00922 can be generated when the SPI_I2S_IT_ERR interrupt is enabled. 00923 [..] 00924 (@) 00925 (+@) It is advised to don't read the calculate CRC values during the communication. 00926 (+@) When the SPI is in slave mode, be careful to enable CRC calculation only 00927 when the clock is stable, that is, when the clock is in the steady state. 00928 If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 00929 to the SCK slave input clock as soon as CRCEN is set, and this, whatever 00930 the value of the SPE bit. 00931 (+@) With high bitrate frequencies, be careful when transmitting the CRC. 00932 As the number of used CPU cycles has to be as low as possible in the CRC 00933 transfer phase, it is forbidden to call software functions in the CRC 00934 transmission sequence to avoid errors in the last data and CRC reception. 00935 In fact, CRCNEXT bit has to be written before the end of the transmission/reception 00936 of the last data. 00937 (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the 00938 degradation of the SPI speed performance due to CPU accesses impacting the 00939 SPI bandwidth. 00940 (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is 00941 used, the NSS pin needs to be kept low between the data phase and the CRC 00942 phase. 00943 (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC 00944 calculation takes place even if a high level is applied on the NSS pin. 00945 This may happen for example in case of a multislave environment where the 00946 communication master addresses slaves alternately. 00947 (+@) Between a slave deselection (high level on NSS) and a new slave selection 00948 (low level on NSS), the CRC value should be cleared on both master and slave 00949 sides in order to resynchronize the master and slave for their respective 00950 CRC calculation. 00951 [..] 00952 (@) To clear the CRC, follow the procedure below: 00953 (#@) Disable SPI using the SPI_Cmd() function. 00954 (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. 00955 (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. 00956 (#@) Enable SPI using the SPI_Cmd() function. 00957 00958 @endverbatim 00959 * @{ 00960 */ 00961 00962 /** 00963 * @brief Configures the CRC calculation length for the selected SPI. 00964 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00965 * @param SPI_CRCLength: specifies the SPI CRC calculation length. 00966 * This parameter can be one of the following values: 00967 * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits 00968 * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits 00969 * @retval None 00970 */ 00971 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) 00972 { 00973 /* Check the parameters */ 00974 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00975 assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); 00976 00977 /* Clear CRCL bit */ 00978 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); 00979 00980 /* Set new CRCL bit value */ 00981 SPIx->CR1 |= SPI_CRCLength; 00982 } 00983 00984 /** 00985 * @brief Enables or disables the CRC value calculation of the transferred bytes. 00986 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 00987 * @param NewState: new state of the SPIx CRC value calculation. 00988 * This parameter can be: ENABLE or DISABLE. 00989 * @retval None 00990 */ 00991 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) 00992 { 00993 /* Check the parameters */ 00994 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 00995 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00996 00997 if (NewState != DISABLE) 00998 { 00999 /* Enable the selected SPI CRC calculation */ 01000 SPIx->CR1 |= SPI_CR1_CRCEN; 01001 } 01002 else 01003 { 01004 /* Disable the selected SPI CRC calculation */ 01005 SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); 01006 } 01007 } 01008 01009 /** 01010 * @brief Transmits the SPIx CRC value. 01011 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 01012 * @retval None 01013 */ 01014 void SPI_TransmitCRC(SPI_TypeDef* SPIx) 01015 { 01016 /* Check the parameters */ 01017 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 01018 01019 /* Enable the selected SPI CRC transmission */ 01020 SPIx->CR1 |= SPI_CR1_CRCNEXT; 01021 } 01022 01023 /** 01024 * @brief Returns the transmit or the receive CRC register value for the specified SPI. 01025 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 01026 * @param SPI_CRC: specifies the CRC register to be read. 01027 * This parameter can be one of the following values: 01028 * @arg SPI_CRC_Tx: Selects Tx CRC register 01029 * @arg SPI_CRC_Rx: Selects Rx CRC register 01030 * @retval The selected CRC register value.. 01031 */ 01032 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) 01033 { 01034 uint16_t crcreg = 0; 01035 /* Check the parameters */ 01036 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 01037 assert_param(IS_SPI_CRC(SPI_CRC)); 01038 01039 if (SPI_CRC != SPI_CRC_Rx) 01040 { 01041 /* Get the Tx CRC register */ 01042 crcreg = SPIx->TXCRCR; 01043 } 01044 else 01045 { 01046 /* Get the Rx CRC register */ 01047 crcreg = SPIx->RXCRCR; 01048 } 01049 /* Return the selected CRC register */ 01050 return crcreg; 01051 } 01052 01053 /** 01054 * @brief Returns the CRC Polynomial register value for the specified SPI. 01055 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 01056 * @retval The CRC Polynomial register value. 01057 */ 01058 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) 01059 { 01060 /* Check the parameters */ 01061 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 01062 01063 /* Return the CRC polynomial register */ 01064 return SPIx->CRCPR; 01065 } 01066 01067 /** 01068 * @} 01069 */ 01070 01071 /** @defgroup SPI_Group4 DMA transfers management functions 01072 * @brief DMA transfers management functions 01073 * 01074 @verbatim 01075 =============================================================================== 01076 ##### DMA transfers management functions ##### 01077 =============================================================================== 01078 01079 @endverbatim 01080 * @{ 01081 */ 01082 01083 /** 01084 * @brief Enables or disables the SPIx/I2Sx DMA interface. 01085 * @param SPIx:To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4 01086 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 01087 * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 01088 * This parameter can be any combination of the following values: 01089 * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request 01090 * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request 01091 * @param NewState: new state of the selected SPI DMA transfer request. 01092 * This parameter can be: ENABLE or DISABLE. 01093 * @retval None 01094 */ 01095 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) 01096 { 01097 /* Check the parameters */ 01098 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 01099 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01100 assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq)); 01101 01102 if (NewState != DISABLE) 01103 { 01104 /* Enable the selected SPI DMA requests */ 01105 SPIx->CR2 |= SPI_I2S_DMAReq; 01106 } 01107 else 01108 { 01109 /* Disable the selected SPI DMA requests */ 01110 SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; 01111 } 01112 } 01113 01114 /** 01115 * @brief Configures the number of data to transfer type(Even/Odd) for the DMA 01116 * last transfers and for the selected SPI. 01117 * @note This function have a meaning only if DMA mode is selected and if 01118 * the packing mode is used (data length <= 8 and DMA transfer size halfword) 01119 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 01120 * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. 01121 * This parameter can be one of the following values: 01122 * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even 01123 * and number of data for reception Even. 01124 * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd 01125 * and number of data for reception Even. 01126 * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even 01127 * and number of data for reception Odd. 01128 * @arg SPI_LastDMATransfer_TxOddRxOdd: RNumber of data for transmission Odd 01129 * and number of data for reception Odd. 01130 * @retval None 01131 */ 01132 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) 01133 { 01134 /* Check the parameters */ 01135 assert_param(IS_SPI_ALL_PERIPH(SPIx)); 01136 assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); 01137 01138 /* Clear LDMA_TX and LDMA_RX bits */ 01139 SPIx->CR2 &= CR2_LDMA_MASK; 01140 01141 /* Set new LDMA_TX and LDMA_RX bits value */ 01142 SPIx->CR2 |= SPI_LastDMATransfer; 01143 } 01144 01145 /** 01146 * @} 01147 */ 01148 01149 /** @defgroup SPI_Group5 Interrupts and flags management functions 01150 * @brief Interrupts and flags management functions 01151 * 01152 @verbatim 01153 =============================================================================== 01154 ##### Interrupts and flags management functions ##### 01155 =============================================================================== 01156 [..] This section provides a set of functions allowing to configure the SPI/I2S 01157 Interrupts sources and check or clear the flags or pending bits status. 01158 The user should identify which mode will be used in his application to manage 01159 the communication: Polling mode, Interrupt mode or DMA mode. 01160 01161 *** Polling Mode *** 01162 ==================== 01163 [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: 01164 (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register. 01165 (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register. 01166 (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. 01167 (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur. 01168 (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur. 01169 (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur. 01170 (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs. 01171 (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. 01172 (#) I2S_FLAG_CHSIDE: to indicate Channel Side. 01173 [..] 01174 (@) Do not use the BSY flag to handle each data transmission or reception. 01175 It is better to use the TXE and RXNE flags instead. 01176 [..] In this Mode it is advised to use the following functions: 01177 (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 01178 (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 01179 01180 *** Interrupt Mode *** 01181 ====================== 01182 [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources 01183 and 5 pending bits: 01184 [..] Pending Bits: 01185 (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register. 01186 (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register. 01187 (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur. 01188 (#) I2S_IT_UDR : to indicate an Underrun Error occurs. 01189 (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs. 01190 [..] Interrupt Source: 01191 (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 01192 interrupt. 01193 (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 01194 empty interrupt. 01195 (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. 01196 [..] In this Mode it is advised to use the following functions: 01197 (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 01198 (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 01199 01200 *** FIFO Status *** 01201 =================== 01202 [..] It is possible to monitor the FIFO status when a transfer is ongoing using the 01203 following function: 01204 (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); 01205 01206 *** DMA Mode *** 01207 ================ 01208 [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: 01209 (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request. 01210 (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request. 01211 [..] In this Mode it is advised to use the following function: 01212 (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 01213 01214 @endverbatim 01215 * @{ 01216 */ 01217 01218 /** 01219 * @brief Enables or disables the specified SPI/I2S interrupts. 01220 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4 01221 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 01222 * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 01223 * This parameter can be one of the following values: 01224 * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask 01225 * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask 01226 * @arg SPI_I2S_IT_ERR: Error interrupt mask 01227 * @param NewState: new state of the specified SPI interrupt. 01228 * This parameter can be: ENABLE or DISABLE. 01229 * @retval None 01230 */ 01231 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) 01232 { 01233 uint16_t itpos = 0, itmask = 0 ; 01234 01235 /* Check the parameters */ 01236 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 01237 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01238 assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); 01239 01240 /* Get the SPI IT index */ 01241 itpos = SPI_I2S_IT >> 4; 01242 01243 /* Set the IT mask */ 01244 itmask = (uint16_t)1 << (uint16_t)itpos; 01245 01246 if (NewState != DISABLE) 01247 { 01248 /* Enable the selected SPI interrupt */ 01249 SPIx->CR2 |= itmask; 01250 } 01251 else 01252 { 01253 /* Disable the selected SPI interrupt */ 01254 SPIx->CR2 &= (uint16_t)~itmask; 01255 } 01256 } 01257 01258 /** 01259 * @brief Returns the current SPIx Transmission FIFO filled level. 01260 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 01261 * @retval The Transmission FIFO filling state. 01262 * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty 01263 * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. 01264 * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. 01265 * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. 01266 */ 01267 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) 01268 { 01269 /* Get the SPIx Transmission FIFO level bits */ 01270 return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); 01271 } 01272 01273 /** 01274 * @brief Returns the current SPIx Reception FIFO filled level. 01275 * @param SPIx: where x can be 1, 2, 3 or 4 to select the SPI peripheral. 01276 * @retval The Reception FIFO filling state. 01277 * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty 01278 * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. 01279 * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. 01280 * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. 01281 */ 01282 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) 01283 { 01284 /* Get the SPIx Reception FIFO level bits */ 01285 return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); 01286 } 01287 01288 /** 01289 * @brief Checks whether the specified SPI flag is set or not. 01290 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4 01291 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 01292 * @param SPI_I2S_FLAG: specifies the SPI flag to check. 01293 * This parameter can be one of the following values: 01294 * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. 01295 * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. 01296 * @arg SPI_I2S_FLAG_BSY: Busy flag. 01297 * @arg SPI_I2S_FLAG_OVR: Overrun flag. 01298 * @arg SPI_I2S_FLAG_MODF: Mode Fault flag. 01299 * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag. 01300 * @arg SPI_I2S_FLAG_FRE: TI frame format error flag. 01301 * @arg I2S_FLAG_UDR: Underrun Error flag. 01302 * @arg I2S_FLAG_CHSIDE: Channel Side flag. 01303 * @retval The new state of SPI_I2S_FLAG (SET or RESET). 01304 */ 01305 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) 01306 { 01307 FlagStatus bitstatus = RESET; 01308 /* Check the parameters */ 01309 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 01310 assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); 01311 01312 /* Check the status of the specified SPI flag */ 01313 if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) 01314 { 01315 /* SPI_I2S_FLAG is set */ 01316 bitstatus = SET; 01317 } 01318 else 01319 { 01320 /* SPI_I2S_FLAG is reset */ 01321 bitstatus = RESET; 01322 } 01323 /* Return the SPI_I2S_FLAG status */ 01324 return bitstatus; 01325 } 01326 01327 /** 01328 * @brief Clears the SPIx CRC Error (CRCERR) flag. 01329 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4 01330 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 01331 * @param SPI_I2S_FLAG: specifies the SPI flag to clear. 01332 * This function clears only CRCERR flag. 01333 * @note OVR (OverRun error) flag is cleared by software sequence: a read 01334 * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 01335 * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). 01336 * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write 01337 * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 01338 * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). 01339 * @retval None 01340 */ 01341 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) 01342 { 01343 /* Check the parameters */ 01344 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 01345 assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG)); 01346 01347 /* Clear the selected SPI CRC Error (CRCERR) flag */ 01348 SPIx->SR = (uint16_t)~SPI_I2S_FLAG; 01349 } 01350 01351 /** 01352 * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. 01353 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3 or 4 01354 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 01355 * @param SPI_I2S_IT: specifies the SPI interrupt source to check. 01356 * This parameter can be one of the following values: 01357 * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. 01358 * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. 01359 * @arg SPI_IT_MODF: Mode Fault interrupt. 01360 * @arg SPI_I2S_IT_OVR: Overrun interrupt. 01361 * @arg I2S_IT_UDR: Underrun interrupt. 01362 * @arg SPI_I2S_IT_FRE: Format Error interrupt. 01363 * @retval The new state of SPI_I2S_IT (SET or RESET). 01364 */ 01365 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) 01366 { 01367 ITStatus bitstatus = RESET; 01368 uint16_t itpos = 0, itmask = 0, enablestatus = 0; 01369 01370 /* Check the parameters */ 01371 assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); 01372 assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); 01373 01374 /* Get the SPI_I2S_IT index */ 01375 itpos = 0x01 << (SPI_I2S_IT & 0x0F); 01376 01377 /* Get the SPI_I2S_IT IT mask */ 01378 itmask = SPI_I2S_IT >> 4; 01379 01380 /* Set the IT mask */ 01381 itmask = 0x01 << itmask; 01382 01383 /* Get the SPI_I2S_IT enable bit status */ 01384 enablestatus = (SPIx->CR2 & itmask) ; 01385 01386 /* Check the status of the specified SPI interrupt */ 01387 if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) 01388 { 01389 /* SPI_I2S_IT is set */ 01390 bitstatus = SET; 01391 } 01392 else 01393 { 01394 /* SPI_I2S_IT is reset */ 01395 bitstatus = RESET; 01396 } 01397 /* Return the SPI_I2S_IT status */ 01398 return bitstatus; 01399 } 01400 01401 /** 01402 * @} 01403 */ 01404 01405 /** 01406 * @} 01407 */ 01408 01409 /** 01410 * @} 01411 */ 01412 01413 /** 01414 * @} 01415 */ 01416 01417 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jul 12 2022 17:34:44 by
1.7.2