Hardware CRC Calculation functions
[SPI_Private_Functions]

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                  ##### Hardware CRC Calculation functions #####
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    [..] This section provides a set of functions allowing to manage the SPI CRC hardware 
         calculation.
    [..] SPI communication using CRC is possible through the following procedure:
         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
             Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
             function.
         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
         (#) Enable the SPI using the SPI_Cmd() function
         (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 
             SPI_TransmitCRC() function to indicate that after transmission of the last 
             data, the CRC should be transmitted.
         (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
             bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
             value. 
             If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
             can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
    [..]
    (@)
         (+@) It is advised to don't read the calculate CRC values during the communication.
         (+@) When the SPI is in slave mode, be careful to enable CRC calculation only 
              when the clock is stable, that is, when the clock is in the steady state. 
              If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
              to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
              the value of the SPE bit.
         (+@) With high bitrate frequencies, be careful when transmitting the CRC.
              As the number of used CPU cycles has to be as low as possible in the CRC 
              transfer phase, it is forbidden to call software functions in the CRC 
              transmission sequence to avoid errors in the last data and CRC reception. 
              In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
              of the last data.
         (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
              degradation of the SPI speed performance due to CPU accesses impacting the 
              SPI bandwidth.
         (+@) When the STM32F30x are configured as slaves and the NSS hardware mode is 
              used, the NSS pin needs to be kept low between the data phase and the CRC 
              phase.
         (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
              calculation takes place even if a high level is applied on the NSS pin. 
              This may happen for example in case of a multislave environment where the 
              communication master addresses slaves alternately.
         (+@) Between a slave deselection (high level on NSS) and a new slave selection 
              (low level on NSS), the CRC value should be cleared on both master and slave
              sides in order to resynchronize the master and slave for their respective 
              CRC calculation.
    [..]          
    (@) To clear the CRC, follow the procedure below:
         (#@) Disable SPI using the SPI_Cmd() function.
         (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
         (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
         (#@) Enable SPI using the SPI_Cmd() function.