Martin Johnson / STM32F3-Discovery

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Peripheral clocks configuration functions
Functions

Peripheral clocks configuration functions
[RCC_Private_Functions]

Peripheral clocks configuration functions. More...

Functions

void RCC_ADCCLKConfig (uint32_t RCC_PLLCLK)
 Configures the ADC clock (ADCCLK).
void RCC_I2CCLKConfig (uint32_t RCC_I2CCLK)
 Configures the I2C clock (I2CCLK).
void RCC_TIMCLKConfig (uint32_t RCC_TIMCLK)
 Configures the TIMx clock sources(TIMCLK).
void RCC_HRTIM1CLKConfig (uint32_t RCC_HRTIMCLK)
 Configures the HRTIM1 clock sources(HRTIM1CLK).
void RCC_USARTCLKConfig (uint32_t RCC_USARTCLK)
 Configures the USART clock (USARTCLK).
void RCC_USBCLKConfig (uint32_t RCC_USBCLKSource)
 Configures the USB clock (USBCLK).
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK).
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK).
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock.
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset.
void RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Enables or disables the AHB peripheral clock.
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock.
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock.
void RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Forces or releases AHB peripheral reset.
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset.
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset.

Detailed Description

Peripheral clocks configuration functions. 

 ===============================================================================
            ##### Peripheral clocks configuration functions #####
 ===============================================================================  
    [..] This section provide functions allowing to configure the Peripheral clocks. 
         (#) The RTC clock which is derived from the LSE, LSI or  HSE_Div32 
             (HSE divided by 32).
         (#) After restart from Reset or wakeup from STANDBY, all peripherals are 
             off except internal SRAM, Flash and SWD. Before to start using 
             a peripheral you have to enable its interface clock. You can do this 
             using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() 
             and RCC_APB1PeriphClockCmd() functions.
         (#) To reset the peripherals configuration (to the default state after 
             device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() 
             and RCC_APB1PeriphResetCmd() functions.

Function Documentation

void RCC_ADCCLKConfig ( uint32_t  RCC_PLLCLK )

Configures the ADC clock (ADCCLK).

Parameters:
RCC_PLLCLK,:defines the ADC clock divider. This clock is derived from the PLL Clock. This parameter can be one of the following values:

  • RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
  • RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
  • RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
  • RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
  • RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
  • RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
  • RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
  • RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
  • RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
  • RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
  • RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
  • RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
  • RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
  • RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
  • RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
  • RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
  • RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
  • RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
  • RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
  • RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
  • RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
  • RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
  • RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
  • RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
  • RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
  • RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
Return values:
None

Definition at line 1277 of file stm32f30x_rcc.c.

void RCC_AHBPeriphClockCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Enables or disables the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_AHBPeriph,:specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOF
  • RCC_AHBPeriph_GPIOG
  • RCC_AHBPeriph_GPIOH
  • RCC_AHBPeriph_TS
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FMC
  • RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_ADC34
  • RCC_AHBPeriph_ADC12
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1603 of file stm32f30x_rcc.c.

void RCC_AHBPeriphResetCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Forces or releases AHB peripheral reset.

Parameters:
RCC_AHBPeriph,:specifies the AHB peripheral to reset. This parameter can be any combination of the following values:

  • RCC_AHBPeriph_FMC
  • RCC_AHBPeriph_GPIOH
  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOF
  • RCC_AHBPeriph_GPIOG
  • RCC_AHBPeriph_TS
  • RCC_AHBPeriph_ADC34
  • RCC_AHBPeriph_ADC12
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1724 of file stm32f30x_rcc.c.

void RCC_APB1PeriphClockCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2
  • RCC_APB1Periph_TIM3
  • RCC_APB1Periph_TIM4
  • RCC_APB1Periph_TIM6
  • RCC_APB1Periph_TIM7
  • RCC_APB1Periph_WWDG
  • RCC_APB1Periph_SPI2
  • RCC_APB1Periph_SPI3
  • RCC_APB1Periph_USART2
  • RCC_APB1Periph_USART3
  • RCC_APB1Periph_UART4
  • RCC_APB1Periph_UART5
  • RCC_APB1Periph_I2C1
  • RCC_APB1Periph_I2C2
  • RCC_APB1Periph_USB
  • RCC_APB1Periph_CAN1
  • RCC_APB1Periph_PWR
  • RCC_APB1Periph_DAC1
  • RCC_APB1Periph_DAC2
  • RCC_APB1Periph_I2C3
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1688 of file stm32f30x_rcc.c.

void RCC_APB1PeriphResetCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB1Periph_TIM2
  • RCC_APB1Periph_TIM3
  • RCC_APB1Periph_TIM4
  • RCC_APB1Periph_TIM6
  • RCC_APB1Periph_TIM7
  • RCC_APB1Periph_WWDG
  • RCC_APB1Periph_SPI2
  • RCC_APB1Periph_SPI3
  • RCC_APB1Periph_USART2
  • RCC_APB1Periph_USART3
  • RCC_APB1Periph_UART4
  • RCC_APB1Periph_UART5
  • RCC_APB1Periph_I2C1
  • RCC_APB1Periph_I2C2
  • RCC_APB1Periph_I2C3
  • RCC_APB1Periph_USB
  • RCC_APB1Periph_CAN1
  • RCC_APB1Periph_PWR
  • RCC_APB1Periph_DAC
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1802 of file stm32f30x_rcc.c.

void RCC_APB2PeriphClockCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG
  • RCC_APB2Periph_SPI1
  • RCC_APB2Periph_USART1
  • RCC_APB2Periph_SPI4
  • RCC_APB2Periph_TIM15
  • RCC_APB2Periph_TIM16
  • RCC_APB2Periph_TIM17
  • RCC_APB2Periph_TIM1
  • RCC_APB2Periph_TIM8
  • RCC_APB2Periph_HRTIM1
  • RCC_APB2Periph_TIM20
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1641 of file stm32f30x_rcc.c.

void RCC_APB2PeriphResetCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:

  • RCC_APB2Periph_SYSCFG
  • RCC_APB2Periph_SPI1
  • RCC_APB2Periph_USART1
  • RCC_APB2Periph_SPI4
  • RCC_APB2Periph_TIM15
  • RCC_APB2Periph_TIM16
  • RCC_APB2Periph_TIM17
  • RCC_APB2Periph_TIM1
  • RCC_APB2Periph_TIM8
  • RCC_APB2Periph_TIM20
  • RCC_APB2Periph_HRTIM1
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1759 of file stm32f30x_rcc.c.

void RCC_BackupResetCmd ( FunctionalState  NewState )

Forces or releases the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.
Parameters:
NewState,:new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1567 of file stm32f30x_rcc.c.

void RCC_HRTIM1CLKConfig ( uint32_t  RCC_HRTIMCLK )

Configures the HRTIM1 clock sources(HRTIM1CLK).

Note:
The configuration of the HRTIM1 clock source is only possible when the SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
If one of the previous conditions is missed, the TIM clock source configuration is lost and calling again this function becomes mandatory.
Parameters:
RCC_HRTIMCLK,:defines the TIMx clock source. This parameter can be one of the following values:

  • RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency when prescaled)
  • RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) (x can be 1 or 8).
Return values:
None

Definition at line 1416 of file stm32f30x_rcc.c.

void RCC_I2CCLKConfig ( uint32_t  RCC_I2CCLK )

Configures the I2C clock (I2CCLK).

Parameters:
RCC_I2CCLK,:defines the I2C clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:

  • RCC_I2CxCLK_HSI: I2Cx clock = HSI
  • RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock (x can be 1 or 2 or 3).
Return values:
None

Definition at line 1310 of file stm32f30x_rcc.c.

void RCC_I2SCLKConfig ( uint32_t  RCC_I2SCLKSource )

Configures the I2S clock source (I2SCLK).

Note:
This function must be called before enabling the SPI2 and SPI3 clocks.
Parameters:
RCC_I2SCLKSource,:specifies the I2S clock source. This parameter can be one of the following values:

  • RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
  • RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
Return values:
None

Definition at line 1535 of file stm32f30x_rcc.c.

void RCC_RTCCLKCmd ( FunctionalState  NewState )

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,:new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

Definition at line 1551 of file stm32f30x_rcc.c.

void RCC_RTCCLKConfig ( uint32_t  RCC_RTCCLKSource )

Configures the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the RTC is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
Parameters:
RCC_RTCCLKSource,:specifies the RTC clock source. This parameter can be one of the following values:

  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 2MHz (when using HSE as RTC clock source).
Return values:
None

Definition at line 1516 of file stm32f30x_rcc.c.

void RCC_TIMCLKConfig ( uint32_t  RCC_TIMCLK )

Configures the TIMx clock sources(TIMCLK).

Note:
For STM32F303xC devices, TIMx can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and HCLK & PCLK2 clocks are not divided in respect to SYSCLK. For the devices STM32F334x8, STM32F302x8 and STM32F303xE, TIMx can be clocked from the PLL running at 144 MHz when the system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively.
If one of the previous conditions is missed, the TIM clock source configuration is lost and calling again this function becomes mandatory.
Parameters:
RCC_TIMCLK,:defines the TIMx clock source. This parameter can be one of the following values:

  • RCC_TIMxCLK_PCLK: TIMx clock = APB clock (doubled frequency when prescaled)
  • RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz) (x can be 1, 8, 15, 16, 17, 20, 2, 3,4).
Note:
For STM32F303xC devices, TIM1 and TIM8 can be clocked at 144MHz. For STM32F303xE devices, TIM1/8/20/2/3/4/15/16/17 can be clocked at 144MHz. For STM32F334x8 devices , only TIM1 can be clocked at 144MHz. For STM32F302x8 devices, TIM1/15/16/17 can be clocked at 144MHz
Return values:
None

Definition at line 1359 of file stm32f30x_rcc.c.

void RCC_USARTCLKConfig ( uint32_t  RCC_USARTCLK )

Configures the USART clock (USARTCLK).

Parameters:
RCC_USARTCLK,:defines the USART clock source. This clock is derived from the HSI or System clock. This parameter can be one of the following values:

  • RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
  • RCC_USARTxCLK_SYSCLK: USART clock = System Clock
  • RCC_USARTxCLK_LSE: USART clock = LSE Clock
  • RCC_USARTxCLK_HSI: USART clock = HSI Clock (x can be 1, 2, 3, 4 or 5).
Return values:
None

Definition at line 1440 of file stm32f30x_rcc.c.

void RCC_USBCLKConfig ( uint32_t  RCC_USBCLKSource )

Configures the USB clock (USBCLK).

Parameters:
RCC_USBCLKSource,:specifies the USB clock source. This clock is derived from the PLL output. This parameter can be one of the following values:

  • RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB clock source
  • RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
Return values:
None

Definition at line 1485 of file stm32f30x_rcc.c.

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