Diff: INIT_HW/INIT_HW.cpp

Revision:

228:fb5b57e3f157

Parent:

23:59218d4a256d

Child:

231:30896263bd8b

--- a/INIT_HW/INIT_HW.cpp	Fri Jul 30 06:04:10 2021 +0000
+++ b/INIT_HW/INIT_HW.cpp	Tue Apr 05 05:12:12 2022 +0000
@@ -38,7 +38,8 @@
     NVIC_EnableIRQ(TIM4_IRQn);                         //Enable TIM4 IRQ
 
     TIM4->DIER |= TIM_DIER_UIE;                                 // enable update interrupt
-    TIM4->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
+//    TIM4->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
+    TIM4->CR1 = 0x10;
     TIM4->CR1 |= TIM_CR1_UDIS;
     TIM4->CR1 |= TIM_CR1_ARPE;                                  // autoreload on, 
     TIM4->RCR |= 0x001;                                         // update event once per up/down count of TIM4 
@@ -47,38 +48,40 @@
     //PWM Setup
 
     TIM4->PSC = 0x0;                                            // no prescaler, timer counts up in sync with the peripheral clock
-    TIM4->ARR = PWM_ARR;                                          // set auto reload
+    TIM4->ARR = PWM_ARR-1;                                          // set auto reload
     TIM4->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
     TIM4->CR1 |= TIM_CR1_CEN;                                   // enable TIM4
     
 }
 
+
 void Init_TMR3(){
     RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;                         // enable TIM3 clock
     
      //ISR Setup     
     
-    NVIC_EnableIRQ(TIM3_IRQn);                         //Enable TIM3 IRQ
+    NVIC_EnableIRQ(TIM3_IRQn);                                  //Enable TIM3 IRQ
 
     TIM3->DIER |= TIM_DIER_UIE;                                 // enable update interrupt
-    TIM3->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
+//    TIM3->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
+    TIM3->CR1 = 0x10;
     TIM3->CR1 |= TIM_CR1_UDIS;
     TIM3->CR1 |= TIM_CR1_ARPE;                                  // autoreload on, 
     TIM3->RCR |= 0x001;                                         // update event once per up/down count of TIM3 
     TIM3->EGR |= TIM_EGR_UG;
 
-    TIM3->PSC = 0x00;                                            // no prescaler, timer counts up in sync with the peripheral clock
-    TIM3->ARR = TMR3_COUNT;                                          // set auto reload, 5 khz
+//    TIM3->PSC = 0x00;                                            // no prescaler, timer counts up in sync with the peripheral clock
+    TIM3->PSC = 0x01;
+    TIM3->ARR = TMR3_COUNT-1;                                          // set auto reload, 5 khz
     TIM3->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
     TIM3->CR1 |= TIM_CR1_CEN;                                   // enable TIM4
 }
 
 void Init_TMR2(){
-    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;                         // enable TIM5 clock
+    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;                         // enable TIM2 clock
     
      //ISR Setup     
-    
-    NVIC_EnableIRQ(TIM2_IRQn);                         //Enable TIM5 IRQ
+    NVIC_EnableIRQ(TIM2_IRQn);                                  //Enable TIM2 IRQ
 
     TIM2->DIER |= TIM_DIER_UIE;                                 // enable update interrupt
     TIM2->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
@@ -87,8 +90,28 @@
     TIM2->RCR |= 0x001;                                         // update event once per up/down count of TIM5
     TIM2->EGR |= TIM_EGR_UG;
 
-    TIM2->PSC = 0x12;                                            // no prescaler, timer counts up in sync with the peripheral clock
-    TIM2->ARR = TMR2_COUNT;                                          // set auto reload, 5 khz
+    TIM2->PSC = 0x00;                                            // no prescaler, timer counts up in sync with the peripheral clock
+    TIM2->ARR = TMR2_COUNT-1;                                          // set auto reload, 5 khz
     TIM2->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
-    TIM2->CR1 |= TIM_CR1_CEN;                                   // enable TIM5
-}
\ No newline at end of file
+    TIM2->CR1 |= TIM_CR1_CEN;                                   // enable TIM2
+}
+
+//void Init_TMR2(){
+//    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;                         // enable TIM5 clock
+//    
+//     //ISR Setup     
+//    
+//    NVIC_EnableIRQ(TIM2_IRQn);                         //Enable TIM5 IRQ
+//
+//    TIM2->DIER |= TIM_DIER_UIE;                                 // enable update interrupt
+//    TIM2->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
+//    TIM2->CR1 |= TIM_CR1_UDIS;
+//    TIM2->CR1 |= TIM_CR1_ARPE;                                  // autoreload on, 
+//    TIM2->RCR |= 0x001;                                         // update event once per up/down count of TIM5
+//    TIM2->EGR |= TIM_EGR_UG;
+//
+//    TIM2->PSC = 0x12;                                            // no prescaler, timer counts up in sync with the peripheral clock
+//    TIM2->ARR = TMR2_COUNT;                                          // set auto reload, 5 khz
+//    TIM2->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
+//    TIM2->CR1 |= TIM_CR1_CEN;                                   // enable TIM5
+//}
\ No newline at end of file