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CyclesSync.c@21:bc8c1cec3da6, 2016-02-03 (annotated)
- Committer:
- igor_v
- Date:
- Wed Feb 03 07:19:30 2016 +0000
- Revision:
- 21:bc8c1cec3da6
- Parent:
- 0:8ad47e2b6f00
- Child:
- 112:4a96133a1311
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Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
igor_v | 0:8ad47e2b6f00 | 1 | /**--------------File Info--------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 2 | ** File name: CycleSync.c |
igor_v | 0:8ad47e2b6f00 | 3 | ** Last modified Date: 2011-09-06 |
igor_v | 0:8ad47e2b6f00 | 4 | ** Last Version: V1.00 |
igor_v | 21:bc8c1cec3da6 | 5 | ** Descriptions: |
igor_v | 0:8ad47e2b6f00 | 6 | ** |
igor_v | 0:8ad47e2b6f00 | 7 | **-------------------------------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 8 | ** Created by: Electrooptica Inc. |
igor_v | 0:8ad47e2b6f00 | 9 | ** Created date: 2011-09-06 |
igor_v | 0:8ad47e2b6f00 | 10 | ** Version: V1.00 |
igor_v | 0:8ad47e2b6f00 | 11 | ** Descriptions: There is the routines for device synchronization |
igor_v | 0:8ad47e2b6f00 | 12 | ** |
igor_v | 21:bc8c1cec3da6 | 13 | **-------------------------------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 14 | *********************************************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 15 | #include "CyclesSync.h" |
igor_v | 0:8ad47e2b6f00 | 16 | #include "CntrlGLD.h" |
igor_v | 0:8ad47e2b6f00 | 17 | #include "SIP.h" |
igor_v | 0:8ad47e2b6f00 | 18 | #include "el_lin.h" |
igor_v | 0:8ad47e2b6f00 | 19 | #include "InputOutput.h" |
igor_v | 0:8ad47e2b6f00 | 20 | |
igor_v | 21:bc8c1cec3da6 | 21 | uint32_t Sys_Clock; //e. counter of system ticks //r. счетчик временной сетки системы |
igor_v | 21:bc8c1cec3da6 | 22 | uint32_t Seconds = 0; //e. seconds from power on //r. число секунд от момента включения питания |
igor_v | 21:bc8c1cec3da6 | 23 | int32_t time_1_Sec = DEVICE_SAMPLE_RATE_uks; //e. pseudosecond timer //r. псевдосекундный таймер |
igor_v | 0:8ad47e2b6f00 | 24 | uint32_t trm_cycl; |
igor_v | 0:8ad47e2b6f00 | 25 | uint32_t count; |
igor_v | 21:bc8c1cec3da6 | 26 | int32_t PrevPeriod = 0; |
igor_v | 0:8ad47e2b6f00 | 27 | uint32_t num; |
igor_v | 0:8ad47e2b6f00 | 28 | volatile uint32_t Latch_Rdy = 0; |
igor_v | 0:8ad47e2b6f00 | 29 | |
igor_v | 21:bc8c1cec3da6 | 30 | int32_t LatchPhase = INT32_MAX; |
igor_v | 0:8ad47e2b6f00 | 31 | uint32_t Ext_Latch_ResetEnable = 1; |
igor_v | 0:8ad47e2b6f00 | 32 | volatile uint32_t data_Rdy = 0; |
igor_v | 0:8ad47e2b6f00 | 33 | |
igor_v | 0:8ad47e2b6f00 | 34 | uint32_t Delay_UART_Enbl = DELAY_UART_ENBL; |
igor_v | 0:8ad47e2b6f00 | 35 | //uint32_t Delay_UART_Disbl = DELAY_UART_ENBL; |
igor_v | 0:8ad47e2b6f00 | 36 | |
igor_v | 21:bc8c1cec3da6 | 37 | uint32_t main_cycle_latch = 0; |
igor_v | 0:8ad47e2b6f00 | 38 | uint32_t Out_main_cycle_latch; //e. counter of main cycles between external latch pulse appearence |
igor_v | 0:8ad47e2b6f00 | 39 | uint32_t T_latch, Out_T_latch, temp_T_latch; |
igor_v | 0:8ad47e2b6f00 | 40 | |
igor_v | 0:8ad47e2b6f00 | 41 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 42 | ** Function name: Latch_Event |
igor_v | 0:8ad47e2b6f00 | 43 | ** |
igor_v | 0:8ad47e2b6f00 | 44 | ** Descriptions: Routine for latch appearing |
igor_v | 0:8ad47e2b6f00 | 45 | ** |
igor_v | 0:8ad47e2b6f00 | 46 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 47 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 48 | ** |
igor_v | 0:8ad47e2b6f00 | 49 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 50 | void Latch_Event() |
igor_v | 0:8ad47e2b6f00 | 51 | { |
igor_v | 21:bc8c1cec3da6 | 52 | static unsigned PreLatch = 0; |
igor_v | 0:8ad47e2b6f00 | 53 | // static int cc = 0; |
igor_v | 21:bc8c1cec3da6 | 54 | if (LatchPhase < INT32_MAX) { //Если LatchPhase(флаг защелки) < меньше максимального 32-х битного инта (при инициализации int32_t LatchPhase = INT32_MAX;) то: |
igor_v | 21:bc8c1cec3da6 | 55 | Latch_Rdy = 1; //e. установить флаг для обработки ниже |
igor_v | 21:bc8c1cec3da6 | 56 | if (RgConB) { //Если RgConB (дополнительный регистр управления, установлен в еденицу при инициализации в мэйне) утановлен в еденицу то: |
igor_v | 21:bc8c1cec3da6 | 57 | if (PreLatch) //e. если мы откладываем защелку |
igor_v | 21:bc8c1cec3da6 | 58 | PreLatch = 0; |
igor_v | 21:bc8c1cec3da6 | 59 | |
igor_v | 21:bc8c1cec3da6 | 60 | else if ((LatchPhase < LPC_PWM1->TC) && (num == Sys_Clock)) { //e. latch have appeared in current cycle |
igor_v | 21:bc8c1cec3da6 | 61 | Latch_Rdy = 0; //e. bring it to the next cycle |
igor_v | 21:bc8c1cec3da6 | 62 | PreLatch = 1; |
igor_v | 21:bc8c1cec3da6 | 63 | } |
igor_v | 21:bc8c1cec3da6 | 64 | } |
igor_v | 21:bc8c1cec3da6 | 65 | } else |
igor_v | 21:bc8c1cec3da6 | 66 | Latch_Rdy = 0; //e. latch is absent |
igor_v | 21:bc8c1cec3da6 | 67 | //---------------------------temp------------------------------- |
igor_v | 21:bc8c1cec3da6 | 68 | /* Latch_Rdy = 0; //e. latch is absent |
igor_v | 21:bc8c1cec3da6 | 69 | if (cc++ == 19) |
igor_v | 21:bc8c1cec3da6 | 70 | { |
igor_v | 21:bc8c1cec3da6 | 71 | cc = 0; |
igor_v | 21:bc8c1cec3da6 | 72 | Latch_Rdy = 1; |
igor_v | 21:bc8c1cec3da6 | 73 | LatchPhase = 2500; |
igor_v | 21:bc8c1cec3da6 | 74 | } */ |
igor_v | 21:bc8c1cec3da6 | 75 | //----------------------temp-------------------------------- |
igor_v | 0:8ad47e2b6f00 | 76 | } |
igor_v | 0:8ad47e2b6f00 | 77 | |
igor_v | 0:8ad47e2b6f00 | 78 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 79 | ** Function name: QEI_IRQHandler |
igor_v | 0:8ad47e2b6f00 | 80 | ** |
igor_v | 0:8ad47e2b6f00 | 81 | ** Descriptions: Latch counters by reference meander |
igor_v | 0:8ad47e2b6f00 | 82 | ** |
igor_v | 0:8ad47e2b6f00 | 83 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 84 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 85 | ** |
igor_v | 0:8ad47e2b6f00 | 86 | ******************************************************************************/ |
igor_v | 21:bc8c1cec3da6 | 87 | __irq void QEI_IRQHandler (void) |
igor_v | 21:bc8c1cec3da6 | 88 | { |
igor_v | 21:bc8c1cec3da6 | 89 | static uint32_t halfQEIPeriod = 0; |
igor_v | 0:8ad47e2b6f00 | 90 | |
igor_v | 21:bc8c1cec3da6 | 91 | Cnt_curr = LPC_QEI->POS; //e. read accumulated value of counter |
igor_v | 21:bc8c1cec3da6 | 92 | if (LPC_QEI->INTSTAT & 0x0008) { |
igor_v | 21:bc8c1cec3da6 | 93 | data_Rdy = 0x0004; //e. data for Cnt_Pls or Cnt_Mns calculation are ready |
igor_v | 0:8ad47e2b6f00 | 94 | |
igor_v | 21:bc8c1cec3da6 | 95 | if (++halfQEIPeriod & 0x0001) { //e. period elapsed, we can calculate Cnt_Dif |
igor_v | 21:bc8c1cec3da6 | 96 | data_Rdy = 0x000C; |
igor_v | 21:bc8c1cec3da6 | 97 | } |
igor_v | 21:bc8c1cec3da6 | 98 | } |
igor_v | 21:bc8c1cec3da6 | 99 | LPC_QEI->CLR = 0x1fff; //e. reset interrupt request //r. сбросить запрос прерывания |
igor_v | 21:bc8c1cec3da6 | 100 | } |
igor_v | 0:8ad47e2b6f00 | 101 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 102 | ** Function name: SetIntLatch |
igor_v | 0:8ad47e2b6f00 | 103 | ** |
igor_v | 0:8ad47e2b6f00 | 104 | ** Descriptions: Set timer for accumulation period |
igor_v | 0:8ad47e2b6f00 | 105 | ** |
igor_v | 0:8ad47e2b6f00 | 106 | ** parameters: Period of accumulation |
igor_v | 0:8ad47e2b6f00 | 107 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 108 | ** |
igor_v | 0:8ad47e2b6f00 | 109 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 110 | void SetIntLatch(uint32_t cycle) |
igor_v | 0:8ad47e2b6f00 | 111 | { |
igor_v | 21:bc8c1cec3da6 | 112 | LPC_TIM3->TCR = 0x2; //switch off and reset timer3 |
igor_v | 21:bc8c1cec3da6 | 113 | if (cycle != 0) { |
igor_v | 21:bc8c1cec3da6 | 114 | LPC_TIM3->MR0 = (cycle<<2); //load new value |
igor_v | 21:bc8c1cec3da6 | 115 | LPC_TIM3->TCR = 1; //switch on timer3 |
igor_v | 21:bc8c1cec3da6 | 116 | } |
igor_v | 0:8ad47e2b6f00 | 117 | } |
igor_v | 0:8ad47e2b6f00 | 118 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 119 | ** Function name: SwitchRefMeandInt |
igor_v | 0:8ad47e2b6f00 | 120 | ** |
igor_v | 0:8ad47e2b6f00 | 121 | ** Descriptions: Enable/disable interrupt from reference meander |
igor_v | 0:8ad47e2b6f00 | 122 | ** |
igor_v | 0:8ad47e2b6f00 | 123 | ** parameters: switcher |
igor_v | 0:8ad47e2b6f00 | 124 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 125 | ** |
igor_v | 0:8ad47e2b6f00 | 126 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 127 | void SwitchRefMeandInt(uint32_t s) |
igor_v | 0:8ad47e2b6f00 | 128 | { |
igor_v | 21:bc8c1cec3da6 | 129 | LPC_QEI->CLR = 0x1fff; //e. reset all interrupts //r. сбросить все прерывания |
igor_v | 21:bc8c1cec3da6 | 130 | if (s) |
igor_v | 21:bc8c1cec3da6 | 131 | LPC_QEI->IEC = 0x1fff; //e. disable direction changing interrupt //r. запретить прерывание при изменении направления |
igor_v | 21:bc8c1cec3da6 | 132 | else |
igor_v | 21:bc8c1cec3da6 | 133 | LPC_QEI->IES = 0x0008; //e. enable direction changing interrupt //r. разрешить прерывание при изменении направления |
igor_v | 0:8ad47e2b6f00 | 134 | } |
igor_v | 0:8ad47e2b6f00 | 135 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 136 | ** Function name: ExtLatch_IRQHandler |
igor_v | 0:8ad47e2b6f00 | 137 | ** |
igor_v | 0:8ad47e2b6f00 | 138 | ** Descriptions: Routine for external latch appearence processing |
igor_v | 0:8ad47e2b6f00 | 139 | ** |
igor_v | 0:8ad47e2b6f00 | 140 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 141 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 142 | ** |
igor_v | 0:8ad47e2b6f00 | 143 | ******************************************************************************/ |
igor_v | 21:bc8c1cec3da6 | 144 | __irq void EINT3_IRQHandler (void) |
igor_v | 21:bc8c1cec3da6 | 145 | { |
igor_v | 21:bc8c1cec3da6 | 146 | //LPC_GPIO2->FIOSET = 0x00000020; //e. turn on the LED |
igor_v | 21:bc8c1cec3da6 | 147 | LatchPhase = LPC_PWM1->TC; //e. read moment of latch |
igor_v | 21:bc8c1cec3da6 | 148 | LPC_TIM0->TCR = 1; //e. start Mltdrop delay timer |
igor_v | 21:bc8c1cec3da6 | 149 | LPC_GPIOINT->IO0IntClr |= 0x0000800;//e. clean interrupt request |
igor_v | 21:bc8c1cec3da6 | 150 | //LPC_GPIO2->FIOCLR = 0x00000020; //e. turn off the LED |
igor_v | 21:bc8c1cec3da6 | 151 | } |
igor_v | 21:bc8c1cec3da6 | 152 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 153 | ** Function name: IntLatch_IRQHandler |
igor_v | 0:8ad47e2b6f00 | 154 | ** |
igor_v | 0:8ad47e2b6f00 | 155 | ** Descriptions: Routine for Internal latch appearence processing |
igor_v | 0:8ad47e2b6f00 | 156 | ** |
igor_v | 0:8ad47e2b6f00 | 157 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 158 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 159 | ** |
igor_v | 0:8ad47e2b6f00 | 160 | ******************************************************************************/ |
igor_v | 21:bc8c1cec3da6 | 161 | __irq void IntLatch_IRQHandler (void) |
igor_v | 21:bc8c1cec3da6 | 162 | { |
igor_v | 21:bc8c1cec3da6 | 163 | //LPC_GPIO2->FIOSET |= 0x00000080; // turn on the LED |
igor_v | 21:bc8c1cec3da6 | 164 | LatchPhase =(int)LPC_PWM1->TC; //e. read moment of latch |
igor_v | 21:bc8c1cec3da6 | 165 | LPC_TIM3->IR = 0x0001; //e. clear interrupt flag |
igor_v | 21:bc8c1cec3da6 | 166 | num = Sys_Clock; |
igor_v | 21:bc8c1cec3da6 | 167 | // count++; |
igor_v | 21:bc8c1cec3da6 | 168 | //LPC_GPIO2->FIOCLR |= 0x00000080; // turn off the LED |
igor_v | 21:bc8c1cec3da6 | 169 | } |
igor_v | 0:8ad47e2b6f00 | 170 | |
igor_v | 21:bc8c1cec3da6 | 171 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 172 | ** Function name: SwitchMode |
igor_v | 0:8ad47e2b6f00 | 173 | ** |
igor_v | 0:8ad47e2b6f00 | 174 | ** Descriptions: Switch mode of device functionality |
igor_v | 0:8ad47e2b6f00 | 175 | ** |
igor_v | 0:8ad47e2b6f00 | 176 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 177 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 178 | ** |
igor_v | 0:8ad47e2b6f00 | 179 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 180 | int SwitchMode() |
igor_v | 0:8ad47e2b6f00 | 181 | { |
igor_v | 21:bc8c1cec3da6 | 182 | //-----------------------disable latch sources --------------------- |
igor_v | 21:bc8c1cec3da6 | 183 | SetIntLatch(0); //e. disable internal latch |
igor_v | 21:bc8c1cec3da6 | 184 | LPC_TIM3->IR = 0x0001; //e. clear internal latch interrupt request |
igor_v | 0:8ad47e2b6f00 | 185 | |
igor_v | 21:bc8c1cec3da6 | 186 | LPC_GPIOINT->IO0IntEnR &= ~0x0000800; //e. disable external latch |
igor_v | 21:bc8c1cec3da6 | 187 | LPC_GPIOINT->IO0IntClr |= 0x0000800; //e. clean external latch interrupt request |
igor_v | 0:8ad47e2b6f00 | 188 | |
igor_v | 21:bc8c1cec3da6 | 189 | LPC_TIM0->TCR = 2; //e. stop and reset the multidrop delay timer |
igor_v | 21:bc8c1cec3da6 | 190 | LPC_TIM0->IR = 0x03F; //e. clear internal latch interrupt request |
igor_v | 21:bc8c1cec3da6 | 191 | //----------------------wait while UART and DMA are active------------- |
igor_v | 21:bc8c1cec3da6 | 192 | if ( LPC_GPDMACH1->CConfig & DMA_BUSY) //e. if DMA channel is busy, wait //r. если канал передачи занят, ждать |
igor_v | 21:bc8c1cec3da6 | 193 | return 0; |
igor_v | 21:bc8c1cec3da6 | 194 | LPC_GPDMACH1->CConfig &= ~DMAChannelEn; //e. disable DMA for UART transmition |
igor_v | 21:bc8c1cec3da6 | 195 | LPC_GPDMACH2->CConfig &= ~DMAChannelEn; |
igor_v | 0:8ad47e2b6f00 | 196 | |
igor_v | 21:bc8c1cec3da6 | 197 | if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //e. transmit buffer is not empty //r. передающий буфер не пуст |
igor_v | 21:bc8c1cec3da6 | 198 | return 0; |
igor_v | 21:bc8c1cec3da6 | 199 | LPC_UART1->FCR |= 0x4; //e. reset TX FIFO |
igor_v | 0:8ad47e2b6f00 | 200 | |
igor_v | 21:bc8c1cec3da6 | 201 | LPC_TIM0->IR = 0x3F; //e. clear all interrupt flags |
igor_v | 0:8ad47e2b6f00 | 202 | //---------------------configure a new exchanging parameters------------ |
igor_v | 21:bc8c1cec3da6 | 203 | if (Device_Mode > 3) { //e. external latch mode enabled |
igor_v | 21:bc8c1cec3da6 | 204 | LPC_TIM0->MR0 = 10; |
igor_v | 21:bc8c1cec3da6 | 205 | LPC_TIM0->MR1 = 50; //e. /10 = delay before enable signal (us) |
igor_v | 21:bc8c1cec3da6 | 206 | // LPC_UART1->FCR &= ~0x08; //e. TX FIFO is not source for DMA request |
igor_v | 0:8ad47e2b6f00 | 207 | |
igor_v | 0:8ad47e2b6f00 | 208 | // LPC_SC->DMAREQSEL = 0xC; //e. external latch delay timer is source for DMA request |
igor_v | 0:8ad47e2b6f00 | 209 | // LPC_GPIOINT->IO0IntEnR |= 0x0000800; //e. enable rising edge interrupt |
igor_v | 21:bc8c1cec3da6 | 210 | } else { //e. internal latch mode enabled |
igor_v | 21:bc8c1cec3da6 | 211 | LPC_TIM0->MR0 = 10; |
igor_v | 21:bc8c1cec3da6 | 212 | LPC_TIM0->MR1 = 5000; //e. /10 = delay before enable signal (us) |
igor_v | 0:8ad47e2b6f00 | 213 | // LPC_SC->DMAREQSEL = 0x3; //e. FIFO generate DMA request |
igor_v | 0:8ad47e2b6f00 | 214 | |
igor_v | 0:8ad47e2b6f00 | 215 | // LPC_SC->EXTINT = 0x8; //e. clean interrupt request |
igor_v | 21:bc8c1cec3da6 | 216 | } |
igor_v | 21:bc8c1cec3da6 | 217 | |
igor_v | 21:bc8c1cec3da6 | 218 | UART_SwitchSpeed(SRgR & 0x0030); |
igor_v | 0:8ad47e2b6f00 | 219 | |
igor_v | 21:bc8c1cec3da6 | 220 | if (Device_Mode == DM_INT_LATCH_DELTA_PS) |
igor_v | 21:bc8c1cec3da6 | 221 | SetIntLatch(50000); |
igor_v | 21:bc8c1cec3da6 | 222 | return 1; |
igor_v | 0:8ad47e2b6f00 | 223 | } |
igor_v | 0:8ad47e2b6f00 | 224 | |
igor_v | 21:bc8c1cec3da6 | 225 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 226 | ** Function name: ServiceTime |
igor_v | 0:8ad47e2b6f00 | 227 | ** |
igor_v | 0:8ad47e2b6f00 | 228 | ** Descriptions: Routine for pseudoseconds counting |
igor_v | 0:8ad47e2b6f00 | 229 | ** |
igor_v | 0:8ad47e2b6f00 | 230 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 231 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 232 | ** |
igor_v | 0:8ad47e2b6f00 | 233 | ******************************************************************************/ |
igor_v | 21:bc8c1cec3da6 | 234 | void ServiceTime(void)// псевдосекундный счетчик. |
igor_v | 0:8ad47e2b6f00 | 235 | { |
igor_v | 21:bc8c1cec3da6 | 236 | time_1_Sec -= PrevPeriod; |
igor_v | 0:8ad47e2b6f00 | 237 | |
igor_v | 21:bc8c1cec3da6 | 238 | if (time_1_Sec < (PrevPeriod>>1)) { //1 sec elapsed with accurate 0.5 of main period |
igor_v | 21:bc8c1cec3da6 | 239 | time_1_Sec = DEVICE_SAMPLE_RATE_uks; |
igor_v | 21:bc8c1cec3da6 | 240 | Seconds++; |
igor_v | 21:bc8c1cec3da6 | 241 | } |
igor_v | 21:bc8c1cec3da6 | 242 | if (Seconds == 3) { |
igor_v | 21:bc8c1cec3da6 | 243 | Seconds++; |
igor_v | 21:bc8c1cec3da6 | 244 | close_all_loops(); |
igor_v | 21:bc8c1cec3da6 | 245 | } |
igor_v | 21:bc8c1cec3da6 | 246 | Sys_Clock++; //e. increment of the system clock register //r. инкремент регистра временной сетки системы |
igor_v | 21:bc8c1cec3da6 | 247 | PrevPeriod = LPC_PWM1->MR0; |
igor_v | 0:8ad47e2b6f00 | 248 | } // ServiceTime |
igor_v | 0:8ad47e2b6f00 | 249 | |
igor_v | 0:8ad47e2b6f00 | 250 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 251 | ** Function name: WDTFeed |
igor_v | 0:8ad47e2b6f00 | 252 | ** |
igor_v | 0:8ad47e2b6f00 | 253 | ** Descriptions: Feed watchdog timer to prevent it from timeout |
igor_v | 0:8ad47e2b6f00 | 254 | ** |
igor_v | 0:8ad47e2b6f00 | 255 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 256 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 257 | ** |
igor_v | 0:8ad47e2b6f00 | 258 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 259 | void WDTFeed( void ) |
igor_v | 0:8ad47e2b6f00 | 260 | { |
igor_v | 21:bc8c1cec3da6 | 261 | LPC_WDT->FEED = 0xAA; /* Feeding sequence */ |
igor_v | 21:bc8c1cec3da6 | 262 | LPC_WDT->FEED = 0x55; |
igor_v | 21:bc8c1cec3da6 | 263 | return; |
igor_v | 0:8ad47e2b6f00 | 264 | } |
igor_v | 0:8ad47e2b6f00 | 265 | |
igor_v | 0:8ad47e2b6f00 | 266 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 267 | ** Function name: CounterIquiryCycle_Init |
igor_v | 0:8ad47e2b6f00 | 268 | ** |
igor_v | 0:8ad47e2b6f00 | 269 | ** Descriptions: CounterIquiryCycle_Init setup demanded GPIOs for PWM1, |
igor_v | 0:8ad47e2b6f00 | 270 | ** reset counter, all latches are enabled, interrupt |
igor_v | 0:8ad47e2b6f00 | 271 | ** on PWMMR0, install PWM interrupt to the VIC table. |
igor_v | 0:8ad47e2b6f00 | 272 | ** |
igor_v | 21:bc8c1cec3da6 | 273 | ** parameters: |
igor_v | 21:bc8c1cec3da6 | 274 | ** Returned value: |
igor_v | 21:bc8c1cec3da6 | 275 | ** |
igor_v | 0:8ad47e2b6f00 | 276 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 277 | void CounterIquiryCycle_Init(uint32_t cycle) |
igor_v | 21:bc8c1cec3da6 | 278 | { |
igor_v | 21:bc8c1cec3da6 | 279 | //PWM1 enabled after reset by default |
igor_v | 21:bc8c1cec3da6 | 280 | LPC_SC->PCLKSEL0 &= ~(3<<12); |
igor_v | 21:bc8c1cec3da6 | 281 | LPC_SC->PCLKSEL0 |= (1<<12); //PWM1 is synchronized by CCLK (100 MHz)(CCLK) PCLKSEL0 - Peripheral Clock Selection registers. |
igor_v | 0:8ad47e2b6f00 | 282 | |
igor_v | 21:bc8c1cec3da6 | 283 | LPC_PWM1->TCR = TCR_RESET; /* Counter Reset */ //#define TCR_RESET 0x00000002 инкрементировать счетчик при спадении импульса ПВМ. |
igor_v | 21:bc8c1cec3da6 | 284 | LPC_PWM1->MCR = PWMMR0I |PWMMR0R; //generate interrupt and reset timer counter ( PWMMR0I - прерывание генерируется когда PWMMR0 совподает со значением PWMTC. ) |
igor_v | 21:bc8c1cec3da6 | 285 | // ( PWMMR0R - сбрасывает PWMTC при совподении PWMTC и PWMMR0. ) |
igor_v | 0:8ad47e2b6f00 | 286 | |
igor_v | 21:bc8c1cec3da6 | 287 | LPC_PWM1->CCR = 0x1; //разрешить прерывание только при совпадении PWMTC с PWMMR0 (еще что то связано с загрузкой ТС) |
igor_v | 0:8ad47e2b6f00 | 288 | |
igor_v | 0:8ad47e2b6f00 | 289 | |
igor_v | 21:bc8c1cec3da6 | 290 | PrevPeriod = 10000; |
igor_v | 21:bc8c1cec3da6 | 291 | LPC_PWM1->MR0 = PrevPeriod; /* set PWM cycle */// задание периода сброса счетчика. |
igor_v | 21:bc8c1cec3da6 | 292 | LPC_PWM1->PCR = PWMENA1; //e. single edge control mode, PWM1 out enabled only включение выхода ШИМ 1. |
igor_v | 21:bc8c1cec3da6 | 293 | LPC_PWM1->LER = LER0_EN ; //e. enable updating of register |
igor_v | 21:bc8c1cec3da6 | 294 | LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN; /* counter enable, PWM enable */ //включение счетчика и ШИМ |
igor_v | 21:bc8c1cec3da6 | 295 | |
igor_v | 21:bc8c1cec3da6 | 296 | NVIC_DisableIRQ(PWM1_IRQn);//запретить прерывание. |
igor_v | 21:bc8c1cec3da6 | 297 | |
igor_v | 21:bc8c1cec3da6 | 298 | |
igor_v | 21:bc8c1cec3da6 | 299 | return ; |
igor_v | 0:8ad47e2b6f00 | 300 | } |
igor_v | 0:8ad47e2b6f00 | 301 | |
igor_v | 0:8ad47e2b6f00 | 302 | __irq void TIMER0_IRQHandler() |
igor_v | 0:8ad47e2b6f00 | 303 | { |
igor_v | 21:bc8c1cec3da6 | 304 | int val = LPC_TIM0->IR; |
igor_v | 21:bc8c1cec3da6 | 305 | LPC_TIM0->IR |= 3; |
igor_v | 0:8ad47e2b6f00 | 306 | |
igor_v | 21:bc8c1cec3da6 | 307 | if (val & 1) { //MAT 1.0 interrupt |
igor_v | 21:bc8c1cec3da6 | 308 | LPC_GPIO2->FIOSET |= 1<<6; // turn on the LED |
igor_v | 21:bc8c1cec3da6 | 309 | LPC_TIM0->IR |= 1; |
igor_v | 21:bc8c1cec3da6 | 310 | return; |
igor_v | 21:bc8c1cec3da6 | 311 | } |
igor_v | 21:bc8c1cec3da6 | 312 | if (val & 2) { //MAT 1.1 interrupt |
igor_v | 21:bc8c1cec3da6 | 313 | LPC_GPIO2->FIOCLR |= 1<<6; // turn on the LED |
igor_v | 21:bc8c1cec3da6 | 314 | LPC_TIM0->IR |= 2; |
igor_v | 21:bc8c1cec3da6 | 315 | return; |
igor_v | 21:bc8c1cec3da6 | 316 | } |
igor_v | 21:bc8c1cec3da6 | 317 | if (val & 4) { //MAT 0.2 interrupt |
igor_v | 0:8ad47e2b6f00 | 318 | // LPC_GPIO0->FIOSET2 |= 0xFF; //set P0.23 |
igor_v | 21:bc8c1cec3da6 | 319 | // LPC_GPIO2->FIOSET |= 0x00000040; // turn on the LED |
igor_v | 21:bc8c1cec3da6 | 320 | // LPC_TIM0->IR |= 4; |
igor_v | 21:bc8c1cec3da6 | 321 | return; |
igor_v | 21:bc8c1cec3da6 | 322 | } |
igor_v | 21:bc8c1cec3da6 | 323 | return; |
igor_v | 0:8ad47e2b6f00 | 324 | } |
igor_v | 0:8ad47e2b6f00 | 325 | |
igor_v | 0:8ad47e2b6f00 | 326 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 327 | ** Function name: ExtLatch_Init |
igor_v | 0:8ad47e2b6f00 | 328 | ** |
igor_v | 21:bc8c1cec3da6 | 329 | ** Descriptions: Initialization of external latch |
igor_v | 0:8ad47e2b6f00 | 330 | ** |
igor_v | 0:8ad47e2b6f00 | 331 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 332 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 333 | ** |
igor_v | 0:8ad47e2b6f00 | 334 | ******************************************************************************/ |
igor_v | 21:bc8c1cec3da6 | 335 | void ExtLatch_Init() |
igor_v | 0:8ad47e2b6f00 | 336 | { |
igor_v | 21:bc8c1cec3da6 | 337 | LPC_PINCON->PINSEL4 &= ~0xC000000; //e. использовать P2.13 как GPIO. |
igor_v | 21:bc8c1cec3da6 | 338 | LPC_PINCON->PINSEL0 &= ~0x0C00000; //e. использовать P0.11 как GPIO. |
igor_v | 21:bc8c1cec3da6 | 339 | LPC_GPIO0->FIODIR &= ~0x0000800; //e. использовать P0.11 вхлод. |
igor_v | 21:bc8c1cec3da6 | 340 | LPC_GPIOINT->IO0IntEnR &= ~0x0000800; //e. отключить внутреннюю защелку. |
igor_v | 21:bc8c1cec3da6 | 341 | LPC_GPIOINT->IO0IntClr |= 0x0000800; //e. сбросить запросы на прерывания |
igor_v | 0:8ad47e2b6f00 | 342 | |
igor_v | 21:bc8c1cec3da6 | 343 | NVIC_EnableIRQ(EINT3_IRQn); // разрешить прерывания. |
igor_v | 0:8ad47e2b6f00 | 344 | |
igor_v | 0:8ad47e2b6f00 | 345 | //+++++++ initialization of timer for multidrop delay generation+++++++++++++++++++++++ |
igor_v | 21:bc8c1cec3da6 | 346 | //e. TIMER0 enabled by default |
igor_v | 21:bc8c1cec3da6 | 347 | LPC_SC->PCLKSEL0 &= ~(3<<2); //e. сбросить частоту таймера 0 |
igor_v | 21:bc8c1cec3da6 | 348 | LPC_SC->PCLKSEL0 |= (3<<2); //e. установить частоту таймера 0 на CLK/8. |
igor_v | 21:bc8c1cec3da6 | 349 | LPC_TIM0->PR = 0; //e. установить делитель частоты в 0. |
igor_v | 21:bc8c1cec3da6 | 350 | LPC_TIM0->IR = 0x3F; //e. очистить флаги прерываний. |
igor_v | 21:bc8c1cec3da6 | 351 | LPC_TIM0->MCR = 1 |(1<<3)|MR1_RESET |MR1_STOP; //e. сбросить и остановить таймер после совпадения MR1 и TC. |
igor_v | 21:bc8c1cec3da6 | 352 | LPC_TIM0->CCR = 0; //e. содержимое таймера загружается при появлении переднего фронта защелки. |
igor_v | 21:bc8c1cec3da6 | 353 | LPC_TIM0->CTCR = 0; //e. timer0 в режиме таймера. |
igor_v | 21:bc8c1cec3da6 | 354 | |
igor_v | 21:bc8c1cec3da6 | 355 | LPC_TIM0->MR0 = /*Device_blk.Address**/10; //e. delay before UART transmitter loading |
igor_v | 21:bc8c1cec3da6 | 356 | LPC_TIM0->MR1 = /*Device_blk.Address**/5000; //e. delay before UART transmitter start |
igor_v | 21:bc8c1cec3da6 | 357 | //e. set first empty) event of timer |
igor_v | 21:bc8c1cec3da6 | 358 | NVIC_DisableIRQ(TIMER0_IRQn); |
igor_v | 0:8ad47e2b6f00 | 359 | } |
igor_v | 0:8ad47e2b6f00 | 360 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 361 | ** Function name: IntLatch_Init |
igor_v | 0:8ad47e2b6f00 | 362 | ** |
igor_v | 0:8ad47e2b6f00 | 363 | ** Descriptions: Initialization of iternal latch cycle generation |
igor_v | 0:8ad47e2b6f00 | 364 | ** |
igor_v | 0:8ad47e2b6f00 | 365 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 366 | ** Returned value: None |
igor_v | 21:bc8c1cec3da6 | 367 | ** |
igor_v | 0:8ad47e2b6f00 | 368 | ******************************************************************************/ |
igor_v | 21:bc8c1cec3da6 | 369 | void IntLatch_Init() |
igor_v | 0:8ad47e2b6f00 | 370 | { |
igor_v | 21:bc8c1cec3da6 | 371 | LPC_SC->PCONP |= (1<<23); //включит TIME3(таймер) |
igor_v | 21:bc8c1cec3da6 | 372 | //e. by default timer3 mode is not counter (T3CTCR[1,0]=0) |
igor_v | 21:bc8c1cec3da6 | 373 | |
igor_v | 21:bc8c1cec3da6 | 374 | LPC_SC->PCLKSEL1 &= SYNC_CLCK4; // частота входного сигнала равна CLCK/4 |
igor_v | 21:bc8c1cec3da6 | 375 | LPC_SC->PCLKSEL1 |= (1<<14); // timer 3 input frequency equal to CLCK/4 |
igor_v | 21:bc8c1cec3da6 | 376 | |
igor_v | 0:8ad47e2b6f00 | 377 | // LPC_PINCON->PINSEL1 |= (3<<16); //e. CAP 3.1 is connected to P0.24 |
igor_v | 21:bc8c1cec3da6 | 378 | //e. by default CAP3.0 is connected to timer3 |
igor_v | 21:bc8c1cec3da6 | 379 | LPC_TIM3->PR = 0; //e. установить предделитель таймера3 на 0. |
igor_v | 21:bc8c1cec3da6 | 380 | LPC_TIM3->IR = 0x0001; //e. очистить флаги прерываний. |
igor_v | 21:bc8c1cec3da6 | 381 | LPC_TIM3->MCR = MR0_RESET |MR0_INT_EN |MR0_NO_STOP; // установка флагов прерываний которые выполняются при совпадении таймера и МСR. |
igor_v | 21:bc8c1cec3da6 | 382 | LPC_TIM3->CCR = 0x0001; //содержимое счетчика загружается по приходу переднего фронта защелки. |
igor_v | 21:bc8c1cec3da6 | 383 | |
igor_v | 21:bc8c1cec3da6 | 384 | NVIC_EnableIRQ(TIMER3_IRQn); //разрешить прерывания. |
igor_v | 0:8ad47e2b6f00 | 385 | } |
igor_v | 0:8ad47e2b6f00 | 386 | /***************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 387 | ** Function name: WDTInit |
igor_v | 0:8ad47e2b6f00 | 388 | ** |
igor_v | 0:8ad47e2b6f00 | 389 | ** Descriptions: Initialize watchdog timer, install the |
igor_v | 0:8ad47e2b6f00 | 390 | ** watchdog timer interrupt handler |
igor_v | 0:8ad47e2b6f00 | 391 | ** |
igor_v | 0:8ad47e2b6f00 | 392 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 393 | ** Returned value: true or false, return false if the VIC table |
igor_v | 0:8ad47e2b6f00 | 394 | ** is full and WDT interrupt handler can be |
igor_v | 0:8ad47e2b6f00 | 395 | ** installed. |
igor_v | 21:bc8c1cec3da6 | 396 | ** |
igor_v | 0:8ad47e2b6f00 | 397 | *****************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 398 | uint32_t WDTInit( void ) |
igor_v | 0:8ad47e2b6f00 | 399 | { |
igor_v | 21:bc8c1cec3da6 | 400 | NVIC_DisableIRQ(WDT_IRQn); |
igor_v | 0:8ad47e2b6f00 | 401 | |
igor_v | 21:bc8c1cec3da6 | 402 | LPC_WDT->TC = WDT_FEED_VALUE; // once WDEN is set, the WDT will start after feeding |
igor_v | 21:bc8c1cec3da6 | 403 | LPC_WDT->MOD = WDEN; |
igor_v | 0:8ad47e2b6f00 | 404 | |
igor_v | 21:bc8c1cec3da6 | 405 | LPC_WDT->FEED = 0xAA; // Feeding sequence |
igor_v | 21:bc8c1cec3da6 | 406 | LPC_WDT->FEED = 0x55; |
igor_v | 21:bc8c1cec3da6 | 407 | |
igor_v | 21:bc8c1cec3da6 | 408 | return 1; |
igor_v | 0:8ad47e2b6f00 | 409 | } |
igor_v | 0:8ad47e2b6f00 | 410 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 411 | ** End Of File |
igor_v | 0:8ad47e2b6f00 | 412 | ******************************************************************************/ |