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CyclesSync.c@0:8ad47e2b6f00, 2016-01-30 (annotated)
- Committer:
- igor_v
- Date:
- Sat Jan 30 13:00:39 2016 +0000
- Revision:
- 0:8ad47e2b6f00
- Child:
- 21:bc8c1cec3da6
2016_01_30;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
igor_v | 0:8ad47e2b6f00 | 1 | |
igor_v | 0:8ad47e2b6f00 | 2 | /**--------------File Info--------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 3 | ** File name: CycleSync.c |
igor_v | 0:8ad47e2b6f00 | 4 | ** Last modified Date: 2011-09-06 |
igor_v | 0:8ad47e2b6f00 | 5 | ** Last Version: V1.00 |
igor_v | 0:8ad47e2b6f00 | 6 | ** Descriptions: |
igor_v | 0:8ad47e2b6f00 | 7 | ** |
igor_v | 0:8ad47e2b6f00 | 8 | **-------------------------------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 9 | ** Created by: Electrooptica Inc. |
igor_v | 0:8ad47e2b6f00 | 10 | ** Created date: 2011-09-06 |
igor_v | 0:8ad47e2b6f00 | 11 | ** Version: V1.00 |
igor_v | 0:8ad47e2b6f00 | 12 | ** Descriptions: There is the routines for device synchronization |
igor_v | 0:8ad47e2b6f00 | 13 | ** |
igor_v | 0:8ad47e2b6f00 | 14 | **-------------------------------------------------------------------------------------------------------- |
igor_v | 0:8ad47e2b6f00 | 15 | *********************************************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 16 | #include "CyclesSync.h" |
igor_v | 0:8ad47e2b6f00 | 17 | #include "CntrlGLD.h" |
igor_v | 0:8ad47e2b6f00 | 18 | #include "SIP.h" |
igor_v | 0:8ad47e2b6f00 | 19 | #include "el_lin.h" |
igor_v | 0:8ad47e2b6f00 | 20 | #include "InputOutput.h" |
igor_v | 0:8ad47e2b6f00 | 21 | |
igor_v | 0:8ad47e2b6f00 | 22 | uint32_t Sys_Clock; //e. counter of system ticks //r. ������� ��������� ����� ������� |
igor_v | 0:8ad47e2b6f00 | 23 | uint32_t Seconds = 0; //e. seconds from power on //r. ����� ������ �� ������� ��������� ������� |
igor_v | 0:8ad47e2b6f00 | 24 | int32_t time_1_Sec = DEVICE_SAMPLE_RATE_uks; //e. pseudosecond timer //r. ��������������� ������ |
igor_v | 0:8ad47e2b6f00 | 25 | uint32_t trm_cycl; |
igor_v | 0:8ad47e2b6f00 | 26 | uint32_t count; |
igor_v | 0:8ad47e2b6f00 | 27 | int32_t PrevPeriod = 0; |
igor_v | 0:8ad47e2b6f00 | 28 | uint32_t num; |
igor_v | 0:8ad47e2b6f00 | 29 | volatile uint32_t Latch_Rdy = 0; |
igor_v | 0:8ad47e2b6f00 | 30 | |
igor_v | 0:8ad47e2b6f00 | 31 | int32_t LatchPhase = INT32_MAX; |
igor_v | 0:8ad47e2b6f00 | 32 | uint32_t Ext_Latch_ResetEnable = 1; |
igor_v | 0:8ad47e2b6f00 | 33 | volatile uint32_t data_Rdy = 0; |
igor_v | 0:8ad47e2b6f00 | 34 | |
igor_v | 0:8ad47e2b6f00 | 35 | uint32_t Delay_UART_Enbl = DELAY_UART_ENBL; |
igor_v | 0:8ad47e2b6f00 | 36 | //uint32_t Delay_UART_Disbl = DELAY_UART_ENBL; |
igor_v | 0:8ad47e2b6f00 | 37 | |
igor_v | 0:8ad47e2b6f00 | 38 | uint32_t main_cycle_latch = 0; |
igor_v | 0:8ad47e2b6f00 | 39 | uint32_t Out_main_cycle_latch; //e. counter of main cycles between external latch pulse appearence |
igor_v | 0:8ad47e2b6f00 | 40 | uint32_t T_latch, Out_T_latch, temp_T_latch; |
igor_v | 0:8ad47e2b6f00 | 41 | |
igor_v | 0:8ad47e2b6f00 | 42 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 43 | ** Function name: Latch_Event |
igor_v | 0:8ad47e2b6f00 | 44 | ** |
igor_v | 0:8ad47e2b6f00 | 45 | ** Descriptions: Routine for latch appearing |
igor_v | 0:8ad47e2b6f00 | 46 | ** |
igor_v | 0:8ad47e2b6f00 | 47 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 48 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 49 | ** |
igor_v | 0:8ad47e2b6f00 | 50 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 51 | void Latch_Event() |
igor_v | 0:8ad47e2b6f00 | 52 | { |
igor_v | 0:8ad47e2b6f00 | 53 | static unsigned PreLatch = 0; |
igor_v | 0:8ad47e2b6f00 | 54 | // static int cc = 0; |
igor_v | 0:8ad47e2b6f00 | 55 | if (LatchPhase < INT32_MAX) //���� LatchPhase(���� �������) < ������ ������������� 32-� ������� ���� (��� ������������� int32_t LatchPhase = INT32_MAX;) ��: |
igor_v | 0:8ad47e2b6f00 | 56 | { |
igor_v | 0:8ad47e2b6f00 | 57 | Latch_Rdy = 1; //e. ���������� ���� ��� ��������� ���� |
igor_v | 0:8ad47e2b6f00 | 58 | if (RgConB) //���� RgConB (�������������� ������� ����������, ���������� � ������� ��� ������������� � �����) ��������� � ������� ��: |
igor_v | 0:8ad47e2b6f00 | 59 | { |
igor_v | 0:8ad47e2b6f00 | 60 | if (PreLatch) //e. ���� �� ����������� ������� |
igor_v | 0:8ad47e2b6f00 | 61 | PreLatch = 0; |
igor_v | 0:8ad47e2b6f00 | 62 | |
igor_v | 0:8ad47e2b6f00 | 63 | else if ((LatchPhase < LPC_PWM1->TC) && (num == Sys_Clock)) //e. latch have appeared in current cycle |
igor_v | 0:8ad47e2b6f00 | 64 | { |
igor_v | 0:8ad47e2b6f00 | 65 | Latch_Rdy = 0; //e. bring it to the next cycle |
igor_v | 0:8ad47e2b6f00 | 66 | PreLatch = 1; |
igor_v | 0:8ad47e2b6f00 | 67 | } |
igor_v | 0:8ad47e2b6f00 | 68 | } |
igor_v | 0:8ad47e2b6f00 | 69 | } |
igor_v | 0:8ad47e2b6f00 | 70 | else |
igor_v | 0:8ad47e2b6f00 | 71 | Latch_Rdy = 0; //e. latch is absent |
igor_v | 0:8ad47e2b6f00 | 72 | //---------------------------temp------------------------------- |
igor_v | 0:8ad47e2b6f00 | 73 | /* Latch_Rdy = 0; //e. latch is absent |
igor_v | 0:8ad47e2b6f00 | 74 | if (cc++ == 19) |
igor_v | 0:8ad47e2b6f00 | 75 | { |
igor_v | 0:8ad47e2b6f00 | 76 | cc = 0; |
igor_v | 0:8ad47e2b6f00 | 77 | Latch_Rdy = 1; |
igor_v | 0:8ad47e2b6f00 | 78 | LatchPhase = 2500; |
igor_v | 0:8ad47e2b6f00 | 79 | } */ |
igor_v | 0:8ad47e2b6f00 | 80 | //----------------------temp-------------------------------- |
igor_v | 0:8ad47e2b6f00 | 81 | } |
igor_v | 0:8ad47e2b6f00 | 82 | |
igor_v | 0:8ad47e2b6f00 | 83 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 84 | ** Function name: QEI_IRQHandler |
igor_v | 0:8ad47e2b6f00 | 85 | ** |
igor_v | 0:8ad47e2b6f00 | 86 | ** Descriptions: Latch counters by reference meander |
igor_v | 0:8ad47e2b6f00 | 87 | ** |
igor_v | 0:8ad47e2b6f00 | 88 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 89 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 90 | ** |
igor_v | 0:8ad47e2b6f00 | 91 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 92 | __irq void QEI_IRQHandler (void) |
igor_v | 0:8ad47e2b6f00 | 93 | { |
igor_v | 0:8ad47e2b6f00 | 94 | static uint32_t halfQEIPeriod = 0; |
igor_v | 0:8ad47e2b6f00 | 95 | |
igor_v | 0:8ad47e2b6f00 | 96 | Cnt_curr = LPC_QEI->POS; //e. read accumulated value of counter |
igor_v | 0:8ad47e2b6f00 | 97 | if (LPC_QEI->INTSTAT & 0x0008) |
igor_v | 0:8ad47e2b6f00 | 98 | { |
igor_v | 0:8ad47e2b6f00 | 99 | data_Rdy = 0x0004; //e. data for Cnt_Pls or Cnt_Mns calculation are ready |
igor_v | 0:8ad47e2b6f00 | 100 | |
igor_v | 0:8ad47e2b6f00 | 101 | if (++halfQEIPeriod & 0x0001) //e. period elapsed, we can calculate Cnt_Dif |
igor_v | 0:8ad47e2b6f00 | 102 | { |
igor_v | 0:8ad47e2b6f00 | 103 | data_Rdy = 0x000C; |
igor_v | 0:8ad47e2b6f00 | 104 | } |
igor_v | 0:8ad47e2b6f00 | 105 | } |
igor_v | 0:8ad47e2b6f00 | 106 | LPC_QEI->CLR = 0x1fff; //e. reset interrupt request //r. �������� ������ ���������� |
igor_v | 0:8ad47e2b6f00 | 107 | } |
igor_v | 0:8ad47e2b6f00 | 108 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 109 | ** Function name: SetIntLatch |
igor_v | 0:8ad47e2b6f00 | 110 | ** |
igor_v | 0:8ad47e2b6f00 | 111 | ** Descriptions: Set timer for accumulation period |
igor_v | 0:8ad47e2b6f00 | 112 | ** |
igor_v | 0:8ad47e2b6f00 | 113 | ** parameters: Period of accumulation |
igor_v | 0:8ad47e2b6f00 | 114 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 115 | ** |
igor_v | 0:8ad47e2b6f00 | 116 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 117 | void SetIntLatch(uint32_t cycle) |
igor_v | 0:8ad47e2b6f00 | 118 | { |
igor_v | 0:8ad47e2b6f00 | 119 | LPC_TIM3->TCR = 0x2; //switch off and reset timer3 |
igor_v | 0:8ad47e2b6f00 | 120 | if (cycle != 0) |
igor_v | 0:8ad47e2b6f00 | 121 | { |
igor_v | 0:8ad47e2b6f00 | 122 | LPC_TIM3->MR0 = (cycle<<2); //load new value |
igor_v | 0:8ad47e2b6f00 | 123 | LPC_TIM3->TCR = 1; //switch on timer3 |
igor_v | 0:8ad47e2b6f00 | 124 | } |
igor_v | 0:8ad47e2b6f00 | 125 | } |
igor_v | 0:8ad47e2b6f00 | 126 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 127 | ** Function name: SwitchRefMeandInt |
igor_v | 0:8ad47e2b6f00 | 128 | ** |
igor_v | 0:8ad47e2b6f00 | 129 | ** Descriptions: Enable/disable interrupt from reference meander |
igor_v | 0:8ad47e2b6f00 | 130 | ** |
igor_v | 0:8ad47e2b6f00 | 131 | ** parameters: switcher |
igor_v | 0:8ad47e2b6f00 | 132 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 133 | ** |
igor_v | 0:8ad47e2b6f00 | 134 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 135 | void SwitchRefMeandInt(uint32_t s) |
igor_v | 0:8ad47e2b6f00 | 136 | { |
igor_v | 0:8ad47e2b6f00 | 137 | LPC_QEI->CLR = 0x1fff; //e. reset all interrupts //r. �������� ��� ���������� |
igor_v | 0:8ad47e2b6f00 | 138 | if (s) |
igor_v | 0:8ad47e2b6f00 | 139 | LPC_QEI->IEC = 0x1fff; //e. disable direction changing interrupt //r. ��������� ���������� ��� ��������� ����������� |
igor_v | 0:8ad47e2b6f00 | 140 | else |
igor_v | 0:8ad47e2b6f00 | 141 | LPC_QEI->IES = 0x0008; //e. enable direction changing interrupt //r. ��������� ���������� ��� ��������� ����������� |
igor_v | 0:8ad47e2b6f00 | 142 | } |
igor_v | 0:8ad47e2b6f00 | 143 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 144 | ** Function name: ExtLatch_IRQHandler |
igor_v | 0:8ad47e2b6f00 | 145 | ** |
igor_v | 0:8ad47e2b6f00 | 146 | ** Descriptions: Routine for external latch appearence processing |
igor_v | 0:8ad47e2b6f00 | 147 | ** |
igor_v | 0:8ad47e2b6f00 | 148 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 149 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 150 | ** |
igor_v | 0:8ad47e2b6f00 | 151 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 152 | __irq void EINT3_IRQHandler (void) |
igor_v | 0:8ad47e2b6f00 | 153 | { |
igor_v | 0:8ad47e2b6f00 | 154 | //LPC_GPIO2->FIOSET = 0x00000020; //e. turn on the LED |
igor_v | 0:8ad47e2b6f00 | 155 | LatchPhase = LPC_PWM1->TC; //e. read moment of latch |
igor_v | 0:8ad47e2b6f00 | 156 | LPC_TIM0->TCR = 1; //e. start Mltdrop delay timer |
igor_v | 0:8ad47e2b6f00 | 157 | LPC_GPIOINT->IO0IntClr |= 0x0000800;//e. clean interrupt request |
igor_v | 0:8ad47e2b6f00 | 158 | //LPC_GPIO2->FIOCLR = 0x00000020; //e. turn off the LED |
igor_v | 0:8ad47e2b6f00 | 159 | } |
igor_v | 0:8ad47e2b6f00 | 160 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 161 | ** Function name: IntLatch_IRQHandler |
igor_v | 0:8ad47e2b6f00 | 162 | ** |
igor_v | 0:8ad47e2b6f00 | 163 | ** Descriptions: Routine for Internal latch appearence processing |
igor_v | 0:8ad47e2b6f00 | 164 | ** |
igor_v | 0:8ad47e2b6f00 | 165 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 166 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 167 | ** |
igor_v | 0:8ad47e2b6f00 | 168 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 169 | __irq void IntLatch_IRQHandler (void) |
igor_v | 0:8ad47e2b6f00 | 170 | { |
igor_v | 0:8ad47e2b6f00 | 171 | //LPC_GPIO2->FIOSET |= 0x00000080; // turn on the LED |
igor_v | 0:8ad47e2b6f00 | 172 | LatchPhase =(int)LPC_PWM1->TC; //e. read moment of latch |
igor_v | 0:8ad47e2b6f00 | 173 | LPC_TIM3->IR = 0x0001; //e. clear interrupt flag |
igor_v | 0:8ad47e2b6f00 | 174 | num = Sys_Clock; |
igor_v | 0:8ad47e2b6f00 | 175 | // count++; |
igor_v | 0:8ad47e2b6f00 | 176 | //LPC_GPIO2->FIOCLR |= 0x00000080; // turn off the LED |
igor_v | 0:8ad47e2b6f00 | 177 | } |
igor_v | 0:8ad47e2b6f00 | 178 | |
igor_v | 0:8ad47e2b6f00 | 179 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 180 | ** Function name: SwitchMode |
igor_v | 0:8ad47e2b6f00 | 181 | ** |
igor_v | 0:8ad47e2b6f00 | 182 | ** Descriptions: Switch mode of device functionality |
igor_v | 0:8ad47e2b6f00 | 183 | ** |
igor_v | 0:8ad47e2b6f00 | 184 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 185 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 186 | ** |
igor_v | 0:8ad47e2b6f00 | 187 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 188 | int SwitchMode() |
igor_v | 0:8ad47e2b6f00 | 189 | { |
igor_v | 0:8ad47e2b6f00 | 190 | //-----------------------disable latch sources --------------------- |
igor_v | 0:8ad47e2b6f00 | 191 | SetIntLatch(0); //e. disable internal latch |
igor_v | 0:8ad47e2b6f00 | 192 | LPC_TIM3->IR = 0x0001; //e. clear internal latch interrupt request |
igor_v | 0:8ad47e2b6f00 | 193 | |
igor_v | 0:8ad47e2b6f00 | 194 | LPC_GPIOINT->IO0IntEnR &= ~0x0000800; //e. disable external latch |
igor_v | 0:8ad47e2b6f00 | 195 | LPC_GPIOINT->IO0IntClr |= 0x0000800; //e. clean external latch interrupt request |
igor_v | 0:8ad47e2b6f00 | 196 | |
igor_v | 0:8ad47e2b6f00 | 197 | LPC_TIM0->TCR = 2; //e. stop and reset the multidrop delay timer |
igor_v | 0:8ad47e2b6f00 | 198 | LPC_TIM0->IR = 0x03F; //e. clear internal latch interrupt request |
igor_v | 0:8ad47e2b6f00 | 199 | //----------------------wait while UART and DMA are active------------- |
igor_v | 0:8ad47e2b6f00 | 200 | if ( LPC_GPDMACH1->CConfig & DMA_BUSY) //e. if DMA channel is busy, wait //r. ���� ����� �������� �����, ����� |
igor_v | 0:8ad47e2b6f00 | 201 | return 0; |
igor_v | 0:8ad47e2b6f00 | 202 | LPC_GPDMACH1->CConfig &= ~DMAChannelEn; //e. disable DMA for UART transmition |
igor_v | 0:8ad47e2b6f00 | 203 | LPC_GPDMACH2->CConfig &= ~DMAChannelEn; |
igor_v | 0:8ad47e2b6f00 | 204 | |
igor_v | 0:8ad47e2b6f00 | 205 | if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //e. transmit buffer is not empty //r. ���������� ����� �� ���� |
igor_v | 0:8ad47e2b6f00 | 206 | return 0; |
igor_v | 0:8ad47e2b6f00 | 207 | LPC_UART1->FCR |= 0x4; //e. reset TX FIFO |
igor_v | 0:8ad47e2b6f00 | 208 | |
igor_v | 0:8ad47e2b6f00 | 209 | LPC_TIM0->IR = 0x3F; //e. clear all interrupt flags |
igor_v | 0:8ad47e2b6f00 | 210 | //---------------------configure a new exchanging parameters------------ |
igor_v | 0:8ad47e2b6f00 | 211 | if (Device_Mode > 3) //e. external latch mode enabled |
igor_v | 0:8ad47e2b6f00 | 212 | { |
igor_v | 0:8ad47e2b6f00 | 213 | LPC_TIM0->MR0 = 10; |
igor_v | 0:8ad47e2b6f00 | 214 | LPC_TIM0->MR1 = 50; //e. /10 = delay before enable signal (us) |
igor_v | 0:8ad47e2b6f00 | 215 | // LPC_UART1->FCR &= ~0x08; //e. TX FIFO is not source for DMA request |
igor_v | 0:8ad47e2b6f00 | 216 | |
igor_v | 0:8ad47e2b6f00 | 217 | // LPC_SC->DMAREQSEL = 0xC; //e. external latch delay timer is source for DMA request |
igor_v | 0:8ad47e2b6f00 | 218 | // LPC_GPIOINT->IO0IntEnR |= 0x0000800; //e. enable rising edge interrupt |
igor_v | 0:8ad47e2b6f00 | 219 | } |
igor_v | 0:8ad47e2b6f00 | 220 | else //e. internal latch mode enabled |
igor_v | 0:8ad47e2b6f00 | 221 | { |
igor_v | 0:8ad47e2b6f00 | 222 | LPC_TIM0->MR0 = 10; |
igor_v | 0:8ad47e2b6f00 | 223 | LPC_TIM0->MR1 = 5000; //e. /10 = delay before enable signal (us) |
igor_v | 0:8ad47e2b6f00 | 224 | // LPC_SC->DMAREQSEL = 0x3; //e. FIFO generate DMA request |
igor_v | 0:8ad47e2b6f00 | 225 | |
igor_v | 0:8ad47e2b6f00 | 226 | // LPC_SC->EXTINT = 0x8; //e. clean interrupt request |
igor_v | 0:8ad47e2b6f00 | 227 | } |
igor_v | 0:8ad47e2b6f00 | 228 | |
igor_v | 0:8ad47e2b6f00 | 229 | UART_SwitchSpeed(SRgR & 0x0030); |
igor_v | 0:8ad47e2b6f00 | 230 | |
igor_v | 0:8ad47e2b6f00 | 231 | if (Device_Mode == DM_INT_LATCH_DELTA_PS) |
igor_v | 0:8ad47e2b6f00 | 232 | SetIntLatch(50000); |
igor_v | 0:8ad47e2b6f00 | 233 | return 1; |
igor_v | 0:8ad47e2b6f00 | 234 | } |
igor_v | 0:8ad47e2b6f00 | 235 | |
igor_v | 0:8ad47e2b6f00 | 236 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 237 | ** Function name: ServiceTime |
igor_v | 0:8ad47e2b6f00 | 238 | ** |
igor_v | 0:8ad47e2b6f00 | 239 | ** Descriptions: Routine for pseudoseconds counting |
igor_v | 0:8ad47e2b6f00 | 240 | ** |
igor_v | 0:8ad47e2b6f00 | 241 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 242 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 243 | ** |
igor_v | 0:8ad47e2b6f00 | 244 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 245 | void ServiceTime(void)// ��������������� �������. |
igor_v | 0:8ad47e2b6f00 | 246 | { |
igor_v | 0:8ad47e2b6f00 | 247 | time_1_Sec -= PrevPeriod; |
igor_v | 0:8ad47e2b6f00 | 248 | |
igor_v | 0:8ad47e2b6f00 | 249 | if (time_1_Sec < (PrevPeriod>>1)) //1 sec elapsed with accurate 0.5 of main period |
igor_v | 0:8ad47e2b6f00 | 250 | { |
igor_v | 0:8ad47e2b6f00 | 251 | time_1_Sec = DEVICE_SAMPLE_RATE_uks; |
igor_v | 0:8ad47e2b6f00 | 252 | Seconds++; |
igor_v | 0:8ad47e2b6f00 | 253 | } |
igor_v | 0:8ad47e2b6f00 | 254 | if (Seconds == 3) { Seconds++;close_all_loops();} |
igor_v | 0:8ad47e2b6f00 | 255 | Sys_Clock++; //e. increment of the system clock register //r. ��������� �������� ��������� ����� ������� |
igor_v | 0:8ad47e2b6f00 | 256 | PrevPeriod = LPC_PWM1->MR0; |
igor_v | 0:8ad47e2b6f00 | 257 | } // ServiceTime |
igor_v | 0:8ad47e2b6f00 | 258 | |
igor_v | 0:8ad47e2b6f00 | 259 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 260 | ** Function name: WDTFeed |
igor_v | 0:8ad47e2b6f00 | 261 | ** |
igor_v | 0:8ad47e2b6f00 | 262 | ** Descriptions: Feed watchdog timer to prevent it from timeout |
igor_v | 0:8ad47e2b6f00 | 263 | ** |
igor_v | 0:8ad47e2b6f00 | 264 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 265 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 266 | ** |
igor_v | 0:8ad47e2b6f00 | 267 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 268 | void WDTFeed( void ) |
igor_v | 0:8ad47e2b6f00 | 269 | { |
igor_v | 0:8ad47e2b6f00 | 270 | LPC_WDT->FEED = 0xAA; /* Feeding sequence */ |
igor_v | 0:8ad47e2b6f00 | 271 | LPC_WDT->FEED = 0x55; |
igor_v | 0:8ad47e2b6f00 | 272 | return; |
igor_v | 0:8ad47e2b6f00 | 273 | } |
igor_v | 0:8ad47e2b6f00 | 274 | |
igor_v | 0:8ad47e2b6f00 | 275 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 276 | ** Function name: CounterIquiryCycle_Init |
igor_v | 0:8ad47e2b6f00 | 277 | ** |
igor_v | 0:8ad47e2b6f00 | 278 | ** Descriptions: CounterIquiryCycle_Init setup demanded GPIOs for PWM1, |
igor_v | 0:8ad47e2b6f00 | 279 | ** reset counter, all latches are enabled, interrupt |
igor_v | 0:8ad47e2b6f00 | 280 | ** on PWMMR0, install PWM interrupt to the VIC table. |
igor_v | 0:8ad47e2b6f00 | 281 | ** |
igor_v | 0:8ad47e2b6f00 | 282 | ** parameters: |
igor_v | 0:8ad47e2b6f00 | 283 | ** Returned value: |
igor_v | 0:8ad47e2b6f00 | 284 | ** |
igor_v | 0:8ad47e2b6f00 | 285 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 286 | void CounterIquiryCycle_Init(uint32_t cycle) |
igor_v | 0:8ad47e2b6f00 | 287 | { |
igor_v | 0:8ad47e2b6f00 | 288 | //PWM1 enabled after reset by default |
igor_v | 0:8ad47e2b6f00 | 289 | LPC_SC->PCLKSEL0 &= ~(3<<12); |
igor_v | 0:8ad47e2b6f00 | 290 | LPC_SC->PCLKSEL0 |= (1<<12); //PWM1 is synchronized by CCLK (100 MHz)(CCLK) PCLKSEL0 - Peripheral Clock Selection registers. |
igor_v | 0:8ad47e2b6f00 | 291 | |
igor_v | 0:8ad47e2b6f00 | 292 | LPC_PWM1->TCR = TCR_RESET; /* Counter Reset */ //#define TCR_RESET 0x00000002 ���������������� ������� ��� �������� �������� ���. |
igor_v | 0:8ad47e2b6f00 | 293 | LPC_PWM1->MCR = PWMMR0I |PWMMR0R; //generate interrupt and reset timer counter ( PWMMR0I - ���������� ������������ ����� PWMMR0 ��������� �� ��������� PWMTC. ) |
igor_v | 0:8ad47e2b6f00 | 294 | // ( PWMMR0R - ���������� PWMTC ��� ���������� PWMTC � PWMMR0. ) |
igor_v | 0:8ad47e2b6f00 | 295 | |
igor_v | 0:8ad47e2b6f00 | 296 | LPC_PWM1->CCR = 0x1; //��������� ���������� ������ ��� ���������� PWMTC � PWMMR0 (��� ��� �� ������� � ��������� ��) |
igor_v | 0:8ad47e2b6f00 | 297 | |
igor_v | 0:8ad47e2b6f00 | 298 | |
igor_v | 0:8ad47e2b6f00 | 299 | PrevPeriod = 10000; |
igor_v | 0:8ad47e2b6f00 | 300 | LPC_PWM1->MR0 = PrevPeriod; /* set PWM cycle */// ������� ������� ������ ��������. |
igor_v | 0:8ad47e2b6f00 | 301 | LPC_PWM1->PCR = PWMENA1; //e. single edge control mode, PWM1 out enabled only ��������� ������ ��� 1. |
igor_v | 0:8ad47e2b6f00 | 302 | LPC_PWM1->LER = LER0_EN ; //e. enable updating of register |
igor_v | 0:8ad47e2b6f00 | 303 | LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN; /* counter enable, PWM enable */ //��������� �������� � ��� |
igor_v | 0:8ad47e2b6f00 | 304 | |
igor_v | 0:8ad47e2b6f00 | 305 | NVIC_DisableIRQ(PWM1_IRQn);//��������� ����������. |
igor_v | 0:8ad47e2b6f00 | 306 | |
igor_v | 0:8ad47e2b6f00 | 307 | |
igor_v | 0:8ad47e2b6f00 | 308 | return ; |
igor_v | 0:8ad47e2b6f00 | 309 | } |
igor_v | 0:8ad47e2b6f00 | 310 | |
igor_v | 0:8ad47e2b6f00 | 311 | __irq void TIMER0_IRQHandler() |
igor_v | 0:8ad47e2b6f00 | 312 | { |
igor_v | 0:8ad47e2b6f00 | 313 | int val = LPC_TIM0->IR; |
igor_v | 0:8ad47e2b6f00 | 314 | LPC_TIM0->IR |= 3; |
igor_v | 0:8ad47e2b6f00 | 315 | |
igor_v | 0:8ad47e2b6f00 | 316 | if (val & 1) //MAT 1.0 interrupt |
igor_v | 0:8ad47e2b6f00 | 317 | { |
igor_v | 0:8ad47e2b6f00 | 318 | LPC_GPIO2->FIOSET |= 1<<6; // turn on the LED |
igor_v | 0:8ad47e2b6f00 | 319 | LPC_TIM0->IR |= 1; |
igor_v | 0:8ad47e2b6f00 | 320 | return; |
igor_v | 0:8ad47e2b6f00 | 321 | } |
igor_v | 0:8ad47e2b6f00 | 322 | if (val & 2) //MAT 1.1 interrupt |
igor_v | 0:8ad47e2b6f00 | 323 | { |
igor_v | 0:8ad47e2b6f00 | 324 | LPC_GPIO2->FIOCLR |= 1<<6; // turn on the LED |
igor_v | 0:8ad47e2b6f00 | 325 | LPC_TIM0->IR |= 2; |
igor_v | 0:8ad47e2b6f00 | 326 | return; |
igor_v | 0:8ad47e2b6f00 | 327 | } |
igor_v | 0:8ad47e2b6f00 | 328 | if (val & 4) //MAT 0.2 interrupt |
igor_v | 0:8ad47e2b6f00 | 329 | { |
igor_v | 0:8ad47e2b6f00 | 330 | // LPC_GPIO0->FIOSET2 |= 0xFF; //set P0.23 |
igor_v | 0:8ad47e2b6f00 | 331 | // LPC_GPIO2->FIOSET |= 0x00000040; // turn on the LED |
igor_v | 0:8ad47e2b6f00 | 332 | // LPC_TIM0->IR |= 4; |
igor_v | 0:8ad47e2b6f00 | 333 | return; |
igor_v | 0:8ad47e2b6f00 | 334 | } |
igor_v | 0:8ad47e2b6f00 | 335 | return; |
igor_v | 0:8ad47e2b6f00 | 336 | } |
igor_v | 0:8ad47e2b6f00 | 337 | |
igor_v | 0:8ad47e2b6f00 | 338 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 339 | ** Function name: ExtLatch_Init |
igor_v | 0:8ad47e2b6f00 | 340 | ** |
igor_v | 0:8ad47e2b6f00 | 341 | ** Descriptions: Initialization of external latch |
igor_v | 0:8ad47e2b6f00 | 342 | ** |
igor_v | 0:8ad47e2b6f00 | 343 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 344 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 345 | ** |
igor_v | 0:8ad47e2b6f00 | 346 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 347 | void ExtLatch_Init() |
igor_v | 0:8ad47e2b6f00 | 348 | { |
igor_v | 0:8ad47e2b6f00 | 349 | LPC_PINCON->PINSEL4 &= ~0xC000000; //e. ������������ P2.13 ��� GPIO. |
igor_v | 0:8ad47e2b6f00 | 350 | LPC_PINCON->PINSEL0 &= ~0x0C00000; //e. ������������ P0.11 ��� GPIO. |
igor_v | 0:8ad47e2b6f00 | 351 | LPC_GPIO0->FIODIR &= ~0x0000800; //e. ������������ P0.11 �����. |
igor_v | 0:8ad47e2b6f00 | 352 | LPC_GPIOINT->IO0IntEnR &= ~0x0000800; //e. ��������� ���������� �������. |
igor_v | 0:8ad47e2b6f00 | 353 | LPC_GPIOINT->IO0IntClr |= 0x0000800; //e. �������� ������� �� ���������� |
igor_v | 0:8ad47e2b6f00 | 354 | |
igor_v | 0:8ad47e2b6f00 | 355 | NVIC_EnableIRQ(EINT3_IRQn); // ��������� ����������. |
igor_v | 0:8ad47e2b6f00 | 356 | |
igor_v | 0:8ad47e2b6f00 | 357 | //+++++++ initialization of timer for multidrop delay generation+++++++++++++++++++++++ |
igor_v | 0:8ad47e2b6f00 | 358 | //e. TIMER0 enabled by default |
igor_v | 0:8ad47e2b6f00 | 359 | LPC_SC->PCLKSEL0 &= ~(3<<2); //e. �������� ������� ������� 0 |
igor_v | 0:8ad47e2b6f00 | 360 | LPC_SC->PCLKSEL0 |= (3<<2); //e. ���������� ������� ������� 0 �� CLK/8. |
igor_v | 0:8ad47e2b6f00 | 361 | LPC_TIM0->PR = 0; //e. ���������� �������� ������� � 0. |
igor_v | 0:8ad47e2b6f00 | 362 | LPC_TIM0->IR = 0x3F; //e. �������� ����� ����������. |
igor_v | 0:8ad47e2b6f00 | 363 | LPC_TIM0->MCR = 1 |(1<<3)|MR1_RESET |MR1_STOP; //e. �������� � ���������� ������ ����� ���������� MR1 � TC. |
igor_v | 0:8ad47e2b6f00 | 364 | LPC_TIM0->CCR = 0; //e. ���������� ������� ����������� ��� ��������� ��������� ������ �������. |
igor_v | 0:8ad47e2b6f00 | 365 | LPC_TIM0->CTCR = 0; //e. timer0 � ������ �������. |
igor_v | 0:8ad47e2b6f00 | 366 | |
igor_v | 0:8ad47e2b6f00 | 367 | LPC_TIM0->MR0 = /*Device_blk.Address**/10; //e. delay before UART transmitter loading |
igor_v | 0:8ad47e2b6f00 | 368 | LPC_TIM0->MR1 = /*Device_blk.Address**/5000; //e. delay before UART transmitter start |
igor_v | 0:8ad47e2b6f00 | 369 | //e. set first empty) event of timer |
igor_v | 0:8ad47e2b6f00 | 370 | NVIC_DisableIRQ(TIMER0_IRQn); |
igor_v | 0:8ad47e2b6f00 | 371 | } |
igor_v | 0:8ad47e2b6f00 | 372 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 373 | ** Function name: IntLatch_Init |
igor_v | 0:8ad47e2b6f00 | 374 | ** |
igor_v | 0:8ad47e2b6f00 | 375 | ** Descriptions: Initialization of iternal latch cycle generation |
igor_v | 0:8ad47e2b6f00 | 376 | ** |
igor_v | 0:8ad47e2b6f00 | 377 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 378 | ** Returned value: None |
igor_v | 0:8ad47e2b6f00 | 379 | ** |
igor_v | 0:8ad47e2b6f00 | 380 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 381 | void IntLatch_Init() |
igor_v | 0:8ad47e2b6f00 | 382 | { |
igor_v | 0:8ad47e2b6f00 | 383 | LPC_SC->PCONP |= (1<<23); //������� TIME3(������) |
igor_v | 0:8ad47e2b6f00 | 384 | //e. by default timer3 mode is not counter (T3CTCR[1,0]=0) |
igor_v | 0:8ad47e2b6f00 | 385 | |
igor_v | 0:8ad47e2b6f00 | 386 | LPC_SC->PCLKSEL1 &= SYNC_CLCK4; // ������� �������� ������� ����� CLCK/4 |
igor_v | 0:8ad47e2b6f00 | 387 | LPC_SC->PCLKSEL1 |= (1<<14); // timer 3 input frequency equal to CLCK/4 |
igor_v | 0:8ad47e2b6f00 | 388 | |
igor_v | 0:8ad47e2b6f00 | 389 | // LPC_PINCON->PINSEL1 |= (3<<16); //e. CAP 3.1 is connected to P0.24 |
igor_v | 0:8ad47e2b6f00 | 390 | //e. by default CAP3.0 is connected to timer3 |
igor_v | 0:8ad47e2b6f00 | 391 | LPC_TIM3->PR = 0; //e. ���������� ������������ �������3 �� 0. |
igor_v | 0:8ad47e2b6f00 | 392 | LPC_TIM3->IR = 0x0001; //e. �������� ����� ����������. |
igor_v | 0:8ad47e2b6f00 | 393 | LPC_TIM3->MCR = MR0_RESET |MR0_INT_EN |MR0_NO_STOP; // ��������� ������ ���������� ������� ����������� ��� ���������� ������� � ��R. |
igor_v | 0:8ad47e2b6f00 | 394 | LPC_TIM3->CCR = 0x0001; //���������� �������� ����������� �� ������� ��������� ������ �������. |
igor_v | 0:8ad47e2b6f00 | 395 | |
igor_v | 0:8ad47e2b6f00 | 396 | NVIC_EnableIRQ(TIMER3_IRQn); //��������� ����������. |
igor_v | 0:8ad47e2b6f00 | 397 | } |
igor_v | 0:8ad47e2b6f00 | 398 | /***************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 399 | ** Function name: WDTInit |
igor_v | 0:8ad47e2b6f00 | 400 | ** |
igor_v | 0:8ad47e2b6f00 | 401 | ** Descriptions: Initialize watchdog timer, install the |
igor_v | 0:8ad47e2b6f00 | 402 | ** watchdog timer interrupt handler |
igor_v | 0:8ad47e2b6f00 | 403 | ** |
igor_v | 0:8ad47e2b6f00 | 404 | ** parameters: None |
igor_v | 0:8ad47e2b6f00 | 405 | ** Returned value: true or false, return false if the VIC table |
igor_v | 0:8ad47e2b6f00 | 406 | ** is full and WDT interrupt handler can be |
igor_v | 0:8ad47e2b6f00 | 407 | ** installed. |
igor_v | 0:8ad47e2b6f00 | 408 | ** |
igor_v | 0:8ad47e2b6f00 | 409 | *****************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 410 | uint32_t WDTInit( void ) |
igor_v | 0:8ad47e2b6f00 | 411 | { |
igor_v | 0:8ad47e2b6f00 | 412 | NVIC_DisableIRQ(WDT_IRQn); |
igor_v | 0:8ad47e2b6f00 | 413 | |
igor_v | 0:8ad47e2b6f00 | 414 | LPC_WDT->TC = WDT_FEED_VALUE; // once WDEN is set, the WDT will start after feeding |
igor_v | 0:8ad47e2b6f00 | 415 | LPC_WDT->MOD = WDEN; |
igor_v | 0:8ad47e2b6f00 | 416 | |
igor_v | 0:8ad47e2b6f00 | 417 | LPC_WDT->FEED = 0xAA; // Feeding sequence |
igor_v | 0:8ad47e2b6f00 | 418 | LPC_WDT->FEED = 0x55; |
igor_v | 0:8ad47e2b6f00 | 419 | |
igor_v | 0:8ad47e2b6f00 | 420 | return 1; |
igor_v | 0:8ad47e2b6f00 | 421 | } |
igor_v | 0:8ad47e2b6f00 | 422 | /****************************************************************************** |
igor_v | 0:8ad47e2b6f00 | 423 | ** End Of File |
igor_v | 0:8ad47e2b6f00 | 424 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 425 |