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core_cm3.h@11:af609f6dee46, 2016-02-01 (annotated)

Committer:: igor_v
Date:: Mon Feb 01 16:40:49 2016 +0000
Revision:: 11:af609f6dee46
Parent:: 0:8ad47e2b6f00
Child:: 21:bc8c1cec3da6

hreny

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User	Revision	Line number	New contents of line
igor_v	0:8ad47e2b6f00	1	/************************************************************************//
igor_v	0:8ad47e2b6f00	2	* @file core_cm3.h
igor_v	0:8ad47e2b6f00	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
igor_v	11:af609f6dee46	4	* @version V1.30
igor_v	11:af609f6dee46	5	* @date 30. October 2009
igor_v	0:8ad47e2b6f00	6	*
igor_v	0:8ad47e2b6f00	7	* @note
igor_v	11:af609f6dee46	8	* Copyright (C) 2009 ARM Limited. All rights reserved.
igor_v	0:8ad47e2b6f00	9	*
igor_v	0:8ad47e2b6f00	10	* @par
igor_v	0:8ad47e2b6f00	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
igor_v	0:8ad47e2b6f00	12	* processor based microcontrollers. This file can be freely distributed
igor_v	0:8ad47e2b6f00	13	* within development tools that are supporting such ARM based processors.
igor_v	0:8ad47e2b6f00	14	*
igor_v	0:8ad47e2b6f00	15	* @par
igor_v	0:8ad47e2b6f00	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
igor_v	0:8ad47e2b6f00	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
igor_v	0:8ad47e2b6f00	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
igor_v	0:8ad47e2b6f00	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
igor_v	0:8ad47e2b6f00	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
igor_v	0:8ad47e2b6f00	21	*
igor_v	0:8ad47e2b6f00	22	******************************************************************************/
igor_v	11:af609f6dee46	23
igor_v	11:af609f6dee46	24	#ifndef __CM3_CORE_H__
igor_v	11:af609f6dee46	25	#define __CM3_CORE_H__
igor_v	11:af609f6dee46	26
igor_v	11:af609f6dee46	27	/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
igor_v	11:af609f6dee46	28	*
igor_v	11:af609f6dee46	29	* List of Lint messages which will be suppressed and not shown:
igor_v	11:af609f6dee46	30	* - Error 10: \n
igor_v	11:af609f6dee46	31	* register uint32_t __regBasePri __asm("basepri"); \n
igor_v	11:af609f6dee46	32	* Error 10: Expecting ';'
igor_v	11:af609f6dee46	33	* .
igor_v	11:af609f6dee46	34	* - Error 530: \n
igor_v	11:af609f6dee46	35	* return(__regBasePri); \n
igor_v	11:af609f6dee46	36	* Warning 530: Symbol '__regBasePri' (line 264) not initialized
igor_v	11:af609f6dee46	37	* .
igor_v	11:af609f6dee46	38	* - Error 550: \n
igor_v	11:af609f6dee46	39	* __regBasePri = (basePri & 0x1ff); \n
igor_v	11:af609f6dee46	40	* Warning 550: Symbol '__regBasePri' (line 271) not accessed
igor_v	11:af609f6dee46	41	* .
igor_v	11:af609f6dee46	42	* - Error 754: \n
igor_v	11:af609f6dee46	43	* uint32_t RESERVED0[24]; \n
igor_v	11:af609f6dee46	44	* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
igor_v	11:af609f6dee46	45	* .
igor_v	11:af609f6dee46	46	* - Error 750: \n
igor_v	11:af609f6dee46	47	* #define __CM3_CORE_H__ \n
igor_v	11:af609f6dee46	48	* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
igor_v	11:af609f6dee46	49	* .
igor_v	11:af609f6dee46	50	* - Error 528: \n
igor_v	11:af609f6dee46	51	* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
igor_v	11:af609f6dee46	52	* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
igor_v	11:af609f6dee46	53	* .
igor_v	11:af609f6dee46	54	* - Error 751: \n
igor_v	11:af609f6dee46	55	* } InterruptType_Type; \n
igor_v	11:af609f6dee46	56	* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
igor_v	11:af609f6dee46	57	* .
igor_v	11:af609f6dee46	58	* Note: To re-enable a Message, insert a space before 'lint' *
igor_v	11:af609f6dee46	59	*
igor_v	11:af609f6dee46	60	*/
igor_v	11:af609f6dee46	61
igor_v	11:af609f6dee46	62	/lint -save /
igor_v	11:af609f6dee46	63	/lint -e10 /
igor_v	11:af609f6dee46	64	/lint -e530 /
igor_v	11:af609f6dee46	65	/lint -e550 /
igor_v	11:af609f6dee46	66	/lint -e754 /
igor_v	11:af609f6dee46	67	/lint -e750 /
igor_v	11:af609f6dee46	68	/lint -e528 /
igor_v	11:af609f6dee46	69	/lint -e751 /
igor_v	11:af609f6dee46	70
igor_v	11:af609f6dee46	71
igor_v	11:af609f6dee46	72	/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
igor_v	11:af609f6dee46	73	This file defines all structures and symbols for CMSIS core:
igor_v	11:af609f6dee46	74	- CMSIS version number
igor_v	11:af609f6dee46	75	- Cortex-M core registers and bitfields
igor_v	11:af609f6dee46	76	- Cortex-M core peripheral base address
igor_v	11:af609f6dee46	77	@{
igor_v	11:af609f6dee46	78	*/
igor_v	0:8ad47e2b6f00	79
igor_v	0:8ad47e2b6f00	80	#ifdef __cplusplus
igor_v	0:8ad47e2b6f00	81	extern "C" {
igor_v	0:8ad47e2b6f00	82	#endif
igor_v	0:8ad47e2b6f00	83
igor_v	11:af609f6dee46	84	#define __CM3_CMSIS_VERSION_MAIN (0x01) /!< [31:16] CMSIS HAL main version /
igor_v	11:af609f6dee46	85	#define __CM3_CMSIS_VERSION_SUB (0x30) /!< [15:0] CMSIS HAL sub version /
igor_v	0:8ad47e2b6f00	86	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
igor_v	0:8ad47e2b6f00	87
igor_v	0:8ad47e2b6f00	88	#define __CORTEX_M (0x03) /!< Cortex core /
igor_v	0:8ad47e2b6f00	89
igor_v	11:af609f6dee46	90	#include <stdint.h> /* Include standard types */
igor_v	11:af609f6dee46	91
igor_v	11:af609f6dee46	92	#if defined (__ICCARM__)
igor_v	11:af609f6dee46	93	#include <intrinsics.h> /* IAR Intrinsics */
igor_v	11:af609f6dee46	94	#endif
igor_v	11:af609f6dee46	95
igor_v	11:af609f6dee46	96
igor_v	11:af609f6dee46	97	#ifndef __NVIC_PRIO_BITS
igor_v	11:af609f6dee46	98	#define __NVIC_PRIO_BITS 4 /!< standard definition for NVIC Priority Bits /
igor_v	11:af609f6dee46	99	#endif
igor_v	11:af609f6dee46	100
igor_v	11:af609f6dee46	101
igor_v	11:af609f6dee46	102
igor_v	11:af609f6dee46	103
igor_v	11:af609f6dee46	104	/**
igor_v	11:af609f6dee46	105	* IO definitions
igor_v	11:af609f6dee46	106	*
igor_v	11:af609f6dee46	107	* define access restrictions to peripheral registers
igor_v	11:af609f6dee46	108	*/
igor_v	11:af609f6dee46	109
igor_v	11:af609f6dee46	110	#ifdef __cplusplus
igor_v	11:af609f6dee46	111	#define __I volatile /!< defines 'read only' permissions /
igor_v	11:af609f6dee46	112	#else
igor_v	11:af609f6dee46	113	#define __I volatile const /!< defines 'read only' permissions /
igor_v	11:af609f6dee46	114	#endif
igor_v	11:af609f6dee46	115	#define __O volatile /!< defines 'write only' permissions /
igor_v	11:af609f6dee46	116	#define __IO volatile /!< defines 'read / write' permissions /
igor_v	11:af609f6dee46	117
igor_v	11:af609f6dee46	118
igor_v	11:af609f6dee46	119
igor_v	11:af609f6dee46	120	/*******************************************************************************
igor_v	11:af609f6dee46	121	* Register Abstraction
igor_v	11:af609f6dee46	122	******************************************************************************/
igor_v	11:af609f6dee46	123	/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
igor_v	11:af609f6dee46	124	@{
igor_v	11:af609f6dee46	125	*/
igor_v	11:af609f6dee46	126
igor_v	11:af609f6dee46	127
igor_v	11:af609f6dee46	128	/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
igor_v	11:af609f6dee46	129	memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
igor_v	11:af609f6dee46	130	@{
igor_v	11:af609f6dee46	131	*/
igor_v	11:af609f6dee46	132	typedef struct
igor_v	11:af609f6dee46	133	{
igor_v	11:af609f6dee46	134	__IO uint32_t ISER[8]; /!< Offset: 0x000 Interrupt Set Enable Register /
igor_v	11:af609f6dee46	135	uint32_t RESERVED0[24];
igor_v	11:af609f6dee46	136	__IO uint32_t ICER[8]; /!< Offset: 0x080 Interrupt Clear Enable Register /
igor_v	11:af609f6dee46	137	uint32_t RSERVED1[24];
igor_v	11:af609f6dee46	138	__IO uint32_t ISPR[8]; /!< Offset: 0x100 Interrupt Set Pending Register /
igor_v	11:af609f6dee46	139	uint32_t RESERVED2[24];
igor_v	11:af609f6dee46	140	__IO uint32_t ICPR[8]; /!< Offset: 0x180 Interrupt Clear Pending Register /
igor_v	11:af609f6dee46	141	uint32_t RESERVED3[24];
igor_v	11:af609f6dee46	142	__IO uint32_t IABR[8]; /!< Offset: 0x200 Interrupt Active bit Register /
igor_v	11:af609f6dee46	143	uint32_t RESERVED4[56];
igor_v	11:af609f6dee46	144	__IO uint8_t IP[240]; /!< Offset: 0x300 Interrupt Priority Register (8Bit wide) /
igor_v	11:af609f6dee46	145	uint32_t RESERVED5[644];
igor_v	11:af609f6dee46	146	__O uint32_t STIR; /!< Offset: 0xE00 Software Trigger Interrupt Register /
igor_v	11:af609f6dee46	147	} NVIC_Type;
igor_v	11:af609f6dee46	148	/@}/ /* end of group CMSIS_CM3_NVIC */
igor_v	11:af609f6dee46	149
igor_v	11:af609f6dee46	150
igor_v	11:af609f6dee46	151	/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
igor_v	11:af609f6dee46	152	memory mapped structure for System Control Block (SCB)
igor_v	11:af609f6dee46	153	@{
igor_v	11:af609f6dee46	154	*/
igor_v	11:af609f6dee46	155	typedef struct
igor_v	11:af609f6dee46	156	{
igor_v	11:af609f6dee46	157	__I uint32_t CPUID; /!< Offset: 0x00 CPU ID Base Register /
igor_v	11:af609f6dee46	158	__IO uint32_t ICSR; /!< Offset: 0x04 Interrupt Control State Register /
igor_v	11:af609f6dee46	159	__IO uint32_t VTOR; /!< Offset: 0x08 Vector Table Offset Register /
igor_v	11:af609f6dee46	160	__IO uint32_t AIRCR; /!< Offset: 0x0C Application Interrupt / Reset Control Register /
igor_v	11:af609f6dee46	161	__IO uint32_t SCR; /!< Offset: 0x10 System Control Register /
igor_v	11:af609f6dee46	162	__IO uint32_t CCR; /!< Offset: 0x14 Configuration Control Register /
igor_v	11:af609f6dee46	163	__IO uint8_t SHP[12]; /!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) /
igor_v	11:af609f6dee46	164	__IO uint32_t SHCSR; /!< Offset: 0x24 System Handler Control and State Register /
igor_v	11:af609f6dee46	165	__IO uint32_t CFSR; /!< Offset: 0x28 Configurable Fault Status Register /
igor_v	11:af609f6dee46	166	__IO uint32_t HFSR; /!< Offset: 0x2C Hard Fault Status Register /
igor_v	11:af609f6dee46	167	__IO uint32_t DFSR; /!< Offset: 0x30 Debug Fault Status Register /
igor_v	11:af609f6dee46	168	__IO uint32_t MMFAR; /!< Offset: 0x34 Mem Manage Address Register /
igor_v	11:af609f6dee46	169	__IO uint32_t BFAR; /!< Offset: 0x38 Bus Fault Address Register /
igor_v	11:af609f6dee46	170	__IO uint32_t AFSR; /!< Offset: 0x3C Auxiliary Fault Status Register /
igor_v	11:af609f6dee46	171	__I uint32_t PFR[2]; /!< Offset: 0x40 Processor Feature Register /
igor_v	11:af609f6dee46	172	__I uint32_t DFR; /!< Offset: 0x48 Debug Feature Register /
igor_v	11:af609f6dee46	173	__I uint32_t ADR; /!< Offset: 0x4C Auxiliary Feature Register /
igor_v	11:af609f6dee46	174	__I uint32_t MMFR[4]; /!< Offset: 0x50 Memory Model Feature Register /
igor_v	11:af609f6dee46	175	__I uint32_t ISAR[5]; /!< Offset: 0x60 ISA Feature Register /
igor_v	11:af609f6dee46	176	} SCB_Type;
igor_v	11:af609f6dee46	177
igor_v	11:af609f6dee46	178	/* SCB CPUID Register Definitions */
igor_v	11:af609f6dee46	179	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
igor_v	11:af609f6dee46	180	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
igor_v	11:af609f6dee46	181
igor_v	11:af609f6dee46	182	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
igor_v	11:af609f6dee46	183	#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
igor_v	11:af609f6dee46	184
igor_v	11:af609f6dee46	185	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
igor_v	11:af609f6dee46	186	#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
igor_v	11:af609f6dee46	187
igor_v	11:af609f6dee46	188	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
igor_v	11:af609f6dee46	189	#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
igor_v	11:af609f6dee46	190
igor_v	11:af609f6dee46	191	/* SCB Interrupt Control State Register Definitions */
igor_v	11:af609f6dee46	192	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
igor_v	11:af609f6dee46	193	#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
igor_v	11:af609f6dee46	194
igor_v	11:af609f6dee46	195	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
igor_v	11:af609f6dee46	196	#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
igor_v	11:af609f6dee46	197
igor_v	11:af609f6dee46	198	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
igor_v	11:af609f6dee46	199	#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
igor_v	11:af609f6dee46	200
igor_v	11:af609f6dee46	201	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
igor_v	11:af609f6dee46	202	#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
igor_v	11:af609f6dee46	203
igor_v	11:af609f6dee46	204	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
igor_v	11:af609f6dee46	205	#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
igor_v	11:af609f6dee46	206
igor_v	11:af609f6dee46	207	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
igor_v	11:af609f6dee46	208	#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
igor_v	11:af609f6dee46	209
igor_v	11:af609f6dee46	210	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
igor_v	11:af609f6dee46	211	#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
igor_v	11:af609f6dee46	212
igor_v	11:af609f6dee46	213	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
igor_v	11:af609f6dee46	214	#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
igor_v	11:af609f6dee46	215
igor_v	11:af609f6dee46	216	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
igor_v	11:af609f6dee46	217	#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
igor_v	11:af609f6dee46	218
igor_v	11:af609f6dee46	219	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
igor_v	11:af609f6dee46	220	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
igor_v	11:af609f6dee46	221
igor_v	11:af609f6dee46	222	/* SCB Interrupt Control State Register Definitions */
igor_v	11:af609f6dee46	223	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
igor_v	11:af609f6dee46	224	#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
igor_v	11:af609f6dee46	225
igor_v	11:af609f6dee46	226	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
igor_v	11:af609f6dee46	227	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
igor_v	11:af609f6dee46	228
igor_v	11:af609f6dee46	229	/* SCB Application Interrupt and Reset Control Register Definitions */
igor_v	11:af609f6dee46	230	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
igor_v	11:af609f6dee46	231	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
igor_v	11:af609f6dee46	232
igor_v	11:af609f6dee46	233	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
igor_v	11:af609f6dee46	234	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
igor_v	11:af609f6dee46	235
igor_v	11:af609f6dee46	236	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
igor_v	11:af609f6dee46	237	#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
igor_v	11:af609f6dee46	238
igor_v	11:af609f6dee46	239	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
igor_v	11:af609f6dee46	240	#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
igor_v	11:af609f6dee46	241
igor_v	11:af609f6dee46	242	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
igor_v	11:af609f6dee46	243	#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
igor_v	11:af609f6dee46	244
igor_v	11:af609f6dee46	245	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
igor_v	11:af609f6dee46	246	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
igor_v	11:af609f6dee46	247
igor_v	11:af609f6dee46	248	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
igor_v	11:af609f6dee46	249	#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
igor_v	11:af609f6dee46	250
igor_v	11:af609f6dee46	251	/* SCB System Control Register Definitions */
igor_v	11:af609f6dee46	252	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
igor_v	11:af609f6dee46	253	#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
igor_v	11:af609f6dee46	254
igor_v	11:af609f6dee46	255	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
igor_v	11:af609f6dee46	256	#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
igor_v	11:af609f6dee46	257
igor_v	11:af609f6dee46	258	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
igor_v	11:af609f6dee46	259	#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
igor_v	11:af609f6dee46	260
igor_v	11:af609f6dee46	261	/* SCB Configuration Control Register Definitions */
igor_v	11:af609f6dee46	262	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
igor_v	11:af609f6dee46	263	#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
igor_v	11:af609f6dee46	264
igor_v	11:af609f6dee46	265	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
igor_v	11:af609f6dee46	266	#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
igor_v	11:af609f6dee46	267
igor_v	11:af609f6dee46	268	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
igor_v	11:af609f6dee46	269	#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
igor_v	11:af609f6dee46	270
igor_v	11:af609f6dee46	271	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
igor_v	11:af609f6dee46	272	#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
igor_v	11:af609f6dee46	273
igor_v	11:af609f6dee46	274	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
igor_v	11:af609f6dee46	275	#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
igor_v	11:af609f6dee46	276
igor_v	11:af609f6dee46	277	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
igor_v	11:af609f6dee46	278	#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
igor_v	11:af609f6dee46	279
igor_v	11:af609f6dee46	280	/* SCB System Handler Control and State Register Definitions */
igor_v	11:af609f6dee46	281	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
igor_v	11:af609f6dee46	282	#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
igor_v	11:af609f6dee46	283
igor_v	11:af609f6dee46	284	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
igor_v	11:af609f6dee46	285	#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
igor_v	11:af609f6dee46	286
igor_v	11:af609f6dee46	287	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
igor_v	11:af609f6dee46	288	#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
igor_v	11:af609f6dee46	289
igor_v	11:af609f6dee46	290	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
igor_v	11:af609f6dee46	291	#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
igor_v	11:af609f6dee46	292
igor_v	11:af609f6dee46	293	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
igor_v	11:af609f6dee46	294	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
igor_v	11:af609f6dee46	295
igor_v	11:af609f6dee46	296	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
igor_v	11:af609f6dee46	297	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
igor_v	11:af609f6dee46	298
igor_v	11:af609f6dee46	299	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
igor_v	11:af609f6dee46	300	#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
igor_v	11:af609f6dee46	301
igor_v	11:af609f6dee46	302	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
igor_v	11:af609f6dee46	303	#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
igor_v	11:af609f6dee46	304
igor_v	11:af609f6dee46	305	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
igor_v	11:af609f6dee46	306	#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
igor_v	11:af609f6dee46	307
igor_v	11:af609f6dee46	308	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
igor_v	11:af609f6dee46	309	#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
igor_v	11:af609f6dee46	310
igor_v	11:af609f6dee46	311	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
igor_v	11:af609f6dee46	312	#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
igor_v	11:af609f6dee46	313
igor_v	11:af609f6dee46	314	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
igor_v	11:af609f6dee46	315	#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
igor_v	11:af609f6dee46	316
igor_v	11:af609f6dee46	317	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
igor_v	11:af609f6dee46	318	#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
igor_v	11:af609f6dee46	319
igor_v	11:af609f6dee46	320	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
igor_v	11:af609f6dee46	321	#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
igor_v	11:af609f6dee46	322
igor_v	11:af609f6dee46	323	/* SCB Configurable Fault Status Registers Definitions */
igor_v	11:af609f6dee46	324	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
igor_v	11:af609f6dee46	325	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
igor_v	11:af609f6dee46	326
igor_v	11:af609f6dee46	327	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
igor_v	11:af609f6dee46	328	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
igor_v	11:af609f6dee46	329
igor_v	11:af609f6dee46	330	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
igor_v	11:af609f6dee46	331	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
igor_v	11:af609f6dee46	332
igor_v	11:af609f6dee46	333	/* SCB Hard Fault Status Registers Definitions */
igor_v	11:af609f6dee46	334	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
igor_v	11:af609f6dee46	335	#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
igor_v	11:af609f6dee46	336
igor_v	11:af609f6dee46	337	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
igor_v	11:af609f6dee46	338	#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
igor_v	11:af609f6dee46	339
igor_v	11:af609f6dee46	340	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
igor_v	11:af609f6dee46	341	#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
igor_v	11:af609f6dee46	342
igor_v	11:af609f6dee46	343	/* SCB Debug Fault Status Register Definitions */
igor_v	11:af609f6dee46	344	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
igor_v	11:af609f6dee46	345	#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
igor_v	11:af609f6dee46	346
igor_v	11:af609f6dee46	347	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
igor_v	11:af609f6dee46	348	#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
igor_v	11:af609f6dee46	349
igor_v	11:af609f6dee46	350	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
igor_v	11:af609f6dee46	351	#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
igor_v	11:af609f6dee46	352
igor_v	11:af609f6dee46	353	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
igor_v	11:af609f6dee46	354	#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
igor_v	11:af609f6dee46	355
igor_v	11:af609f6dee46	356	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
igor_v	11:af609f6dee46	357	#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
igor_v	11:af609f6dee46	358	/@}/ /* end of group CMSIS_CM3_SCB */
igor_v	11:af609f6dee46	359
igor_v	11:af609f6dee46	360
igor_v	11:af609f6dee46	361	/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
igor_v	11:af609f6dee46	362	memory mapped structure for SysTick
igor_v	11:af609f6dee46	363	@{
igor_v	11:af609f6dee46	364	*/
igor_v	11:af609f6dee46	365	typedef struct
igor_v	11:af609f6dee46	366	{
igor_v	11:af609f6dee46	367	__IO uint32_t CTRL; /!< Offset: 0x00 SysTick Control and Status Register /
igor_v	11:af609f6dee46	368	__IO uint32_t LOAD; /!< Offset: 0x04 SysTick Reload Value Register /
igor_v	11:af609f6dee46	369	__IO uint32_t VAL; /!< Offset: 0x08 SysTick Current Value Register /
igor_v	11:af609f6dee46	370	__I uint32_t CALIB; /!< Offset: 0x0C SysTick Calibration Register /
igor_v	11:af609f6dee46	371	} SysTick_Type;
igor_v	11:af609f6dee46	372
igor_v	11:af609f6dee46	373	/* SysTick Control / Status Register Definitions */
igor_v	11:af609f6dee46	374	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
igor_v	11:af609f6dee46	375	#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
igor_v	11:af609f6dee46	376
igor_v	11:af609f6dee46	377	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
igor_v	11:af609f6dee46	378	#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
igor_v	11:af609f6dee46	379
igor_v	11:af609f6dee46	380	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
igor_v	11:af609f6dee46	381	#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
igor_v	11:af609f6dee46	382
igor_v	11:af609f6dee46	383	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
igor_v	11:af609f6dee46	384	#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
igor_v	11:af609f6dee46	385
igor_v	11:af609f6dee46	386	/* SysTick Reload Register Definitions */
igor_v	11:af609f6dee46	387	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
igor_v	11:af609f6dee46	388	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
igor_v	11:af609f6dee46	389
igor_v	11:af609f6dee46	390	/* SysTick Current Register Definitions */
igor_v	11:af609f6dee46	391	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
igor_v	11:af609f6dee46	392	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
igor_v	11:af609f6dee46	393
igor_v	11:af609f6dee46	394	/* SysTick Calibration Register Definitions */
igor_v	11:af609f6dee46	395	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
igor_v	11:af609f6dee46	396	#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
igor_v	11:af609f6dee46	397
igor_v	11:af609f6dee46	398	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
igor_v	11:af609f6dee46	399	#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
igor_v	11:af609f6dee46	400
igor_v	11:af609f6dee46	401	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
igor_v	11:af609f6dee46	402	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
igor_v	11:af609f6dee46	403	/@}/ /* end of group CMSIS_CM3_SysTick */
igor_v	11:af609f6dee46	404
igor_v	11:af609f6dee46	405
igor_v	11:af609f6dee46	406	/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
igor_v	11:af609f6dee46	407	memory mapped structure for Instrumentation Trace Macrocell (ITM)
igor_v	11:af609f6dee46	408	@{
igor_v	11:af609f6dee46	409	*/
igor_v	11:af609f6dee46	410	typedef struct
igor_v	11:af609f6dee46	411	{
igor_v	11:af609f6dee46	412	__O union
igor_v	11:af609f6dee46	413	{
igor_v	11:af609f6dee46	414	__O uint8_t u8; /!< Offset: ITM Stimulus Port 8-bit /
igor_v	11:af609f6dee46	415	__O uint16_t u16; /!< Offset: ITM Stimulus Port 16-bit /
igor_v	11:af609f6dee46	416	__O uint32_t u32; /!< Offset: ITM Stimulus Port 32-bit /
igor_v	11:af609f6dee46	417	} PORT [32]; /!< Offset: 0x00 ITM Stimulus Port Registers /
igor_v	11:af609f6dee46	418	uint32_t RESERVED0[864];
igor_v	11:af609f6dee46	419	__IO uint32_t TER; /!< Offset: ITM Trace Enable Register /
igor_v	11:af609f6dee46	420	uint32_t RESERVED1[15];
igor_v	11:af609f6dee46	421	__IO uint32_t TPR; /!< Offset: ITM Trace Privilege Register /
igor_v	11:af609f6dee46	422	uint32_t RESERVED2[15];
igor_v	11:af609f6dee46	423	__IO uint32_t TCR; /!< Offset: ITM Trace Control Register /
igor_v	11:af609f6dee46	424	uint32_t RESERVED3[29];
igor_v	11:af609f6dee46	425	__IO uint32_t IWR; /!< Offset: ITM Integration Write Register /
igor_v	11:af609f6dee46	426	__IO uint32_t IRR; /!< Offset: ITM Integration Read Register /
igor_v	11:af609f6dee46	427	__IO uint32_t IMCR; /!< Offset: ITM Integration Mode Control Register /
igor_v	11:af609f6dee46	428	uint32_t RESERVED4[43];
igor_v	11:af609f6dee46	429	__IO uint32_t LAR; /!< Offset: ITM Lock Access Register /
igor_v	11:af609f6dee46	430	__IO uint32_t LSR; /!< Offset: ITM Lock Status Register /
igor_v	11:af609f6dee46	431	uint32_t RESERVED5[6];
igor_v	11:af609f6dee46	432	__I uint32_t PID4; /!< Offset: ITM Peripheral Identification Register #4 /
igor_v	11:af609f6dee46	433	__I uint32_t PID5; /!< Offset: ITM Peripheral Identification Register #5 /
igor_v	11:af609f6dee46	434	__I uint32_t PID6; /!< Offset: ITM Peripheral Identification Register #6 /
igor_v	11:af609f6dee46	435	__I uint32_t PID7; /!< Offset: ITM Peripheral Identification Register #7 /
igor_v	11:af609f6dee46	436	__I uint32_t PID0; /!< Offset: ITM Peripheral Identification Register #0 /
igor_v	11:af609f6dee46	437	__I uint32_t PID1; /!< Offset: ITM Peripheral Identification Register #1 /
igor_v	11:af609f6dee46	438	__I uint32_t PID2; /!< Offset: ITM Peripheral Identification Register #2 /
igor_v	11:af609f6dee46	439	__I uint32_t PID3; /!< Offset: ITM Peripheral Identification Register #3 /
igor_v	11:af609f6dee46	440	__I uint32_t CID0; /!< Offset: ITM Component Identification Register #0 /
igor_v	11:af609f6dee46	441	__I uint32_t CID1; /!< Offset: ITM Component Identification Register #1 /
igor_v	11:af609f6dee46	442	__I uint32_t CID2; /!< Offset: ITM Component Identification Register #2 /
igor_v	11:af609f6dee46	443	__I uint32_t CID3; /!< Offset: ITM Component Identification Register #3 /
igor_v	11:af609f6dee46	444	} ITM_Type;
igor_v	11:af609f6dee46	445
igor_v	11:af609f6dee46	446	/* ITM Trace Privilege Register Definitions */
igor_v	11:af609f6dee46	447	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
igor_v	11:af609f6dee46	448	#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
igor_v	11:af609f6dee46	449
igor_v	11:af609f6dee46	450	/* ITM Trace Control Register Definitions */
igor_v	11:af609f6dee46	451	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
igor_v	11:af609f6dee46	452	#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
igor_v	11:af609f6dee46	453
igor_v	11:af609f6dee46	454	#define ITM_TCR_ATBID_Pos 16 /!< ITM TCR: ATBID Position /
igor_v	11:af609f6dee46	455	#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /!< ITM TCR: ATBID Mask /
igor_v	11:af609f6dee46	456
igor_v	11:af609f6dee46	457	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
igor_v	11:af609f6dee46	458	#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
igor_v	11:af609f6dee46	459
igor_v	11:af609f6dee46	460	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
igor_v	11:af609f6dee46	461	#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
igor_v	11:af609f6dee46	462
igor_v	11:af609f6dee46	463	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
igor_v	11:af609f6dee46	464	#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
igor_v	11:af609f6dee46	465
igor_v	11:af609f6dee46	466	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
igor_v	11:af609f6dee46	467	#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
igor_v	11:af609f6dee46	468
igor_v	11:af609f6dee46	469	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
igor_v	11:af609f6dee46	470	#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
igor_v	11:af609f6dee46	471
igor_v	11:af609f6dee46	472	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
igor_v	11:af609f6dee46	473	#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
igor_v	11:af609f6dee46	474
igor_v	11:af609f6dee46	475	/* ITM Integration Write Register Definitions */
igor_v	11:af609f6dee46	476	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
igor_v	11:af609f6dee46	477	#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
igor_v	11:af609f6dee46	478
igor_v	11:af609f6dee46	479	/* ITM Integration Read Register Definitions */
igor_v	11:af609f6dee46	480	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
igor_v	11:af609f6dee46	481	#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
igor_v	11:af609f6dee46	482
igor_v	11:af609f6dee46	483	/* ITM Integration Mode Control Register Definitions */
igor_v	11:af609f6dee46	484	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
igor_v	11:af609f6dee46	485	#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
igor_v	11:af609f6dee46	486
igor_v	11:af609f6dee46	487	/* ITM Lock Status Register Definitions */
igor_v	11:af609f6dee46	488	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
igor_v	11:af609f6dee46	489	#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
igor_v	11:af609f6dee46	490
igor_v	11:af609f6dee46	491	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
igor_v	11:af609f6dee46	492	#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
igor_v	11:af609f6dee46	493
igor_v	11:af609f6dee46	494	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
igor_v	11:af609f6dee46	495	#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
igor_v	11:af609f6dee46	496	/@}/ /* end of group CMSIS_CM3_ITM */
igor_v	11:af609f6dee46	497
igor_v	11:af609f6dee46	498
igor_v	11:af609f6dee46	499	/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
igor_v	11:af609f6dee46	500	memory mapped structure for Interrupt Type
igor_v	11:af609f6dee46	501	@{
igor_v	11:af609f6dee46	502	*/
igor_v	11:af609f6dee46	503	typedef struct
igor_v	11:af609f6dee46	504	{
igor_v	11:af609f6dee46	505	uint32_t RESERVED0;
igor_v	11:af609f6dee46	506	__I uint32_t ICTR; /!< Offset: 0x04 Interrupt Control Type Register /
igor_v	11:af609f6dee46	507	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
igor_v	11:af609f6dee46	508	__IO uint32_t ACTLR; /!< Offset: 0x08 Auxiliary Control Register /
igor_v	11:af609f6dee46	509	#else
igor_v	11:af609f6dee46	510	uint32_t RESERVED1;
igor_v	11:af609f6dee46	511	#endif
igor_v	11:af609f6dee46	512	} InterruptType_Type;
igor_v	11:af609f6dee46	513
igor_v	11:af609f6dee46	514	/* Interrupt Controller Type Register Definitions */
igor_v	11:af609f6dee46	515	#define InterruptType_ICTR_INTLINESNUM_Pos 0 /!< InterruptType ICTR: INTLINESNUM Position /
igor_v	11:af609f6dee46	516	#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /!< InterruptType ICTR: INTLINESNUM Mask /
igor_v	11:af609f6dee46	517
igor_v	11:af609f6dee46	518	/* Auxiliary Control Register Definitions */
igor_v	11:af609f6dee46	519	#define InterruptType_ACTLR_DISFOLD_Pos 2 /!< InterruptType ACTLR: DISFOLD Position /
igor_v	11:af609f6dee46	520	#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /!< InterruptType ACTLR: DISFOLD Mask /
igor_v	11:af609f6dee46	521
igor_v	11:af609f6dee46	522	#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /!< InterruptType ACTLR: DISDEFWBUF Position /
igor_v	11:af609f6dee46	523	#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /!< InterruptType ACTLR: DISDEFWBUF Mask /
igor_v	11:af609f6dee46	524
igor_v	11:af609f6dee46	525	#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /!< InterruptType ACTLR: DISMCYCINT Position /
igor_v	11:af609f6dee46	526	#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /!< InterruptType ACTLR: DISMCYCINT Mask /
igor_v	11:af609f6dee46	527	/@}/ /* end of group CMSIS_CM3_InterruptType */
igor_v	11:af609f6dee46	528
igor_v	11:af609f6dee46	529
igor_v	11:af609f6dee46	530	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
igor_v	11:af609f6dee46	531	/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
igor_v	11:af609f6dee46	532	memory mapped structure for Memory Protection Unit (MPU)
igor_v	11:af609f6dee46	533	@{
igor_v	11:af609f6dee46	534	*/
igor_v	11:af609f6dee46	535	typedef struct
igor_v	11:af609f6dee46	536	{
igor_v	11:af609f6dee46	537	__I uint32_t TYPE; /!< Offset: 0x00 MPU Type Register /
igor_v	11:af609f6dee46	538	__IO uint32_t CTRL; /!< Offset: 0x04 MPU Control Register /
igor_v	11:af609f6dee46	539	__IO uint32_t RNR; /!< Offset: 0x08 MPU Region RNRber Register /
igor_v	11:af609f6dee46	540	__IO uint32_t RBAR; /!< Offset: 0x0C MPU Region Base Address Register /
igor_v	11:af609f6dee46	541	__IO uint32_t RASR; /!< Offset: 0x10 MPU Region Attribute and Size Register /
igor_v	11:af609f6dee46	542	__IO uint32_t RBAR_A1; /!< Offset: 0x14 MPU Alias 1 Region Base Address Register /
igor_v	11:af609f6dee46	543	__IO uint32_t RASR_A1; /!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register /
igor_v	11:af609f6dee46	544	__IO uint32_t RBAR_A2; /!< Offset: 0x1C MPU Alias 2 Region Base Address Register /
igor_v	11:af609f6dee46	545	__IO uint32_t RASR_A2; /!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register /
igor_v	11:af609f6dee46	546	__IO uint32_t RBAR_A3; /!< Offset: 0x24 MPU Alias 3 Region Base Address Register /
igor_v	11:af609f6dee46	547	__IO uint32_t RASR_A3; /!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register /
igor_v	11:af609f6dee46	548	} MPU_Type;
igor_v	11:af609f6dee46	549
igor_v	11:af609f6dee46	550	/* MPU Type Register */
igor_v	11:af609f6dee46	551	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
igor_v	11:af609f6dee46	552	#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
igor_v	11:af609f6dee46	553
igor_v	11:af609f6dee46	554	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
igor_v	11:af609f6dee46	555	#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
igor_v	11:af609f6dee46	556
igor_v	11:af609f6dee46	557	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
igor_v	11:af609f6dee46	558	#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
igor_v	11:af609f6dee46	559
igor_v	11:af609f6dee46	560	/* MPU Control Register */
igor_v	11:af609f6dee46	561	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
igor_v	11:af609f6dee46	562	#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
igor_v	11:af609f6dee46	563
igor_v	11:af609f6dee46	564	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
igor_v	11:af609f6dee46	565	#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
igor_v	11:af609f6dee46	566
igor_v	11:af609f6dee46	567	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
igor_v	11:af609f6dee46	568	#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
igor_v	11:af609f6dee46	569
igor_v	11:af609f6dee46	570	/* MPU Region Number Register */
igor_v	11:af609f6dee46	571	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
igor_v	11:af609f6dee46	572	#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
igor_v	11:af609f6dee46	573
igor_v	11:af609f6dee46	574	/* MPU Region Base Address Register */
igor_v	11:af609f6dee46	575	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
igor_v	11:af609f6dee46	576	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
igor_v	11:af609f6dee46	577
igor_v	11:af609f6dee46	578	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
igor_v	11:af609f6dee46	579	#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
igor_v	11:af609f6dee46	580
igor_v	11:af609f6dee46	581	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
igor_v	11:af609f6dee46	582	#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
igor_v	11:af609f6dee46	583
igor_v	11:af609f6dee46	584	/* MPU Region Attribute and Size Register */
igor_v	11:af609f6dee46	585	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: XN Position /
igor_v	11:af609f6dee46	586	#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /!< MPU RASR: XN Mask /
igor_v	11:af609f6dee46	587
igor_v	11:af609f6dee46	588	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: AP Position /
igor_v	11:af609f6dee46	589	#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /!< MPU RASR: AP Mask /
igor_v	11:af609f6dee46	590
igor_v	11:af609f6dee46	591	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: TEX Position /
igor_v	11:af609f6dee46	592	#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /!< MPU RASR: TEX Mask /
igor_v	11:af609f6dee46	593
igor_v	11:af609f6dee46	594	#define MPU_RASR_S_Pos 18 /!< MPU RASR: Shareable bit Position /
igor_v	11:af609f6dee46	595	#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /!< MPU RASR: Shareable bit Mask /
igor_v	11:af609f6dee46	596
igor_v	11:af609f6dee46	597	#define MPU_RASR_C_Pos 17 /!< MPU RASR: Cacheable bit Position /
igor_v	11:af609f6dee46	598	#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /!< MPU RASR: Cacheable bit Mask /
igor_v	11:af609f6dee46	599
igor_v	11:af609f6dee46	600	#define MPU_RASR_B_Pos 16 /!< MPU RASR: Bufferable bit Position /
igor_v	11:af609f6dee46	601	#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /!< MPU RASR: Bufferable bit Mask /
igor_v	11:af609f6dee46	602
igor_v	11:af609f6dee46	603	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
igor_v	11:af609f6dee46	604	#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
igor_v	11:af609f6dee46	605
igor_v	11:af609f6dee46	606	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
igor_v	11:af609f6dee46	607	#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
igor_v	11:af609f6dee46	608
igor_v	11:af609f6dee46	609	#define MPU_RASR_ENA_Pos 0 /!< MPU RASR: Region enable bit Position /
igor_v	11:af609f6dee46	610	#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /!< MPU RASR: Region enable bit Disable Mask /
igor_v	11:af609f6dee46	611
igor_v	11:af609f6dee46	612	/@}/ /* end of group CMSIS_CM3_MPU */
igor_v	11:af609f6dee46	613	#endif
igor_v	11:af609f6dee46	614
igor_v	11:af609f6dee46	615
igor_v	11:af609f6dee46	616	/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
igor_v	11:af609f6dee46	617	memory mapped structure for Core Debug Register
igor_v	11:af609f6dee46	618	@{
igor_v	11:af609f6dee46	619	*/
igor_v	11:af609f6dee46	620	typedef struct
igor_v	11:af609f6dee46	621	{
igor_v	11:af609f6dee46	622	__IO uint32_t DHCSR; /!< Offset: 0x00 Debug Halting Control and Status Register /
igor_v	11:af609f6dee46	623	__O uint32_t DCRSR; /!< Offset: 0x04 Debug Core Register Selector Register /
igor_v	11:af609f6dee46	624	__IO uint32_t DCRDR; /!< Offset: 0x08 Debug Core Register Data Register /
igor_v	11:af609f6dee46	625	__IO uint32_t DEMCR; /!< Offset: 0x0C Debug Exception and Monitor Control Register /
igor_v	11:af609f6dee46	626	} CoreDebug_Type;
igor_v	11:af609f6dee46	627
igor_v	11:af609f6dee46	628	/* Debug Halting Control and Status Register */
igor_v	11:af609f6dee46	629	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
igor_v	11:af609f6dee46	630	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
igor_v	11:af609f6dee46	631
igor_v	11:af609f6dee46	632	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
igor_v	11:af609f6dee46	633	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
igor_v	11:af609f6dee46	634
igor_v	11:af609f6dee46	635	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
igor_v	11:af609f6dee46	636	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
igor_v	11:af609f6dee46	637
igor_v	11:af609f6dee46	638	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
igor_v	11:af609f6dee46	639	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
igor_v	11:af609f6dee46	640
igor_v	11:af609f6dee46	641	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
igor_v	11:af609f6dee46	642	#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
igor_v	11:af609f6dee46	643
igor_v	11:af609f6dee46	644	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
igor_v	11:af609f6dee46	645	#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
igor_v	11:af609f6dee46	646
igor_v	11:af609f6dee46	647	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
igor_v	11:af609f6dee46	648	#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
igor_v	11:af609f6dee46	649
igor_v	11:af609f6dee46	650	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
igor_v	11:af609f6dee46	651	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
igor_v	11:af609f6dee46	652
igor_v	11:af609f6dee46	653	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
igor_v	11:af609f6dee46	654	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
igor_v	11:af609f6dee46	655
igor_v	11:af609f6dee46	656	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
igor_v	11:af609f6dee46	657	#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
igor_v	11:af609f6dee46	658
igor_v	11:af609f6dee46	659	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
igor_v	11:af609f6dee46	660	#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
igor_v	11:af609f6dee46	661
igor_v	11:af609f6dee46	662	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
igor_v	11:af609f6dee46	663	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
igor_v	11:af609f6dee46	664
igor_v	11:af609f6dee46	665	/* Debug Core Register Selector Register */
igor_v	11:af609f6dee46	666	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
igor_v	11:af609f6dee46	667	#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
igor_v	11:af609f6dee46	668
igor_v	11:af609f6dee46	669	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
igor_v	11:af609f6dee46	670	#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
igor_v	11:af609f6dee46	671
igor_v	11:af609f6dee46	672	/* Debug Exception and Monitor Control Register */
igor_v	11:af609f6dee46	673	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
igor_v	11:af609f6dee46	674	#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
igor_v	11:af609f6dee46	675
igor_v	11:af609f6dee46	676	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
igor_v	11:af609f6dee46	677	#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
igor_v	11:af609f6dee46	678
igor_v	11:af609f6dee46	679	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
igor_v	11:af609f6dee46	680	#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
igor_v	11:af609f6dee46	681
igor_v	11:af609f6dee46	682	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
igor_v	11:af609f6dee46	683	#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
igor_v	11:af609f6dee46	684
igor_v	11:af609f6dee46	685	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
igor_v	11:af609f6dee46	686	#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
igor_v	11:af609f6dee46	687
igor_v	11:af609f6dee46	688	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
igor_v	11:af609f6dee46	689	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
igor_v	11:af609f6dee46	690
igor_v	11:af609f6dee46	691	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
igor_v	11:af609f6dee46	692	#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
igor_v	11:af609f6dee46	693
igor_v	11:af609f6dee46	694	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
igor_v	11:af609f6dee46	695	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
igor_v	11:af609f6dee46	696
igor_v	11:af609f6dee46	697	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
igor_v	11:af609f6dee46	698	#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
igor_v	11:af609f6dee46	699
igor_v	11:af609f6dee46	700	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
igor_v	11:af609f6dee46	701	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
igor_v	11:af609f6dee46	702
igor_v	11:af609f6dee46	703	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
igor_v	11:af609f6dee46	704	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
igor_v	11:af609f6dee46	705
igor_v	11:af609f6dee46	706	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
igor_v	11:af609f6dee46	707	#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
igor_v	11:af609f6dee46	708
igor_v	11:af609f6dee46	709	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
igor_v	11:af609f6dee46	710	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
igor_v	11:af609f6dee46	711	/@}/ /* end of group CMSIS_CM3_CoreDebug */
igor_v	11:af609f6dee46	712
igor_v	11:af609f6dee46	713
igor_v	11:af609f6dee46	714	/* Memory mapping of Cortex-M3 Hardware */
igor_v	11:af609f6dee46	715	#define SCS_BASE (0xE000E000) /!< System Control Space Base Address /
igor_v	11:af609f6dee46	716	#define ITM_BASE (0xE0000000) /!< ITM Base Address /
igor_v	11:af609f6dee46	717	#define CoreDebug_BASE (0xE000EDF0) /!< Core Debug Base Address /
igor_v	11:af609f6dee46	718	#define SysTick_BASE (SCS_BASE + 0x0010) /!< SysTick Base Address /
igor_v	11:af609f6dee46	719	#define NVIC_BASE (SCS_BASE + 0x0100) /!< NVIC Base Address /
igor_v	11:af609f6dee46	720	#define SCB_BASE (SCS_BASE + 0x0D00) /!< System Control Block Base Address /
igor_v	11:af609f6dee46	721
igor_v	11:af609f6dee46	722	#define InterruptType ((InterruptType_Type ) SCS_BASE) /!< Interrupt Type Register */
igor_v	11:af609f6dee46	723	#define SCB ((SCB_Type ) SCB_BASE) /!< SCB configuration struct */
igor_v	11:af609f6dee46	724	#define SysTick ((SysTick_Type ) SysTick_BASE) /!< SysTick configuration struct */
igor_v	11:af609f6dee46	725	#define NVIC ((NVIC_Type ) NVIC_BASE) /!< NVIC configuration struct */
igor_v	11:af609f6dee46	726	#define ITM ((ITM_Type ) ITM_BASE) /!< ITM configuration struct */
igor_v	11:af609f6dee46	727	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
igor_v	11:af609f6dee46	728
igor_v	11:af609f6dee46	729	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
igor_v	11:af609f6dee46	730	#define MPU_BASE (SCS_BASE + 0x0D90) /!< Memory Protection Unit /
igor_v	11:af609f6dee46	731	#define MPU ((MPU_Type) MPU_BASE) /!< Memory Protection Unit */
igor_v	11:af609f6dee46	732	#endif
igor_v	11:af609f6dee46	733
igor_v	11:af609f6dee46	734	/@}/ /* end of group CMSIS_CM3_core_register */
igor_v	11:af609f6dee46	735
igor_v	11:af609f6dee46	736
igor_v	11:af609f6dee46	737	/*******************************************************************************
igor_v	11:af609f6dee46	738	* Hardware Abstraction Layer
igor_v	11:af609f6dee46	739	******************************************************************************/
igor_v	0:8ad47e2b6f00	740
igor_v	0:8ad47e2b6f00	741	#if defined ( __CC_ARM )
igor_v	0:8ad47e2b6f00	742	#define __ASM __asm /!< asm keyword for ARM Compiler /
igor_v	0:8ad47e2b6f00	743	#define __INLINE __inline /!< inline keyword for ARM Compiler /
igor_v	0:8ad47e2b6f00	744
igor_v	0:8ad47e2b6f00	745	#elif defined ( __ICCARM__ )
igor_v	0:8ad47e2b6f00	746	#define __ASM __asm /!< asm keyword for IAR Compiler /
igor_v	0:8ad47e2b6f00	747	#define __INLINE inline /!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! /
igor_v	0:8ad47e2b6f00	748
igor_v	0:8ad47e2b6f00	749	#elif defined ( __GNUC__ )
igor_v	0:8ad47e2b6f00	750	#define __ASM __asm /!< asm keyword for GNU Compiler /
igor_v	0:8ad47e2b6f00	751	#define __INLINE inline /!< inline keyword for GNU Compiler /
igor_v	0:8ad47e2b6f00	752
igor_v	0:8ad47e2b6f00	753	#elif defined ( __TASKING__ )
igor_v	0:8ad47e2b6f00	754	#define __ASM __asm /!< asm keyword for TASKING Compiler /
igor_v	0:8ad47e2b6f00	755	#define __INLINE inline /!< inline keyword for TASKING Compiler /
igor_v	0:8ad47e2b6f00	756
igor_v	0:8ad47e2b6f00	757	#endif
igor_v	0:8ad47e2b6f00	758
igor_v	11:af609f6dee46	759
igor_v	11:af609f6dee46	760	/* ################### Compiler specific Intrinsics ########################### */
igor_v	11:af609f6dee46	761
igor_v	11:af609f6dee46	762	#if defined ( __CC_ARM ) /------------------RealView Compiler -----------------/
igor_v	11:af609f6dee46	763	/* ARM armcc specific functions */
igor_v	11:af609f6dee46	764
igor_v	11:af609f6dee46	765	#define __enable_fault_irq __enable_fiq
igor_v	11:af609f6dee46	766	#define __disable_fault_irq __disable_fiq
igor_v	11:af609f6dee46	767
igor_v	11:af609f6dee46	768	#define __NOP __nop
igor_v	11:af609f6dee46	769	#define __WFI __wfi
igor_v	11:af609f6dee46	770	#define __WFE __wfe
igor_v	11:af609f6dee46	771	#define __SEV __sev
igor_v	11:af609f6dee46	772	#define __ISB() __isb(0)
igor_v	11:af609f6dee46	773	#define __DSB() __dsb(0)
igor_v	11:af609f6dee46	774	#define __DMB() __dmb(0)
igor_v	11:af609f6dee46	775	#define __REV __rev
igor_v	11:af609f6dee46	776	#define __RBIT __rbit
igor_v	11:af609f6dee46	777	#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
igor_v	11:af609f6dee46	778	#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
igor_v	11:af609f6dee46	779	#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
igor_v	11:af609f6dee46	780	#define __STREXB(value, ptr) __strex(value, ptr)
igor_v	11:af609f6dee46	781	#define __STREXH(value, ptr) __strex(value, ptr)
igor_v	11:af609f6dee46	782	#define __STREXW(value, ptr) __strex(value, ptr)
igor_v	11:af609f6dee46	783
igor_v	11:af609f6dee46	784
igor_v	11:af609f6dee46	785	/* intrinsic unsigned long long __ldrexd(volatile void ptr) /
igor_v	11:af609f6dee46	786	/* intrinsic int __strexd(unsigned long long val, volatile void ptr) /
igor_v	11:af609f6dee46	787	/* intrinsic void __enable_irq(); */
igor_v	11:af609f6dee46	788	/* intrinsic void __disable_irq(); */
igor_v	11:af609f6dee46	789
igor_v	11:af609f6dee46	790
igor_v	11:af609f6dee46	791	/**
igor_v	11:af609f6dee46	792	* @brief Return the Process Stack Pointer
igor_v	11:af609f6dee46	793	*
igor_v	11:af609f6dee46	794	* @return ProcessStackPointer
igor_v	11:af609f6dee46	795	*
igor_v	11:af609f6dee46	796	* Return the actual process stack pointer
igor_v	11:af609f6dee46	797	*/
igor_v	11:af609f6dee46	798	extern uint32_t __get_PSP(void);
igor_v	0:8ad47e2b6f00	799
igor_v	11:af609f6dee46	800	/**
igor_v	11:af609f6dee46	801	* @brief Set the Process Stack Pointer
igor_v	11:af609f6dee46	802	*
igor_v	11:af609f6dee46	803	* @param topOfProcStack Process Stack Pointer
igor_v	11:af609f6dee46	804	*
igor_v	11:af609f6dee46	805	* Assign the value ProcessStackPointer to the MSP
igor_v	11:af609f6dee46	806	* (process stack pointer) Cortex processor register
igor_v	11:af609f6dee46	807	*/
igor_v	11:af609f6dee46	808	extern void __set_PSP(uint32_t topOfProcStack);
igor_v	11:af609f6dee46	809
igor_v	11:af609f6dee46	810	/**
igor_v	11:af609f6dee46	811	* @brief Return the Main Stack Pointer
igor_v	11:af609f6dee46	812	*
igor_v	11:af609f6dee46	813	* @return Main Stack Pointer
igor_v	11:af609f6dee46	814	*
igor_v	11:af609f6dee46	815	* Return the current value of the MSP (main stack pointer)
igor_v	11:af609f6dee46	816	* Cortex processor register
igor_v	11:af609f6dee46	817	*/
igor_v	11:af609f6dee46	818	extern uint32_t __get_MSP(void);
igor_v	11:af609f6dee46	819
igor_v	11:af609f6dee46	820	/**
igor_v	11:af609f6dee46	821	* @brief Set the Main Stack Pointer
igor_v	11:af609f6dee46	822	*
igor_v	11:af609f6dee46	823	* @param topOfMainStack Main Stack Pointer
igor_v	11:af609f6dee46	824	*
igor_v	11:af609f6dee46	825	* Assign the value mainStackPointer to the MSP
igor_v	11:af609f6dee46	826	* (main stack pointer) Cortex processor register
igor_v	11:af609f6dee46	827	*/
igor_v	11:af609f6dee46	828	extern void __set_MSP(uint32_t topOfMainStack);
igor_v	11:af609f6dee46	829
igor_v	11:af609f6dee46	830	/**
igor_v	11:af609f6dee46	831	* @brief Reverse byte order in unsigned short value
igor_v	11:af609f6dee46	832	*
igor_v	11:af609f6dee46	833	* @param value value to reverse
igor_v	11:af609f6dee46	834	* @return reversed value
igor_v	11:af609f6dee46	835	*
igor_v	11:af609f6dee46	836	* Reverse byte order in unsigned short value
igor_v	11:af609f6dee46	837	*/
igor_v	11:af609f6dee46	838	extern uint32_t __REV16(uint16_t value);
igor_v	11:af609f6dee46	839
igor_v	11:af609f6dee46	840	/**
igor_v	11:af609f6dee46	841	* @brief Reverse byte order in signed short value with sign extension to integer
igor_v	11:af609f6dee46	842	*
igor_v	11:af609f6dee46	843	* @param value value to reverse
igor_v	11:af609f6dee46	844	* @return reversed value
igor_v	11:af609f6dee46	845	*
igor_v	11:af609f6dee46	846	* Reverse byte order in signed short value with sign extension to integer
igor_v	11:af609f6dee46	847	*/
igor_v	11:af609f6dee46	848	extern int32_t __REVSH(int16_t value);
igor_v	0:8ad47e2b6f00	849
igor_v	0:8ad47e2b6f00	850
igor_v	11:af609f6dee46	851	#if (__ARMCC_VERSION < 400000)
igor_v	11:af609f6dee46	852
igor_v	11:af609f6dee46	853	/**
igor_v	11:af609f6dee46	854	* @brief Remove the exclusive lock created by ldrex
igor_v	11:af609f6dee46	855	*
igor_v	11:af609f6dee46	856	* Removes the exclusive lock which is created by ldrex.
igor_v	11:af609f6dee46	857	*/
igor_v	11:af609f6dee46	858	extern void __CLREX(void);
igor_v	11:af609f6dee46	859
igor_v	11:af609f6dee46	860	/**
igor_v	11:af609f6dee46	861	* @brief Return the Base Priority value
igor_v	11:af609f6dee46	862	*
igor_v	11:af609f6dee46	863	* @return BasePriority
igor_v	11:af609f6dee46	864	*
igor_v	11:af609f6dee46	865	* Return the content of the base priority register
igor_v	11:af609f6dee46	866	*/
igor_v	11:af609f6dee46	867	extern uint32_t __get_BASEPRI(void);
igor_v	11:af609f6dee46	868
igor_v	11:af609f6dee46	869	/**
igor_v	11:af609f6dee46	870	* @brief Set the Base Priority value
igor_v	11:af609f6dee46	871	*
igor_v	11:af609f6dee46	872	* @param basePri BasePriority
igor_v	11:af609f6dee46	873	*
igor_v	11:af609f6dee46	874	* Set the base priority register
igor_v	11:af609f6dee46	875	*/
igor_v	11:af609f6dee46	876	extern void __set_BASEPRI(uint32_t basePri);
igor_v	11:af609f6dee46	877
igor_v	11:af609f6dee46	878	/**
igor_v	11:af609f6dee46	879	* @brief Return the Priority Mask value
igor_v	11:af609f6dee46	880	*
igor_v	11:af609f6dee46	881	* @return PriMask
igor_v	11:af609f6dee46	882	*
igor_v	11:af609f6dee46	883	* Return state of the priority mask bit from the priority mask register
igor_v	11:af609f6dee46	884	*/
igor_v	11:af609f6dee46	885	extern uint32_t __get_PRIMASK(void);
igor_v	11:af609f6dee46	886
igor_v	11:af609f6dee46	887	/**
igor_v	11:af609f6dee46	888	* @brief Set the Priority Mask value
igor_v	11:af609f6dee46	889	*
igor_v	11:af609f6dee46	890	* @param priMask PriMask
igor_v	11:af609f6dee46	891	*
igor_v	11:af609f6dee46	892	* Set the priority mask bit in the priority mask register
igor_v	11:af609f6dee46	893	*/
igor_v	11:af609f6dee46	894	extern void __set_PRIMASK(uint32_t priMask);
igor_v	0:8ad47e2b6f00	895
igor_v	11:af609f6dee46	896	/**
igor_v	11:af609f6dee46	897	* @brief Return the Fault Mask value
igor_v	11:af609f6dee46	898	*
igor_v	11:af609f6dee46	899	* @return FaultMask
igor_v	11:af609f6dee46	900	*
igor_v	11:af609f6dee46	901	* Return the content of the fault mask register
igor_v	11:af609f6dee46	902	*/
igor_v	11:af609f6dee46	903	extern uint32_t __get_FAULTMASK(void);
igor_v	11:af609f6dee46	904
igor_v	11:af609f6dee46	905	/**
igor_v	11:af609f6dee46	906	* @brief Set the Fault Mask value
igor_v	11:af609f6dee46	907	*
igor_v	11:af609f6dee46	908	* @param faultMask faultMask value
igor_v	11:af609f6dee46	909	*
igor_v	11:af609f6dee46	910	* Set the fault mask register
igor_v	11:af609f6dee46	911	*/
igor_v	11:af609f6dee46	912	extern void __set_FAULTMASK(uint32_t faultMask);
igor_v	11:af609f6dee46	913
igor_v	11:af609f6dee46	914	/**
igor_v	11:af609f6dee46	915	* @brief Return the Control Register value
igor_v	11:af609f6dee46	916	*
igor_v	11:af609f6dee46	917	* @return Control value
igor_v	11:af609f6dee46	918	*
igor_v	11:af609f6dee46	919	* Return the content of the control register
igor_v	11:af609f6dee46	920	*/
igor_v	11:af609f6dee46	921	extern uint32_t __get_CONTROL(void);
igor_v	11:af609f6dee46	922
igor_v	11:af609f6dee46	923	/**
igor_v	11:af609f6dee46	924	* @brief Set the Control Register value
igor_v	11:af609f6dee46	925	*
igor_v	11:af609f6dee46	926	* @param control Control value
igor_v	11:af609f6dee46	927	*
igor_v	11:af609f6dee46	928	* Set the control register
igor_v	11:af609f6dee46	929	*/
igor_v	11:af609f6dee46	930	extern void __set_CONTROL(uint32_t control);
igor_v	11:af609f6dee46	931
igor_v	11:af609f6dee46	932	#else /* (__ARMCC_VERSION >= 400000) */
igor_v	11:af609f6dee46	933
igor_v	11:af609f6dee46	934	/**
igor_v	11:af609f6dee46	935	* @brief Remove the exclusive lock created by ldrex
igor_v	11:af609f6dee46	936	*
igor_v	11:af609f6dee46	937	* Removes the exclusive lock which is created by ldrex.
igor_v	11:af609f6dee46	938	*/
igor_v	11:af609f6dee46	939	#define __CLREX __clrex
igor_v	0:8ad47e2b6f00	940
igor_v	11:af609f6dee46	941	/**
igor_v	11:af609f6dee46	942	* @brief Return the Base Priority value
igor_v	11:af609f6dee46	943	*
igor_v	11:af609f6dee46	944	* @return BasePriority
igor_v	11:af609f6dee46	945	*
igor_v	11:af609f6dee46	946	* Return the content of the base priority register
igor_v	11:af609f6dee46	947	*/
igor_v	11:af609f6dee46	948	static __INLINE uint32_t __get_BASEPRI(void)
igor_v	11:af609f6dee46	949	{
igor_v	11:af609f6dee46	950	register uint32_t __regBasePri __ASM("basepri");
igor_v	11:af609f6dee46	951	return(__regBasePri);
igor_v	11:af609f6dee46	952	}
igor_v	11:af609f6dee46	953
igor_v	11:af609f6dee46	954	/**
igor_v	11:af609f6dee46	955	* @brief Set the Base Priority value
igor_v	11:af609f6dee46	956	*
igor_v	11:af609f6dee46	957	* @param basePri BasePriority
igor_v	11:af609f6dee46	958	*
igor_v	11:af609f6dee46	959	* Set the base priority register
igor_v	11:af609f6dee46	960	*/
igor_v	11:af609f6dee46	961	static __INLINE void __set_BASEPRI(uint32_t basePri)
igor_v	11:af609f6dee46	962	{
igor_v	11:af609f6dee46	963	register uint32_t __regBasePri __ASM("basepri");
igor_v	11:af609f6dee46	964	__regBasePri = (basePri & 0xff);
igor_v	11:af609f6dee46	965	}
igor_v	11:af609f6dee46	966
igor_v	11:af609f6dee46	967	/**
igor_v	11:af609f6dee46	968	* @brief Return the Priority Mask value
igor_v	11:af609f6dee46	969	*
igor_v	11:af609f6dee46	970	* @return PriMask
igor_v	11:af609f6dee46	971	*
igor_v	11:af609f6dee46	972	* Return state of the priority mask bit from the priority mask register
igor_v	11:af609f6dee46	973	*/
igor_v	11:af609f6dee46	974	static __INLINE uint32_t __get_PRIMASK(void)
igor_v	11:af609f6dee46	975	{
igor_v	11:af609f6dee46	976	register uint32_t __regPriMask __ASM("primask");
igor_v	11:af609f6dee46	977	return(__regPriMask);
igor_v	11:af609f6dee46	978	}
igor_v	11:af609f6dee46	979
igor_v	11:af609f6dee46	980	/**
igor_v	11:af609f6dee46	981	* @brief Set the Priority Mask value
igor_v	11:af609f6dee46	982	*
igor_v	11:af609f6dee46	983	* @param priMask PriMask
igor_v	11:af609f6dee46	984	*
igor_v	11:af609f6dee46	985	* Set the priority mask bit in the priority mask register
igor_v	11:af609f6dee46	986	*/
igor_v	11:af609f6dee46	987	static __INLINE void __set_PRIMASK(uint32_t priMask)
igor_v	11:af609f6dee46	988	{
igor_v	11:af609f6dee46	989	register uint32_t __regPriMask __ASM("primask");
igor_v	11:af609f6dee46	990	__regPriMask = (priMask);
igor_v	11:af609f6dee46	991	}
igor_v	0:8ad47e2b6f00	992
igor_v	11:af609f6dee46	993	/**
igor_v	11:af609f6dee46	994	* @brief Return the Fault Mask value
igor_v	11:af609f6dee46	995	*
igor_v	11:af609f6dee46	996	* @return FaultMask
igor_v	11:af609f6dee46	997	*
igor_v	11:af609f6dee46	998	* Return the content of the fault mask register
igor_v	11:af609f6dee46	999	*/
igor_v	11:af609f6dee46	1000	static __INLINE uint32_t __get_FAULTMASK(void)
igor_v	11:af609f6dee46	1001	{
igor_v	11:af609f6dee46	1002	register uint32_t __regFaultMask __ASM("faultmask");
igor_v	11:af609f6dee46	1003	return(__regFaultMask);
igor_v	11:af609f6dee46	1004	}
igor_v	11:af609f6dee46	1005
igor_v	11:af609f6dee46	1006	/**
igor_v	11:af609f6dee46	1007	* @brief Set the Fault Mask value
igor_v	11:af609f6dee46	1008	*
igor_v	11:af609f6dee46	1009	* @param faultMask faultMask value
igor_v	11:af609f6dee46	1010	*
igor_v	11:af609f6dee46	1011	* Set the fault mask register
igor_v	11:af609f6dee46	1012	*/
igor_v	11:af609f6dee46	1013	static __INLINE void __set_FAULTMASK(uint32_t faultMask)
igor_v	11:af609f6dee46	1014	{
igor_v	11:af609f6dee46	1015	register uint32_t __regFaultMask __ASM("faultmask");
igor_v	11:af609f6dee46	1016	__regFaultMask = (faultMask & 1);
igor_v	11:af609f6dee46	1017	}
igor_v	11:af609f6dee46	1018
igor_v	11:af609f6dee46	1019	/**
igor_v	11:af609f6dee46	1020	* @brief Return the Control Register value
igor_v	11:af609f6dee46	1021	*
igor_v	11:af609f6dee46	1022	* @return Control value
igor_v	11:af609f6dee46	1023	*
igor_v	11:af609f6dee46	1024	* Return the content of the control register
igor_v	11:af609f6dee46	1025	*/
igor_v	11:af609f6dee46	1026	static __INLINE uint32_t __get_CONTROL(void)
igor_v	11:af609f6dee46	1027	{
igor_v	11:af609f6dee46	1028	register uint32_t __regControl __ASM("control");
igor_v	11:af609f6dee46	1029	return(__regControl);
igor_v	11:af609f6dee46	1030	}
igor_v	11:af609f6dee46	1031
igor_v	11:af609f6dee46	1032	/**
igor_v	11:af609f6dee46	1033	* @brief Set the Control Register value
igor_v	11:af609f6dee46	1034	*
igor_v	11:af609f6dee46	1035	* @param control Control value
igor_v	11:af609f6dee46	1036	*
igor_v	11:af609f6dee46	1037	* Set the control register
igor_v	11:af609f6dee46	1038	*/
igor_v	11:af609f6dee46	1039	static __INLINE void __set_CONTROL(uint32_t control)
igor_v	11:af609f6dee46	1040	{
igor_v	11:af609f6dee46	1041	register uint32_t __regControl __ASM("control");
igor_v	11:af609f6dee46	1042	__regControl = control;
igor_v	11:af609f6dee46	1043	}
igor_v	11:af609f6dee46	1044
igor_v	11:af609f6dee46	1045	#endif /* __ARMCC_VERSION */
igor_v	0:8ad47e2b6f00	1046
igor_v	0:8ad47e2b6f00	1047
igor_v	0:8ad47e2b6f00	1048
igor_v	11:af609f6dee46	1049	#elif (defined (__ICCARM__)) /------------------ ICC Compiler -------------------/
igor_v	11:af609f6dee46	1050	/* IAR iccarm specific functions */
igor_v	0:8ad47e2b6f00	1051
igor_v	11:af609f6dee46	1052	#define __enable_irq __enable_interrupt /!< global Interrupt enable /
igor_v	11:af609f6dee46	1053	#define __disable_irq __disable_interrupt /!< global Interrupt disable /
igor_v	11:af609f6dee46	1054
igor_v	11:af609f6dee46	1055	static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
igor_v	11:af609f6dee46	1056	static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
igor_v	0:8ad47e2b6f00	1057
igor_v	11:af609f6dee46	1058	#define __NOP __no_operation /!< no operation intrinsic in IAR Compiler /
igor_v	11:af609f6dee46	1059	static __INLINE void __WFI() { __ASM ("wfi"); }
igor_v	11:af609f6dee46	1060	static __INLINE void __WFE() { __ASM ("wfe"); }
igor_v	11:af609f6dee46	1061	static __INLINE void __SEV() { __ASM ("sev"); }
igor_v	11:af609f6dee46	1062	static __INLINE void __CLREX() { __ASM ("clrex"); }
igor_v	11:af609f6dee46	1063
igor_v	11:af609f6dee46	1064	/* intrinsic void __ISB(void) */
igor_v	11:af609f6dee46	1065	/* intrinsic void __DSB(void) */
igor_v	11:af609f6dee46	1066	/* intrinsic void __DMB(void) */
igor_v	11:af609f6dee46	1067	/* intrinsic void __set_PRIMASK(); */
igor_v	11:af609f6dee46	1068	/* intrinsic void __get_PRIMASK(); */
igor_v	11:af609f6dee46	1069	/* intrinsic void __set_FAULTMASK(); */
igor_v	11:af609f6dee46	1070	/* intrinsic void __get_FAULTMASK(); */
igor_v	11:af609f6dee46	1071	/* intrinsic uint32_t __REV(uint32_t value); */
igor_v	11:af609f6dee46	1072	/* intrinsic uint32_t __REVSH(uint32_t value); */
igor_v	11:af609f6dee46	1073	/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
igor_v	11:af609f6dee46	1074	/* intrinsic unsigned long __LDREX(unsigned long ); /
igor_v	0:8ad47e2b6f00	1075
igor_v	0:8ad47e2b6f00	1076
igor_v	11:af609f6dee46	1077	/**
igor_v	11:af609f6dee46	1078	* @brief Return the Process Stack Pointer
igor_v	11:af609f6dee46	1079	*
igor_v	11:af609f6dee46	1080	* @return ProcessStackPointer
igor_v	11:af609f6dee46	1081	*
igor_v	11:af609f6dee46	1082	* Return the actual process stack pointer
igor_v	11:af609f6dee46	1083	*/
igor_v	11:af609f6dee46	1084	extern uint32_t __get_PSP(void);
igor_v	11:af609f6dee46	1085
igor_v	11:af609f6dee46	1086	/**
igor_v	11:af609f6dee46	1087	* @brief Set the Process Stack Pointer
igor_v	11:af609f6dee46	1088	*
igor_v	11:af609f6dee46	1089	* @param topOfProcStack Process Stack Pointer
igor_v	11:af609f6dee46	1090	*
igor_v	11:af609f6dee46	1091	* Assign the value ProcessStackPointer to the MSP
igor_v	11:af609f6dee46	1092	* (process stack pointer) Cortex processor register
igor_v	11:af609f6dee46	1093	*/
igor_v	11:af609f6dee46	1094	extern void __set_PSP(uint32_t topOfProcStack);
igor_v	11:af609f6dee46	1095
igor_v	11:af609f6dee46	1096	/**
igor_v	11:af609f6dee46	1097	* @brief Return the Main Stack Pointer
igor_v	11:af609f6dee46	1098	*
igor_v	11:af609f6dee46	1099	* @return Main Stack Pointer
igor_v	11:af609f6dee46	1100	*
igor_v	11:af609f6dee46	1101	* Return the current value of the MSP (main stack pointer)
igor_v	11:af609f6dee46	1102	* Cortex processor register
igor_v	11:af609f6dee46	1103	*/
igor_v	11:af609f6dee46	1104	extern uint32_t __get_MSP(void);
igor_v	11:af609f6dee46	1105
igor_v	11:af609f6dee46	1106	/**
igor_v	11:af609f6dee46	1107	* @brief Set the Main Stack Pointer
igor_v	11:af609f6dee46	1108	*
igor_v	11:af609f6dee46	1109	* @param topOfMainStack Main Stack Pointer
igor_v	11:af609f6dee46	1110	*
igor_v	11:af609f6dee46	1111	* Assign the value mainStackPointer to the MSP
igor_v	11:af609f6dee46	1112	* (main stack pointer) Cortex processor register
igor_v	11:af609f6dee46	1113	*/
igor_v	11:af609f6dee46	1114	extern void __set_MSP(uint32_t topOfMainStack);
igor_v	11:af609f6dee46	1115
igor_v	11:af609f6dee46	1116	/**
igor_v	11:af609f6dee46	1117	* @brief Reverse byte order in unsigned short value
igor_v	11:af609f6dee46	1118	*
igor_v	11:af609f6dee46	1119	* @param value value to reverse
igor_v	11:af609f6dee46	1120	* @return reversed value
igor_v	11:af609f6dee46	1121	*
igor_v	11:af609f6dee46	1122	* Reverse byte order in unsigned short value
igor_v	11:af609f6dee46	1123	*/
igor_v	11:af609f6dee46	1124	extern uint32_t __REV16(uint16_t value);
igor_v	11:af609f6dee46	1125
igor_v	11:af609f6dee46	1126	/**
igor_v	11:af609f6dee46	1127	* @brief Reverse bit order of value
igor_v	11:af609f6dee46	1128	*
igor_v	11:af609f6dee46	1129	* @param value value to reverse
igor_v	11:af609f6dee46	1130	* @return reversed value
igor_v	11:af609f6dee46	1131	*
igor_v	11:af609f6dee46	1132	* Reverse bit order of value
igor_v	11:af609f6dee46	1133	*/
igor_v	11:af609f6dee46	1134	extern uint32_t __RBIT(uint32_t value);
igor_v	11:af609f6dee46	1135
igor_v	11:af609f6dee46	1136	/**
igor_v	11:af609f6dee46	1137	* @brief LDR Exclusive (8 bit)
igor_v	11:af609f6dee46	1138	*
igor_v	11:af609f6dee46	1139	* @param *addr address pointer
igor_v	11:af609f6dee46	1140	* @return value of (*address)
igor_v	11:af609f6dee46	1141	*
igor_v	11:af609f6dee46	1142	* Exclusive LDR command for 8 bit values)
igor_v	0:8ad47e2b6f00	1143	*/
igor_v	11:af609f6dee46	1144	extern uint8_t __LDREXB(uint8_t *addr);
igor_v	11:af609f6dee46	1145
igor_v	11:af609f6dee46	1146	/**
igor_v	11:af609f6dee46	1147	* @brief LDR Exclusive (16 bit)
igor_v	11:af609f6dee46	1148	*
igor_v	11:af609f6dee46	1149	* @param *addr address pointer
igor_v	11:af609f6dee46	1150	* @return value of (*address)
igor_v	11:af609f6dee46	1151	*
igor_v	11:af609f6dee46	1152	* Exclusive LDR command for 16 bit values
igor_v	11:af609f6dee46	1153	*/
igor_v	11:af609f6dee46	1154	extern uint16_t __LDREXH(uint16_t *addr);
igor_v	11:af609f6dee46	1155
igor_v	11:af609f6dee46	1156	/**
igor_v	11:af609f6dee46	1157	* @brief LDR Exclusive (32 bit)
igor_v	11:af609f6dee46	1158	*
igor_v	11:af609f6dee46	1159	* @param *addr address pointer
igor_v	11:af609f6dee46	1160	* @return value of (*address)
igor_v	11:af609f6dee46	1161	*
igor_v	11:af609f6dee46	1162	* Exclusive LDR command for 32 bit values
igor_v	11:af609f6dee46	1163	*/
igor_v	11:af609f6dee46	1164	extern uint32_t __LDREXW(uint32_t *addr);
igor_v	11:af609f6dee46	1165
igor_v	11:af609f6dee46	1166	/**
igor_v	11:af609f6dee46	1167	* @brief STR Exclusive (8 bit)
igor_v	11:af609f6dee46	1168	*
igor_v	11:af609f6dee46	1169	* @param value value to store
igor_v	11:af609f6dee46	1170	* @param *addr address pointer
igor_v	11:af609f6dee46	1171	* @return successful / failed
igor_v	11:af609f6dee46	1172	*
igor_v	11:af609f6dee46	1173	* Exclusive STR command for 8 bit values
igor_v	11:af609f6dee46	1174	*/
igor_v	11:af609f6dee46	1175	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
igor_v	11:af609f6dee46	1176
igor_v	11:af609f6dee46	1177	/**
igor_v	11:af609f6dee46	1178	* @brief STR Exclusive (16 bit)
igor_v	11:af609f6dee46	1179	*
igor_v	11:af609f6dee46	1180	* @param value value to store
igor_v	11:af609f6dee46	1181	* @param *addr address pointer
igor_v	11:af609f6dee46	1182	* @return successful / failed
igor_v	11:af609f6dee46	1183	*
igor_v	11:af609f6dee46	1184	* Exclusive STR command for 16 bit values
igor_v	11:af609f6dee46	1185	*/
igor_v	11:af609f6dee46	1186	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
igor_v	11:af609f6dee46	1187
igor_v	11:af609f6dee46	1188	/**
igor_v	11:af609f6dee46	1189	* @brief STR Exclusive (32 bit)
igor_v	11:af609f6dee46	1190	*
igor_v	11:af609f6dee46	1191	* @param value value to store
igor_v	11:af609f6dee46	1192	* @param *addr address pointer
igor_v	11:af609f6dee46	1193	* @return successful / failed
igor_v	11:af609f6dee46	1194	*
igor_v	11:af609f6dee46	1195	* Exclusive STR command for 32 bit values
igor_v	11:af609f6dee46	1196	*/
igor_v	11:af609f6dee46	1197	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
igor_v	11:af609f6dee46	1198
igor_v	11:af609f6dee46	1199
igor_v	11:af609f6dee46	1200
igor_v	11:af609f6dee46	1201	#elif (defined (__GNUC__)) /------------------ GNU Compiler ---------------------/
igor_v	11:af609f6dee46	1202	/* GNU gcc specific functions */
igor_v	11:af609f6dee46	1203
igor_v	11:af609f6dee46	1204	static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
igor_v	11:af609f6dee46	1205	static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
igor_v	11:af609f6dee46	1206
igor_v	11:af609f6dee46	1207	static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
igor_v	11:af609f6dee46	1208	static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
igor_v	11:af609f6dee46	1209
igor_v	11:af609f6dee46	1210	static __INLINE void __NOP() { __ASM volatile ("nop"); }
igor_v	11:af609f6dee46	1211	static __INLINE void __WFI() { __ASM volatile ("wfi"); }
igor_v	11:af609f6dee46	1212	static __INLINE void __WFE() { __ASM volatile ("wfe"); }
igor_v	11:af609f6dee46	1213	static __INLINE void __SEV() { __ASM volatile ("sev"); }
igor_v	11:af609f6dee46	1214	static __INLINE void __ISB() { __ASM volatile ("isb"); }
igor_v	11:af609f6dee46	1215	static __INLINE void __DSB() { __ASM volatile ("dsb"); }
igor_v	11:af609f6dee46	1216	static __INLINE void __DMB() { __ASM volatile ("dmb"); }
igor_v	11:af609f6dee46	1217	static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
igor_v	0:8ad47e2b6f00	1218
igor_v	0:8ad47e2b6f00	1219
igor_v	11:af609f6dee46	1220	/**
igor_v	11:af609f6dee46	1221	* @brief Return the Process Stack Pointer
igor_v	11:af609f6dee46	1222	*
igor_v	11:af609f6dee46	1223	* @return ProcessStackPointer
igor_v	11:af609f6dee46	1224	*
igor_v	11:af609f6dee46	1225	* Return the actual process stack pointer
igor_v	11:af609f6dee46	1226	*/
igor_v	11:af609f6dee46	1227	extern uint32_t __get_PSP(void);
igor_v	11:af609f6dee46	1228
igor_v	11:af609f6dee46	1229	/**
igor_v	11:af609f6dee46	1230	* @brief Set the Process Stack Pointer
igor_v	11:af609f6dee46	1231	*
igor_v	11:af609f6dee46	1232	* @param topOfProcStack Process Stack Pointer
igor_v	11:af609f6dee46	1233	*
igor_v	11:af609f6dee46	1234	* Assign the value ProcessStackPointer to the MSP
igor_v	11:af609f6dee46	1235	* (process stack pointer) Cortex processor register
igor_v	11:af609f6dee46	1236	*/
igor_v	11:af609f6dee46	1237	extern void __set_PSP(uint32_t topOfProcStack);
igor_v	11:af609f6dee46	1238
igor_v	11:af609f6dee46	1239	/**
igor_v	11:af609f6dee46	1240	* @brief Return the Main Stack Pointer
igor_v	11:af609f6dee46	1241	*
igor_v	11:af609f6dee46	1242	* @return Main Stack Pointer
igor_v	11:af609f6dee46	1243	*
igor_v	11:af609f6dee46	1244	* Return the current value of the MSP (main stack pointer)
igor_v	11:af609f6dee46	1245	* Cortex processor register
igor_v	11:af609f6dee46	1246	*/
igor_v	11:af609f6dee46	1247	extern uint32_t __get_MSP(void);
igor_v	11:af609f6dee46	1248
igor_v	11:af609f6dee46	1249	/**
igor_v	11:af609f6dee46	1250	* @brief Set the Main Stack Pointer
igor_v	11:af609f6dee46	1251	*
igor_v	11:af609f6dee46	1252	* @param topOfMainStack Main Stack Pointer
igor_v	11:af609f6dee46	1253	*
igor_v	11:af609f6dee46	1254	* Assign the value mainStackPointer to the MSP
igor_v	11:af609f6dee46	1255	* (main stack pointer) Cortex processor register
igor_v	11:af609f6dee46	1256	*/
igor_v	11:af609f6dee46	1257	extern void __set_MSP(uint32_t topOfMainStack);
igor_v	11:af609f6dee46	1258
igor_v	11:af609f6dee46	1259	/**
igor_v	11:af609f6dee46	1260	* @brief Return the Base Priority value
igor_v	11:af609f6dee46	1261	*
igor_v	11:af609f6dee46	1262	* @return BasePriority
igor_v	11:af609f6dee46	1263	*
igor_v	11:af609f6dee46	1264	* Return the content of the base priority register
igor_v	11:af609f6dee46	1265	*/
igor_v	11:af609f6dee46	1266	extern uint32_t __get_BASEPRI(void);
igor_v	11:af609f6dee46	1267
igor_v	11:af609f6dee46	1268	/**
igor_v	11:af609f6dee46	1269	* @brief Set the Base Priority value
igor_v	11:af609f6dee46	1270	*
igor_v	11:af609f6dee46	1271	* @param basePri BasePriority
igor_v	11:af609f6dee46	1272	*
igor_v	11:af609f6dee46	1273	* Set the base priority register
igor_v	11:af609f6dee46	1274	*/
igor_v	11:af609f6dee46	1275	extern void __set_BASEPRI(uint32_t basePri);
igor_v	11:af609f6dee46	1276
igor_v	11:af609f6dee46	1277	/**
igor_v	11:af609f6dee46	1278	* @brief Return the Priority Mask value
igor_v	11:af609f6dee46	1279	*
igor_v	11:af609f6dee46	1280	* @return PriMask
igor_v	11:af609f6dee46	1281	*
igor_v	11:af609f6dee46	1282	* Return state of the priority mask bit from the priority mask register
igor_v	11:af609f6dee46	1283	*/
igor_v	11:af609f6dee46	1284	extern uint32_t __get_PRIMASK(void);
igor_v	11:af609f6dee46	1285
igor_v	11:af609f6dee46	1286	/**
igor_v	11:af609f6dee46	1287	* @brief Set the Priority Mask value
igor_v	11:af609f6dee46	1288	*
igor_v	11:af609f6dee46	1289	* @param priMask PriMask
igor_v	11:af609f6dee46	1290	*
igor_v	11:af609f6dee46	1291	* Set the priority mask bit in the priority mask register
igor_v	11:af609f6dee46	1292	*/
igor_v	11:af609f6dee46	1293	extern void __set_PRIMASK(uint32_t priMask);
igor_v	11:af609f6dee46	1294
igor_v	11:af609f6dee46	1295	/**
igor_v	11:af609f6dee46	1296	* @brief Return the Fault Mask value
igor_v	11:af609f6dee46	1297	*
igor_v	11:af609f6dee46	1298	* @return FaultMask
igor_v	11:af609f6dee46	1299	*
igor_v	11:af609f6dee46	1300	* Return the content of the fault mask register
igor_v	11:af609f6dee46	1301	*/
igor_v	11:af609f6dee46	1302	extern uint32_t __get_FAULTMASK(void);
igor_v	11:af609f6dee46	1303
igor_v	11:af609f6dee46	1304	/**
igor_v	11:af609f6dee46	1305	* @brief Set the Fault Mask value
igor_v	11:af609f6dee46	1306	*
igor_v	11:af609f6dee46	1307	* @param faultMask faultMask value
igor_v	11:af609f6dee46	1308	*
igor_v	11:af609f6dee46	1309	* Set the fault mask register
igor_v	11:af609f6dee46	1310	*/
igor_v	11:af609f6dee46	1311	extern void __set_FAULTMASK(uint32_t faultMask);
igor_v	11:af609f6dee46	1312
igor_v	11:af609f6dee46	1313	/**
igor_v	11:af609f6dee46	1314	* @brief Return the Control Register value
igor_v	11:af609f6dee46	1315	*
igor_v	11:af609f6dee46	1316	* @return Control value
igor_v	11:af609f6dee46	1317	*
igor_v	11:af609f6dee46	1318	* Return the content of the control register
igor_v	0:8ad47e2b6f00	1319	*/
igor_v	11:af609f6dee46	1320	extern uint32_t __get_CONTROL(void);
igor_v	11:af609f6dee46	1321
igor_v	11:af609f6dee46	1322	/**
igor_v	11:af609f6dee46	1323	* @brief Set the Control Register value
igor_v	11:af609f6dee46	1324	*
igor_v	11:af609f6dee46	1325	* @param control Control value
igor_v	11:af609f6dee46	1326	*
igor_v	11:af609f6dee46	1327	* Set the control register
igor_v	11:af609f6dee46	1328	*/
igor_v	11:af609f6dee46	1329	extern void __set_CONTROL(uint32_t control);
igor_v	11:af609f6dee46	1330
igor_v	11:af609f6dee46	1331	/**
igor_v	11:af609f6dee46	1332	* @brief Reverse byte order in integer value
igor_v	11:af609f6dee46	1333	*
igor_v	11:af609f6dee46	1334	* @param value value to reverse
igor_v	11:af609f6dee46	1335	* @return reversed value
igor_v	11:af609f6dee46	1336	*
igor_v	11:af609f6dee46	1337	* Reverse byte order in integer value
igor_v	11:af609f6dee46	1338	*/
igor_v	11:af609f6dee46	1339	extern uint32_t __REV(uint32_t value);
igor_v	11:af609f6dee46	1340
igor_v	11:af609f6dee46	1341	/**
igor_v	11:af609f6dee46	1342	* @brief Reverse byte order in unsigned short value
igor_v	11:af609f6dee46	1343	*
igor_v	11:af609f6dee46	1344	* @param value value to reverse
igor_v	11:af609f6dee46	1345	* @return reversed value
igor_v	11:af609f6dee46	1346	*
igor_v	11:af609f6dee46	1347	* Reverse byte order in unsigned short value
igor_v	11:af609f6dee46	1348	*/
igor_v	11:af609f6dee46	1349	extern uint32_t __REV16(uint16_t value);
igor_v	11:af609f6dee46	1350
igor_v	11:af609f6dee46	1351	/**
igor_v	11:af609f6dee46	1352	* @brief Reverse byte order in signed short value with sign extension to integer
igor_v	11:af609f6dee46	1353	*
igor_v	11:af609f6dee46	1354	* @param value value to reverse
igor_v	11:af609f6dee46	1355	* @return reversed value
igor_v	11:af609f6dee46	1356	*
igor_v	11:af609f6dee46	1357	* Reverse byte order in signed short value with sign extension to integer
igor_v	11:af609f6dee46	1358	*/
igor_v	11:af609f6dee46	1359	extern int32_t __REVSH(int16_t value);
igor_v	11:af609f6dee46	1360
igor_v	11:af609f6dee46	1361	/**
igor_v	11:af609f6dee46	1362	* @brief Reverse bit order of value
igor_v	11:af609f6dee46	1363	*
igor_v	11:af609f6dee46	1364	* @param value value to reverse
igor_v	11:af609f6dee46	1365	* @return reversed value
igor_v	11:af609f6dee46	1366	*
igor_v	11:af609f6dee46	1367	* Reverse bit order of value
igor_v	11:af609f6dee46	1368	*/
igor_v	11:af609f6dee46	1369	extern uint32_t __RBIT(uint32_t value);
igor_v	11:af609f6dee46	1370
igor_v	11:af609f6dee46	1371	/**
igor_v	11:af609f6dee46	1372	* @brief LDR Exclusive (8 bit)
igor_v	11:af609f6dee46	1373	*
igor_v	11:af609f6dee46	1374	* @param *addr address pointer
igor_v	11:af609f6dee46	1375	* @return value of (*address)
igor_v	11:af609f6dee46	1376	*
igor_v	11:af609f6dee46	1377	* Exclusive LDR command for 8 bit value
igor_v	11:af609f6dee46	1378	*/
igor_v	11:af609f6dee46	1379	extern uint8_t __LDREXB(uint8_t *addr);
igor_v	11:af609f6dee46	1380
igor_v	11:af609f6dee46	1381	/**
igor_v	11:af609f6dee46	1382	* @brief LDR Exclusive (16 bit)
igor_v	11:af609f6dee46	1383	*
igor_v	11:af609f6dee46	1384	* @param *addr address pointer
igor_v	11:af609f6dee46	1385	* @return value of (*address)
igor_v	11:af609f6dee46	1386	*
igor_v	11:af609f6dee46	1387	* Exclusive LDR command for 16 bit values
igor_v	11:af609f6dee46	1388	*/
igor_v	11:af609f6dee46	1389	extern uint16_t __LDREXH(uint16_t *addr);
igor_v	11:af609f6dee46	1390
igor_v	11:af609f6dee46	1391	/**
igor_v	11:af609f6dee46	1392	* @brief LDR Exclusive (32 bit)
igor_v	11:af609f6dee46	1393	*
igor_v	11:af609f6dee46	1394	* @param *addr address pointer
igor_v	11:af609f6dee46	1395	* @return value of (*address)
igor_v	11:af609f6dee46	1396	*
igor_v	11:af609f6dee46	1397	* Exclusive LDR command for 32 bit values
igor_v	11:af609f6dee46	1398	*/
igor_v	11:af609f6dee46	1399	extern uint32_t __LDREXW(uint32_t *addr);
igor_v	11:af609f6dee46	1400
igor_v	11:af609f6dee46	1401	/**
igor_v	11:af609f6dee46	1402	* @brief STR Exclusive (8 bit)
igor_v	11:af609f6dee46	1403	*
igor_v	11:af609f6dee46	1404	* @param value value to store
igor_v	11:af609f6dee46	1405	* @param *addr address pointer
igor_v	11:af609f6dee46	1406	* @return successful / failed
igor_v	11:af609f6dee46	1407	*
igor_v	11:af609f6dee46	1408	* Exclusive STR command for 8 bit values
igor_v	11:af609f6dee46	1409	*/
igor_v	11:af609f6dee46	1410	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
igor_v	11:af609f6dee46	1411
igor_v	11:af609f6dee46	1412	/**
igor_v	11:af609f6dee46	1413	* @brief STR Exclusive (16 bit)
igor_v	11:af609f6dee46	1414	*
igor_v	11:af609f6dee46	1415	* @param value value to store
igor_v	11:af609f6dee46	1416	* @param *addr address pointer
igor_v	11:af609f6dee46	1417	* @return successful / failed
igor_v	11:af609f6dee46	1418	*
igor_v	11:af609f6dee46	1419	* Exclusive STR command for 16 bit values
igor_v	11:af609f6dee46	1420	*/
igor_v	11:af609f6dee46	1421	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
igor_v	11:af609f6dee46	1422
igor_v	11:af609f6dee46	1423	/**
igor_v	11:af609f6dee46	1424	* @brief STR Exclusive (32 bit)
igor_v	11:af609f6dee46	1425	*
igor_v	11:af609f6dee46	1426	* @param value value to store
igor_v	11:af609f6dee46	1427	* @param *addr address pointer
igor_v	11:af609f6dee46	1428	* @return successful / failed
igor_v	11:af609f6dee46	1429	*
igor_v	11:af609f6dee46	1430	* Exclusive STR command for 32 bit values
igor_v	11:af609f6dee46	1431	*/
igor_v	11:af609f6dee46	1432	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
igor_v	0:8ad47e2b6f00	1433
igor_v	0:8ad47e2b6f00	1434
igor_v	11:af609f6dee46	1435	#elif (defined (__TASKING__)) /------------------ TASKING Compiler ---------------------/
igor_v	11:af609f6dee46	1436	/* TASKING carm specific functions */
igor_v	0:8ad47e2b6f00	1437
igor_v	11:af609f6dee46	1438	/*
igor_v	11:af609f6dee46	1439	* The CMSIS functions have been implemented as intrinsics in the compiler.
igor_v	11:af609f6dee46	1440	* Please use "carm -?i" to get an up to date list of all instrinsics,
igor_v	11:af609f6dee46	1441	* Including the CMSIS ones.
igor_v	0:8ad47e2b6f00	1442	*/
igor_v	0:8ad47e2b6f00	1443
igor_v	0:8ad47e2b6f00	1444	#endif
igor_v	0:8ad47e2b6f00	1445
igor_v	0:8ad47e2b6f00	1446
igor_v	11:af609f6dee46	1447	/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
igor_v	11:af609f6dee46	1448	Core Function Interface containing:
igor_v	0:8ad47e2b6f00	1449	- Core NVIC Functions
igor_v	0:8ad47e2b6f00	1450	- Core SysTick Functions
igor_v	11:af609f6dee46	1451	- Core Reset Functions
igor_v	0:8ad47e2b6f00	1452	*/
igor_v	11:af609f6dee46	1453	/@{/
igor_v	0:8ad47e2b6f00	1454
igor_v	0:8ad47e2b6f00	1455	/* ########################## NVIC functions #################################### */
igor_v	0:8ad47e2b6f00	1456
igor_v	11:af609f6dee46	1457	/**
igor_v	11:af609f6dee46	1458	* @brief Set the Priority Grouping in NVIC Interrupt Controller
igor_v	11:af609f6dee46	1459	*
igor_v	11:af609f6dee46	1460	* @param PriorityGroup is priority grouping field
igor_v	11:af609f6dee46	1461	*
igor_v	11:af609f6dee46	1462	* Set the priority grouping field using the required unlock sequence.
igor_v	11:af609f6dee46	1463	* The parameter priority_grouping is assigned to the field
igor_v	11:af609f6dee46	1464	* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
igor_v	11:af609f6dee46	1465	* In case of a conflict between priority grouping and available
igor_v	11:af609f6dee46	1466	* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
igor_v	0:8ad47e2b6f00	1467	*/
igor_v	0:8ad47e2b6f00	1468	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
igor_v	0:8ad47e2b6f00	1469	{
igor_v	0:8ad47e2b6f00	1470	uint32_t reg_value;
igor_v	0:8ad47e2b6f00	1471	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	0:8ad47e2b6f00	1472
igor_v	0:8ad47e2b6f00	1473	reg_value = SCB->AIRCR; /* read old register configuration */
igor_v	0:8ad47e2b6f00	1474	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
igor_v	0:8ad47e2b6f00	1475	reg_value = (reg_value \|
igor_v	0:8ad47e2b6f00	1476	(0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
igor_v	0:8ad47e2b6f00	1477	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
igor_v	0:8ad47e2b6f00	1478	SCB->AIRCR = reg_value;
igor_v	0:8ad47e2b6f00	1479	}
igor_v	0:8ad47e2b6f00	1480
igor_v	11:af609f6dee46	1481	/**
igor_v	11:af609f6dee46	1482	* @brief Get the Priority Grouping from NVIC Interrupt Controller
igor_v	11:af609f6dee46	1483	*
igor_v	11:af609f6dee46	1484	* @return priority grouping field
igor_v	11:af609f6dee46	1485	*
igor_v	11:af609f6dee46	1486	* Get the priority grouping from NVIC Interrupt Controller.
igor_v	11:af609f6dee46	1487	* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
igor_v	0:8ad47e2b6f00	1488	*/
igor_v	0:8ad47e2b6f00	1489	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
igor_v	0:8ad47e2b6f00	1490	{
igor_v	0:8ad47e2b6f00	1491	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
igor_v	0:8ad47e2b6f00	1492	}
igor_v	0:8ad47e2b6f00	1493
igor_v	11:af609f6dee46	1494	/**
igor_v	11:af609f6dee46	1495	* @brief Enable Interrupt in NVIC Interrupt Controller
igor_v	11:af609f6dee46	1496	*
igor_v	11:af609f6dee46	1497	* @param IRQn The positive number of the external interrupt to enable
igor_v	11:af609f6dee46	1498	*
igor_v	11:af609f6dee46	1499	* Enable a device specific interupt in the NVIC interrupt controller.
igor_v	11:af609f6dee46	1500	* The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	1501	*/
igor_v	0:8ad47e2b6f00	1502	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1503	{
igor_v	0:8ad47e2b6f00	1504	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
igor_v	0:8ad47e2b6f00	1505	}
igor_v	0:8ad47e2b6f00	1506
igor_v	11:af609f6dee46	1507	/**
igor_v	11:af609f6dee46	1508	* @brief Disable the interrupt line for external interrupt specified
igor_v	11:af609f6dee46	1509	*
igor_v	11:af609f6dee46	1510	* @param IRQn The positive number of the external interrupt to disable
igor_v	11:af609f6dee46	1511	*
igor_v	11:af609f6dee46	1512	* Disable a device specific interupt in the NVIC interrupt controller.
igor_v	11:af609f6dee46	1513	* The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	1514	*/
igor_v	0:8ad47e2b6f00	1515	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1516	{
igor_v	0:8ad47e2b6f00	1517	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
igor_v	0:8ad47e2b6f00	1518	}
igor_v	0:8ad47e2b6f00	1519
igor_v	11:af609f6dee46	1520	/**
igor_v	11:af609f6dee46	1521	* @brief Read the interrupt pending bit for a device specific interrupt source
igor_v	11:af609f6dee46	1522	*
igor_v	11:af609f6dee46	1523	* @param IRQn The number of the device specifc interrupt
igor_v	11:af609f6dee46	1524	* @return 1 = interrupt pending, 0 = interrupt not pending
igor_v	11:af609f6dee46	1525	*
igor_v	11:af609f6dee46	1526	* Read the pending register in NVIC and return 1 if its status is pending,
igor_v	11:af609f6dee46	1527	* otherwise it returns 0
igor_v	0:8ad47e2b6f00	1528	*/
igor_v	0:8ad47e2b6f00	1529	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1530	{
igor_v	0:8ad47e2b6f00	1531	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
igor_v	0:8ad47e2b6f00	1532	}
igor_v	0:8ad47e2b6f00	1533
igor_v	11:af609f6dee46	1534	/**
igor_v	11:af609f6dee46	1535	* @brief Set the pending bit for an external interrupt
igor_v	11:af609f6dee46	1536	*
igor_v	11:af609f6dee46	1537	* @param IRQn The number of the interrupt for set pending
igor_v	11:af609f6dee46	1538	*
igor_v	11:af609f6dee46	1539	* Set the pending bit for the specified interrupt.
igor_v	11:af609f6dee46	1540	* The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	1541	*/
igor_v	0:8ad47e2b6f00	1542	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1543	{
igor_v	0:8ad47e2b6f00	1544	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
igor_v	0:8ad47e2b6f00	1545	}
igor_v	0:8ad47e2b6f00	1546
igor_v	11:af609f6dee46	1547	/**
igor_v	11:af609f6dee46	1548	* @brief Clear the pending bit for an external interrupt
igor_v	11:af609f6dee46	1549	*
igor_v	11:af609f6dee46	1550	* @param IRQn The number of the interrupt for clear pending
igor_v	11:af609f6dee46	1551	*
igor_v	11:af609f6dee46	1552	* Clear the pending bit for the specified interrupt.
igor_v	11:af609f6dee46	1553	* The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	1554	*/
igor_v	0:8ad47e2b6f00	1555	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1556	{
igor_v	0:8ad47e2b6f00	1557	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
igor_v	0:8ad47e2b6f00	1558	}
igor_v	0:8ad47e2b6f00	1559
igor_v	11:af609f6dee46	1560	/**
igor_v	11:af609f6dee46	1561	* @brief Read the active bit for an external interrupt
igor_v	11:af609f6dee46	1562	*
igor_v	11:af609f6dee46	1563	* @param IRQn The number of the interrupt for read active bit
igor_v	11:af609f6dee46	1564	* @return 1 = interrupt active, 0 = interrupt not active
igor_v	11:af609f6dee46	1565	*
igor_v	11:af609f6dee46	1566	* Read the active register in NVIC and returns 1 if its status is active,
igor_v	11:af609f6dee46	1567	* otherwise it returns 0.
igor_v	0:8ad47e2b6f00	1568	*/
igor_v	0:8ad47e2b6f00	1569	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1570	{
igor_v	0:8ad47e2b6f00	1571	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
igor_v	0:8ad47e2b6f00	1572	}
igor_v	0:8ad47e2b6f00	1573
igor_v	11:af609f6dee46	1574	/**
igor_v	11:af609f6dee46	1575	* @brief Set the priority for an interrupt
igor_v	11:af609f6dee46	1576	*
igor_v	11:af609f6dee46	1577	* @param IRQn The number of the interrupt for set priority
igor_v	11:af609f6dee46	1578	* @param priority The priority to set
igor_v	11:af609f6dee46	1579	*
igor_v	11:af609f6dee46	1580	* Set the priority for the specified interrupt. The interrupt
igor_v	11:af609f6dee46	1581	* number can be positive to specify an external (device specific)
igor_v	11:af609f6dee46	1582	* interrupt, or negative to specify an internal (core) interrupt.
igor_v	11:af609f6dee46	1583	*
igor_v	11:af609f6dee46	1584	* Note: The priority cannot be set for every core interrupt.
igor_v	0:8ad47e2b6f00	1585	*/
igor_v	0:8ad47e2b6f00	1586	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
igor_v	0:8ad47e2b6f00	1587	{
igor_v	11:af609f6dee46	1588	if(IRQn < 0) {
igor_v	11:af609f6dee46	1589	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
igor_v	11:af609f6dee46	1590	else {
igor_v	11:af609f6dee46	1591	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
igor_v	0:8ad47e2b6f00	1592	}
igor_v	0:8ad47e2b6f00	1593
igor_v	11:af609f6dee46	1594	/**
igor_v	11:af609f6dee46	1595	* @brief Read the priority for an interrupt
igor_v	11:af609f6dee46	1596	*
igor_v	11:af609f6dee46	1597	* @param IRQn The number of the interrupt for get priority
igor_v	11:af609f6dee46	1598	* @return The priority for the interrupt
igor_v	11:af609f6dee46	1599	*
igor_v	11:af609f6dee46	1600	* Read the priority for the specified interrupt. The interrupt
igor_v	11:af609f6dee46	1601	* number can be positive to specify an external (device specific)
igor_v	11:af609f6dee46	1602	* interrupt, or negative to specify an internal (core) interrupt.
igor_v	11:af609f6dee46	1603	*
igor_v	11:af609f6dee46	1604	* The returned priority value is automatically aligned to the implemented
igor_v	11:af609f6dee46	1605	* priority bits of the microcontroller.
igor_v	11:af609f6dee46	1606	*
igor_v	11:af609f6dee46	1607	* Note: The priority cannot be set for every core interrupt.
igor_v	0:8ad47e2b6f00	1608	*/
igor_v	0:8ad47e2b6f00	1609	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1610	{
igor_v	0:8ad47e2b6f00	1611
igor_v	0:8ad47e2b6f00	1612	if(IRQn < 0) {
igor_v	11:af609f6dee46	1613	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
igor_v	0:8ad47e2b6f00	1614	else {
igor_v	0:8ad47e2b6f00	1615	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
igor_v	0:8ad47e2b6f00	1616	}
igor_v	0:8ad47e2b6f00	1617
igor_v	0:8ad47e2b6f00	1618
igor_v	11:af609f6dee46	1619	/**
igor_v	11:af609f6dee46	1620	* @brief Encode the priority for an interrupt
igor_v	11:af609f6dee46	1621	*
igor_v	11:af609f6dee46	1622	* @param PriorityGroup The used priority group
igor_v	11:af609f6dee46	1623	* @param PreemptPriority The preemptive priority value (starting from 0)
igor_v	11:af609f6dee46	1624	* @param SubPriority The sub priority value (starting from 0)
igor_v	11:af609f6dee46	1625	* @return The encoded priority for the interrupt
igor_v	11:af609f6dee46	1626	*
igor_v	11:af609f6dee46	1627	* Encode the priority for an interrupt with the given priority group,
igor_v	11:af609f6dee46	1628	* preemptive priority value and sub priority value.
igor_v	11:af609f6dee46	1629	* In case of a conflict between priority grouping and available
igor_v	11:af609f6dee46	1630	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
igor_v	11:af609f6dee46	1631	*
igor_v	11:af609f6dee46	1632	* The returned priority value can be used for NVIC_SetPriority(...) function
igor_v	0:8ad47e2b6f00	1633	*/
igor_v	0:8ad47e2b6f00	1634	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
igor_v	0:8ad47e2b6f00	1635	{
igor_v	0:8ad47e2b6f00	1636	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	0:8ad47e2b6f00	1637	uint32_t PreemptPriorityBits;
igor_v	0:8ad47e2b6f00	1638	uint32_t SubPriorityBits;
igor_v	0:8ad47e2b6f00	1639
igor_v	0:8ad47e2b6f00	1640	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
igor_v	0:8ad47e2b6f00	1641	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
igor_v	0:8ad47e2b6f00	1642
igor_v	0:8ad47e2b6f00	1643	return (
igor_v	0:8ad47e2b6f00	1644	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
igor_v	0:8ad47e2b6f00	1645	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
igor_v	0:8ad47e2b6f00	1646	);
igor_v	0:8ad47e2b6f00	1647	}
igor_v	0:8ad47e2b6f00	1648
igor_v	0:8ad47e2b6f00	1649
igor_v	11:af609f6dee46	1650	/**
igor_v	11:af609f6dee46	1651	* @brief Decode the priority of an interrupt
igor_v	11:af609f6dee46	1652	*
igor_v	11:af609f6dee46	1653	* @param Priority The priority for the interrupt
igor_v	11:af609f6dee46	1654	* @param PriorityGroup The used priority group
igor_v	11:af609f6dee46	1655	* @param pPreemptPriority The preemptive priority value (starting from 0)
igor_v	11:af609f6dee46	1656	* @param pSubPriority The sub priority value (starting from 0)
igor_v	11:af609f6dee46	1657	*
igor_v	11:af609f6dee46	1658	* Decode an interrupt priority value with the given priority group to
igor_v	11:af609f6dee46	1659	* preemptive priority value and sub priority value.
igor_v	11:af609f6dee46	1660	* In case of a conflict between priority grouping and available
igor_v	11:af609f6dee46	1661	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
igor_v	11:af609f6dee46	1662	*
igor_v	11:af609f6dee46	1663	* The priority value can be retrieved with NVIC_GetPriority(...) function
igor_v	0:8ad47e2b6f00	1664	*/
igor_v	0:8ad47e2b6f00	1665	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
igor_v	0:8ad47e2b6f00	1666	{
igor_v	0:8ad47e2b6f00	1667	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	0:8ad47e2b6f00	1668	uint32_t PreemptPriorityBits;
igor_v	0:8ad47e2b6f00	1669	uint32_t SubPriorityBits;
igor_v	0:8ad47e2b6f00	1670
igor_v	0:8ad47e2b6f00	1671	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
igor_v	0:8ad47e2b6f00	1672	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
igor_v	0:8ad47e2b6f00	1673
igor_v	0:8ad47e2b6f00	1674	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
igor_v	0:8ad47e2b6f00	1675	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
igor_v	0:8ad47e2b6f00	1676	}
igor_v	0:8ad47e2b6f00	1677
igor_v	0:8ad47e2b6f00	1678
igor_v	0:8ad47e2b6f00	1679
igor_v	0:8ad47e2b6f00	1680	/* ################################## SysTick function ############################################ */
igor_v	0:8ad47e2b6f00	1681
igor_v	11:af609f6dee46	1682	#if (!defined (__Vendor_SysTickConfig)) \|\| (__Vendor_SysTickConfig == 0)
igor_v	0:8ad47e2b6f00	1683
igor_v	11:af609f6dee46	1684	/**
igor_v	11:af609f6dee46	1685	* @brief Initialize and start the SysTick counter and its interrupt.
igor_v	11:af609f6dee46	1686	*
igor_v	11:af609f6dee46	1687	* @param ticks number of ticks between two interrupts
igor_v	11:af609f6dee46	1688	* @return 1 = failed, 0 = successful
igor_v	11:af609f6dee46	1689	*
igor_v	11:af609f6dee46	1690	* Initialise the system tick timer and its interrupt and start the
igor_v	11:af609f6dee46	1691	* system tick timer / counter in free running mode to generate
igor_v	11:af609f6dee46	1692	* periodical interrupts.
igor_v	0:8ad47e2b6f00	1693	*/
igor_v	0:8ad47e2b6f00	1694	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
igor_v	0:8ad47e2b6f00	1695	{
igor_v	0:8ad47e2b6f00	1696	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
igor_v	0:8ad47e2b6f00	1697
igor_v	0:8ad47e2b6f00	1698	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
igor_v	0:8ad47e2b6f00	1699	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
igor_v	0:8ad47e2b6f00	1700	SysTick->VAL = 0; /* Load the SysTick Counter Value */
igor_v	0:8ad47e2b6f00	1701	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
igor_v	0:8ad47e2b6f00	1702	SysTick_CTRL_TICKINT_Msk \|
igor_v	0:8ad47e2b6f00	1703	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
igor_v	0:8ad47e2b6f00	1704	return (0); /* Function successful */
igor_v	0:8ad47e2b6f00	1705	}
igor_v	0:8ad47e2b6f00	1706
igor_v	0:8ad47e2b6f00	1707	#endif
igor_v	0:8ad47e2b6f00	1708
igor_v	11:af609f6dee46	1709
igor_v	11:af609f6dee46	1710
igor_v	11:af609f6dee46	1711
igor_v	11:af609f6dee46	1712	/* ################################## Reset function ############################################ */
igor_v	11:af609f6dee46	1713
igor_v	11:af609f6dee46	1714	/**
igor_v	11:af609f6dee46	1715	* @brief Initiate a system reset request.
igor_v	11:af609f6dee46	1716	*
igor_v	11:af609f6dee46	1717	* Initiate a system reset request to reset the MCU
igor_v	11:af609f6dee46	1718	*/
igor_v	11:af609f6dee46	1719	static __INLINE void NVIC_SystemReset(void)
igor_v	11:af609f6dee46	1720	{
igor_v	11:af609f6dee46	1721	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
igor_v	11:af609f6dee46	1722	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
igor_v	11:af609f6dee46	1723	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
igor_v	11:af609f6dee46	1724	__DSB(); /* Ensure completion of memory access */
igor_v	11:af609f6dee46	1725	while(1); /* wait until reset */
igor_v	11:af609f6dee46	1726	}
igor_v	11:af609f6dee46	1727
igor_v	11:af609f6dee46	1728	/@}/ /* end of group CMSIS_CM3_Core_FunctionInterface */
igor_v	0:8ad47e2b6f00	1729
igor_v	0:8ad47e2b6f00	1730
igor_v	0:8ad47e2b6f00	1731
igor_v	0:8ad47e2b6f00	1732	/* ##################################### Debug In/Output function ########################################### */
igor_v	0:8ad47e2b6f00	1733
igor_v	11:af609f6dee46	1734	/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
igor_v	11:af609f6dee46	1735	Core Debug Interface containing:
igor_v	11:af609f6dee46	1736	- Core Debug Receive / Transmit Functions
igor_v	11:af609f6dee46	1737	- Core Debug Defines
igor_v	11:af609f6dee46	1738	- Core Debug Variables
igor_v	11:af609f6dee46	1739	*/
igor_v	11:af609f6dee46	1740	/@{/
igor_v	11:af609f6dee46	1741
igor_v	11:af609f6dee46	1742	extern volatile int ITM_RxBuffer; /!< variable to receive characters /
igor_v	11:af609f6dee46	1743	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< value identifying ITM_RxBuffer is ready for next character /
igor_v	0:8ad47e2b6f00	1744
igor_v	0:8ad47e2b6f00	1745
igor_v	11:af609f6dee46	1746	/**
igor_v	11:af609f6dee46	1747	* @brief Outputs a character via the ITM channel 0
igor_v	11:af609f6dee46	1748	*
igor_v	11:af609f6dee46	1749	* @param ch character to output
igor_v	11:af609f6dee46	1750	* @return character to output
igor_v	11:af609f6dee46	1751	*
igor_v	11:af609f6dee46	1752	* The function outputs a character via the ITM channel 0.
igor_v	11:af609f6dee46	1753	* The function returns when no debugger is connected that has booked the output.
igor_v	11:af609f6dee46	1754	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
igor_v	0:8ad47e2b6f00	1755	*/
igor_v	0:8ad47e2b6f00	1756	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
igor_v	0:8ad47e2b6f00	1757	{
igor_v	0:8ad47e2b6f00	1758	if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
igor_v	0:8ad47e2b6f00	1759	(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
igor_v	11:af609f6dee46	1760	(ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
igor_v	0:8ad47e2b6f00	1761	{
igor_v	0:8ad47e2b6f00	1762	while (ITM->PORT[0].u32 == 0);
igor_v	0:8ad47e2b6f00	1763	ITM->PORT[0].u8 = (uint8_t) ch;
igor_v	0:8ad47e2b6f00	1764	}
igor_v	0:8ad47e2b6f00	1765	return (ch);
igor_v	0:8ad47e2b6f00	1766	}
igor_v	0:8ad47e2b6f00	1767
igor_v	0:8ad47e2b6f00	1768
igor_v	11:af609f6dee46	1769	/**
igor_v	11:af609f6dee46	1770	* @brief Inputs a character via variable ITM_RxBuffer
igor_v	11:af609f6dee46	1771	*
igor_v	11:af609f6dee46	1772	* @return received character, -1 = no character received
igor_v	11:af609f6dee46	1773	*
igor_v	11:af609f6dee46	1774	* The function inputs a character via variable ITM_RxBuffer.
igor_v	11:af609f6dee46	1775	* The function returns when no debugger is connected that has booked the output.
igor_v	11:af609f6dee46	1776	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
igor_v	0:8ad47e2b6f00	1777	*/
igor_v	11:af609f6dee46	1778	static __INLINE int ITM_ReceiveChar (void) {
igor_v	11:af609f6dee46	1779	int ch = -1; /* no character available */
igor_v	0:8ad47e2b6f00	1780
igor_v	0:8ad47e2b6f00	1781	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
igor_v	0:8ad47e2b6f00	1782	ch = ITM_RxBuffer;
igor_v	0:8ad47e2b6f00	1783	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
igor_v	0:8ad47e2b6f00	1784	}
igor_v	0:8ad47e2b6f00	1785
igor_v	0:8ad47e2b6f00	1786	return (ch);
igor_v	0:8ad47e2b6f00	1787	}
igor_v	0:8ad47e2b6f00	1788
igor_v	0:8ad47e2b6f00	1789
igor_v	11:af609f6dee46	1790	/**
igor_v	11:af609f6dee46	1791	* @brief Check if a character via variable ITM_RxBuffer is available
igor_v	11:af609f6dee46	1792	*
igor_v	11:af609f6dee46	1793	* @return 1 = character available, 0 = no character available
igor_v	11:af609f6dee46	1794	*
igor_v	11:af609f6dee46	1795	* The function checks variable ITM_RxBuffer whether a character is available or not.
igor_v	11:af609f6dee46	1796	* The function returns '1' if a character is available and '0' if no character is available.
igor_v	0:8ad47e2b6f00	1797	*/
igor_v	11:af609f6dee46	1798	static __INLINE int ITM_CheckChar (void) {
igor_v	0:8ad47e2b6f00	1799
igor_v	0:8ad47e2b6f00	1800	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
igor_v	0:8ad47e2b6f00	1801	return (0); /* no character available */
igor_v	0:8ad47e2b6f00	1802	} else {
igor_v	0:8ad47e2b6f00	1803	return (1); /* character available */
igor_v	0:8ad47e2b6f00	1804	}
igor_v	0:8ad47e2b6f00	1805	}
igor_v	0:8ad47e2b6f00	1806
igor_v	11:af609f6dee46	1807	/@}/ /* end of group CMSIS_CM3_core_DebugInterface */
igor_v	0:8ad47e2b6f00	1808
igor_v	0:8ad47e2b6f00	1809
igor_v	0:8ad47e2b6f00	1810	#ifdef __cplusplus
igor_v	0:8ad47e2b6f00	1811	}
igor_v	0:8ad47e2b6f00	1812	#endif
igor_v	0:8ad47e2b6f00	1813
igor_v	11:af609f6dee46	1814	/@}/ /* end of group CMSIS_CM3_core_definitions */
igor_v	11:af609f6dee46	1815
igor_v	11:af609f6dee46	1816	#endif /* __CM3_CORE_H__ */
igor_v	11:af609f6dee46	1817
igor_v	0:8ad47e2b6f00	1818	/lint -restore /
igor_v	0:8ad47e2b6f00	1819

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	20 Oct 2016
Imports:	4
Forks:	1
Commits:	220
Dependents:	0
Dependencies:	1
Followers:	1

core_cm3.h@11:af609f6dee46, 2016-02-01 (annotated)

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