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core_cm3.h@0:8ad47e2b6f00, 2016-01-30 (annotated)

Committer:: igor_v
Date:: Sat Jan 30 13:00:39 2016 +0000
Revision:: 0:8ad47e2b6f00
Child:: 11:af609f6dee46

2016_01_30;

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User	Revision	Line number	New contents of line
igor_v	0:8ad47e2b6f00	1	/************************************************************************//
igor_v	0:8ad47e2b6f00	2	* @file core_cm3.h
igor_v	0:8ad47e2b6f00	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
igor_v	0:8ad47e2b6f00	4	* @version V2.01
igor_v	0:8ad47e2b6f00	5	* @date 06. December 2010
igor_v	0:8ad47e2b6f00	6	*
igor_v	0:8ad47e2b6f00	7	* @note
igor_v	0:8ad47e2b6f00	8	* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
igor_v	0:8ad47e2b6f00	9	*
igor_v	0:8ad47e2b6f00	10	* @par
igor_v	0:8ad47e2b6f00	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
igor_v	0:8ad47e2b6f00	12	* processor based microcontrollers. This file can be freely distributed
igor_v	0:8ad47e2b6f00	13	* within development tools that are supporting such ARM based processors.
igor_v	0:8ad47e2b6f00	14	*
igor_v	0:8ad47e2b6f00	15	* @par
igor_v	0:8ad47e2b6f00	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
igor_v	0:8ad47e2b6f00	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
igor_v	0:8ad47e2b6f00	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
igor_v	0:8ad47e2b6f00	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
igor_v	0:8ad47e2b6f00	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
igor_v	0:8ad47e2b6f00	21	*
igor_v	0:8ad47e2b6f00	22	******************************************************************************/
igor_v	0:8ad47e2b6f00	23	#if defined ( __ICCARM__ )
igor_v	0:8ad47e2b6f00	24	#pragma system_include /* treat file as system include file for MISRA check */
igor_v	0:8ad47e2b6f00	25	#endif
igor_v	0:8ad47e2b6f00	26
igor_v	0:8ad47e2b6f00	27	#ifdef __cplusplus
igor_v	0:8ad47e2b6f00	28	extern "C" {
igor_v	0:8ad47e2b6f00	29	#endif
igor_v	0:8ad47e2b6f00	30
igor_v	0:8ad47e2b6f00	31	#ifndef __CORE_CM3_H_GENERIC
igor_v	0:8ad47e2b6f00	32	#define __CORE_CM3_H_GENERIC
igor_v	0:8ad47e2b6f00	33
igor_v	0:8ad47e2b6f00	34
igor_v	0:8ad47e2b6f00	35	/** \mainpage CMSIS Cortex-M3
igor_v	0:8ad47e2b6f00	36
igor_v	0:8ad47e2b6f00	37	This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
igor_v	0:8ad47e2b6f00	38	It consists of:
igor_v	0:8ad47e2b6f00	39
igor_v	0:8ad47e2b6f00	40	- Cortex-M Core Register Definitions
igor_v	0:8ad47e2b6f00	41	- Cortex-M functions
igor_v	0:8ad47e2b6f00	42	- Cortex-M instructions
igor_v	0:8ad47e2b6f00	43
igor_v	0:8ad47e2b6f00	44	The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
igor_v	0:8ad47e2b6f00	45	access to the Cortex-M Core
igor_v	0:8ad47e2b6f00	46	*/
igor_v	0:8ad47e2b6f00	47
igor_v	0:8ad47e2b6f00	48	/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
igor_v	0:8ad47e2b6f00	49	List of Lint messages which will be suppressed and not shown:
igor_v	0:8ad47e2b6f00	50	- not yet checked
igor_v	0:8ad47e2b6f00	51	.
igor_v	0:8ad47e2b6f00	52	Note: To re-enable a Message, insert a space before 'lint' *
igor_v	0:8ad47e2b6f00	53
igor_v	0:8ad47e2b6f00	54	*/
igor_v	0:8ad47e2b6f00	55
igor_v	0:8ad47e2b6f00	56
igor_v	0:8ad47e2b6f00	57	/*******************************************************************************
igor_v	0:8ad47e2b6f00	58	* CMSIS definitions
igor_v	0:8ad47e2b6f00	59	******************************************************************************/
igor_v	0:8ad47e2b6f00	60	/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
igor_v	0:8ad47e2b6f00	61	This file defines all structures and symbols for CMSIS core:
igor_v	0:8ad47e2b6f00	62	- CMSIS version number
igor_v	0:8ad47e2b6f00	63	- Cortex-M core
igor_v	0:8ad47e2b6f00	64	- Cortex-M core Revision Number
igor_v	0:8ad47e2b6f00	65	@{
igor_v	0:8ad47e2b6f00	66	*/
igor_v	0:8ad47e2b6f00	67
igor_v	0:8ad47e2b6f00	68	/* CMSIS CM3 definitions */
igor_v	0:8ad47e2b6f00	69	#define __CM3_CMSIS_VERSION_MAIN (0x02) /!< [31:16] CMSIS HAL main version /
igor_v	0:8ad47e2b6f00	70	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
igor_v	0:8ad47e2b6f00	71	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
igor_v	0:8ad47e2b6f00	72
igor_v	0:8ad47e2b6f00	73	#define __CORTEX_M (0x03) /!< Cortex core /
igor_v	0:8ad47e2b6f00	74
igor_v	0:8ad47e2b6f00	75
igor_v	0:8ad47e2b6f00	76	#if defined ( __CC_ARM )
igor_v	0:8ad47e2b6f00	77	#define __ASM __asm /!< asm keyword for ARM Compiler /
igor_v	0:8ad47e2b6f00	78	#define __INLINE __inline /!< inline keyword for ARM Compiler /
igor_v	0:8ad47e2b6f00	79
igor_v	0:8ad47e2b6f00	80	#elif defined ( __ICCARM__ )
igor_v	0:8ad47e2b6f00	81	#define __ASM __asm /!< asm keyword for IAR Compiler /
igor_v	0:8ad47e2b6f00	82	#define __INLINE inline /!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! /
igor_v	0:8ad47e2b6f00	83
igor_v	0:8ad47e2b6f00	84	#elif defined ( __GNUC__ )
igor_v	0:8ad47e2b6f00	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
igor_v	0:8ad47e2b6f00	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
igor_v	0:8ad47e2b6f00	87
igor_v	0:8ad47e2b6f00	88	#elif defined ( __TASKING__ )
igor_v	0:8ad47e2b6f00	89	#define __ASM __asm /!< asm keyword for TASKING Compiler /
igor_v	0:8ad47e2b6f00	90	#define __INLINE inline /!< inline keyword for TASKING Compiler /
igor_v	0:8ad47e2b6f00	91
igor_v	0:8ad47e2b6f00	92	#endif
igor_v	0:8ad47e2b6f00	93
igor_v	0:8ad47e2b6f00	94	#include <stdint.h> /!< standard types definitions /
igor_v	0:8ad47e2b6f00	95	#include "core_cmInstr.h" /!< Core Instruction Access /
igor_v	0:8ad47e2b6f00	96	#include "core_cmFunc.h" /!< Core Function Access /
igor_v	0:8ad47e2b6f00	97
igor_v	0:8ad47e2b6f00	98	#endif /* __CORE_CM3_H_GENERIC */
igor_v	0:8ad47e2b6f00	99
igor_v	0:8ad47e2b6f00	100
igor_v	0:8ad47e2b6f00	101	#ifndef __CMSIS_GENERIC
igor_v	0:8ad47e2b6f00	102
igor_v	0:8ad47e2b6f00	103	#ifndef __CORE_CM3_H_DEPENDANT
igor_v	0:8ad47e2b6f00	104	#define __CORE_CM3_H_DEPENDANT
igor_v	0:8ad47e2b6f00	105
igor_v	0:8ad47e2b6f00	106	/* IO definitions (access restrictions to peripheral registers) */
igor_v	0:8ad47e2b6f00	107	#ifdef __cplusplus
igor_v	0:8ad47e2b6f00	108	#define __I volatile /!< defines 'read only' permissions /
igor_v	0:8ad47e2b6f00	109	#else
igor_v	0:8ad47e2b6f00	110	#define __I volatile const /!< defines 'read only' permissions /
igor_v	0:8ad47e2b6f00	111	#endif
igor_v	0:8ad47e2b6f00	112	#define __O volatile /!< defines 'write only' permissions /
igor_v	0:8ad47e2b6f00	113	#define __IO volatile /!< defines 'read / write' permissions /
igor_v	0:8ad47e2b6f00	114
igor_v	0:8ad47e2b6f00	115	/@} end of group CMSIS_core_definitions /
igor_v	0:8ad47e2b6f00	116
igor_v	0:8ad47e2b6f00	117
igor_v	0:8ad47e2b6f00	118
igor_v	0:8ad47e2b6f00	119	/*******************************************************************************
igor_v	0:8ad47e2b6f00	120	* Register Abstraction
igor_v	0:8ad47e2b6f00	121	******************************************************************************/
igor_v	0:8ad47e2b6f00	122	/** \defgroup CMSIS_core_register CMSIS Core Register
igor_v	0:8ad47e2b6f00	123	Core Register contain:
igor_v	0:8ad47e2b6f00	124	- Core Register
igor_v	0:8ad47e2b6f00	125	- Core NVIC Register
igor_v	0:8ad47e2b6f00	126	- Core SCB Register
igor_v	0:8ad47e2b6f00	127	- Core SysTick Register
igor_v	0:8ad47e2b6f00	128	- Core Debug Register
igor_v	0:8ad47e2b6f00	129	- Core MPU Register
igor_v	0:8ad47e2b6f00	130	*/
igor_v	0:8ad47e2b6f00	131
igor_v	0:8ad47e2b6f00	132	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	133	\defgroup CMSIS_CORE CMSIS Core
igor_v	0:8ad47e2b6f00	134	Type definitions for the Cortex-M Core Registers
igor_v	0:8ad47e2b6f00	135	@{
igor_v	0:8ad47e2b6f00	136	*/
igor_v	0:8ad47e2b6f00	137
igor_v	0:8ad47e2b6f00	138	/** \brief Union type to access the Application Program Status Register (APSR).
igor_v	0:8ad47e2b6f00	139	*/
igor_v	0:8ad47e2b6f00	140	typedef union
igor_v	0:8ad47e2b6f00	141	{
igor_v	0:8ad47e2b6f00	142	struct
igor_v	0:8ad47e2b6f00	143	{
igor_v	0:8ad47e2b6f00	144	#if (__CORTEX_M != 0x04)
igor_v	0:8ad47e2b6f00	145	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
igor_v	0:8ad47e2b6f00	146	#else
igor_v	0:8ad47e2b6f00	147	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
igor_v	0:8ad47e2b6f00	148	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
igor_v	0:8ad47e2b6f00	149	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
igor_v	0:8ad47e2b6f00	150	#endif
igor_v	0:8ad47e2b6f00	151	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
igor_v	0:8ad47e2b6f00	152	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
igor_v	0:8ad47e2b6f00	153	uint32_t C:1; /!< bit: 29 Carry condition code flag /
igor_v	0:8ad47e2b6f00	154	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
igor_v	0:8ad47e2b6f00	155	uint32_t N:1; /!< bit: 31 Negative condition code flag /
igor_v	0:8ad47e2b6f00	156	} b; /!< Structure used for bit access /
igor_v	0:8ad47e2b6f00	157	uint32_t w; /!< Type used for word access /
igor_v	0:8ad47e2b6f00	158	} APSR_Type;
igor_v	0:8ad47e2b6f00	159
igor_v	0:8ad47e2b6f00	160
igor_v	0:8ad47e2b6f00	161	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
igor_v	0:8ad47e2b6f00	162	*/
igor_v	0:8ad47e2b6f00	163	typedef union
igor_v	0:8ad47e2b6f00	164	{
igor_v	0:8ad47e2b6f00	165	struct
igor_v	0:8ad47e2b6f00	166	{
igor_v	0:8ad47e2b6f00	167	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
igor_v	0:8ad47e2b6f00	168	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
igor_v	0:8ad47e2b6f00	169	} b; /!< Structure used for bit access /
igor_v	0:8ad47e2b6f00	170	uint32_t w; /!< Type used for word access /
igor_v	0:8ad47e2b6f00	171	} IPSR_Type;
igor_v	0:8ad47e2b6f00	172
igor_v	0:8ad47e2b6f00	173
igor_v	0:8ad47e2b6f00	174	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
igor_v	0:8ad47e2b6f00	175	*/
igor_v	0:8ad47e2b6f00	176	typedef union
igor_v	0:8ad47e2b6f00	177	{
igor_v	0:8ad47e2b6f00	178	struct
igor_v	0:8ad47e2b6f00	179	{
igor_v	0:8ad47e2b6f00	180	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
igor_v	0:8ad47e2b6f00	181	#if (__CORTEX_M != 0x04)
igor_v	0:8ad47e2b6f00	182	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
igor_v	0:8ad47e2b6f00	183	#else
igor_v	0:8ad47e2b6f00	184	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
igor_v	0:8ad47e2b6f00	185	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
igor_v	0:8ad47e2b6f00	186	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
igor_v	0:8ad47e2b6f00	187	#endif
igor_v	0:8ad47e2b6f00	188	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
igor_v	0:8ad47e2b6f00	189	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
igor_v	0:8ad47e2b6f00	190	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
igor_v	0:8ad47e2b6f00	191	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
igor_v	0:8ad47e2b6f00	192	uint32_t C:1; /!< bit: 29 Carry condition code flag /
igor_v	0:8ad47e2b6f00	193	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
igor_v	0:8ad47e2b6f00	194	uint32_t N:1; /!< bit: 31 Negative condition code flag /
igor_v	0:8ad47e2b6f00	195	} b; /!< Structure used for bit access /
igor_v	0:8ad47e2b6f00	196	uint32_t w; /!< Type used for word access /
igor_v	0:8ad47e2b6f00	197	} xPSR_Type;
igor_v	0:8ad47e2b6f00	198
igor_v	0:8ad47e2b6f00	199
igor_v	0:8ad47e2b6f00	200	/** \brief Union type to access the Control Registers (CONTROL).
igor_v	0:8ad47e2b6f00	201	*/
igor_v	0:8ad47e2b6f00	202	typedef union
igor_v	0:8ad47e2b6f00	203	{
igor_v	0:8ad47e2b6f00	204	struct
igor_v	0:8ad47e2b6f00	205	{
igor_v	0:8ad47e2b6f00	206	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
igor_v	0:8ad47e2b6f00	207	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
igor_v	0:8ad47e2b6f00	208	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
igor_v	0:8ad47e2b6f00	209	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
igor_v	0:8ad47e2b6f00	210	} b; /!< Structure used for bit access /
igor_v	0:8ad47e2b6f00	211	uint32_t w; /!< Type used for word access /
igor_v	0:8ad47e2b6f00	212	} CONTROL_Type;
igor_v	0:8ad47e2b6f00	213
igor_v	0:8ad47e2b6f00	214	/@} end of group CMSIS_CORE /
igor_v	0:8ad47e2b6f00	215
igor_v	0:8ad47e2b6f00	216
igor_v	0:8ad47e2b6f00	217	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	218	\defgroup CMSIS_NVIC CMSIS NVIC
igor_v	0:8ad47e2b6f00	219	Type definitions for the Cortex-M NVIC Registers
igor_v	0:8ad47e2b6f00	220	@{
igor_v	0:8ad47e2b6f00	221	*/
igor_v	0:8ad47e2b6f00	222
igor_v	0:8ad47e2b6f00	223	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
igor_v	0:8ad47e2b6f00	224	*/
igor_v	0:8ad47e2b6f00	225	typedef struct
igor_v	0:8ad47e2b6f00	226	{
igor_v	0:8ad47e2b6f00	227	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
igor_v	0:8ad47e2b6f00	228	uint32_t RESERVED0[24];
igor_v	0:8ad47e2b6f00	229	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
igor_v	0:8ad47e2b6f00	230	uint32_t RSERVED1[24];
igor_v	0:8ad47e2b6f00	231	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
igor_v	0:8ad47e2b6f00	232	uint32_t RESERVED2[24];
igor_v	0:8ad47e2b6f00	233	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
igor_v	0:8ad47e2b6f00	234	uint32_t RESERVED3[24];
igor_v	0:8ad47e2b6f00	235	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
igor_v	0:8ad47e2b6f00	236	uint32_t RESERVED4[56];
igor_v	0:8ad47e2b6f00	237	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
igor_v	0:8ad47e2b6f00	238	uint32_t RESERVED5[644];
igor_v	0:8ad47e2b6f00	239	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
igor_v	0:8ad47e2b6f00	240	} NVIC_Type;
igor_v	0:8ad47e2b6f00	241
igor_v	0:8ad47e2b6f00	242	/@} end of group CMSIS_NVIC /
igor_v	0:8ad47e2b6f00	243
igor_v	0:8ad47e2b6f00	244
igor_v	0:8ad47e2b6f00	245	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	246	\defgroup CMSIS_SCB CMSIS SCB
igor_v	0:8ad47e2b6f00	247	Type definitions for the Cortex-M System Control Block Registers
igor_v	0:8ad47e2b6f00	248	@{
igor_v	0:8ad47e2b6f00	249	*/
igor_v	0:8ad47e2b6f00	250
igor_v	0:8ad47e2b6f00	251	/** \brief Structure type to access the System Control Block (SCB).
igor_v	0:8ad47e2b6f00	252	*/
igor_v	0:8ad47e2b6f00	253	typedef struct
igor_v	0:8ad47e2b6f00	254	{
igor_v	0:8ad47e2b6f00	255	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPU ID Base Register /
igor_v	0:8ad47e2b6f00	256	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control State Register /
igor_v	0:8ad47e2b6f00	257	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
igor_v	0:8ad47e2b6f00	258	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register /
igor_v	0:8ad47e2b6f00	259	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
igor_v	0:8ad47e2b6f00	260	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
igor_v	0:8ad47e2b6f00	261	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
igor_v	0:8ad47e2b6f00	262	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
igor_v	0:8ad47e2b6f00	263	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
igor_v	0:8ad47e2b6f00	264	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) Hard Fault Status Register /
igor_v	0:8ad47e2b6f00	265	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
igor_v	0:8ad47e2b6f00	266	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) Mem Manage Address Register /
igor_v	0:8ad47e2b6f00	267	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) Bus Fault Address Register /
igor_v	0:8ad47e2b6f00	268	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
igor_v	0:8ad47e2b6f00	269	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
igor_v	0:8ad47e2b6f00	270	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
igor_v	0:8ad47e2b6f00	271	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
igor_v	0:8ad47e2b6f00	272	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
igor_v	0:8ad47e2b6f00	273	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) ISA Feature Register /
igor_v	0:8ad47e2b6f00	274	} SCB_Type;
igor_v	0:8ad47e2b6f00	275
igor_v	0:8ad47e2b6f00	276	/* SCB CPUID Register Definitions */
igor_v	0:8ad47e2b6f00	277	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
igor_v	0:8ad47e2b6f00	278	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
igor_v	0:8ad47e2b6f00	279
igor_v	0:8ad47e2b6f00	280	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
igor_v	0:8ad47e2b6f00	281	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
igor_v	0:8ad47e2b6f00	282
igor_v	0:8ad47e2b6f00	283	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
igor_v	0:8ad47e2b6f00	284	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
igor_v	0:8ad47e2b6f00	285
igor_v	0:8ad47e2b6f00	286	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
igor_v	0:8ad47e2b6f00	287	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
igor_v	0:8ad47e2b6f00	288
igor_v	0:8ad47e2b6f00	289	/* SCB Interrupt Control State Register Definitions */
igor_v	0:8ad47e2b6f00	290	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
igor_v	0:8ad47e2b6f00	291	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
igor_v	0:8ad47e2b6f00	292
igor_v	0:8ad47e2b6f00	293	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
igor_v	0:8ad47e2b6f00	294	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
igor_v	0:8ad47e2b6f00	295
igor_v	0:8ad47e2b6f00	296	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
igor_v	0:8ad47e2b6f00	297	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
igor_v	0:8ad47e2b6f00	298
igor_v	0:8ad47e2b6f00	299	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
igor_v	0:8ad47e2b6f00	300	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
igor_v	0:8ad47e2b6f00	301
igor_v	0:8ad47e2b6f00	302	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
igor_v	0:8ad47e2b6f00	303	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
igor_v	0:8ad47e2b6f00	304
igor_v	0:8ad47e2b6f00	305	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
igor_v	0:8ad47e2b6f00	306	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
igor_v	0:8ad47e2b6f00	307
igor_v	0:8ad47e2b6f00	308	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
igor_v	0:8ad47e2b6f00	309	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
igor_v	0:8ad47e2b6f00	310
igor_v	0:8ad47e2b6f00	311	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
igor_v	0:8ad47e2b6f00	312	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
igor_v	0:8ad47e2b6f00	313
igor_v	0:8ad47e2b6f00	314	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
igor_v	0:8ad47e2b6f00	315	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
igor_v	0:8ad47e2b6f00	316
igor_v	0:8ad47e2b6f00	317	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
igor_v	0:8ad47e2b6f00	318	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
igor_v	0:8ad47e2b6f00	319
igor_v	0:8ad47e2b6f00	320	/* SCB Interrupt Control State Register Definitions */
igor_v	0:8ad47e2b6f00	321	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
igor_v	0:8ad47e2b6f00	322	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
igor_v	0:8ad47e2b6f00	323
igor_v	0:8ad47e2b6f00	324	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
igor_v	0:8ad47e2b6f00	325	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
igor_v	0:8ad47e2b6f00	326
igor_v	0:8ad47e2b6f00	327	/* SCB Application Interrupt and Reset Control Register Definitions */
igor_v	0:8ad47e2b6f00	328	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
igor_v	0:8ad47e2b6f00	329	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
igor_v	0:8ad47e2b6f00	330
igor_v	0:8ad47e2b6f00	331	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
igor_v	0:8ad47e2b6f00	332	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
igor_v	0:8ad47e2b6f00	333
igor_v	0:8ad47e2b6f00	334	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
igor_v	0:8ad47e2b6f00	335	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
igor_v	0:8ad47e2b6f00	336
igor_v	0:8ad47e2b6f00	337	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
igor_v	0:8ad47e2b6f00	338	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
igor_v	0:8ad47e2b6f00	339
igor_v	0:8ad47e2b6f00	340	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
igor_v	0:8ad47e2b6f00	341	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
igor_v	0:8ad47e2b6f00	342
igor_v	0:8ad47e2b6f00	343	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
igor_v	0:8ad47e2b6f00	344	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
igor_v	0:8ad47e2b6f00	345
igor_v	0:8ad47e2b6f00	346	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
igor_v	0:8ad47e2b6f00	347	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
igor_v	0:8ad47e2b6f00	348
igor_v	0:8ad47e2b6f00	349	/* SCB System Control Register Definitions */
igor_v	0:8ad47e2b6f00	350	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
igor_v	0:8ad47e2b6f00	351	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
igor_v	0:8ad47e2b6f00	352
igor_v	0:8ad47e2b6f00	353	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
igor_v	0:8ad47e2b6f00	354	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
igor_v	0:8ad47e2b6f00	355
igor_v	0:8ad47e2b6f00	356	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
igor_v	0:8ad47e2b6f00	357	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
igor_v	0:8ad47e2b6f00	358
igor_v	0:8ad47e2b6f00	359	/* SCB Configuration Control Register Definitions */
igor_v	0:8ad47e2b6f00	360	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
igor_v	0:8ad47e2b6f00	361	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
igor_v	0:8ad47e2b6f00	362
igor_v	0:8ad47e2b6f00	363	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
igor_v	0:8ad47e2b6f00	364	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
igor_v	0:8ad47e2b6f00	365
igor_v	0:8ad47e2b6f00	366	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
igor_v	0:8ad47e2b6f00	367	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
igor_v	0:8ad47e2b6f00	368
igor_v	0:8ad47e2b6f00	369	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
igor_v	0:8ad47e2b6f00	370	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
igor_v	0:8ad47e2b6f00	371
igor_v	0:8ad47e2b6f00	372	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
igor_v	0:8ad47e2b6f00	373	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
igor_v	0:8ad47e2b6f00	374
igor_v	0:8ad47e2b6f00	375	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
igor_v	0:8ad47e2b6f00	376	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
igor_v	0:8ad47e2b6f00	377
igor_v	0:8ad47e2b6f00	378	/* SCB System Handler Control and State Register Definitions */
igor_v	0:8ad47e2b6f00	379	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
igor_v	0:8ad47e2b6f00	380	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
igor_v	0:8ad47e2b6f00	381
igor_v	0:8ad47e2b6f00	382	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
igor_v	0:8ad47e2b6f00	383	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
igor_v	0:8ad47e2b6f00	384
igor_v	0:8ad47e2b6f00	385	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
igor_v	0:8ad47e2b6f00	386	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
igor_v	0:8ad47e2b6f00	387
igor_v	0:8ad47e2b6f00	388	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
igor_v	0:8ad47e2b6f00	389	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
igor_v	0:8ad47e2b6f00	390
igor_v	0:8ad47e2b6f00	391	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
igor_v	0:8ad47e2b6f00	392	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
igor_v	0:8ad47e2b6f00	393
igor_v	0:8ad47e2b6f00	394	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
igor_v	0:8ad47e2b6f00	395	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
igor_v	0:8ad47e2b6f00	396
igor_v	0:8ad47e2b6f00	397	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
igor_v	0:8ad47e2b6f00	398	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
igor_v	0:8ad47e2b6f00	399
igor_v	0:8ad47e2b6f00	400	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
igor_v	0:8ad47e2b6f00	401	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
igor_v	0:8ad47e2b6f00	402
igor_v	0:8ad47e2b6f00	403	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
igor_v	0:8ad47e2b6f00	404	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
igor_v	0:8ad47e2b6f00	405
igor_v	0:8ad47e2b6f00	406	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
igor_v	0:8ad47e2b6f00	407	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
igor_v	0:8ad47e2b6f00	408
igor_v	0:8ad47e2b6f00	409	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
igor_v	0:8ad47e2b6f00	410	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
igor_v	0:8ad47e2b6f00	411
igor_v	0:8ad47e2b6f00	412	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
igor_v	0:8ad47e2b6f00	413	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
igor_v	0:8ad47e2b6f00	414
igor_v	0:8ad47e2b6f00	415	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
igor_v	0:8ad47e2b6f00	416	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
igor_v	0:8ad47e2b6f00	417
igor_v	0:8ad47e2b6f00	418	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
igor_v	0:8ad47e2b6f00	419	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
igor_v	0:8ad47e2b6f00	420
igor_v	0:8ad47e2b6f00	421	/* SCB Configurable Fault Status Registers Definitions */
igor_v	0:8ad47e2b6f00	422	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
igor_v	0:8ad47e2b6f00	423	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
igor_v	0:8ad47e2b6f00	424
igor_v	0:8ad47e2b6f00	425	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
igor_v	0:8ad47e2b6f00	426	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
igor_v	0:8ad47e2b6f00	427
igor_v	0:8ad47e2b6f00	428	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
igor_v	0:8ad47e2b6f00	429	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
igor_v	0:8ad47e2b6f00	430
igor_v	0:8ad47e2b6f00	431	/* SCB Hard Fault Status Registers Definitions */
igor_v	0:8ad47e2b6f00	432	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
igor_v	0:8ad47e2b6f00	433	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
igor_v	0:8ad47e2b6f00	434
igor_v	0:8ad47e2b6f00	435	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
igor_v	0:8ad47e2b6f00	436	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
igor_v	0:8ad47e2b6f00	437
igor_v	0:8ad47e2b6f00	438	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
igor_v	0:8ad47e2b6f00	439	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
igor_v	0:8ad47e2b6f00	440
igor_v	0:8ad47e2b6f00	441	/* SCB Debug Fault Status Register Definitions */
igor_v	0:8ad47e2b6f00	442	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
igor_v	0:8ad47e2b6f00	443	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
igor_v	0:8ad47e2b6f00	444
igor_v	0:8ad47e2b6f00	445	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
igor_v	0:8ad47e2b6f00	446	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
igor_v	0:8ad47e2b6f00	447
igor_v	0:8ad47e2b6f00	448	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
igor_v	0:8ad47e2b6f00	449	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
igor_v	0:8ad47e2b6f00	450
igor_v	0:8ad47e2b6f00	451	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
igor_v	0:8ad47e2b6f00	452	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
igor_v	0:8ad47e2b6f00	453
igor_v	0:8ad47e2b6f00	454	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
igor_v	0:8ad47e2b6f00	455	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
igor_v	0:8ad47e2b6f00	456
igor_v	0:8ad47e2b6f00	457	/@} end of group CMSIS_SCB /
igor_v	0:8ad47e2b6f00	458
igor_v	0:8ad47e2b6f00	459
igor_v	0:8ad47e2b6f00	460	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	461	\defgroup CMSIS_SysTick CMSIS SysTick
igor_v	0:8ad47e2b6f00	462	Type definitions for the Cortex-M System Timer Registers
igor_v	0:8ad47e2b6f00	463	@{
igor_v	0:8ad47e2b6f00	464	*/
igor_v	0:8ad47e2b6f00	465
igor_v	0:8ad47e2b6f00	466	/** \brief Structure type to access the System Timer (SysTick).
igor_v	0:8ad47e2b6f00	467	*/
igor_v	0:8ad47e2b6f00	468	typedef struct
igor_v	0:8ad47e2b6f00	469	{
igor_v	0:8ad47e2b6f00	470	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
igor_v	0:8ad47e2b6f00	471	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
igor_v	0:8ad47e2b6f00	472	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
igor_v	0:8ad47e2b6f00	473	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
igor_v	0:8ad47e2b6f00	474	} SysTick_Type;
igor_v	0:8ad47e2b6f00	475
igor_v	0:8ad47e2b6f00	476	/* SysTick Control / Status Register Definitions */
igor_v	0:8ad47e2b6f00	477	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
igor_v	0:8ad47e2b6f00	478	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
igor_v	0:8ad47e2b6f00	479
igor_v	0:8ad47e2b6f00	480	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
igor_v	0:8ad47e2b6f00	481	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
igor_v	0:8ad47e2b6f00	482
igor_v	0:8ad47e2b6f00	483	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
igor_v	0:8ad47e2b6f00	484	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
igor_v	0:8ad47e2b6f00	485
igor_v	0:8ad47e2b6f00	486	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
igor_v	0:8ad47e2b6f00	487	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
igor_v	0:8ad47e2b6f00	488
igor_v	0:8ad47e2b6f00	489	/* SysTick Reload Register Definitions */
igor_v	0:8ad47e2b6f00	490	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
igor_v	0:8ad47e2b6f00	491	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
igor_v	0:8ad47e2b6f00	492
igor_v	0:8ad47e2b6f00	493	/* SysTick Current Register Definitions */
igor_v	0:8ad47e2b6f00	494	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
igor_v	0:8ad47e2b6f00	495	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
igor_v	0:8ad47e2b6f00	496
igor_v	0:8ad47e2b6f00	497	/* SysTick Calibration Register Definitions */
igor_v	0:8ad47e2b6f00	498	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
igor_v	0:8ad47e2b6f00	499	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
igor_v	0:8ad47e2b6f00	500
igor_v	0:8ad47e2b6f00	501	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
igor_v	0:8ad47e2b6f00	502	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
igor_v	0:8ad47e2b6f00	503
igor_v	0:8ad47e2b6f00	504	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
igor_v	0:8ad47e2b6f00	505	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
igor_v	0:8ad47e2b6f00	506
igor_v	0:8ad47e2b6f00	507	/@} end of group CMSIS_SysTick /
igor_v	0:8ad47e2b6f00	508
igor_v	0:8ad47e2b6f00	509
igor_v	0:8ad47e2b6f00	510	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	511	\defgroup CMSIS_ITM CMSIS ITM
igor_v	0:8ad47e2b6f00	512	Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
igor_v	0:8ad47e2b6f00	513	@{
igor_v	0:8ad47e2b6f00	514	*/
igor_v	0:8ad47e2b6f00	515
igor_v	0:8ad47e2b6f00	516	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
igor_v	0:8ad47e2b6f00	517	*/
igor_v	0:8ad47e2b6f00	518	typedef struct
igor_v	0:8ad47e2b6f00	519	{
igor_v	0:8ad47e2b6f00	520	__O union
igor_v	0:8ad47e2b6f00	521	{
igor_v	0:8ad47e2b6f00	522	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
igor_v	0:8ad47e2b6f00	523	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
igor_v	0:8ad47e2b6f00	524	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
igor_v	0:8ad47e2b6f00	525	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
igor_v	0:8ad47e2b6f00	526	uint32_t RESERVED0[864];
igor_v	0:8ad47e2b6f00	527	__IO uint32_t TER; /!< Offset: (R/W) ITM Trace Enable Register /
igor_v	0:8ad47e2b6f00	528	uint32_t RESERVED1[15];
igor_v	0:8ad47e2b6f00	529	__IO uint32_t TPR; /!< Offset: (R/W) ITM Trace Privilege Register /
igor_v	0:8ad47e2b6f00	530	uint32_t RESERVED2[15];
igor_v	0:8ad47e2b6f00	531	__IO uint32_t TCR; /!< Offset: (R/W) ITM Trace Control Register /
igor_v	0:8ad47e2b6f00	532	uint32_t RESERVED3[29];
igor_v	0:8ad47e2b6f00	533	__IO uint32_t IWR; /!< Offset: (R/W) ITM Integration Write Register /
igor_v	0:8ad47e2b6f00	534	__IO uint32_t IRR; /!< Offset: (R/W) ITM Integration Read Register /
igor_v	0:8ad47e2b6f00	535	__IO uint32_t IMCR; /!< Offset: (R/W) ITM Integration Mode Control Register /
igor_v	0:8ad47e2b6f00	536	uint32_t RESERVED4[43];
igor_v	0:8ad47e2b6f00	537	__IO uint32_t LAR; /!< Offset: (R/W) ITM Lock Access Register /
igor_v	0:8ad47e2b6f00	538	__IO uint32_t LSR; /!< Offset: (R/W) ITM Lock Status Register /
igor_v	0:8ad47e2b6f00	539	uint32_t RESERVED5[6];
igor_v	0:8ad47e2b6f00	540	__I uint32_t PID4; /!< Offset: (R/ ) ITM Peripheral Identification Register #4 /
igor_v	0:8ad47e2b6f00	541	__I uint32_t PID5; /!< Offset: (R/ ) ITM Peripheral Identification Register #5 /
igor_v	0:8ad47e2b6f00	542	__I uint32_t PID6; /!< Offset: (R/ ) ITM Peripheral Identification Register #6 /
igor_v	0:8ad47e2b6f00	543	__I uint32_t PID7; /!< Offset: (R/ ) ITM Peripheral Identification Register #7 /
igor_v	0:8ad47e2b6f00	544	__I uint32_t PID0; /!< Offset: (R/ ) ITM Peripheral Identification Register #0 /
igor_v	0:8ad47e2b6f00	545	__I uint32_t PID1; /!< Offset: (R/ ) ITM Peripheral Identification Register #1 /
igor_v	0:8ad47e2b6f00	546	__I uint32_t PID2; /!< Offset: (R/ ) ITM Peripheral Identification Register #2 /
igor_v	0:8ad47e2b6f00	547	__I uint32_t PID3; /!< Offset: (R/ ) ITM Peripheral Identification Register #3 /
igor_v	0:8ad47e2b6f00	548	__I uint32_t CID0; /!< Offset: (R/ ) ITM Component Identification Register #0 /
igor_v	0:8ad47e2b6f00	549	__I uint32_t CID1; /!< Offset: (R/ ) ITM Component Identification Register #1 /
igor_v	0:8ad47e2b6f00	550	__I uint32_t CID2; /!< Offset: (R/ ) ITM Component Identification Register #2 /
igor_v	0:8ad47e2b6f00	551	__I uint32_t CID3; /!< Offset: (R/ ) ITM Component Identification Register #3 /
igor_v	0:8ad47e2b6f00	552	} ITM_Type;
igor_v	0:8ad47e2b6f00	553
igor_v	0:8ad47e2b6f00	554	/* ITM Trace Privilege Register Definitions */
igor_v	0:8ad47e2b6f00	555	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
igor_v	0:8ad47e2b6f00	556	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
igor_v	0:8ad47e2b6f00	557
igor_v	0:8ad47e2b6f00	558	/* ITM Trace Control Register Definitions */
igor_v	0:8ad47e2b6f00	559	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
igor_v	0:8ad47e2b6f00	560	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
igor_v	0:8ad47e2b6f00	561
igor_v	0:8ad47e2b6f00	562	#define ITM_TCR_ATBID_Pos 16 /!< ITM TCR: ATBID Position /
igor_v	0:8ad47e2b6f00	563	#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /!< ITM TCR: ATBID Mask /
igor_v	0:8ad47e2b6f00	564
igor_v	0:8ad47e2b6f00	565	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
igor_v	0:8ad47e2b6f00	566	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
igor_v	0:8ad47e2b6f00	567
igor_v	0:8ad47e2b6f00	568	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
igor_v	0:8ad47e2b6f00	569	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
igor_v	0:8ad47e2b6f00	570
igor_v	0:8ad47e2b6f00	571	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
igor_v	0:8ad47e2b6f00	572	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
igor_v	0:8ad47e2b6f00	573
igor_v	0:8ad47e2b6f00	574	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
igor_v	0:8ad47e2b6f00	575	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
igor_v	0:8ad47e2b6f00	576
igor_v	0:8ad47e2b6f00	577	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
igor_v	0:8ad47e2b6f00	578	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
igor_v	0:8ad47e2b6f00	579
igor_v	0:8ad47e2b6f00	580	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
igor_v	0:8ad47e2b6f00	581	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
igor_v	0:8ad47e2b6f00	582
igor_v	0:8ad47e2b6f00	583	/* ITM Integration Write Register Definitions */
igor_v	0:8ad47e2b6f00	584	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
igor_v	0:8ad47e2b6f00	585	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
igor_v	0:8ad47e2b6f00	586
igor_v	0:8ad47e2b6f00	587	/* ITM Integration Read Register Definitions */
igor_v	0:8ad47e2b6f00	588	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
igor_v	0:8ad47e2b6f00	589	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
igor_v	0:8ad47e2b6f00	590
igor_v	0:8ad47e2b6f00	591	/* ITM Integration Mode Control Register Definitions */
igor_v	0:8ad47e2b6f00	592	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
igor_v	0:8ad47e2b6f00	593	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
igor_v	0:8ad47e2b6f00	594
igor_v	0:8ad47e2b6f00	595	/* ITM Lock Status Register Definitions */
igor_v	0:8ad47e2b6f00	596	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
igor_v	0:8ad47e2b6f00	597	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
igor_v	0:8ad47e2b6f00	598
igor_v	0:8ad47e2b6f00	599	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
igor_v	0:8ad47e2b6f00	600	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
igor_v	0:8ad47e2b6f00	601
igor_v	0:8ad47e2b6f00	602	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
igor_v	0:8ad47e2b6f00	603	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
igor_v	0:8ad47e2b6f00	604
igor_v	0:8ad47e2b6f00	605	/@}/ /* end of group CMSIS_ITM */
igor_v	0:8ad47e2b6f00	606
igor_v	0:8ad47e2b6f00	607
igor_v	0:8ad47e2b6f00	608	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	609	\defgroup CMSIS_InterruptType CMSIS Interrupt Type
igor_v	0:8ad47e2b6f00	610	Type definitions for the Cortex-M Interrupt Type Register
igor_v	0:8ad47e2b6f00	611	@{
igor_v	0:8ad47e2b6f00	612	*/
igor_v	0:8ad47e2b6f00	613
igor_v	0:8ad47e2b6f00	614	/** \brief Structure type to access the Interrupt Type Register.
igor_v	0:8ad47e2b6f00	615	*/
igor_v	0:8ad47e2b6f00	616	typedef struct
igor_v	0:8ad47e2b6f00	617	{
igor_v	0:8ad47e2b6f00	618	uint32_t RESERVED0;
igor_v	0:8ad47e2b6f00	619	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Control Type Register /
igor_v	0:8ad47e2b6f00	620	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
igor_v	0:8ad47e2b6f00	621	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
igor_v	0:8ad47e2b6f00	622	#else
igor_v	0:8ad47e2b6f00	623	uint32_t RESERVED1;
igor_v	0:8ad47e2b6f00	624	#endif
igor_v	0:8ad47e2b6f00	625	} InterruptType_Type;
igor_v	0:8ad47e2b6f00	626
igor_v	0:8ad47e2b6f00	627	/* Interrupt Controller Type Register Definitions */
igor_v	0:8ad47e2b6f00	628	#define IntType_ICTR_INTLINESNUM_Pos 0 /!< InterruptType ICTR: INTLINESNUM Position /
igor_v	0:8ad47e2b6f00	629	#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /!< InterruptType ICTR: INTLINESNUM Mask /
igor_v	0:8ad47e2b6f00	630
igor_v	0:8ad47e2b6f00	631	/* Auxiliary Control Register Definitions */
igor_v	0:8ad47e2b6f00	632	#define IntType_ACTLR_DISFOLD_Pos 2 /!< InterruptType ACTLR: DISFOLD Position /
igor_v	0:8ad47e2b6f00	633	#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /!< InterruptType ACTLR: DISFOLD Mask /
igor_v	0:8ad47e2b6f00	634
igor_v	0:8ad47e2b6f00	635	#define IntType_ACTLR_DISDEFWBUF_Pos 1 /!< InterruptType ACTLR: DISDEFWBUF Position /
igor_v	0:8ad47e2b6f00	636	#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /!< InterruptType ACTLR: DISDEFWBUF Mask /
igor_v	0:8ad47e2b6f00	637
igor_v	0:8ad47e2b6f00	638	#define IntType_ACTLR_DISMCYCINT_Pos 0 /!< InterruptType ACTLR: DISMCYCINT Position /
igor_v	0:8ad47e2b6f00	639	#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /!< InterruptType ACTLR: DISMCYCINT Mask /
igor_v	0:8ad47e2b6f00	640
igor_v	0:8ad47e2b6f00	641	/@}/ /* end of group CMSIS_InterruptType */
igor_v	0:8ad47e2b6f00	642
igor_v	0:8ad47e2b6f00	643
igor_v	0:8ad47e2b6f00	644	#if (__MPU_PRESENT == 1)
igor_v	0:8ad47e2b6f00	645	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	646	\defgroup CMSIS_MPU CMSIS MPU
igor_v	0:8ad47e2b6f00	647	Type definitions for the Cortex-M Memory Protection Unit (MPU)
igor_v	0:8ad47e2b6f00	648	@{
igor_v	0:8ad47e2b6f00	649	*/
igor_v	0:8ad47e2b6f00	650
igor_v	0:8ad47e2b6f00	651	/** \brief Structure type to access the Memory Protection Unit (MPU).
igor_v	0:8ad47e2b6f00	652	*/
igor_v	0:8ad47e2b6f00	653	typedef struct
igor_v	0:8ad47e2b6f00	654	{
igor_v	0:8ad47e2b6f00	655	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
igor_v	0:8ad47e2b6f00	656	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
igor_v	0:8ad47e2b6f00	657	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
igor_v	0:8ad47e2b6f00	658	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
igor_v	0:8ad47e2b6f00	659	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
igor_v	0:8ad47e2b6f00	660	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
igor_v	0:8ad47e2b6f00	661	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
igor_v	0:8ad47e2b6f00	662	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
igor_v	0:8ad47e2b6f00	663	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
igor_v	0:8ad47e2b6f00	664	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
igor_v	0:8ad47e2b6f00	665	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
igor_v	0:8ad47e2b6f00	666	} MPU_Type;
igor_v	0:8ad47e2b6f00	667
igor_v	0:8ad47e2b6f00	668	/* MPU Type Register */
igor_v	0:8ad47e2b6f00	669	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
igor_v	0:8ad47e2b6f00	670	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
igor_v	0:8ad47e2b6f00	671
igor_v	0:8ad47e2b6f00	672	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
igor_v	0:8ad47e2b6f00	673	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
igor_v	0:8ad47e2b6f00	674
igor_v	0:8ad47e2b6f00	675	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
igor_v	0:8ad47e2b6f00	676	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
igor_v	0:8ad47e2b6f00	677
igor_v	0:8ad47e2b6f00	678	/* MPU Control Register */
igor_v	0:8ad47e2b6f00	679	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
igor_v	0:8ad47e2b6f00	680	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
igor_v	0:8ad47e2b6f00	681
igor_v	0:8ad47e2b6f00	682	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
igor_v	0:8ad47e2b6f00	683	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
igor_v	0:8ad47e2b6f00	684
igor_v	0:8ad47e2b6f00	685	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
igor_v	0:8ad47e2b6f00	686	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
igor_v	0:8ad47e2b6f00	687
igor_v	0:8ad47e2b6f00	688	/* MPU Region Number Register */
igor_v	0:8ad47e2b6f00	689	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
igor_v	0:8ad47e2b6f00	690	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
igor_v	0:8ad47e2b6f00	691
igor_v	0:8ad47e2b6f00	692	/* MPU Region Base Address Register */
igor_v	0:8ad47e2b6f00	693	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
igor_v	0:8ad47e2b6f00	694	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
igor_v	0:8ad47e2b6f00	695
igor_v	0:8ad47e2b6f00	696	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
igor_v	0:8ad47e2b6f00	697	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
igor_v	0:8ad47e2b6f00	698
igor_v	0:8ad47e2b6f00	699	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
igor_v	0:8ad47e2b6f00	700	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
igor_v	0:8ad47e2b6f00	701
igor_v	0:8ad47e2b6f00	702	/* MPU Region Attribute and Size Register */
igor_v	0:8ad47e2b6f00	703	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: XN Position /
igor_v	0:8ad47e2b6f00	704	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: XN Mask /
igor_v	0:8ad47e2b6f00	705
igor_v	0:8ad47e2b6f00	706	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: AP Position /
igor_v	0:8ad47e2b6f00	707	#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /!< MPU RASR: AP Mask /
igor_v	0:8ad47e2b6f00	708
igor_v	0:8ad47e2b6f00	709	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: TEX Position /
igor_v	0:8ad47e2b6f00	710	#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: TEX Mask /
igor_v	0:8ad47e2b6f00	711
igor_v	0:8ad47e2b6f00	712	#define MPU_RASR_S_Pos 18 /!< MPU RASR: Shareable bit Position /
igor_v	0:8ad47e2b6f00	713	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: Shareable bit Mask /
igor_v	0:8ad47e2b6f00	714
igor_v	0:8ad47e2b6f00	715	#define MPU_RASR_C_Pos 17 /!< MPU RASR: Cacheable bit Position /
igor_v	0:8ad47e2b6f00	716	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: Cacheable bit Mask /
igor_v	0:8ad47e2b6f00	717
igor_v	0:8ad47e2b6f00	718	#define MPU_RASR_B_Pos 16 /!< MPU RASR: Bufferable bit Position /
igor_v	0:8ad47e2b6f00	719	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: Bufferable bit Mask /
igor_v	0:8ad47e2b6f00	720
igor_v	0:8ad47e2b6f00	721	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
igor_v	0:8ad47e2b6f00	722	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
igor_v	0:8ad47e2b6f00	723
igor_v	0:8ad47e2b6f00	724	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
igor_v	0:8ad47e2b6f00	725	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
igor_v	0:8ad47e2b6f00	726
igor_v	0:8ad47e2b6f00	727	#define MPU_RASR_ENA_Pos 0 /!< MPU RASR: Region enable bit Position /
igor_v	0:8ad47e2b6f00	728	#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /!< MPU RASR: Region enable bit Disable Mask /
igor_v	0:8ad47e2b6f00	729
igor_v	0:8ad47e2b6f00	730	/@} end of group CMSIS_MPU /
igor_v	0:8ad47e2b6f00	731	#endif
igor_v	0:8ad47e2b6f00	732
igor_v	0:8ad47e2b6f00	733
igor_v	0:8ad47e2b6f00	734	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	735	\defgroup CMSIS_CoreDebug CMSIS Core Debug
igor_v	0:8ad47e2b6f00	736	Type definitions for the Cortex-M Core Debug Registers
igor_v	0:8ad47e2b6f00	737	@{
igor_v	0:8ad47e2b6f00	738	*/
igor_v	0:8ad47e2b6f00	739
igor_v	0:8ad47e2b6f00	740	/** \brief Structure type to access the Core Debug Register (CoreDebug).
igor_v	0:8ad47e2b6f00	741	*/
igor_v	0:8ad47e2b6f00	742	typedef struct
igor_v	0:8ad47e2b6f00	743	{
igor_v	0:8ad47e2b6f00	744	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
igor_v	0:8ad47e2b6f00	745	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
igor_v	0:8ad47e2b6f00	746	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
igor_v	0:8ad47e2b6f00	747	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
igor_v	0:8ad47e2b6f00	748	} CoreDebug_Type;
igor_v	0:8ad47e2b6f00	749
igor_v	0:8ad47e2b6f00	750	/* Debug Halting Control and Status Register */
igor_v	0:8ad47e2b6f00	751	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
igor_v	0:8ad47e2b6f00	752	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
igor_v	0:8ad47e2b6f00	753
igor_v	0:8ad47e2b6f00	754	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
igor_v	0:8ad47e2b6f00	755	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
igor_v	0:8ad47e2b6f00	756
igor_v	0:8ad47e2b6f00	757	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
igor_v	0:8ad47e2b6f00	758	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
igor_v	0:8ad47e2b6f00	759
igor_v	0:8ad47e2b6f00	760	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
igor_v	0:8ad47e2b6f00	761	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
igor_v	0:8ad47e2b6f00	762
igor_v	0:8ad47e2b6f00	763	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
igor_v	0:8ad47e2b6f00	764	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
igor_v	0:8ad47e2b6f00	765
igor_v	0:8ad47e2b6f00	766	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
igor_v	0:8ad47e2b6f00	767	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
igor_v	0:8ad47e2b6f00	768
igor_v	0:8ad47e2b6f00	769	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
igor_v	0:8ad47e2b6f00	770	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
igor_v	0:8ad47e2b6f00	771
igor_v	0:8ad47e2b6f00	772	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
igor_v	0:8ad47e2b6f00	773	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
igor_v	0:8ad47e2b6f00	774
igor_v	0:8ad47e2b6f00	775	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
igor_v	0:8ad47e2b6f00	776	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
igor_v	0:8ad47e2b6f00	777
igor_v	0:8ad47e2b6f00	778	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
igor_v	0:8ad47e2b6f00	779	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
igor_v	0:8ad47e2b6f00	780
igor_v	0:8ad47e2b6f00	781	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
igor_v	0:8ad47e2b6f00	782	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
igor_v	0:8ad47e2b6f00	783
igor_v	0:8ad47e2b6f00	784	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
igor_v	0:8ad47e2b6f00	785	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
igor_v	0:8ad47e2b6f00	786
igor_v	0:8ad47e2b6f00	787	/* Debug Core Register Selector Register */
igor_v	0:8ad47e2b6f00	788	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
igor_v	0:8ad47e2b6f00	789	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
igor_v	0:8ad47e2b6f00	790
igor_v	0:8ad47e2b6f00	791	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
igor_v	0:8ad47e2b6f00	792	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
igor_v	0:8ad47e2b6f00	793
igor_v	0:8ad47e2b6f00	794	/* Debug Exception and Monitor Control Register */
igor_v	0:8ad47e2b6f00	795	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
igor_v	0:8ad47e2b6f00	796	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
igor_v	0:8ad47e2b6f00	797
igor_v	0:8ad47e2b6f00	798	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
igor_v	0:8ad47e2b6f00	799	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
igor_v	0:8ad47e2b6f00	800
igor_v	0:8ad47e2b6f00	801	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
igor_v	0:8ad47e2b6f00	802	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
igor_v	0:8ad47e2b6f00	803
igor_v	0:8ad47e2b6f00	804	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
igor_v	0:8ad47e2b6f00	805	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
igor_v	0:8ad47e2b6f00	806
igor_v	0:8ad47e2b6f00	807	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
igor_v	0:8ad47e2b6f00	808	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
igor_v	0:8ad47e2b6f00	809
igor_v	0:8ad47e2b6f00	810	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
igor_v	0:8ad47e2b6f00	811	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
igor_v	0:8ad47e2b6f00	812
igor_v	0:8ad47e2b6f00	813	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
igor_v	0:8ad47e2b6f00	814	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
igor_v	0:8ad47e2b6f00	815
igor_v	0:8ad47e2b6f00	816	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
igor_v	0:8ad47e2b6f00	817	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
igor_v	0:8ad47e2b6f00	818
igor_v	0:8ad47e2b6f00	819	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
igor_v	0:8ad47e2b6f00	820	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
igor_v	0:8ad47e2b6f00	821
igor_v	0:8ad47e2b6f00	822	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
igor_v	0:8ad47e2b6f00	823	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
igor_v	0:8ad47e2b6f00	824
igor_v	0:8ad47e2b6f00	825	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
igor_v	0:8ad47e2b6f00	826	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
igor_v	0:8ad47e2b6f00	827
igor_v	0:8ad47e2b6f00	828	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
igor_v	0:8ad47e2b6f00	829	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
igor_v	0:8ad47e2b6f00	830
igor_v	0:8ad47e2b6f00	831	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
igor_v	0:8ad47e2b6f00	832	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
igor_v	0:8ad47e2b6f00	833
igor_v	0:8ad47e2b6f00	834	/@} end of group CMSIS_CoreDebug /
igor_v	0:8ad47e2b6f00	835
igor_v	0:8ad47e2b6f00	836
igor_v	0:8ad47e2b6f00	837	/** \ingroup CMSIS_core_register
igor_v	0:8ad47e2b6f00	838	@{
igor_v	0:8ad47e2b6f00	839	*/
igor_v	0:8ad47e2b6f00	840
igor_v	0:8ad47e2b6f00	841	/* Memory mapping of Cortex-M3 Hardware */
igor_v	0:8ad47e2b6f00	842	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
igor_v	0:8ad47e2b6f00	843	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
igor_v	0:8ad47e2b6f00	844	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
igor_v	0:8ad47e2b6f00	845	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
igor_v	0:8ad47e2b6f00	846	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
igor_v	0:8ad47e2b6f00	847	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
igor_v	0:8ad47e2b6f00	848
igor_v	0:8ad47e2b6f00	849	#define InterruptType ((InterruptType_Type ) SCS_BASE) /!< Interrupt Type Register */
igor_v	0:8ad47e2b6f00	850	#define SCB ((SCB_Type ) SCB_BASE) /!< SCB configuration struct */
igor_v	0:8ad47e2b6f00	851	#define SysTick ((SysTick_Type ) SysTick_BASE) /!< SysTick configuration struct */
igor_v	0:8ad47e2b6f00	852	#define NVIC ((NVIC_Type ) NVIC_BASE) /!< NVIC configuration struct */
igor_v	0:8ad47e2b6f00	853	#define ITM ((ITM_Type ) ITM_BASE) /!< ITM configuration struct */
igor_v	0:8ad47e2b6f00	854	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
igor_v	0:8ad47e2b6f00	855
igor_v	0:8ad47e2b6f00	856	#if (__MPU_PRESENT == 1)
igor_v	0:8ad47e2b6f00	857	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
igor_v	0:8ad47e2b6f00	858	#define MPU ((MPU_Type) MPU_BASE) /!< Memory Protection Unit */
igor_v	0:8ad47e2b6f00	859	#endif
igor_v	0:8ad47e2b6f00	860
igor_v	0:8ad47e2b6f00	861	/@} /
igor_v	0:8ad47e2b6f00	862
igor_v	0:8ad47e2b6f00	863
igor_v	0:8ad47e2b6f00	864
igor_v	0:8ad47e2b6f00	865	/*******************************************************************************
igor_v	0:8ad47e2b6f00	866	* Hardware Abstraction Layer
igor_v	0:8ad47e2b6f00	867	******************************************************************************/
igor_v	0:8ad47e2b6f00	868	/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
igor_v	0:8ad47e2b6f00	869	Core Function Interface contains:
igor_v	0:8ad47e2b6f00	870	- Core NVIC Functions
igor_v	0:8ad47e2b6f00	871	- Core SysTick Functions
igor_v	0:8ad47e2b6f00	872	- Core Debug Functions
igor_v	0:8ad47e2b6f00	873	- Core Register Access Functions
igor_v	0:8ad47e2b6f00	874	*/
igor_v	0:8ad47e2b6f00	875
igor_v	0:8ad47e2b6f00	876
igor_v	0:8ad47e2b6f00	877
igor_v	0:8ad47e2b6f00	878	/* ########################## NVIC functions #################################### */
igor_v	0:8ad47e2b6f00	879	/** \ingroup CMSIS_Core_FunctionInterface
igor_v	0:8ad47e2b6f00	880	\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
igor_v	0:8ad47e2b6f00	881	@{
igor_v	0:8ad47e2b6f00	882	*/
igor_v	0:8ad47e2b6f00	883
igor_v	0:8ad47e2b6f00	884	/** \brief Set Priority Grouping
igor_v	0:8ad47e2b6f00	885
igor_v	0:8ad47e2b6f00	886	This function sets the priority grouping field using the required unlock sequence.
igor_v	0:8ad47e2b6f00	887	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
igor_v	0:8ad47e2b6f00	888	Only values from 0..7 are used.
igor_v	0:8ad47e2b6f00	889	In case of a conflict between priority grouping and available
igor_v	0:8ad47e2b6f00	890	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
igor_v	0:8ad47e2b6f00	891
igor_v	0:8ad47e2b6f00	892	\param [in] PriorityGroup Priority grouping field
igor_v	0:8ad47e2b6f00	893	*/
igor_v	0:8ad47e2b6f00	894	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
igor_v	0:8ad47e2b6f00	895	{
igor_v	0:8ad47e2b6f00	896	uint32_t reg_value;
igor_v	0:8ad47e2b6f00	897	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	0:8ad47e2b6f00	898
igor_v	0:8ad47e2b6f00	899	reg_value = SCB->AIRCR; /* read old register configuration */
igor_v	0:8ad47e2b6f00	900	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
igor_v	0:8ad47e2b6f00	901	reg_value = (reg_value \|
igor_v	0:8ad47e2b6f00	902	(0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
igor_v	0:8ad47e2b6f00	903	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
igor_v	0:8ad47e2b6f00	904	SCB->AIRCR = reg_value;
igor_v	0:8ad47e2b6f00	905	}
igor_v	0:8ad47e2b6f00	906
igor_v	0:8ad47e2b6f00	907
igor_v	0:8ad47e2b6f00	908	/** \brief Get Priority Grouping
igor_v	0:8ad47e2b6f00	909
igor_v	0:8ad47e2b6f00	910	This function gets the priority grouping from NVIC Interrupt Controller.
igor_v	0:8ad47e2b6f00	911	Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
igor_v	0:8ad47e2b6f00	912
igor_v	0:8ad47e2b6f00	913	\return Priority grouping field
igor_v	0:8ad47e2b6f00	914	*/
igor_v	0:8ad47e2b6f00	915	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
igor_v	0:8ad47e2b6f00	916	{
igor_v	0:8ad47e2b6f00	917	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
igor_v	0:8ad47e2b6f00	918	}
igor_v	0:8ad47e2b6f00	919
igor_v	0:8ad47e2b6f00	920
igor_v	0:8ad47e2b6f00	921	/** \brief Enable External Interrupt
igor_v	0:8ad47e2b6f00	922
igor_v	0:8ad47e2b6f00	923	This function enables a device specific interupt in the NVIC interrupt controller.
igor_v	0:8ad47e2b6f00	924	The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	925
igor_v	0:8ad47e2b6f00	926	\param [in] IRQn Number of the external interrupt to enable
igor_v	0:8ad47e2b6f00	927	*/
igor_v	0:8ad47e2b6f00	928	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	929	{
igor_v	0:8ad47e2b6f00	930	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
igor_v	0:8ad47e2b6f00	931	}
igor_v	0:8ad47e2b6f00	932
igor_v	0:8ad47e2b6f00	933
igor_v	0:8ad47e2b6f00	934	/** \brief Disable External Interrupt
igor_v	0:8ad47e2b6f00	935
igor_v	0:8ad47e2b6f00	936	This function disables a device specific interupt in the NVIC interrupt controller.
igor_v	0:8ad47e2b6f00	937	The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	938
igor_v	0:8ad47e2b6f00	939	\param [in] IRQn Number of the external interrupt to disable
igor_v	0:8ad47e2b6f00	940	*/
igor_v	0:8ad47e2b6f00	941	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	942	{
igor_v	0:8ad47e2b6f00	943	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
igor_v	0:8ad47e2b6f00	944	}
igor_v	0:8ad47e2b6f00	945
igor_v	0:8ad47e2b6f00	946
igor_v	0:8ad47e2b6f00	947	/** \brief Get Pending Interrupt
igor_v	0:8ad47e2b6f00	948
igor_v	0:8ad47e2b6f00	949	This function reads the pending register in the NVIC and returns the pending bit
igor_v	0:8ad47e2b6f00	950	for the specified interrupt.
igor_v	0:8ad47e2b6f00	951
igor_v	0:8ad47e2b6f00	952	\param [in] IRQn Number of the interrupt for get pending
igor_v	0:8ad47e2b6f00	953	\return 0 Interrupt status is not pending
igor_v	0:8ad47e2b6f00	954	\return 1 Interrupt status is pending
igor_v	0:8ad47e2b6f00	955	*/
igor_v	0:8ad47e2b6f00	956	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	957	{
igor_v	0:8ad47e2b6f00	958	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
igor_v	0:8ad47e2b6f00	959	}
igor_v	0:8ad47e2b6f00	960
igor_v	0:8ad47e2b6f00	961
igor_v	0:8ad47e2b6f00	962	/** \brief Set Pending Interrupt
igor_v	0:8ad47e2b6f00	963
igor_v	0:8ad47e2b6f00	964	This function sets the pending bit for the specified interrupt.
igor_v	0:8ad47e2b6f00	965	The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	966
igor_v	0:8ad47e2b6f00	967	\param [in] IRQn Number of the interrupt for set pending
igor_v	0:8ad47e2b6f00	968	*/
igor_v	0:8ad47e2b6f00	969	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	970	{
igor_v	0:8ad47e2b6f00	971	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
igor_v	0:8ad47e2b6f00	972	}
igor_v	0:8ad47e2b6f00	973
igor_v	0:8ad47e2b6f00	974
igor_v	0:8ad47e2b6f00	975	/** \brief Clear Pending Interrupt
igor_v	0:8ad47e2b6f00	976
igor_v	0:8ad47e2b6f00	977	This function clears the pending bit for the specified interrupt.
igor_v	0:8ad47e2b6f00	978	The interrupt number cannot be a negative value.
igor_v	0:8ad47e2b6f00	979
igor_v	0:8ad47e2b6f00	980	\param [in] IRQn Number of the interrupt for clear pending
igor_v	0:8ad47e2b6f00	981	*/
igor_v	0:8ad47e2b6f00	982	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	983	{
igor_v	0:8ad47e2b6f00	984	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
igor_v	0:8ad47e2b6f00	985	}
igor_v	0:8ad47e2b6f00	986
igor_v	0:8ad47e2b6f00	987
igor_v	0:8ad47e2b6f00	988	/** \brief Get Active Interrupt
igor_v	0:8ad47e2b6f00	989
igor_v	0:8ad47e2b6f00	990	This function reads the active register in NVIC and returns the active bit.
igor_v	0:8ad47e2b6f00	991	\param [in] IRQn Number of the interrupt for get active
igor_v	0:8ad47e2b6f00	992	\return 0 Interrupt status is not active
igor_v	0:8ad47e2b6f00	993	\return 1 Interrupt status is active
igor_v	0:8ad47e2b6f00	994	*/
igor_v	0:8ad47e2b6f00	995	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	996	{
igor_v	0:8ad47e2b6f00	997	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
igor_v	0:8ad47e2b6f00	998	}
igor_v	0:8ad47e2b6f00	999
igor_v	0:8ad47e2b6f00	1000
igor_v	0:8ad47e2b6f00	1001	/** \brief Set Interrupt Priority
igor_v	0:8ad47e2b6f00	1002
igor_v	0:8ad47e2b6f00	1003	This function sets the priority for the specified interrupt. The interrupt
igor_v	0:8ad47e2b6f00	1004	number can be positive to specify an external (device specific)
igor_v	0:8ad47e2b6f00	1005	interrupt, or negative to specify an internal (core) interrupt.
igor_v	0:8ad47e2b6f00	1006
igor_v	0:8ad47e2b6f00	1007	Note: The priority cannot be set for every core interrupt.
igor_v	0:8ad47e2b6f00	1008
igor_v	0:8ad47e2b6f00	1009	\param [in] IRQn Number of the interrupt for set priority
igor_v	0:8ad47e2b6f00	1010	\param [in] priority Priority to set
igor_v	0:8ad47e2b6f00	1011	*/
igor_v	0:8ad47e2b6f00	1012	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
igor_v	0:8ad47e2b6f00	1013	{
igor_v	0:8ad47e2b6f00	1014	if(IRQn < 0)
igor_v	0:8ad47e2b6f00	1015	{
igor_v	0:8ad47e2b6f00	1016	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
igor_v	0:8ad47e2b6f00	1017	} /* set Priority for Cortex-M System Interrupts */
igor_v	0:8ad47e2b6f00	1018	else
igor_v	0:8ad47e2b6f00	1019	{
igor_v	0:8ad47e2b6f00	1020	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
igor_v	0:8ad47e2b6f00	1021	} /* set Priority for device specific Interrupts */
igor_v	0:8ad47e2b6f00	1022	}
igor_v	0:8ad47e2b6f00	1023
igor_v	0:8ad47e2b6f00	1024
igor_v	0:8ad47e2b6f00	1025	/** \brief Get Interrupt Priority
igor_v	0:8ad47e2b6f00	1026
igor_v	0:8ad47e2b6f00	1027	This function reads the priority for the specified interrupt. The interrupt
igor_v	0:8ad47e2b6f00	1028	number can be positive to specify an external (device specific)
igor_v	0:8ad47e2b6f00	1029	interrupt, or negative to specify an internal (core) interrupt.
igor_v	0:8ad47e2b6f00	1030
igor_v	0:8ad47e2b6f00	1031	The returned priority value is automatically aligned to the implemented
igor_v	0:8ad47e2b6f00	1032	priority bits of the microcontroller.
igor_v	0:8ad47e2b6f00	1033
igor_v	0:8ad47e2b6f00	1034	\param [in] IRQn Number of the interrupt for get priority
igor_v	0:8ad47e2b6f00	1035	\return Interrupt Priority
igor_v	0:8ad47e2b6f00	1036	*/
igor_v	0:8ad47e2b6f00	1037	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
igor_v	0:8ad47e2b6f00	1038	{
igor_v	0:8ad47e2b6f00	1039
igor_v	0:8ad47e2b6f00	1040	if(IRQn < 0) {
igor_v	0:8ad47e2b6f00	1041	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
igor_v	0:8ad47e2b6f00	1042	else {
igor_v	0:8ad47e2b6f00	1043	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
igor_v	0:8ad47e2b6f00	1044	}
igor_v	0:8ad47e2b6f00	1045
igor_v	0:8ad47e2b6f00	1046
igor_v	0:8ad47e2b6f00	1047	/** \brief Encode Priority
igor_v	0:8ad47e2b6f00	1048
igor_v	0:8ad47e2b6f00	1049	This function encodes the priority for an interrupt with the given priority group,
igor_v	0:8ad47e2b6f00	1050	preemptive priority value and sub priority value.
igor_v	0:8ad47e2b6f00	1051	In case of a conflict between priority grouping and available
igor_v	0:8ad47e2b6f00	1052	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
igor_v	0:8ad47e2b6f00	1053
igor_v	0:8ad47e2b6f00	1054	The returned priority value can be used for NVIC_SetPriority(...) function
igor_v	0:8ad47e2b6f00	1055
igor_v	0:8ad47e2b6f00	1056	\param [in] PriorityGroup Used priority group
igor_v	0:8ad47e2b6f00	1057	\param [in] PreemptPriority Preemptive priority value (starting from 0)
igor_v	0:8ad47e2b6f00	1058	\param [in] SubPriority Sub priority value (starting from 0)
igor_v	0:8ad47e2b6f00	1059	\return Encoded priority for the interrupt
igor_v	0:8ad47e2b6f00	1060	*/
igor_v	0:8ad47e2b6f00	1061	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
igor_v	0:8ad47e2b6f00	1062	{
igor_v	0:8ad47e2b6f00	1063	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	0:8ad47e2b6f00	1064	uint32_t PreemptPriorityBits;
igor_v	0:8ad47e2b6f00	1065	uint32_t SubPriorityBits;
igor_v	0:8ad47e2b6f00	1066
igor_v	0:8ad47e2b6f00	1067	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
igor_v	0:8ad47e2b6f00	1068	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
igor_v	0:8ad47e2b6f00	1069
igor_v	0:8ad47e2b6f00	1070	return (
igor_v	0:8ad47e2b6f00	1071	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
igor_v	0:8ad47e2b6f00	1072	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
igor_v	0:8ad47e2b6f00	1073	);
igor_v	0:8ad47e2b6f00	1074	}
igor_v	0:8ad47e2b6f00	1075
igor_v	0:8ad47e2b6f00	1076
igor_v	0:8ad47e2b6f00	1077	/** \brief Decode Priority
igor_v	0:8ad47e2b6f00	1078
igor_v	0:8ad47e2b6f00	1079	This function decodes an interrupt priority value with the given priority group to
igor_v	0:8ad47e2b6f00	1080	preemptive priority value and sub priority value.
igor_v	0:8ad47e2b6f00	1081	In case of a conflict between priority grouping and available
igor_v	0:8ad47e2b6f00	1082	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
igor_v	0:8ad47e2b6f00	1083
igor_v	0:8ad47e2b6f00	1084	The priority value can be retrieved with NVIC_GetPriority(...) function
igor_v	0:8ad47e2b6f00	1085
igor_v	0:8ad47e2b6f00	1086	\param [in] Priority Priority value
igor_v	0:8ad47e2b6f00	1087	\param [in] PriorityGroup Used priority group
igor_v	0:8ad47e2b6f00	1088	\param [out] pPreemptPriority Preemptive priority value (starting from 0)
igor_v	0:8ad47e2b6f00	1089	\param [out] pSubPriority Sub priority value (starting from 0)
igor_v	0:8ad47e2b6f00	1090	*/
igor_v	0:8ad47e2b6f00	1091	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
igor_v	0:8ad47e2b6f00	1092	{
igor_v	0:8ad47e2b6f00	1093	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
igor_v	0:8ad47e2b6f00	1094	uint32_t PreemptPriorityBits;
igor_v	0:8ad47e2b6f00	1095	uint32_t SubPriorityBits;
igor_v	0:8ad47e2b6f00	1096
igor_v	0:8ad47e2b6f00	1097	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
igor_v	0:8ad47e2b6f00	1098	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
igor_v	0:8ad47e2b6f00	1099
igor_v	0:8ad47e2b6f00	1100	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
igor_v	0:8ad47e2b6f00	1101	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
igor_v	0:8ad47e2b6f00	1102	}
igor_v	0:8ad47e2b6f00	1103
igor_v	0:8ad47e2b6f00	1104
igor_v	0:8ad47e2b6f00	1105	/** \brief System Reset
igor_v	0:8ad47e2b6f00	1106
igor_v	0:8ad47e2b6f00	1107	This function initiate a system reset request to reset the MCU.
igor_v	0:8ad47e2b6f00	1108	*/
igor_v	0:8ad47e2b6f00	1109	static __INLINE void NVIC_SystemReset(void)
igor_v	0:8ad47e2b6f00	1110	{
igor_v	0:8ad47e2b6f00	1111	__DSB(); /* Ensure all outstanding memory accesses included
igor_v	0:8ad47e2b6f00	1112	buffered write are completed before reset */
igor_v	0:8ad47e2b6f00	1113	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
igor_v	0:8ad47e2b6f00	1114	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
igor_v	0:8ad47e2b6f00	1115	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
igor_v	0:8ad47e2b6f00	1116	__DSB(); /* Ensure completion of memory access */
igor_v	0:8ad47e2b6f00	1117	while(1); /* wait until reset */
igor_v	0:8ad47e2b6f00	1118	}
igor_v	0:8ad47e2b6f00	1119
igor_v	0:8ad47e2b6f00	1120	/@} end of CMSIS_Core_NVICFunctions /
igor_v	0:8ad47e2b6f00	1121
igor_v	0:8ad47e2b6f00	1122
igor_v	0:8ad47e2b6f00	1123
igor_v	0:8ad47e2b6f00	1124	/* ################################## SysTick function ############################################ */
igor_v	0:8ad47e2b6f00	1125	/** \ingroup CMSIS_Core_FunctionInterface
igor_v	0:8ad47e2b6f00	1126	\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
igor_v	0:8ad47e2b6f00	1127	@{
igor_v	0:8ad47e2b6f00	1128	*/
igor_v	0:8ad47e2b6f00	1129
igor_v	0:8ad47e2b6f00	1130	#if (__Vendor_SysTickConfig == 0)
igor_v	0:8ad47e2b6f00	1131
igor_v	0:8ad47e2b6f00	1132	/** \brief System Tick Configuration
igor_v	0:8ad47e2b6f00	1133
igor_v	0:8ad47e2b6f00	1134	This function initialises the system tick timer and its interrupt and start the system tick timer.
igor_v	0:8ad47e2b6f00	1135	Counter is in free running mode to generate periodical interrupts.
igor_v	0:8ad47e2b6f00	1136
igor_v	0:8ad47e2b6f00	1137	\param [in] ticks Number of ticks between two interrupts
igor_v	0:8ad47e2b6f00	1138	\return 0 Function succeeded
igor_v	0:8ad47e2b6f00	1139	\return 1 Function failed
igor_v	0:8ad47e2b6f00	1140	*/
igor_v	0:8ad47e2b6f00	1141	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
igor_v	0:8ad47e2b6f00	1142	{
igor_v	0:8ad47e2b6f00	1143	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
igor_v	0:8ad47e2b6f00	1144
igor_v	0:8ad47e2b6f00	1145	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
igor_v	0:8ad47e2b6f00	1146	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
igor_v	0:8ad47e2b6f00	1147	SysTick->VAL = 0; /* Load the SysTick Counter Value */
igor_v	0:8ad47e2b6f00	1148	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
igor_v	0:8ad47e2b6f00	1149	SysTick_CTRL_TICKINT_Msk \|
igor_v	0:8ad47e2b6f00	1150	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
igor_v	0:8ad47e2b6f00	1151	return (0); /* Function successful */
igor_v	0:8ad47e2b6f00	1152	}
igor_v	0:8ad47e2b6f00	1153
igor_v	0:8ad47e2b6f00	1154	#endif
igor_v	0:8ad47e2b6f00	1155
igor_v	0:8ad47e2b6f00	1156	/@} end of CMSIS_Core_SysTickFunctions /
igor_v	0:8ad47e2b6f00	1157
igor_v	0:8ad47e2b6f00	1158
igor_v	0:8ad47e2b6f00	1159
igor_v	0:8ad47e2b6f00	1160	/* ##################################### Debug In/Output function ########################################### */
igor_v	0:8ad47e2b6f00	1161	/** \ingroup CMSIS_Core_FunctionInterface
igor_v	0:8ad47e2b6f00	1162	\defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
igor_v	0:8ad47e2b6f00	1163	@{
igor_v	0:8ad47e2b6f00	1164	*/
igor_v	0:8ad47e2b6f00	1165
igor_v	0:8ad47e2b6f00	1166	extern volatile int32_t ITM_RxBuffer; /!< external variable to receive characters /
igor_v	0:8ad47e2b6f00	1167	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< value identifying ITM_RxBuffer is ready for next character /
igor_v	0:8ad47e2b6f00	1168
igor_v	0:8ad47e2b6f00	1169
igor_v	0:8ad47e2b6f00	1170	/** \brief ITM Send Character
igor_v	0:8ad47e2b6f00	1171
igor_v	0:8ad47e2b6f00	1172	This function transmits a character via the ITM channel 0.
igor_v	0:8ad47e2b6f00	1173	It just returns when no debugger is connected that has booked the output.
igor_v	0:8ad47e2b6f00	1174	It is blocking when a debugger is connected, but the previous character send is not transmitted.
igor_v	0:8ad47e2b6f00	1175
igor_v	0:8ad47e2b6f00	1176	\param [in] ch Character to transmit
igor_v	0:8ad47e2b6f00	1177	\return Character to transmit
igor_v	0:8ad47e2b6f00	1178	*/
igor_v	0:8ad47e2b6f00	1179	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
igor_v	0:8ad47e2b6f00	1180	{
igor_v	0:8ad47e2b6f00	1181	if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
igor_v	0:8ad47e2b6f00	1182	(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
igor_v	0:8ad47e2b6f00	1183	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
igor_v	0:8ad47e2b6f00	1184	{
igor_v	0:8ad47e2b6f00	1185	while (ITM->PORT[0].u32 == 0);
igor_v	0:8ad47e2b6f00	1186	ITM->PORT[0].u8 = (uint8_t) ch;
igor_v	0:8ad47e2b6f00	1187	}
igor_v	0:8ad47e2b6f00	1188	return (ch);
igor_v	0:8ad47e2b6f00	1189	}
igor_v	0:8ad47e2b6f00	1190
igor_v	0:8ad47e2b6f00	1191
igor_v	0:8ad47e2b6f00	1192	/** \brief ITM Receive Character
igor_v	0:8ad47e2b6f00	1193
igor_v	0:8ad47e2b6f00	1194	This function inputs a character via external variable ITM_RxBuffer.
igor_v	0:8ad47e2b6f00	1195	It just returns when no debugger is connected that has booked the output.
igor_v	0:8ad47e2b6f00	1196	It is blocking when a debugger is connected, but the previous character send is not transmitted.
igor_v	0:8ad47e2b6f00	1197
igor_v	0:8ad47e2b6f00	1198	\return Received character
igor_v	0:8ad47e2b6f00	1199	\return -1 No character received
igor_v	0:8ad47e2b6f00	1200	*/
igor_v	0:8ad47e2b6f00	1201	static __INLINE int32_t ITM_ReceiveChar (void) {
igor_v	0:8ad47e2b6f00	1202	int32_t ch = -1; /* no character available */
igor_v	0:8ad47e2b6f00	1203
igor_v	0:8ad47e2b6f00	1204	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
igor_v	0:8ad47e2b6f00	1205	ch = ITM_RxBuffer;
igor_v	0:8ad47e2b6f00	1206	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
igor_v	0:8ad47e2b6f00	1207	}
igor_v	0:8ad47e2b6f00	1208
igor_v	0:8ad47e2b6f00	1209	return (ch);
igor_v	0:8ad47e2b6f00	1210	}
igor_v	0:8ad47e2b6f00	1211
igor_v	0:8ad47e2b6f00	1212
igor_v	0:8ad47e2b6f00	1213	/** \brief ITM Check Character
igor_v	0:8ad47e2b6f00	1214
igor_v	0:8ad47e2b6f00	1215	This function checks external variable ITM_RxBuffer whether a character is available or not.
igor_v	0:8ad47e2b6f00	1216	It returns '1' if a character is available and '0' if no character is available.
igor_v	0:8ad47e2b6f00	1217
igor_v	0:8ad47e2b6f00	1218	\return 0 No character available
igor_v	0:8ad47e2b6f00	1219	\return 1 Character available
igor_v	0:8ad47e2b6f00	1220	*/
igor_v	0:8ad47e2b6f00	1221	static __INLINE int32_t ITM_CheckChar (void) {
igor_v	0:8ad47e2b6f00	1222
igor_v	0:8ad47e2b6f00	1223	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
igor_v	0:8ad47e2b6f00	1224	return (0); /* no character available */
igor_v	0:8ad47e2b6f00	1225	} else {
igor_v	0:8ad47e2b6f00	1226	return (1); /* character available */
igor_v	0:8ad47e2b6f00	1227	}
igor_v	0:8ad47e2b6f00	1228	}
igor_v	0:8ad47e2b6f00	1229
igor_v	0:8ad47e2b6f00	1230	/@} end of CMSIS_core_DebugFunctions /
igor_v	0:8ad47e2b6f00	1231
igor_v	0:8ad47e2b6f00	1232	#endif /* __CORE_CM3_H_DEPENDANT */
igor_v	0:8ad47e2b6f00	1233
igor_v	0:8ad47e2b6f00	1234	#endif /* __CMSIS_GENERIC */
igor_v	0:8ad47e2b6f00	1235
igor_v	0:8ad47e2b6f00	1236	#ifdef __cplusplus
igor_v	0:8ad47e2b6f00	1237	}
igor_v	0:8ad47e2b6f00	1238	#endif
igor_v	0:8ad47e2b6f00	1239
igor_v	0:8ad47e2b6f00	1240	/lint -restore /
igor_v	0:8ad47e2b6f00	1241

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	20 Oct 2016
Imports:	4
Forks:	1
Commits:	220
Dependents:	0
Dependencies:	1
Followers:	1

core_cm3.h@0:8ad47e2b6f00, 2016-01-30 (annotated)

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