Martin Kojtal / mbed-dev

forked

targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 mbed port to NXP LPC43xx
<> 144:ef7eb2e8f9f7 2 ========================
<> 144:ef7eb2e8f9f7 3 Updated: 07/11/14
<> 144:ef7eb2e8f9f7 4
<> 144:ef7eb2e8f9f7 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
<> 144:ef7eb2e8f9f7 6 microcontroller package. This port allows mbed developers to take advantage
<> 144:ef7eb2e8f9f7 7 of the LPC43xx in their application using APIs that they are familiar with.
<> 144:ef7eb2e8f9f7 8 Some of the key features of the LPC43xx include:
<> 144:ef7eb2e8f9f7 9
<> 144:ef7eb2e8f9f7 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
<> 144:ef7eb2e8f9f7 11 * Up to 264 KB SRAM, 1 MB internal flash
<> 144:ef7eb2e8f9f7 12 * Two High-speed USB 2.0 interfaces
<> 144:ef7eb2e8f9f7 13 * Ethernet MAC
<> 144:ef7eb2e8f9f7 14 * LCD interface
<> 144:ef7eb2e8f9f7 15 * Quad-SPI Flash Interface (SPIFI)
<> 144:ef7eb2e8f9f7 16 * State Configurable Timer (SCT)
<> 144:ef7eb2e8f9f7 17 * Serial GPIO (SGPIO)
<> 144:ef7eb2e8f9f7 18 * Up to 164 GPIO
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
<> 144:ef7eb2e8f9f7 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 Compatibility
<> 144:ef7eb2e8f9f7 26 -------------
<> 144:ef7eb2e8f9f7 27 * This port has been tested with the following boards:
<> 144:ef7eb2e8f9f7 28 Board MCU RAM/Flash
<> 144:ef7eb2e8f9f7 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
<> 144:ef7eb2e8f9f7 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
<> 144:ef7eb2e8f9f7 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
<> 144:ef7eb2e8f9f7 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
<> 144:ef7eb2e8f9f7 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
<> 144:ef7eb2e8f9f7 36 for flash programming.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
<> 144:ef7eb2e8f9f7 39 codebase. The core declaration specifies the binaries to be built:
<> 144:ef7eb2e8f9f7 40 mbed define CMSIS define MCU Target
<> 144:ef7eb2e8f9f7 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
<> 144:ef7eb2e8f9f7 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
<> 144:ef7eb2e8f9f7 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
<> 144:ef7eb2e8f9f7 44 These MCUs all share the peripheral IP, common driver code is feasible.
<> 144:ef7eb2e8f9f7 45 Yet each variant can have different memory segments, peripherals, etc.
<> 144:ef7eb2e8f9f7 46 Plus, each board design can integrate different external peripherals
<> 144:ef7eb2e8f9f7 47 or interfaces. A future release of the mbed SDK and its build tools will
<> 144:ef7eb2e8f9f7 48 support specifying the target board when building binaries. At this time
<> 144:ef7eb2e8f9f7 49 building binaries for different targets requires an external project or
<> 144:ef7eb2e8f9f7 50 Makefile.
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 * No testing has been done with LPC18xx hardware.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 Notes
<> 144:ef7eb2e8f9f7 55 -----
<> 144:ef7eb2e8f9f7 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
<> 144:ef7eb2e8f9f7 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
<> 144:ef7eb2e8f9f7 58 the pin identifier encodes the offsets. Macros are used for decoding.
<> 144:ef7eb2e8f9f7 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
<> 144:ef7eb2e8f9f7 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 * Pin names use multiple aliases to support Arduino naming conventions as well
<> 144:ef7eb2e8f9f7 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
<> 144:ef7eb2e8f9f7 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
<> 144:ef7eb2e8f9f7 69 See the board pinout graphic and the PinNames.h for available aliases.
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
<> 144:ef7eb2e8f9f7 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
<> 144:ef7eb2e8f9f7 73 pin can only interrupt on the rising or falling edge, not both as required
<> 144:ef7eb2e8f9f7 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
<> 144:ef7eb2e8f9f7 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
<> 144:ef7eb2e8f9f7 76 A future implementation may provide group interrupt support.
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
<> 144:ef7eb2e8f9f7 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
<> 144:ef7eb2e8f9f7 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
<> 144:ef7eb2e8f9f7 81 when building the library.