Martin Kojtal / mbed-dev

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targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 mbed port to NXP LPC43xx
bogdanm 0:9b334a45a8ff 2 ========================
bogdanm 0:9b334a45a8ff 3 Updated: 07/11/14
bogdanm 0:9b334a45a8ff 4
bogdanm 0:9b334a45a8ff 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
bogdanm 0:9b334a45a8ff 6 microcontroller package. This port allows mbed developers to take advantage
bogdanm 0:9b334a45a8ff 7 of the LPC43xx in their application using APIs that they are familiar with.
bogdanm 0:9b334a45a8ff 8 Some of the key features of the LPC43xx include:
bogdanm 0:9b334a45a8ff 9
bogdanm 0:9b334a45a8ff 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
bogdanm 0:9b334a45a8ff 11 * Up to 264 KB SRAM, 1 MB internal flash
bogdanm 0:9b334a45a8ff 12 * Two High-speed USB 2.0 interfaces
bogdanm 0:9b334a45a8ff 13 * Ethernet MAC
bogdanm 0:9b334a45a8ff 14 * LCD interface
bogdanm 0:9b334a45a8ff 15 * Quad-SPI Flash Interface (SPIFI)
bogdanm 0:9b334a45a8ff 16 * State Configurable Timer (SCT)
bogdanm 0:9b334a45a8ff 17 * Serial GPIO (SGPIO)
bogdanm 0:9b334a45a8ff 18 * Up to 164 GPIO
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
bogdanm 0:9b334a45a8ff 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 Compatibility
bogdanm 0:9b334a45a8ff 26 -------------
bogdanm 0:9b334a45a8ff 27 * This port has been tested with the following boards:
bogdanm 0:9b334a45a8ff 28 Board MCU RAM/Flash
bogdanm 0:9b334a45a8ff 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
bogdanm 0:9b334a45a8ff 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
bogdanm 0:9b334a45a8ff 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
bogdanm 0:9b334a45a8ff 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
bogdanm 0:9b334a45a8ff 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
bogdanm 0:9b334a45a8ff 36 for flash programming.
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
bogdanm 0:9b334a45a8ff 39 codebase. The core declaration specifies the binaries to be built:
bogdanm 0:9b334a45a8ff 40 mbed define CMSIS define MCU Target
bogdanm 0:9b334a45a8ff 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
bogdanm 0:9b334a45a8ff 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
bogdanm 0:9b334a45a8ff 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
bogdanm 0:9b334a45a8ff 44 These MCUs all share the peripheral IP, common driver code is feasible.
bogdanm 0:9b334a45a8ff 45 Yet each variant can have different memory segments, peripherals, etc.
bogdanm 0:9b334a45a8ff 46 Plus, each board design can integrate different external peripherals
bogdanm 0:9b334a45a8ff 47 or interfaces. A future release of the mbed SDK and its build tools will
bogdanm 0:9b334a45a8ff 48 support specifying the target board when building binaries. At this time
bogdanm 0:9b334a45a8ff 49 building binaries for different targets requires an external project or
bogdanm 0:9b334a45a8ff 50 Makefile.
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 * No testing has been done with LPC18xx hardware.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 Notes
bogdanm 0:9b334a45a8ff 55 -----
bogdanm 0:9b334a45a8ff 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
bogdanm 0:9b334a45a8ff 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
bogdanm 0:9b334a45a8ff 58 the pin identifier encodes the offsets. Macros are used for decoding.
bogdanm 0:9b334a45a8ff 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
bogdanm 0:9b334a45a8ff 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 * Pin names use multiple aliases to support Arduino naming conventions as well
bogdanm 0:9b334a45a8ff 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
bogdanm 0:9b334a45a8ff 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
bogdanm 0:9b334a45a8ff 69 See the board pinout graphic and the PinNames.h for available aliases.
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
bogdanm 0:9b334a45a8ff 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
bogdanm 0:9b334a45a8ff 73 pin can only interrupt on the rising or falling edge, not both as required
bogdanm 0:9b334a45a8ff 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
bogdanm 0:9b334a45a8ff 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
bogdanm 0:9b334a45a8ff 76 A future implementation may provide group interrupt support.
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
bogdanm 0:9b334a45a8ff 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
bogdanm 0:9b334a45a8ff 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
bogdanm 0:9b334a45a8ff 81 when building the library.