nRF51822 - Nordic stack and drivers for the mbed BLE API. Ve…

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Nordic stack and drivers for the mbed BLE API. Version to work around build bug.

Dependents: microbit_rubber_ducky microbit_mouse_BLE microbit_mouse_BLE_daybreak_version microbit_presenter

Fork of nRF51822 by Nordic Semiconductor

source/nordic_sdk/components/device/nrf51.h@616:b52326e38ebd, 2016-08-31 (annotated)

Committer:: JonnyA
Date:: Wed Aug 31 18:59:36 2016 +0000
Revision:: 616:b52326e38ebd
Parent:: 607:e98331f1d6b5

Workaround for build system bug

Who changed what in which revision?

User	Revision	Line number	New contents of line
vcoubard	607:e98331f1d6b5	1	/*
vcoubard	607:e98331f1d6b5	2	* Copyright (c) Nordic Semiconductor ASA
vcoubard	607:e98331f1d6b5	3	* All rights reserved.
vcoubard	607:e98331f1d6b5	4	*
vcoubard	607:e98331f1d6b5	5	* Redistribution and use in source and binary forms, with or without modification,
vcoubard	607:e98331f1d6b5	6	* are permitted provided that the following conditions are met:
vcoubard	607:e98331f1d6b5	7	*
vcoubard	607:e98331f1d6b5	8	* 1. Redistributions of source code must retain the above copyright notice, this
vcoubard	607:e98331f1d6b5	9	* list of conditions and the following disclaimer.
vcoubard	607:e98331f1d6b5	10	*
vcoubard	607:e98331f1d6b5	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
vcoubard	607:e98331f1d6b5	12	* list of conditions and the following disclaimer in the documentation and/or
vcoubard	607:e98331f1d6b5	13	* other materials provided with the distribution.
vcoubard	607:e98331f1d6b5	14	*
vcoubard	607:e98331f1d6b5	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
vcoubard	607:e98331f1d6b5	16	* contributors to this software may be used to endorse or promote products
vcoubard	607:e98331f1d6b5	17	* derived from this software without specific prior written permission.
vcoubard	607:e98331f1d6b5	18	*
vcoubard	607:e98331f1d6b5	19	*
vcoubard	607:e98331f1d6b5	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
vcoubard	607:e98331f1d6b5	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
vcoubard	607:e98331f1d6b5	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
vcoubard	607:e98331f1d6b5	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
vcoubard	607:e98331f1d6b5	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
vcoubard	607:e98331f1d6b5	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
vcoubard	607:e98331f1d6b5	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
vcoubard	607:e98331f1d6b5	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
vcoubard	607:e98331f1d6b5	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
vcoubard	607:e98331f1d6b5	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
vcoubard	607:e98331f1d6b5	30	*
vcoubard	607:e98331f1d6b5	31	*/
vcoubard	607:e98331f1d6b5	32
vcoubard	607:e98331f1d6b5	33	#ifndef NRF51_H
vcoubard	607:e98331f1d6b5	34	#define NRF51_H
vcoubard	607:e98331f1d6b5	35
vcoubard	607:e98331f1d6b5	36	#ifdef __cplusplus
vcoubard	607:e98331f1d6b5	37	extern "C" {
vcoubard	607:e98331f1d6b5	38	#endif
vcoubard	607:e98331f1d6b5	39
vcoubard	607:e98331f1d6b5	40
vcoubard	607:e98331f1d6b5	41	/* ------------------------- Interrupt Number Definition ------------------------ */
vcoubard	607:e98331f1d6b5	42
vcoubard	607:e98331f1d6b5	43	typedef enum {
vcoubard	607:e98331f1d6b5	44	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
vcoubard	607:e98331f1d6b5	45	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
vcoubard	607:e98331f1d6b5	46	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
vcoubard	607:e98331f1d6b5	47	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
vcoubard	607:e98331f1d6b5	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
vcoubard	607:e98331f1d6b5	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
vcoubard	607:e98331f1d6b5	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
vcoubard	607:e98331f1d6b5	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
vcoubard	607:e98331f1d6b5	52	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
vcoubard	607:e98331f1d6b5	53	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
vcoubard	607:e98331f1d6b5	54	RADIO_IRQn = 1, /!< 1 RADIO /
vcoubard	607:e98331f1d6b5	55	UART0_IRQn = 2, /!< 2 UART0 /
vcoubard	607:e98331f1d6b5	56	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
vcoubard	607:e98331f1d6b5	57	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
vcoubard	607:e98331f1d6b5	58	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
vcoubard	607:e98331f1d6b5	59	ADC_IRQn = 7, /!< 7 ADC /
vcoubard	607:e98331f1d6b5	60	TIMER0_IRQn = 8, /!< 8 TIMER0 /
vcoubard	607:e98331f1d6b5	61	TIMER1_IRQn = 9, /!< 9 TIMER1 /
vcoubard	607:e98331f1d6b5	62	TIMER2_IRQn = 10, /!< 10 TIMER2 /
vcoubard	607:e98331f1d6b5	63	RTC0_IRQn = 11, /!< 11 RTC0 /
vcoubard	607:e98331f1d6b5	64	TEMP_IRQn = 12, /!< 12 TEMP /
vcoubard	607:e98331f1d6b5	65	RNG_IRQn = 13, /!< 13 RNG /
vcoubard	607:e98331f1d6b5	66	ECB_IRQn = 14, /!< 14 ECB /
vcoubard	607:e98331f1d6b5	67	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
vcoubard	607:e98331f1d6b5	68	WDT_IRQn = 16, /!< 16 WDT /
vcoubard	607:e98331f1d6b5	69	RTC1_IRQn = 17, /!< 17 RTC1 /
vcoubard	607:e98331f1d6b5	70	QDEC_IRQn = 18, /!< 18 QDEC /
vcoubard	607:e98331f1d6b5	71	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
vcoubard	607:e98331f1d6b5	72	SWI0_IRQn = 20, /!< 20 SWI0 /
vcoubard	607:e98331f1d6b5	73	SWI1_IRQn = 21, /!< 21 SWI1 /
vcoubard	607:e98331f1d6b5	74	SWI2_IRQn = 22, /!< 22 SWI2 /
vcoubard	607:e98331f1d6b5	75	SWI3_IRQn = 23, /!< 23 SWI3 /
vcoubard	607:e98331f1d6b5	76	SWI4_IRQn = 24, /!< 24 SWI4 /
vcoubard	607:e98331f1d6b5	77	SWI5_IRQn = 25 /!< 25 SWI5 /
vcoubard	607:e98331f1d6b5	78	} IRQn_Type;
vcoubard	607:e98331f1d6b5	79
vcoubard	607:e98331f1d6b5	80
vcoubard	607:e98331f1d6b5	81	/** @addtogroup Configuration_of_CMSIS
vcoubard	607:e98331f1d6b5	82	* @{
vcoubard	607:e98331f1d6b5	83	*/
vcoubard	607:e98331f1d6b5	84
vcoubard	607:e98331f1d6b5	85
vcoubard	607:e98331f1d6b5	86	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	87	/* ================ Processor and Core Peripheral Section ================ */
vcoubard	607:e98331f1d6b5	88	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	89
vcoubard	607:e98331f1d6b5	90	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
vcoubard	607:e98331f1d6b5	91	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
vcoubard	607:e98331f1d6b5	92	#define __MPU_PRESENT 0 /!< MPU present or not /
vcoubard	607:e98331f1d6b5	93	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
vcoubard	607:e98331f1d6b5	94	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
vcoubard	607:e98331f1d6b5	95	/** @} / / End of group Configuration_of_CMSIS */
vcoubard	607:e98331f1d6b5	96
vcoubard	607:e98331f1d6b5	97	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
vcoubard	607:e98331f1d6b5	98	#include "system_nrf51.h" /!< nrf51 System /
vcoubard	607:e98331f1d6b5	99
vcoubard	607:e98331f1d6b5	100
vcoubard	607:e98331f1d6b5	101	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	102	/* ================ Device Specific Peripheral Section ================ */
vcoubard	607:e98331f1d6b5	103	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	104
vcoubard	607:e98331f1d6b5	105
vcoubard	607:e98331f1d6b5	106	/** @addtogroup Device_Peripheral_Registers
vcoubard	607:e98331f1d6b5	107	* @{
vcoubard	607:e98331f1d6b5	108	*/
vcoubard	607:e98331f1d6b5	109
vcoubard	607:e98331f1d6b5	110
vcoubard	607:e98331f1d6b5	111	/* ------------------- Start of section using anonymous unions ------------------ */
vcoubard	607:e98331f1d6b5	112	#if defined(__CC_ARM)
vcoubard	607:e98331f1d6b5	113	#pragma push
vcoubard	607:e98331f1d6b5	114	#pragma anon_unions
vcoubard	607:e98331f1d6b5	115	#elif defined(__ICCARM__)
vcoubard	607:e98331f1d6b5	116	#pragma language=extended
vcoubard	607:e98331f1d6b5	117	#elif defined(__GNUC__)
vcoubard	607:e98331f1d6b5	118	/* anonymous unions are enabled by default */
vcoubard	607:e98331f1d6b5	119	#elif defined(__TMS470__)
vcoubard	607:e98331f1d6b5	120	/* anonymous unions are enabled by default */
vcoubard	607:e98331f1d6b5	121	#elif defined(__TASKING__)
vcoubard	607:e98331f1d6b5	122	#pragma warning 586
vcoubard	607:e98331f1d6b5	123	#else
vcoubard	607:e98331f1d6b5	124	#warning Not supported compiler type
vcoubard	607:e98331f1d6b5	125	#endif
vcoubard	607:e98331f1d6b5	126
vcoubard	607:e98331f1d6b5	127
vcoubard	607:e98331f1d6b5	128	typedef struct {
vcoubard	607:e98331f1d6b5	129	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
vcoubard	607:e98331f1d6b5	130	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
vcoubard	607:e98331f1d6b5	131	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
vcoubard	607:e98331f1d6b5	132	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
vcoubard	607:e98331f1d6b5	133	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
vcoubard	607:e98331f1d6b5	134	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
vcoubard	607:e98331f1d6b5	135	} AMLI_RAMPRI_Type;
vcoubard	607:e98331f1d6b5	136
vcoubard	607:e98331f1d6b5	137	typedef struct {
vcoubard	607:e98331f1d6b5	138	__IO uint32_t SCK; /!< Pin select for SCK. /
vcoubard	607:e98331f1d6b5	139	__IO uint32_t MOSI; /!< Pin select for MOSI. /
vcoubard	607:e98331f1d6b5	140	__IO uint32_t MISO; /!< Pin select for MISO. /
vcoubard	607:e98331f1d6b5	141	} SPIM_PSEL_Type;
vcoubard	607:e98331f1d6b5	142
vcoubard	607:e98331f1d6b5	143	typedef struct {
vcoubard	607:e98331f1d6b5	144	__IO uint32_t PTR; /!< Data pointer. /
vcoubard	607:e98331f1d6b5	145	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
vcoubard	607:e98331f1d6b5	146	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
vcoubard	607:e98331f1d6b5	147	} SPIM_RXD_Type;
vcoubard	607:e98331f1d6b5	148
vcoubard	607:e98331f1d6b5	149	typedef struct {
vcoubard	607:e98331f1d6b5	150	__IO uint32_t PTR; /!< Data pointer. /
vcoubard	607:e98331f1d6b5	151	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
vcoubard	607:e98331f1d6b5	152	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
vcoubard	607:e98331f1d6b5	153	} SPIM_TXD_Type;
vcoubard	607:e98331f1d6b5	154
vcoubard	607:e98331f1d6b5	155	typedef struct {
vcoubard	607:e98331f1d6b5	156	__O uint32_t EN; /!< Enable channel group. /
vcoubard	607:e98331f1d6b5	157	__O uint32_t DIS; /!< Disable channel group. /
vcoubard	607:e98331f1d6b5	158	} PPI_TASKS_CHG_Type;
vcoubard	607:e98331f1d6b5	159
vcoubard	607:e98331f1d6b5	160	typedef struct {
vcoubard	607:e98331f1d6b5	161	__IO uint32_t EEP; /!< Channel event end-point. /
vcoubard	607:e98331f1d6b5	162	__IO uint32_t TEP; /!< Channel task end-point. /
vcoubard	607:e98331f1d6b5	163	} PPI_CH_Type;
vcoubard	607:e98331f1d6b5	164
vcoubard	607:e98331f1d6b5	165
vcoubard	607:e98331f1d6b5	166	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	167	/* ================ POWER ================ */
vcoubard	607:e98331f1d6b5	168	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	169
vcoubard	607:e98331f1d6b5	170
vcoubard	607:e98331f1d6b5	171	/**
vcoubard	607:e98331f1d6b5	172	* @brief Power Control. (POWER)
vcoubard	607:e98331f1d6b5	173	*/
vcoubard	607:e98331f1d6b5	174
vcoubard	607:e98331f1d6b5	175	typedef struct { /!< POWER Structure /
vcoubard	607:e98331f1d6b5	176	__I uint32_t RESERVED0[30];
vcoubard	607:e98331f1d6b5	177	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
vcoubard	607:e98331f1d6b5	178	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
vcoubard	607:e98331f1d6b5	179	__I uint32_t RESERVED1[34];
vcoubard	607:e98331f1d6b5	180	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
vcoubard	607:e98331f1d6b5	181	__I uint32_t RESERVED2[126];
vcoubard	607:e98331f1d6b5	182	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	183	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	184	__I uint32_t RESERVED3[61];
vcoubard	607:e98331f1d6b5	185	__IO uint32_t RESETREAS; /!< Reset reason. /
vcoubard	607:e98331f1d6b5	186	__I uint32_t RESERVED4[9];
vcoubard	607:e98331f1d6b5	187	__I uint32_t RAMSTATUS; /!< Ram status register. /
vcoubard	607:e98331f1d6b5	188	__I uint32_t RESERVED5[53];
vcoubard	607:e98331f1d6b5	189	__O uint32_t SYSTEMOFF; /!< System off register. /
vcoubard	607:e98331f1d6b5	190	__I uint32_t RESERVED6[3];
vcoubard	607:e98331f1d6b5	191	__IO uint32_t POFCON; /!< Power failure configuration. /
vcoubard	607:e98331f1d6b5	192	__I uint32_t RESERVED7[2];
vcoubard	607:e98331f1d6b5	193	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
vcoubard	607:e98331f1d6b5	194	register. */
vcoubard	607:e98331f1d6b5	195	__I uint32_t RESERVED8;
vcoubard	607:e98331f1d6b5	196	__IO uint32_t RAMON; /!< Ram on/off. /
vcoubard	607:e98331f1d6b5	197	__I uint32_t RESERVED9[7];
vcoubard	607:e98331f1d6b5	198	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
vcoubard	607:e98331f1d6b5	199	is a retained register. */
vcoubard	607:e98331f1d6b5	200	__I uint32_t RESERVED10[3];
vcoubard	607:e98331f1d6b5	201	__IO uint32_t RAMONB; /!< Ram on/off. /
vcoubard	607:e98331f1d6b5	202	__I uint32_t RESERVED11[8];
vcoubard	607:e98331f1d6b5	203	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
vcoubard	607:e98331f1d6b5	204	__I uint32_t RESERVED12[291];
vcoubard	607:e98331f1d6b5	205	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
vcoubard	607:e98331f1d6b5	206	} NRF_POWER_Type;
vcoubard	607:e98331f1d6b5	207
vcoubard	607:e98331f1d6b5	208
vcoubard	607:e98331f1d6b5	209	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	210	/* ================ CLOCK ================ */
vcoubard	607:e98331f1d6b5	211	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	212
vcoubard	607:e98331f1d6b5	213
vcoubard	607:e98331f1d6b5	214	/**
vcoubard	607:e98331f1d6b5	215	* @brief Clock control. (CLOCK)
vcoubard	607:e98331f1d6b5	216	*/
vcoubard	607:e98331f1d6b5	217
vcoubard	607:e98331f1d6b5	218	typedef struct { /!< CLOCK Structure /
vcoubard	607:e98331f1d6b5	219	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
vcoubard	607:e98331f1d6b5	220	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
vcoubard	607:e98331f1d6b5	221	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
vcoubard	607:e98331f1d6b5	222	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
vcoubard	607:e98331f1d6b5	223	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
vcoubard	607:e98331f1d6b5	224	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
vcoubard	607:e98331f1d6b5	225	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
vcoubard	607:e98331f1d6b5	226	__I uint32_t RESERVED0[57];
vcoubard	607:e98331f1d6b5	227	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
vcoubard	607:e98331f1d6b5	228	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
vcoubard	607:e98331f1d6b5	229	__I uint32_t RESERVED1;
vcoubard	607:e98331f1d6b5	230	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
vcoubard	607:e98331f1d6b5	231	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
vcoubard	607:e98331f1d6b5	232	__I uint32_t RESERVED2[124];
vcoubard	607:e98331f1d6b5	233	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	234	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	235	__I uint32_t RESERVED3[63];
vcoubard	607:e98331f1d6b5	236	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
vcoubard	607:e98331f1d6b5	237	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
vcoubard	607:e98331f1d6b5	238	__I uint32_t RESERVED4;
vcoubard	607:e98331f1d6b5	239	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
vcoubard	607:e98331f1d6b5	240	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
vcoubard	607:e98331f1d6b5	241	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
vcoubard	607:e98331f1d6b5	242	triggered. */
vcoubard	607:e98331f1d6b5	243	__I uint32_t RESERVED5[62];
vcoubard	607:e98331f1d6b5	244	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
vcoubard	607:e98331f1d6b5	245	__I uint32_t RESERVED6[7];
vcoubard	607:e98331f1d6b5	246	__IO uint32_t CTIV; /!< Calibration timer interval. /
vcoubard	607:e98331f1d6b5	247	__I uint32_t RESERVED7[5];
vcoubard	607:e98331f1d6b5	248	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
vcoubard	607:e98331f1d6b5	249	} NRF_CLOCK_Type;
vcoubard	607:e98331f1d6b5	250
vcoubard	607:e98331f1d6b5	251
vcoubard	607:e98331f1d6b5	252	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	253	/* ================ MPU ================ */
vcoubard	607:e98331f1d6b5	254	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	255
vcoubard	607:e98331f1d6b5	256
vcoubard	607:e98331f1d6b5	257	/**
vcoubard	607:e98331f1d6b5	258	* @brief Memory Protection Unit. (MPU)
vcoubard	607:e98331f1d6b5	259	*/
vcoubard	607:e98331f1d6b5	260
vcoubard	607:e98331f1d6b5	261	typedef struct { /!< MPU Structure /
vcoubard	607:e98331f1d6b5	262	__I uint32_t RESERVED0[330];
vcoubard	607:e98331f1d6b5	263	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
vcoubard	607:e98331f1d6b5	264	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
vcoubard	607:e98331f1d6b5	265	__I uint32_t RESERVED1[52];
vcoubard	607:e98331f1d6b5	266	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
vcoubard	607:e98331f1d6b5	267	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
vcoubard	607:e98331f1d6b5	268	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
vcoubard	607:e98331f1d6b5	269	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
vcoubard	607:e98331f1d6b5	270	} NRF_MPU_Type;
vcoubard	607:e98331f1d6b5	271
vcoubard	607:e98331f1d6b5	272
vcoubard	607:e98331f1d6b5	273	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	274	/* ================ AMLI ================ */
vcoubard	607:e98331f1d6b5	275	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	276
vcoubard	607:e98331f1d6b5	277
vcoubard	607:e98331f1d6b5	278	/**
vcoubard	607:e98331f1d6b5	279	* @brief AHB Multi-Layer Interface. (AMLI)
vcoubard	607:e98331f1d6b5	280	*/
vcoubard	607:e98331f1d6b5	281
vcoubard	607:e98331f1d6b5	282	typedef struct { /!< AMLI Structure /
vcoubard	607:e98331f1d6b5	283	__I uint32_t RESERVED0[896];
vcoubard	607:e98331f1d6b5	284	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
vcoubard	607:e98331f1d6b5	285	} NRF_AMLI_Type;
vcoubard	607:e98331f1d6b5	286
vcoubard	607:e98331f1d6b5	287
vcoubard	607:e98331f1d6b5	288	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	289	/* ================ RADIO ================ */
vcoubard	607:e98331f1d6b5	290	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	291
vcoubard	607:e98331f1d6b5	292
vcoubard	607:e98331f1d6b5	293	/**
vcoubard	607:e98331f1d6b5	294	* @brief The radio. (RADIO)
vcoubard	607:e98331f1d6b5	295	*/
vcoubard	607:e98331f1d6b5	296
vcoubard	607:e98331f1d6b5	297	typedef struct { /!< RADIO Structure /
vcoubard	607:e98331f1d6b5	298	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
vcoubard	607:e98331f1d6b5	299	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
vcoubard	607:e98331f1d6b5	300	__O uint32_t TASKS_START; /!< Start radio. /
vcoubard	607:e98331f1d6b5	301	__O uint32_t TASKS_STOP; /!< Stop radio. /
vcoubard	607:e98331f1d6b5	302	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
vcoubard	607:e98331f1d6b5	303	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
vcoubard	607:e98331f1d6b5	304	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
vcoubard	607:e98331f1d6b5	305	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
vcoubard	607:e98331f1d6b5	306	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
vcoubard	607:e98331f1d6b5	307	__I uint32_t RESERVED0[55];
vcoubard	607:e98331f1d6b5	308	__IO uint32_t EVENTS_READY; /!< Ready event. /
vcoubard	607:e98331f1d6b5	309	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
vcoubard	607:e98331f1d6b5	310	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
vcoubard	607:e98331f1d6b5	311	__IO uint32_t EVENTS_END; /!< End event. /
vcoubard	607:e98331f1d6b5	312	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
vcoubard	607:e98331f1d6b5	313	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
vcoubard	607:e98331f1d6b5	314	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
vcoubard	607:e98331f1d6b5	315	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
vcoubard	607:e98331f1d6b5	316	sample is ready for readout at the RSSISAMPLE register. */
vcoubard	607:e98331f1d6b5	317	__I uint32_t RESERVED1[2];
vcoubard	607:e98331f1d6b5	318	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
vcoubard	607:e98331f1d6b5	319	__I uint32_t RESERVED2[53];
vcoubard	607:e98331f1d6b5	320	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
vcoubard	607:e98331f1d6b5	321	__I uint32_t RESERVED3[64];
vcoubard	607:e98331f1d6b5	322	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	323	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	324	__I uint32_t RESERVED4[61];
vcoubard	607:e98331f1d6b5	325	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
vcoubard	607:e98331f1d6b5	326	__I uint32_t RESERVED5;
vcoubard	607:e98331f1d6b5	327	__I uint32_t RXMATCH; /!< Received address. /
vcoubard	607:e98331f1d6b5	328	__I uint32_t RXCRC; /!< Received CRC. /
vcoubard	607:e98331f1d6b5	329	__I uint32_t DAI; /!< Device address match index. /
vcoubard	607:e98331f1d6b5	330	__I uint32_t RESERVED6[60];
vcoubard	607:e98331f1d6b5	331	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
vcoubard	607:e98331f1d6b5	332	__IO uint32_t FREQUENCY; /!< Frequency. /
vcoubard	607:e98331f1d6b5	333	__IO uint32_t TXPOWER; /!< Output power. /
vcoubard	607:e98331f1d6b5	334	__IO uint32_t MODE; /!< Data rate and modulation. /
vcoubard	607:e98331f1d6b5	335	__IO uint32_t PCNF0; /!< Packet configuration 0. /
vcoubard	607:e98331f1d6b5	336	__IO uint32_t PCNF1; /!< Packet configuration 1. /
vcoubard	607:e98331f1d6b5	337	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
vcoubard	607:e98331f1d6b5	338	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
vcoubard	607:e98331f1d6b5	339	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
vcoubard	607:e98331f1d6b5	340	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
vcoubard	607:e98331f1d6b5	341	__IO uint32_t TXADDRESS; /!< Transmit address select. /
vcoubard	607:e98331f1d6b5	342	__IO uint32_t RXADDRESSES; /!< Receive address select. /
vcoubard	607:e98331f1d6b5	343	__IO uint32_t CRCCNF; /!< CRC configuration. /
vcoubard	607:e98331f1d6b5	344	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
vcoubard	607:e98331f1d6b5	345	__IO uint32_t CRCINIT; /!< CRC initial value. /
vcoubard	607:e98331f1d6b5	346	__IO uint32_t TEST; /!< Test features enable register. /
vcoubard	607:e98331f1d6b5	347	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
vcoubard	607:e98331f1d6b5	348	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
vcoubard	607:e98331f1d6b5	349	__I uint32_t RESERVED7;
vcoubard	607:e98331f1d6b5	350	__I uint32_t STATE; /!< Current radio state. /
vcoubard	607:e98331f1d6b5	351	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
vcoubard	607:e98331f1d6b5	352	__I uint32_t RESERVED8[2];
vcoubard	607:e98331f1d6b5	353	__IO uint32_t BCC; /!< Bit counter compare. /
vcoubard	607:e98331f1d6b5	354	__I uint32_t RESERVED9[39];
vcoubard	607:e98331f1d6b5	355	__IO uint32_t DAB[8]; /!< Device address base segment. /
vcoubard	607:e98331f1d6b5	356	__IO uint32_t DAP[8]; /!< Device address prefix. /
vcoubard	607:e98331f1d6b5	357	__IO uint32_t DACNF; /!< Device address match configuration. /
vcoubard	607:e98331f1d6b5	358	__I uint32_t RESERVED10[56];
vcoubard	607:e98331f1d6b5	359	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
vcoubard	607:e98331f1d6b5	360	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
vcoubard	607:e98331f1d6b5	361	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
vcoubard	607:e98331f1d6b5	362	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
vcoubard	607:e98331f1d6b5	363	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
vcoubard	607:e98331f1d6b5	364	__I uint32_t RESERVED11[561];
vcoubard	607:e98331f1d6b5	365	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	366	} NRF_RADIO_Type;
vcoubard	607:e98331f1d6b5	367
vcoubard	607:e98331f1d6b5	368
vcoubard	607:e98331f1d6b5	369	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	370	/* ================ UART ================ */
vcoubard	607:e98331f1d6b5	371	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	372
vcoubard	607:e98331f1d6b5	373
vcoubard	607:e98331f1d6b5	374	/**
vcoubard	607:e98331f1d6b5	375	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
vcoubard	607:e98331f1d6b5	376	*/
vcoubard	607:e98331f1d6b5	377
vcoubard	607:e98331f1d6b5	378	typedef struct { /!< UART Structure /
vcoubard	607:e98331f1d6b5	379	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
vcoubard	607:e98331f1d6b5	380	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
vcoubard	607:e98331f1d6b5	381	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
vcoubard	607:e98331f1d6b5	382	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
vcoubard	607:e98331f1d6b5	383	__I uint32_t RESERVED0[3];
vcoubard	607:e98331f1d6b5	384	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
vcoubard	607:e98331f1d6b5	385	__I uint32_t RESERVED1[56];
vcoubard	607:e98331f1d6b5	386	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
vcoubard	607:e98331f1d6b5	387	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
vcoubard	607:e98331f1d6b5	388	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
vcoubard	607:e98331f1d6b5	389	__I uint32_t RESERVED2[4];
vcoubard	607:e98331f1d6b5	390	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
vcoubard	607:e98331f1d6b5	391	__I uint32_t RESERVED3;
vcoubard	607:e98331f1d6b5	392	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
vcoubard	607:e98331f1d6b5	393	__I uint32_t RESERVED4[7];
vcoubard	607:e98331f1d6b5	394	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
vcoubard	607:e98331f1d6b5	395	__I uint32_t RESERVED5[46];
vcoubard	607:e98331f1d6b5	396	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
vcoubard	607:e98331f1d6b5	397	__I uint32_t RESERVED6[64];
vcoubard	607:e98331f1d6b5	398	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	399	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	400	__I uint32_t RESERVED7[93];
vcoubard	607:e98331f1d6b5	401	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
vcoubard	607:e98331f1d6b5	402	__I uint32_t RESERVED8[31];
vcoubard	607:e98331f1d6b5	403	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
vcoubard	607:e98331f1d6b5	404	__I uint32_t RESERVED9;
vcoubard	607:e98331f1d6b5	405	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
vcoubard	607:e98331f1d6b5	406	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
vcoubard	607:e98331f1d6b5	407	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
vcoubard	607:e98331f1d6b5	408	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
vcoubard	607:e98331f1d6b5	409	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
vcoubard	607:e98331f1d6b5	410	Once read the character is consumed. If read when no character
vcoubard	607:e98331f1d6b5	411	available, the UART will stop working. */
vcoubard	607:e98331f1d6b5	412	__O uint32_t TXD; /!< TXD register. /
vcoubard	607:e98331f1d6b5	413	__I uint32_t RESERVED10;
vcoubard	607:e98331f1d6b5	414	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
vcoubard	607:e98331f1d6b5	415	__I uint32_t RESERVED11[17];
vcoubard	607:e98331f1d6b5	416	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
vcoubard	607:e98331f1d6b5	417	__I uint32_t RESERVED12[675];
vcoubard	607:e98331f1d6b5	418	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	419	} NRF_UART_Type;
vcoubard	607:e98331f1d6b5	420
vcoubard	607:e98331f1d6b5	421
vcoubard	607:e98331f1d6b5	422	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	423	/* ================ SPI ================ */
vcoubard	607:e98331f1d6b5	424	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	425
vcoubard	607:e98331f1d6b5	426
vcoubard	607:e98331f1d6b5	427	/**
vcoubard	607:e98331f1d6b5	428	* @brief SPI master 0. (SPI)
vcoubard	607:e98331f1d6b5	429	*/
vcoubard	607:e98331f1d6b5	430
vcoubard	607:e98331f1d6b5	431	typedef struct { /!< SPI Structure /
vcoubard	607:e98331f1d6b5	432	__I uint32_t RESERVED0[66];
vcoubard	607:e98331f1d6b5	433	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
vcoubard	607:e98331f1d6b5	434	__I uint32_t RESERVED1[126];
vcoubard	607:e98331f1d6b5	435	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	436	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	437	__I uint32_t RESERVED2[125];
vcoubard	607:e98331f1d6b5	438	__IO uint32_t ENABLE; /!< Enable SPI. /
vcoubard	607:e98331f1d6b5	439	__I uint32_t RESERVED3;
vcoubard	607:e98331f1d6b5	440	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
vcoubard	607:e98331f1d6b5	441	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
vcoubard	607:e98331f1d6b5	442	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
vcoubard	607:e98331f1d6b5	443	__I uint32_t RESERVED4;
vcoubard	607:e98331f1d6b5	444	__I uint32_t RXD; /!< RX data. /
vcoubard	607:e98331f1d6b5	445	__IO uint32_t TXD; /!< TX data. /
vcoubard	607:e98331f1d6b5	446	__I uint32_t RESERVED5;
vcoubard	607:e98331f1d6b5	447	__IO uint32_t FREQUENCY; /!< SPI frequency /
vcoubard	607:e98331f1d6b5	448	__I uint32_t RESERVED6[11];
vcoubard	607:e98331f1d6b5	449	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	607:e98331f1d6b5	450	__I uint32_t RESERVED7[681];
vcoubard	607:e98331f1d6b5	451	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	452	} NRF_SPI_Type;
vcoubard	607:e98331f1d6b5	453
vcoubard	607:e98331f1d6b5	454
vcoubard	607:e98331f1d6b5	455	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	456	/* ================ TWI ================ */
vcoubard	607:e98331f1d6b5	457	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	458
vcoubard	607:e98331f1d6b5	459
vcoubard	607:e98331f1d6b5	460	/**
vcoubard	607:e98331f1d6b5	461	* @brief Two-wire interface master 0. (TWI)
vcoubard	607:e98331f1d6b5	462	*/
vcoubard	607:e98331f1d6b5	463
vcoubard	607:e98331f1d6b5	464	typedef struct { /!< TWI Structure /
vcoubard	607:e98331f1d6b5	465	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
vcoubard	607:e98331f1d6b5	466	__I uint32_t RESERVED0;
vcoubard	607:e98331f1d6b5	467	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
vcoubard	607:e98331f1d6b5	468	__I uint32_t RESERVED1[2];
vcoubard	607:e98331f1d6b5	469	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
vcoubard	607:e98331f1d6b5	470	__I uint32_t RESERVED2;
vcoubard	607:e98331f1d6b5	471	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
vcoubard	607:e98331f1d6b5	472	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
vcoubard	607:e98331f1d6b5	473	__I uint32_t RESERVED3[56];
vcoubard	607:e98331f1d6b5	474	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
vcoubard	607:e98331f1d6b5	475	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
vcoubard	607:e98331f1d6b5	476	__I uint32_t RESERVED4[4];
vcoubard	607:e98331f1d6b5	477	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
vcoubard	607:e98331f1d6b5	478	__I uint32_t RESERVED5;
vcoubard	607:e98331f1d6b5	479	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
vcoubard	607:e98331f1d6b5	480	__I uint32_t RESERVED6[4];
vcoubard	607:e98331f1d6b5	481	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
vcoubard	607:e98331f1d6b5	482	__I uint32_t RESERVED7[3];
vcoubard	607:e98331f1d6b5	483	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
vcoubard	607:e98331f1d6b5	484	__I uint32_t RESERVED8[45];
vcoubard	607:e98331f1d6b5	485	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
vcoubard	607:e98331f1d6b5	486	__I uint32_t RESERVED9[64];
vcoubard	607:e98331f1d6b5	487	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	488	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	489	__I uint32_t RESERVED10[110];
vcoubard	607:e98331f1d6b5	490	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
vcoubard	607:e98331f1d6b5	491	__I uint32_t RESERVED11[14];
vcoubard	607:e98331f1d6b5	492	__IO uint32_t ENABLE; /!< Enable two-wire master. /
vcoubard	607:e98331f1d6b5	493	__I uint32_t RESERVED12;
vcoubard	607:e98331f1d6b5	494	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
vcoubard	607:e98331f1d6b5	495	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
vcoubard	607:e98331f1d6b5	496	__I uint32_t RESERVED13[2];
vcoubard	607:e98331f1d6b5	497	__I uint32_t RXD; /!< RX data register. /
vcoubard	607:e98331f1d6b5	498	__IO uint32_t TXD; /!< TX data register. /
vcoubard	607:e98331f1d6b5	499	__I uint32_t RESERVED14;
vcoubard	607:e98331f1d6b5	500	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
vcoubard	607:e98331f1d6b5	501	__I uint32_t RESERVED15[24];
vcoubard	607:e98331f1d6b5	502	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
vcoubard	607:e98331f1d6b5	503	__I uint32_t RESERVED16[668];
vcoubard	607:e98331f1d6b5	504	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	505	} NRF_TWI_Type;
vcoubard	607:e98331f1d6b5	506
vcoubard	607:e98331f1d6b5	507
vcoubard	607:e98331f1d6b5	508	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	509	/* ================ SPIS ================ */
vcoubard	607:e98331f1d6b5	510	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	511
vcoubard	607:e98331f1d6b5	512
vcoubard	607:e98331f1d6b5	513	/**
vcoubard	607:e98331f1d6b5	514	* @brief SPI slave 1. (SPIS)
vcoubard	607:e98331f1d6b5	515	*/
vcoubard	607:e98331f1d6b5	516
vcoubard	607:e98331f1d6b5	517	typedef struct { /!< SPIS Structure /
vcoubard	607:e98331f1d6b5	518	__I uint32_t RESERVED0[9];
vcoubard	607:e98331f1d6b5	519	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
vcoubard	607:e98331f1d6b5	520	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
vcoubard	607:e98331f1d6b5	521	__I uint32_t RESERVED1[54];
vcoubard	607:e98331f1d6b5	522	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
vcoubard	607:e98331f1d6b5	523	__I uint32_t RESERVED2[2];
vcoubard	607:e98331f1d6b5	524	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
vcoubard	607:e98331f1d6b5	525	__I uint32_t RESERVED3[5];
vcoubard	607:e98331f1d6b5	526	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
vcoubard	607:e98331f1d6b5	527	__I uint32_t RESERVED4[53];
vcoubard	607:e98331f1d6b5	528	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
vcoubard	607:e98331f1d6b5	529	__I uint32_t RESERVED5[64];
vcoubard	607:e98331f1d6b5	530	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	531	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	532	__I uint32_t RESERVED6[61];
vcoubard	607:e98331f1d6b5	533	__I uint32_t SEMSTAT; /!< Semaphore status. /
vcoubard	607:e98331f1d6b5	534	__I uint32_t RESERVED7[15];
vcoubard	607:e98331f1d6b5	535	__IO uint32_t STATUS; /!< Status from last transaction. /
vcoubard	607:e98331f1d6b5	536	__I uint32_t RESERVED8[47];
vcoubard	607:e98331f1d6b5	537	__IO uint32_t ENABLE; /!< Enable SPIS. /
vcoubard	607:e98331f1d6b5	538	__I uint32_t RESERVED9;
vcoubard	607:e98331f1d6b5	539	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
vcoubard	607:e98331f1d6b5	540	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
vcoubard	607:e98331f1d6b5	541	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
vcoubard	607:e98331f1d6b5	542	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
vcoubard	607:e98331f1d6b5	543	__I uint32_t RESERVED10[7];
vcoubard	607:e98331f1d6b5	544	__IO uint32_t RXDPTR; /!< RX data pointer. /
vcoubard	607:e98331f1d6b5	545	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
vcoubard	607:e98331f1d6b5	546	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
vcoubard	607:e98331f1d6b5	547	__I uint32_t RESERVED11;
vcoubard	607:e98331f1d6b5	548	__IO uint32_t TXDPTR; /!< TX data pointer. /
vcoubard	607:e98331f1d6b5	549	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
vcoubard	607:e98331f1d6b5	550	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
vcoubard	607:e98331f1d6b5	551	__I uint32_t RESERVED12;
vcoubard	607:e98331f1d6b5	552	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	607:e98331f1d6b5	553	__I uint32_t RESERVED13;
vcoubard	607:e98331f1d6b5	554	__IO uint32_t DEF; /!< Default character. /
vcoubard	607:e98331f1d6b5	555	__I uint32_t RESERVED14[24];
vcoubard	607:e98331f1d6b5	556	__IO uint32_t ORC; /!< Over-read character. /
vcoubard	607:e98331f1d6b5	557	__I uint32_t RESERVED15[654];
vcoubard	607:e98331f1d6b5	558	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	559	} NRF_SPIS_Type;
vcoubard	607:e98331f1d6b5	560
vcoubard	607:e98331f1d6b5	561
vcoubard	607:e98331f1d6b5	562	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	563	/* ================ SPIM ================ */
vcoubard	607:e98331f1d6b5	564	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	565
vcoubard	607:e98331f1d6b5	566
vcoubard	607:e98331f1d6b5	567	/**
vcoubard	607:e98331f1d6b5	568	* @brief SPI master with easyDMA 1. (SPIM)
vcoubard	607:e98331f1d6b5	569	*/
vcoubard	607:e98331f1d6b5	570
vcoubard	607:e98331f1d6b5	571	typedef struct { /!< SPIM Structure /
vcoubard	607:e98331f1d6b5	572	__I uint32_t RESERVED0[4];
vcoubard	607:e98331f1d6b5	573	__O uint32_t TASKS_START; /!< Start SPI transaction. /
vcoubard	607:e98331f1d6b5	574	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
vcoubard	607:e98331f1d6b5	575	__I uint32_t RESERVED1;
vcoubard	607:e98331f1d6b5	576	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
vcoubard	607:e98331f1d6b5	577	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
vcoubard	607:e98331f1d6b5	578	__I uint32_t RESERVED2[56];
vcoubard	607:e98331f1d6b5	579	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
vcoubard	607:e98331f1d6b5	580	__I uint32_t RESERVED3[2];
vcoubard	607:e98331f1d6b5	581	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
vcoubard	607:e98331f1d6b5	582	__I uint32_t RESERVED4[3];
vcoubard	607:e98331f1d6b5	583	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
vcoubard	607:e98331f1d6b5	584	__I uint32_t RESERVED5[10];
vcoubard	607:e98331f1d6b5	585	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
vcoubard	607:e98331f1d6b5	586	__I uint32_t RESERVED6[109];
vcoubard	607:e98331f1d6b5	587	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	588	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	589	__I uint32_t RESERVED7[125];
vcoubard	607:e98331f1d6b5	590	__IO uint32_t ENABLE; /!< Enable SPIM. /
vcoubard	607:e98331f1d6b5	591	__I uint32_t RESERVED8;
vcoubard	607:e98331f1d6b5	592	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
vcoubard	607:e98331f1d6b5	593	__I uint32_t RESERVED9[4];
vcoubard	607:e98331f1d6b5	594	__IO uint32_t FREQUENCY; /!< SPI frequency. /
vcoubard	607:e98331f1d6b5	595	__I uint32_t RESERVED10[3];
vcoubard	607:e98331f1d6b5	596	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
vcoubard	607:e98331f1d6b5	597	__I uint32_t RESERVED11;
vcoubard	607:e98331f1d6b5	598	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
vcoubard	607:e98331f1d6b5	599	__I uint32_t RESERVED12;
vcoubard	607:e98331f1d6b5	600	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	607:e98331f1d6b5	601	__I uint32_t RESERVED13[26];
vcoubard	607:e98331f1d6b5	602	__IO uint32_t ORC; /!< Over-read character. /
vcoubard	607:e98331f1d6b5	603	__I uint32_t RESERVED14[654];
vcoubard	607:e98331f1d6b5	604	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	605	} NRF_SPIM_Type;
vcoubard	607:e98331f1d6b5	606
vcoubard	607:e98331f1d6b5	607
vcoubard	607:e98331f1d6b5	608	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	609	/* ================ GPIOTE ================ */
vcoubard	607:e98331f1d6b5	610	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	611
vcoubard	607:e98331f1d6b5	612
vcoubard	607:e98331f1d6b5	613	/**
vcoubard	607:e98331f1d6b5	614	* @brief GPIO tasks and events. (GPIOTE)
vcoubard	607:e98331f1d6b5	615	*/
vcoubard	607:e98331f1d6b5	616
vcoubard	607:e98331f1d6b5	617	typedef struct { /!< GPIOTE Structure /
vcoubard	607:e98331f1d6b5	618	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
vcoubard	607:e98331f1d6b5	619	__I uint32_t RESERVED0[60];
vcoubard	607:e98331f1d6b5	620	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
vcoubard	607:e98331f1d6b5	621	__I uint32_t RESERVED1[27];
vcoubard	607:e98331f1d6b5	622	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
vcoubard	607:e98331f1d6b5	623	__I uint32_t RESERVED2[97];
vcoubard	607:e98331f1d6b5	624	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	625	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	626	__I uint32_t RESERVED3[129];
vcoubard	607:e98331f1d6b5	627	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
vcoubard	607:e98331f1d6b5	628	__I uint32_t RESERVED4[695];
vcoubard	607:e98331f1d6b5	629	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	630	} NRF_GPIOTE_Type;
vcoubard	607:e98331f1d6b5	631
vcoubard	607:e98331f1d6b5	632
vcoubard	607:e98331f1d6b5	633	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	634	/* ================ ADC ================ */
vcoubard	607:e98331f1d6b5	635	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	636
vcoubard	607:e98331f1d6b5	637
vcoubard	607:e98331f1d6b5	638	/**
vcoubard	607:e98331f1d6b5	639	* @brief Analog to digital converter. (ADC)
vcoubard	607:e98331f1d6b5	640	*/
vcoubard	607:e98331f1d6b5	641
vcoubard	607:e98331f1d6b5	642	typedef struct { /!< ADC Structure /
vcoubard	607:e98331f1d6b5	643	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
vcoubard	607:e98331f1d6b5	644	__O uint32_t TASKS_STOP; /!< Stop ADC. /
vcoubard	607:e98331f1d6b5	645	__I uint32_t RESERVED0[62];
vcoubard	607:e98331f1d6b5	646	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
vcoubard	607:e98331f1d6b5	647	__I uint32_t RESERVED1[128];
vcoubard	607:e98331f1d6b5	648	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	649	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	650	__I uint32_t RESERVED2[61];
vcoubard	607:e98331f1d6b5	651	__I uint32_t BUSY; /!< ADC busy register. /
vcoubard	607:e98331f1d6b5	652	__I uint32_t RESERVED3[63];
vcoubard	607:e98331f1d6b5	653	__IO uint32_t ENABLE; /!< ADC enable. /
vcoubard	607:e98331f1d6b5	654	__IO uint32_t CONFIG; /!< ADC configuration register. /
vcoubard	607:e98331f1d6b5	655	__I uint32_t RESULT; /!< Result of ADC conversion. /
vcoubard	607:e98331f1d6b5	656	__I uint32_t RESERVED4[700];
vcoubard	607:e98331f1d6b5	657	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	658	} NRF_ADC_Type;
vcoubard	607:e98331f1d6b5	659
vcoubard	607:e98331f1d6b5	660
vcoubard	607:e98331f1d6b5	661	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	662	/* ================ TIMER ================ */
vcoubard	607:e98331f1d6b5	663	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	664
vcoubard	607:e98331f1d6b5	665
vcoubard	607:e98331f1d6b5	666	/**
vcoubard	607:e98331f1d6b5	667	* @brief Timer 0. (TIMER)
vcoubard	607:e98331f1d6b5	668	*/
vcoubard	607:e98331f1d6b5	669
vcoubard	607:e98331f1d6b5	670	typedef struct { /!< TIMER Structure /
vcoubard	607:e98331f1d6b5	671	__O uint32_t TASKS_START; /!< Start Timer. /
vcoubard	607:e98331f1d6b5	672	__O uint32_t TASKS_STOP; /!< Stop Timer. /
vcoubard	607:e98331f1d6b5	673	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
vcoubard	607:e98331f1d6b5	674	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
vcoubard	607:e98331f1d6b5	675	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
vcoubard	607:e98331f1d6b5	676	__I uint32_t RESERVED0[11];
vcoubard	607:e98331f1d6b5	677	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
vcoubard	607:e98331f1d6b5	678	__I uint32_t RESERVED1[60];
vcoubard	607:e98331f1d6b5	679	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
vcoubard	607:e98331f1d6b5	680	__I uint32_t RESERVED2[44];
vcoubard	607:e98331f1d6b5	681	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
vcoubard	607:e98331f1d6b5	682	__I uint32_t RESERVED3[64];
vcoubard	607:e98331f1d6b5	683	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	684	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	685	__I uint32_t RESERVED4[126];
vcoubard	607:e98331f1d6b5	686	__IO uint32_t MODE; /!< Timer Mode selection. /
vcoubard	607:e98331f1d6b5	687	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
vcoubard	607:e98331f1d6b5	688	__I uint32_t RESERVED5;
vcoubard	607:e98331f1d6b5	689	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
vcoubard	607:e98331f1d6b5	690	clock frequency is divided by 2^SCALE. */
vcoubard	607:e98331f1d6b5	691	__I uint32_t RESERVED6[11];
vcoubard	607:e98331f1d6b5	692	__IO uint32_t CC[4]; /!< Capture/compare registers. /
vcoubard	607:e98331f1d6b5	693	__I uint32_t RESERVED7[683];
vcoubard	607:e98331f1d6b5	694	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	695	} NRF_TIMER_Type;
vcoubard	607:e98331f1d6b5	696
vcoubard	607:e98331f1d6b5	697
vcoubard	607:e98331f1d6b5	698	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	699	/* ================ RTC ================ */
vcoubard	607:e98331f1d6b5	700	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	701
vcoubard	607:e98331f1d6b5	702
vcoubard	607:e98331f1d6b5	703	/**
vcoubard	607:e98331f1d6b5	704	* @brief Real time counter 0. (RTC)
vcoubard	607:e98331f1d6b5	705	*/
vcoubard	607:e98331f1d6b5	706
vcoubard	607:e98331f1d6b5	707	typedef struct { /!< RTC Structure /
vcoubard	607:e98331f1d6b5	708	__O uint32_t TASKS_START; /!< Start RTC Counter. /
vcoubard	607:e98331f1d6b5	709	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
vcoubard	607:e98331f1d6b5	710	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
vcoubard	607:e98331f1d6b5	711	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
vcoubard	607:e98331f1d6b5	712	__I uint32_t RESERVED0[60];
vcoubard	607:e98331f1d6b5	713	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
vcoubard	607:e98331f1d6b5	714	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
vcoubard	607:e98331f1d6b5	715	__I uint32_t RESERVED1[14];
vcoubard	607:e98331f1d6b5	716	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
vcoubard	607:e98331f1d6b5	717	__I uint32_t RESERVED2[109];
vcoubard	607:e98331f1d6b5	718	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	719	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	720	__I uint32_t RESERVED3[13];
vcoubard	607:e98331f1d6b5	721	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
vcoubard	607:e98331f1d6b5	722	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
vcoubard	607:e98331f1d6b5	723	the value of EVTEN. */
vcoubard	607:e98331f1d6b5	724	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
vcoubard	607:e98331f1d6b5	725	gives the value of EVTEN. */
vcoubard	607:e98331f1d6b5	726	__I uint32_t RESERVED4[110];
vcoubard	607:e98331f1d6b5	727	__I uint32_t COUNTER; /!< Current COUNTER value. /
vcoubard	607:e98331f1d6b5	728	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
vcoubard	607:e98331f1d6b5	729	Must be written when RTC is STOPed. */
vcoubard	607:e98331f1d6b5	730	__I uint32_t RESERVED5[13];
vcoubard	607:e98331f1d6b5	731	__IO uint32_t CC[4]; /!< Capture/compare registers. /
vcoubard	607:e98331f1d6b5	732	__I uint32_t RESERVED6[683];
vcoubard	607:e98331f1d6b5	733	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	734	} NRF_RTC_Type;
vcoubard	607:e98331f1d6b5	735
vcoubard	607:e98331f1d6b5	736
vcoubard	607:e98331f1d6b5	737	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	738	/* ================ TEMP ================ */
vcoubard	607:e98331f1d6b5	739	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	740
vcoubard	607:e98331f1d6b5	741
vcoubard	607:e98331f1d6b5	742	/**
vcoubard	607:e98331f1d6b5	743	* @brief Temperature Sensor. (TEMP)
vcoubard	607:e98331f1d6b5	744	*/
vcoubard	607:e98331f1d6b5	745
vcoubard	607:e98331f1d6b5	746	typedef struct { /!< TEMP Structure /
vcoubard	607:e98331f1d6b5	747	__O uint32_t TASKS_START; /!< Start temperature measurement. /
vcoubard	607:e98331f1d6b5	748	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
vcoubard	607:e98331f1d6b5	749	__I uint32_t RESERVED0[62];
vcoubard	607:e98331f1d6b5	750	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
vcoubard	607:e98331f1d6b5	751	__I uint32_t RESERVED1[128];
vcoubard	607:e98331f1d6b5	752	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	753	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	754	__I uint32_t RESERVED2[127];
vcoubard	607:e98331f1d6b5	755	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
vcoubard	607:e98331f1d6b5	756	__I uint32_t RESERVED3[700];
vcoubard	607:e98331f1d6b5	757	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	758	} NRF_TEMP_Type;
vcoubard	607:e98331f1d6b5	759
vcoubard	607:e98331f1d6b5	760
vcoubard	607:e98331f1d6b5	761	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	762	/* ================ RNG ================ */
vcoubard	607:e98331f1d6b5	763	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	764
vcoubard	607:e98331f1d6b5	765
vcoubard	607:e98331f1d6b5	766	/**
vcoubard	607:e98331f1d6b5	767	* @brief Random Number Generator. (RNG)
vcoubard	607:e98331f1d6b5	768	*/
vcoubard	607:e98331f1d6b5	769
vcoubard	607:e98331f1d6b5	770	typedef struct { /!< RNG Structure /
vcoubard	607:e98331f1d6b5	771	__O uint32_t TASKS_START; /!< Start the random number generator. /
vcoubard	607:e98331f1d6b5	772	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
vcoubard	607:e98331f1d6b5	773	__I uint32_t RESERVED0[62];
vcoubard	607:e98331f1d6b5	774	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
vcoubard	607:e98331f1d6b5	775	__I uint32_t RESERVED1[63];
vcoubard	607:e98331f1d6b5	776	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
vcoubard	607:e98331f1d6b5	777	__I uint32_t RESERVED2[64];
vcoubard	607:e98331f1d6b5	778	__IO uint32_t INTENSET; /!< Interrupt enable set register /
vcoubard	607:e98331f1d6b5	779	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
vcoubard	607:e98331f1d6b5	780	__I uint32_t RESERVED3[126];
vcoubard	607:e98331f1d6b5	781	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	607:e98331f1d6b5	782	__I uint32_t VALUE; /!< RNG random number. /
vcoubard	607:e98331f1d6b5	783	__I uint32_t RESERVED4[700];
vcoubard	607:e98331f1d6b5	784	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	785	} NRF_RNG_Type;
vcoubard	607:e98331f1d6b5	786
vcoubard	607:e98331f1d6b5	787
vcoubard	607:e98331f1d6b5	788	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	789	/* ================ ECB ================ */
vcoubard	607:e98331f1d6b5	790	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	791
vcoubard	607:e98331f1d6b5	792
vcoubard	607:e98331f1d6b5	793	/**
vcoubard	607:e98331f1d6b5	794	* @brief AES ECB Mode Encryption. (ECB)
vcoubard	607:e98331f1d6b5	795	*/
vcoubard	607:e98331f1d6b5	796
vcoubard	607:e98331f1d6b5	797	typedef struct { /!< ECB Structure /
vcoubard	607:e98331f1d6b5	798	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
vcoubard	607:e98331f1d6b5	799	will not initiate a new encryption and the ERRORECB event will
vcoubard	607:e98331f1d6b5	800	be triggered. */
vcoubard	607:e98331f1d6b5	801	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
vcoubard	607:e98331f1d6b5	802	this will will trigger the ERRORECB event. */
vcoubard	607:e98331f1d6b5	803	__I uint32_t RESERVED0[62];
vcoubard	607:e98331f1d6b5	804	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
vcoubard	607:e98331f1d6b5	805	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
vcoubard	607:e98331f1d6b5	806	error. */
vcoubard	607:e98331f1d6b5	807	__I uint32_t RESERVED1[127];
vcoubard	607:e98331f1d6b5	808	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	809	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	810	__I uint32_t RESERVED2[126];
vcoubard	607:e98331f1d6b5	811	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
vcoubard	607:e98331f1d6b5	812	__I uint32_t RESERVED3[701];
vcoubard	607:e98331f1d6b5	813	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	814	} NRF_ECB_Type;
vcoubard	607:e98331f1d6b5	815
vcoubard	607:e98331f1d6b5	816
vcoubard	607:e98331f1d6b5	817	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	818	/* ================ AAR ================ */
vcoubard	607:e98331f1d6b5	819	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	820
vcoubard	607:e98331f1d6b5	821
vcoubard	607:e98331f1d6b5	822	/**
vcoubard	607:e98331f1d6b5	823	* @brief Accelerated Address Resolver. (AAR)
vcoubard	607:e98331f1d6b5	824	*/
vcoubard	607:e98331f1d6b5	825
vcoubard	607:e98331f1d6b5	826	typedef struct { /!< AAR Structure /
vcoubard	607:e98331f1d6b5	827	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
vcoubard	607:e98331f1d6b5	828	data structure. */
vcoubard	607:e98331f1d6b5	829	__I uint32_t RESERVED0;
vcoubard	607:e98331f1d6b5	830	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
vcoubard	607:e98331f1d6b5	831	__I uint32_t RESERVED1[61];
vcoubard	607:e98331f1d6b5	832	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
vcoubard	607:e98331f1d6b5	833	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
vcoubard	607:e98331f1d6b5	834	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
vcoubard	607:e98331f1d6b5	835	__I uint32_t RESERVED2[126];
vcoubard	607:e98331f1d6b5	836	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	837	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	838	__I uint32_t RESERVED3[61];
vcoubard	607:e98331f1d6b5	839	__I uint32_t STATUS; /!< Resolution status. /
vcoubard	607:e98331f1d6b5	840	__I uint32_t RESERVED4[63];
vcoubard	607:e98331f1d6b5	841	__IO uint32_t ENABLE; /!< Enable AAR. /
vcoubard	607:e98331f1d6b5	842	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
vcoubard	607:e98331f1d6b5	843	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
vcoubard	607:e98331f1d6b5	844	__I uint32_t RESERVED5;
vcoubard	607:e98331f1d6b5	845	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
vcoubard	607:e98331f1d6b5	846	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard	607:e98331f1d6b5	847	during resolution. A minimum of 3 bytes must be reserved. */
vcoubard	607:e98331f1d6b5	848	__I uint32_t RESERVED6[697];
vcoubard	607:e98331f1d6b5	849	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	850	} NRF_AAR_Type;
vcoubard	607:e98331f1d6b5	851
vcoubard	607:e98331f1d6b5	852
vcoubard	607:e98331f1d6b5	853	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	854	/* ================ CCM ================ */
vcoubard	607:e98331f1d6b5	855	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	856
vcoubard	607:e98331f1d6b5	857
vcoubard	607:e98331f1d6b5	858	/**
vcoubard	607:e98331f1d6b5	859	* @brief AES CCM Mode Encryption. (CCM)
vcoubard	607:e98331f1d6b5	860	*/
vcoubard	607:e98331f1d6b5	861
vcoubard	607:e98331f1d6b5	862	typedef struct { /!< CCM Structure /
vcoubard	607:e98331f1d6b5	863	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
vcoubard	607:e98331f1d6b5	864	itself when completed. */
vcoubard	607:e98331f1d6b5	865	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
vcoubard	607:e98331f1d6b5	866	completed. */
vcoubard	607:e98331f1d6b5	867	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
vcoubard	607:e98331f1d6b5	868	__I uint32_t RESERVED0[61];
vcoubard	607:e98331f1d6b5	869	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
vcoubard	607:e98331f1d6b5	870	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
vcoubard	607:e98331f1d6b5	871	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
vcoubard	607:e98331f1d6b5	872	__I uint32_t RESERVED1[61];
vcoubard	607:e98331f1d6b5	873	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
vcoubard	607:e98331f1d6b5	874	__I uint32_t RESERVED2[64];
vcoubard	607:e98331f1d6b5	875	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	876	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	877	__I uint32_t RESERVED3[61];
vcoubard	607:e98331f1d6b5	878	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
vcoubard	607:e98331f1d6b5	879	__I uint32_t RESERVED4[63];
vcoubard	607:e98331f1d6b5	880	__IO uint32_t ENABLE; /!< CCM enable. /
vcoubard	607:e98331f1d6b5	881	__IO uint32_t MODE; /!< Operation mode. /
vcoubard	607:e98331f1d6b5	882	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
vcoubard	607:e98331f1d6b5	883	__IO uint32_t INPTR; /!< Pointer to the input packet. /
vcoubard	607:e98331f1d6b5	884	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
vcoubard	607:e98331f1d6b5	885	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
vcoubard	607:e98331f1d6b5	886	during resolution. A minimum of 43 bytes must be reserved. */
vcoubard	607:e98331f1d6b5	887	__I uint32_t RESERVED5[697];
vcoubard	607:e98331f1d6b5	888	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	889	} NRF_CCM_Type;
vcoubard	607:e98331f1d6b5	890
vcoubard	607:e98331f1d6b5	891
vcoubard	607:e98331f1d6b5	892	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	893	/* ================ WDT ================ */
vcoubard	607:e98331f1d6b5	894	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	895
vcoubard	607:e98331f1d6b5	896
vcoubard	607:e98331f1d6b5	897	/**
vcoubard	607:e98331f1d6b5	898	* @brief Watchdog Timer. (WDT)
vcoubard	607:e98331f1d6b5	899	*/
vcoubard	607:e98331f1d6b5	900
vcoubard	607:e98331f1d6b5	901	typedef struct { /!< WDT Structure /
vcoubard	607:e98331f1d6b5	902	__O uint32_t TASKS_START; /!< Start the watchdog. /
vcoubard	607:e98331f1d6b5	903	__I uint32_t RESERVED0[63];
vcoubard	607:e98331f1d6b5	904	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
vcoubard	607:e98331f1d6b5	905	__I uint32_t RESERVED1[128];
vcoubard	607:e98331f1d6b5	906	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	907	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	908	__I uint32_t RESERVED2[61];
vcoubard	607:e98331f1d6b5	909	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
vcoubard	607:e98331f1d6b5	910	__I uint32_t REQSTATUS; /!< Request status. /
vcoubard	607:e98331f1d6b5	911	__I uint32_t RESERVED3[63];
vcoubard	607:e98331f1d6b5	912	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
vcoubard	607:e98331f1d6b5	913	__IO uint32_t RREN; /!< Reload request enable. /
vcoubard	607:e98331f1d6b5	914	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	607:e98331f1d6b5	915	__I uint32_t RESERVED4[60];
vcoubard	607:e98331f1d6b5	916	__O uint32_t RR[8]; /!< Reload requests registers. /
vcoubard	607:e98331f1d6b5	917	__I uint32_t RESERVED5[631];
vcoubard	607:e98331f1d6b5	918	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	919	} NRF_WDT_Type;
vcoubard	607:e98331f1d6b5	920
vcoubard	607:e98331f1d6b5	921
vcoubard	607:e98331f1d6b5	922	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	923	/* ================ QDEC ================ */
vcoubard	607:e98331f1d6b5	924	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	925
vcoubard	607:e98331f1d6b5	926
vcoubard	607:e98331f1d6b5	927	/**
vcoubard	607:e98331f1d6b5	928	* @brief Rotary decoder. (QDEC)
vcoubard	607:e98331f1d6b5	929	*/
vcoubard	607:e98331f1d6b5	930
vcoubard	607:e98331f1d6b5	931	typedef struct { /!< QDEC Structure /
vcoubard	607:e98331f1d6b5	932	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
vcoubard	607:e98331f1d6b5	933	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
vcoubard	607:e98331f1d6b5	934	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
vcoubard	607:e98331f1d6b5	935	and clears the ACC registers. */
vcoubard	607:e98331f1d6b5	936	__I uint32_t RESERVED0[61];
vcoubard	607:e98331f1d6b5	937	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
vcoubard	607:e98331f1d6b5	938	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
vcoubard	607:e98331f1d6b5	939	ACC register different than zero. */
vcoubard	607:e98331f1d6b5	940	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
vcoubard	607:e98331f1d6b5	941	__I uint32_t RESERVED1[61];
vcoubard	607:e98331f1d6b5	942	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
vcoubard	607:e98331f1d6b5	943	__I uint32_t RESERVED2[64];
vcoubard	607:e98331f1d6b5	944	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	945	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	946	__I uint32_t RESERVED3[125];
vcoubard	607:e98331f1d6b5	947	__IO uint32_t ENABLE; /!< Enable the QDEC. /
vcoubard	607:e98331f1d6b5	948	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
vcoubard	607:e98331f1d6b5	949	__IO uint32_t SAMPLEPER; /!< Sample period. /
vcoubard	607:e98331f1d6b5	950	__I int32_t SAMPLE; /!< Motion sample value. /
vcoubard	607:e98331f1d6b5	951	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
vcoubard	607:e98331f1d6b5	952	__I int32_t ACC; /!< Accumulated valid transitions register. /
vcoubard	607:e98331f1d6b5	953	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
vcoubard	607:e98331f1d6b5	954	task. */
vcoubard	607:e98331f1d6b5	955	__IO uint32_t PSELLED; /!< Pin select for LED output. /
vcoubard	607:e98331f1d6b5	956	__IO uint32_t PSELA; /!< Pin select for phase A input. /
vcoubard	607:e98331f1d6b5	957	__IO uint32_t PSELB; /!< Pin select for phase B input. /
vcoubard	607:e98331f1d6b5	958	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
vcoubard	607:e98331f1d6b5	959	__I uint32_t RESERVED4[5];
vcoubard	607:e98331f1d6b5	960	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
vcoubard	607:e98331f1d6b5	961	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
vcoubard	607:e98331f1d6b5	962	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
vcoubard	607:e98331f1d6b5	963	task. */
vcoubard	607:e98331f1d6b5	964	__I uint32_t RESERVED5[684];
vcoubard	607:e98331f1d6b5	965	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	966	} NRF_QDEC_Type;
vcoubard	607:e98331f1d6b5	967
vcoubard	607:e98331f1d6b5	968
vcoubard	607:e98331f1d6b5	969	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	970	/* ================ LPCOMP ================ */
vcoubard	607:e98331f1d6b5	971	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	972
vcoubard	607:e98331f1d6b5	973
vcoubard	607:e98331f1d6b5	974	/**
vcoubard	607:e98331f1d6b5	975	* @brief Low power comparator. (LPCOMP)
vcoubard	607:e98331f1d6b5	976	*/
vcoubard	607:e98331f1d6b5	977
vcoubard	607:e98331f1d6b5	978	typedef struct { /!< LPCOMP Structure /
vcoubard	607:e98331f1d6b5	979	__O uint32_t TASKS_START; /!< Start the comparator. /
vcoubard	607:e98331f1d6b5	980	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
vcoubard	607:e98331f1d6b5	981	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
vcoubard	607:e98331f1d6b5	982	__I uint32_t RESERVED0[61];
vcoubard	607:e98331f1d6b5	983	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
vcoubard	607:e98331f1d6b5	984	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
vcoubard	607:e98331f1d6b5	985	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
vcoubard	607:e98331f1d6b5	986	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
vcoubard	607:e98331f1d6b5	987	__I uint32_t RESERVED1[60];
vcoubard	607:e98331f1d6b5	988	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
vcoubard	607:e98331f1d6b5	989	__I uint32_t RESERVED2[64];
vcoubard	607:e98331f1d6b5	990	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
vcoubard	607:e98331f1d6b5	991	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
vcoubard	607:e98331f1d6b5	992	__I uint32_t RESERVED3[61];
vcoubard	607:e98331f1d6b5	993	__I uint32_t RESULT; /!< Result of last compare. /
vcoubard	607:e98331f1d6b5	994	__I uint32_t RESERVED4[63];
vcoubard	607:e98331f1d6b5	995	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
vcoubard	607:e98331f1d6b5	996	__IO uint32_t PSEL; /!< Input pin select. /
vcoubard	607:e98331f1d6b5	997	__IO uint32_t REFSEL; /!< Reference select. /
vcoubard	607:e98331f1d6b5	998	__IO uint32_t EXTREFSEL; /!< External reference select. /
vcoubard	607:e98331f1d6b5	999	__I uint32_t RESERVED5[4];
vcoubard	607:e98331f1d6b5	1000	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
vcoubard	607:e98331f1d6b5	1001	__I uint32_t RESERVED6[694];
vcoubard	607:e98331f1d6b5	1002	__IO uint32_t POWER; /!< Peripheral power control. /
vcoubard	607:e98331f1d6b5	1003	} NRF_LPCOMP_Type;
vcoubard	607:e98331f1d6b5	1004
vcoubard	607:e98331f1d6b5	1005
vcoubard	607:e98331f1d6b5	1006	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1007	/* ================ SWI ================ */
vcoubard	607:e98331f1d6b5	1008	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1009
vcoubard	607:e98331f1d6b5	1010
vcoubard	607:e98331f1d6b5	1011	/**
vcoubard	607:e98331f1d6b5	1012	* @brief SW Interrupts. (SWI)
vcoubard	607:e98331f1d6b5	1013	*/
vcoubard	607:e98331f1d6b5	1014
vcoubard	607:e98331f1d6b5	1015	typedef struct { /!< SWI Structure /
vcoubard	607:e98331f1d6b5	1016	__I uint32_t UNUSED; /!< Unused. /
vcoubard	607:e98331f1d6b5	1017	} NRF_SWI_Type;
vcoubard	607:e98331f1d6b5	1018
vcoubard	607:e98331f1d6b5	1019
vcoubard	607:e98331f1d6b5	1020	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1021	/* ================ NVMC ================ */
vcoubard	607:e98331f1d6b5	1022	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1023
vcoubard	607:e98331f1d6b5	1024
vcoubard	607:e98331f1d6b5	1025	/**
vcoubard	607:e98331f1d6b5	1026	* @brief Non Volatile Memory Controller. (NVMC)
vcoubard	607:e98331f1d6b5	1027	*/
vcoubard	607:e98331f1d6b5	1028
vcoubard	607:e98331f1d6b5	1029	typedef struct { /!< NVMC Structure /
vcoubard	607:e98331f1d6b5	1030	__I uint32_t RESERVED0[256];
vcoubard	607:e98331f1d6b5	1031	__I uint32_t READY; /!< Ready flag. /
vcoubard	607:e98331f1d6b5	1032	__I uint32_t RESERVED1[64];
vcoubard	607:e98331f1d6b5	1033	__IO uint32_t CONFIG; /!< Configuration register. /
vcoubard	607:e98331f1d6b5	1034
vcoubard	607:e98331f1d6b5	1035	union {
vcoubard	607:e98331f1d6b5	1036	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
vcoubard	607:e98331f1d6b5	1037	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
vcoubard	607:e98331f1d6b5	1038	};
vcoubard	607:e98331f1d6b5	1039	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
vcoubard	607:e98331f1d6b5	1040	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
vcoubard	607:e98331f1d6b5	1041	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
vcoubard	607:e98331f1d6b5	1042	} NRF_NVMC_Type;
vcoubard	607:e98331f1d6b5	1043
vcoubard	607:e98331f1d6b5	1044
vcoubard	607:e98331f1d6b5	1045	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1046	/* ================ PPI ================ */
vcoubard	607:e98331f1d6b5	1047	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1048
vcoubard	607:e98331f1d6b5	1049
vcoubard	607:e98331f1d6b5	1050	/**
vcoubard	607:e98331f1d6b5	1051	* @brief PPI controller. (PPI)
vcoubard	607:e98331f1d6b5	1052	*/
vcoubard	607:e98331f1d6b5	1053
vcoubard	607:e98331f1d6b5	1054	typedef struct { /!< PPI Structure /
vcoubard	607:e98331f1d6b5	1055	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
vcoubard	607:e98331f1d6b5	1056	__I uint32_t RESERVED0[312];
vcoubard	607:e98331f1d6b5	1057	__IO uint32_t CHEN; /!< Channel enable. /
vcoubard	607:e98331f1d6b5	1058	__IO uint32_t CHENSET; /!< Channel enable set. /
vcoubard	607:e98331f1d6b5	1059	__IO uint32_t CHENCLR; /!< Channel enable clear. /
vcoubard	607:e98331f1d6b5	1060	__I uint32_t RESERVED1;
vcoubard	607:e98331f1d6b5	1061	PPI_CH_Type CH[16]; /!< PPI Channel. /
vcoubard	607:e98331f1d6b5	1062	__I uint32_t RESERVED2[156];
vcoubard	607:e98331f1d6b5	1063	__IO uint32_t CHG[4]; /!< Channel group configuration. /
vcoubard	607:e98331f1d6b5	1064	} NRF_PPI_Type;
vcoubard	607:e98331f1d6b5	1065
vcoubard	607:e98331f1d6b5	1066
vcoubard	607:e98331f1d6b5	1067	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1068	/* ================ FICR ================ */
vcoubard	607:e98331f1d6b5	1069	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1070
vcoubard	607:e98331f1d6b5	1071
vcoubard	607:e98331f1d6b5	1072	/**
vcoubard	607:e98331f1d6b5	1073	* @brief Factory Information Configuration. (FICR)
vcoubard	607:e98331f1d6b5	1074	*/
vcoubard	607:e98331f1d6b5	1075
vcoubard	607:e98331f1d6b5	1076	typedef struct { /!< FICR Structure /
vcoubard	607:e98331f1d6b5	1077	__I uint32_t RESERVED0[4];
vcoubard	607:e98331f1d6b5	1078	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
vcoubard	607:e98331f1d6b5	1079	__I uint32_t CODESIZE; /!< Code memory size in pages. /
vcoubard	607:e98331f1d6b5	1080	__I uint32_t RESERVED1[4];
vcoubard	607:e98331f1d6b5	1081	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
vcoubard	607:e98331f1d6b5	1082	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
vcoubard	607:e98331f1d6b5	1083	__I uint32_t RESERVED2;
vcoubard	607:e98331f1d6b5	1084	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
vcoubard	607:e98331f1d6b5	1085
vcoubard	607:e98331f1d6b5	1086	union {
vcoubard	607:e98331f1d6b5	1087	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
vcoubard	607:e98331f1d6b5	1088	kept for backward compatinility purposes. Use SIZERAMBLOCKS
vcoubard	607:e98331f1d6b5	1089	instead. */
vcoubard	607:e98331f1d6b5	1090	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
vcoubard	607:e98331f1d6b5	1091	};
vcoubard	607:e98331f1d6b5	1092	__I uint32_t RESERVED3[5];
vcoubard	607:e98331f1d6b5	1093	__I uint32_t CONFIGID; /!< Configuration identifier. /
vcoubard	607:e98331f1d6b5	1094	__I uint32_t DEVICEID[2]; /!< Device identifier. /
vcoubard	607:e98331f1d6b5	1095	__I uint32_t RESERVED4[6];
vcoubard	607:e98331f1d6b5	1096	__I uint32_t ER[4]; /!< Encryption root. /
vcoubard	607:e98331f1d6b5	1097	__I uint32_t IR[4]; /!< Identity root. /
vcoubard	607:e98331f1d6b5	1098	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
vcoubard	607:e98331f1d6b5	1099	__I uint32_t DEVICEADDR[2]; /!< Device address. /
vcoubard	607:e98331f1d6b5	1100	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
vcoubard	607:e98331f1d6b5	1101	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
vcoubard	607:e98331f1d6b5	1102	mode. */
vcoubard	607:e98331f1d6b5	1103	__I uint32_t RESERVED5[10];
vcoubard	607:e98331f1d6b5	1104	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
vcoubard	607:e98331f1d6b5	1105	mode. */
vcoubard	607:e98331f1d6b5	1106	} NRF_FICR_Type;
vcoubard	607:e98331f1d6b5	1107
vcoubard	607:e98331f1d6b5	1108
vcoubard	607:e98331f1d6b5	1109	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1110	/* ================ UICR ================ */
vcoubard	607:e98331f1d6b5	1111	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1112
vcoubard	607:e98331f1d6b5	1113
vcoubard	607:e98331f1d6b5	1114	/**
vcoubard	607:e98331f1d6b5	1115	* @brief User Information Configuration. (UICR)
vcoubard	607:e98331f1d6b5	1116	*/
vcoubard	607:e98331f1d6b5	1117
vcoubard	607:e98331f1d6b5	1118	typedef struct { /!< UICR Structure /
vcoubard	607:e98331f1d6b5	1119	__IO uint32_t CLENR0; /!< Length of code region 0. /
vcoubard	607:e98331f1d6b5	1120	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
vcoubard	607:e98331f1d6b5	1121	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
vcoubard	607:e98331f1d6b5	1122	__I uint32_t RESERVED0;
vcoubard	607:e98331f1d6b5	1123	__I uint32_t FWID; /!< Firmware ID. /
vcoubard	607:e98331f1d6b5	1124
vcoubard	607:e98331f1d6b5	1125	union {
vcoubard	607:e98331f1d6b5	1126	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
vcoubard	607:e98331f1d6b5	1127	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
vcoubard	607:e98331f1d6b5	1128	};
vcoubard	607:e98331f1d6b5	1129	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
vcoubard	607:e98331f1d6b5	1130	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
vcoubard	607:e98331f1d6b5	1131	} NRF_UICR_Type;
vcoubard	607:e98331f1d6b5	1132
vcoubard	607:e98331f1d6b5	1133
vcoubard	607:e98331f1d6b5	1134	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1135	/* ================ GPIO ================ */
vcoubard	607:e98331f1d6b5	1136	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1137
vcoubard	607:e98331f1d6b5	1138
vcoubard	607:e98331f1d6b5	1139	/**
vcoubard	607:e98331f1d6b5	1140	* @brief General purpose input and output. (GPIO)
vcoubard	607:e98331f1d6b5	1141	*/
vcoubard	607:e98331f1d6b5	1142
vcoubard	607:e98331f1d6b5	1143	typedef struct { /!< GPIO Structure /
vcoubard	607:e98331f1d6b5	1144	__I uint32_t RESERVED0[321];
vcoubard	607:e98331f1d6b5	1145	__IO uint32_t OUT; /!< Write GPIO port. /
vcoubard	607:e98331f1d6b5	1146	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
vcoubard	607:e98331f1d6b5	1147	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
vcoubard	607:e98331f1d6b5	1148	__I uint32_t IN; /!< Read GPIO port. /
vcoubard	607:e98331f1d6b5	1149	__IO uint32_t DIR; /!< Direction of GPIO pins. /
vcoubard	607:e98331f1d6b5	1150	__IO uint32_t DIRSET; /!< DIR set register. /
vcoubard	607:e98331f1d6b5	1151	__IO uint32_t DIRCLR; /!< DIR clear register. /
vcoubard	607:e98331f1d6b5	1152	__I uint32_t RESERVED1[120];
vcoubard	607:e98331f1d6b5	1153	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
vcoubard	607:e98331f1d6b5	1154	} NRF_GPIO_Type;
vcoubard	607:e98331f1d6b5	1155
vcoubard	607:e98331f1d6b5	1156
vcoubard	607:e98331f1d6b5	1157	/* -------------------- End of section using anonymous unions ------------------- */
vcoubard	607:e98331f1d6b5	1158	#if defined(__CC_ARM)
vcoubard	607:e98331f1d6b5	1159	#pragma pop
vcoubard	607:e98331f1d6b5	1160	#elif defined(__ICCARM__)
vcoubard	607:e98331f1d6b5	1161	/* leave anonymous unions enabled */
vcoubard	607:e98331f1d6b5	1162	#elif defined(__GNUC__)
vcoubard	607:e98331f1d6b5	1163	/* anonymous unions are enabled by default */
vcoubard	607:e98331f1d6b5	1164	#elif defined(__TMS470__)
vcoubard	607:e98331f1d6b5	1165	/* anonymous unions are enabled by default */
vcoubard	607:e98331f1d6b5	1166	#elif defined(__TASKING__)
vcoubard	607:e98331f1d6b5	1167	#pragma warning restore
vcoubard	607:e98331f1d6b5	1168	#else
vcoubard	607:e98331f1d6b5	1169	#warning Not supported compiler type
vcoubard	607:e98331f1d6b5	1170	#endif
vcoubard	607:e98331f1d6b5	1171
vcoubard	607:e98331f1d6b5	1172
vcoubard	607:e98331f1d6b5	1173
vcoubard	607:e98331f1d6b5	1174
vcoubard	607:e98331f1d6b5	1175	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1176	/* ================ Peripheral memory map ================ */
vcoubard	607:e98331f1d6b5	1177	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1178
vcoubard	607:e98331f1d6b5	1179	#define NRF_POWER_BASE 0x40000000UL
vcoubard	607:e98331f1d6b5	1180	#define NRF_CLOCK_BASE 0x40000000UL
vcoubard	607:e98331f1d6b5	1181	#define NRF_MPU_BASE 0x40000000UL
vcoubard	607:e98331f1d6b5	1182	#define NRF_AMLI_BASE 0x40000000UL
vcoubard	607:e98331f1d6b5	1183	#define NRF_RADIO_BASE 0x40001000UL
vcoubard	607:e98331f1d6b5	1184	#define NRF_UART0_BASE 0x40002000UL
vcoubard	607:e98331f1d6b5	1185	#define NRF_SPI0_BASE 0x40003000UL
vcoubard	607:e98331f1d6b5	1186	#define NRF_TWI0_BASE 0x40003000UL
vcoubard	607:e98331f1d6b5	1187	#define NRF_SPI1_BASE 0x40004000UL
vcoubard	607:e98331f1d6b5	1188	#define NRF_TWI1_BASE 0x40004000UL
vcoubard	607:e98331f1d6b5	1189	#define NRF_SPIS1_BASE 0x40004000UL
vcoubard	607:e98331f1d6b5	1190	#define NRF_SPIM1_BASE 0x40004000UL
vcoubard	607:e98331f1d6b5	1191	#define NRF_GPIOTE_BASE 0x40006000UL
vcoubard	607:e98331f1d6b5	1192	#define NRF_ADC_BASE 0x40007000UL
vcoubard	607:e98331f1d6b5	1193	#define NRF_TIMER0_BASE 0x40008000UL
vcoubard	607:e98331f1d6b5	1194	#define NRF_TIMER1_BASE 0x40009000UL
vcoubard	607:e98331f1d6b5	1195	#define NRF_TIMER2_BASE 0x4000A000UL
vcoubard	607:e98331f1d6b5	1196	#define NRF_RTC0_BASE 0x4000B000UL
vcoubard	607:e98331f1d6b5	1197	#define NRF_TEMP_BASE 0x4000C000UL
vcoubard	607:e98331f1d6b5	1198	#define NRF_RNG_BASE 0x4000D000UL
vcoubard	607:e98331f1d6b5	1199	#define NRF_ECB_BASE 0x4000E000UL
vcoubard	607:e98331f1d6b5	1200	#define NRF_AAR_BASE 0x4000F000UL
vcoubard	607:e98331f1d6b5	1201	#define NRF_CCM_BASE 0x4000F000UL
vcoubard	607:e98331f1d6b5	1202	#define NRF_WDT_BASE 0x40010000UL
vcoubard	607:e98331f1d6b5	1203	#define NRF_RTC1_BASE 0x40011000UL
vcoubard	607:e98331f1d6b5	1204	#define NRF_QDEC_BASE 0x40012000UL
vcoubard	607:e98331f1d6b5	1205	#define NRF_LPCOMP_BASE 0x40013000UL
vcoubard	607:e98331f1d6b5	1206	#define NRF_SWI_BASE 0x40014000UL
vcoubard	607:e98331f1d6b5	1207	#define NRF_NVMC_BASE 0x4001E000UL
vcoubard	607:e98331f1d6b5	1208	#define NRF_PPI_BASE 0x4001F000UL
vcoubard	607:e98331f1d6b5	1209	#define NRF_FICR_BASE 0x10000000UL
vcoubard	607:e98331f1d6b5	1210	#define NRF_UICR_BASE 0x10001000UL
vcoubard	607:e98331f1d6b5	1211	#define NRF_GPIO_BASE 0x50000000UL
vcoubard	607:e98331f1d6b5	1212
vcoubard	607:e98331f1d6b5	1213
vcoubard	607:e98331f1d6b5	1214	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1215	/* ================ Peripheral declaration ================ */
vcoubard	607:e98331f1d6b5	1216	/* ================================================================================ */
vcoubard	607:e98331f1d6b5	1217
vcoubard	607:e98331f1d6b5	1218	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
vcoubard	607:e98331f1d6b5	1219	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
vcoubard	607:e98331f1d6b5	1220	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
vcoubard	607:e98331f1d6b5	1221	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
vcoubard	607:e98331f1d6b5	1222	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
vcoubard	607:e98331f1d6b5	1223	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
vcoubard	607:e98331f1d6b5	1224	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
vcoubard	607:e98331f1d6b5	1225	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
vcoubard	607:e98331f1d6b5	1226	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
vcoubard	607:e98331f1d6b5	1227	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
vcoubard	607:e98331f1d6b5	1228	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
vcoubard	607:e98331f1d6b5	1229	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
vcoubard	607:e98331f1d6b5	1230	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
vcoubard	607:e98331f1d6b5	1231	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
vcoubard	607:e98331f1d6b5	1232	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
vcoubard	607:e98331f1d6b5	1233	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
vcoubard	607:e98331f1d6b5	1234	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
vcoubard	607:e98331f1d6b5	1235	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
vcoubard	607:e98331f1d6b5	1236	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
vcoubard	607:e98331f1d6b5	1237	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
vcoubard	607:e98331f1d6b5	1238	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
vcoubard	607:e98331f1d6b5	1239	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
vcoubard	607:e98331f1d6b5	1240	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
vcoubard	607:e98331f1d6b5	1241	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
vcoubard	607:e98331f1d6b5	1242	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
vcoubard	607:e98331f1d6b5	1243	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
vcoubard	607:e98331f1d6b5	1244	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
vcoubard	607:e98331f1d6b5	1245	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
vcoubard	607:e98331f1d6b5	1246	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
vcoubard	607:e98331f1d6b5	1247	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
vcoubard	607:e98331f1d6b5	1248	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
vcoubard	607:e98331f1d6b5	1249	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
vcoubard	607:e98331f1d6b5	1250	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
vcoubard	607:e98331f1d6b5	1251
vcoubard	607:e98331f1d6b5	1252
vcoubard	607:e98331f1d6b5	1253	/** @} / / End of group Device_Peripheral_Registers */
vcoubard	607:e98331f1d6b5	1254	/** @} / / End of group nrf51 */
vcoubard	607:e98331f1d6b5	1255	/** @} / / End of group Nordic Semiconductor */
vcoubard	607:e98331f1d6b5	1256
vcoubard	607:e98331f1d6b5	1257	#ifdef __cplusplus
vcoubard	607:e98331f1d6b5	1258	}
vcoubard	607:e98331f1d6b5	1259	#endif
vcoubard	607:e98331f1d6b5	1260
vcoubard	607:e98331f1d6b5	1261
vcoubard	607:e98331f1d6b5	1262	#endif /* nrf51_H */
vcoubard	607:e98331f1d6b5	1263

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Type:	Library
Created:	31 Aug 2016
Imports:	1
Forks:	0
Commits:	617
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source/nordic_sdk/components/device/nrf51.h@616:b52326e38ebd, 2016-08-31 (annotated)

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