Johannes Stratmann
added prescaler for 16 bit pwm in LPC1347 target
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mbed official
Diff: targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h
- Revision:
- 80:bdf1132a57cf
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
diff -r 7f02dc905b68 -r bdf1132a57cf targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h
--- a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h Wed Mar 02 10:15:13 2016 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h Wed Mar 02 14:30:11 2016 +0000
@@ -1,41 +1,37 @@
/* MPS2 CMSIS Library
*
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
+*
+* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
-*
-* 1. Redistributions of source code must retain the above copyright notice,
+*
+* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
-*
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
-*
-* 3. Neither the name of the copyright holder nor the names of its contributors
-* may be used to endorse or promote products derived from this software without
+*
+* 3. Neither the name of the copyright holder nor the names of its contributors
+* may be used to endorse or promote products derived from this software without
* specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* @file CMSDK_CM4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
* Device CMSDK_CM4
-* @version V3.01
-* @date 06. March 2012
-*
-* @note configured for CM7 without FPU
*
*******************************************************************************/
@@ -45,80 +41,57 @@
#ifdef __cplusplus
extern "C" {
-#endif
-
-/** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions
- This file defines all structures and symbols for CMSDK_CM4:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - Peripheral definitions
- @{
-*/
+#endif
-/******************************************************************************/
-/* Processor and Core Peripherals */
-/******************************************************************************/
-/** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions
- Configuration of the Cortex-M4 Processor and Core Peripherals
- @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
+/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
-/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-/****** CMSDK Specific Interrupt Numbers *******************************************************/
- UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
- UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
- UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
- UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
- UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
- UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
-// UARTRX3_IRQn = 6, /*!< UART 2 RX Interrupt //only used in extended version */
-// UARTTX3_IRQn = 7, /*!< UART 2 TX Interrupt //only used in extended version */
- PORT0_ALL_IRQn = 6, /*!< Port 1 combined Interrupt */
- PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
- TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
- TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
- DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
- SPI_IRQn = 11, /*!< SPI Interrupt */
- UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
- ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
- I2S_IRQn = 14, /*!< I2S Interrupt */
- TSC_IRQn = 15, /* Touch Screen Interrupt */
-// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
- PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
- PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
- PORT0_2_IRQn = 18,
- PORT0_3_IRQn = 19,
- PORT0_4_IRQn = 20,
- PORT0_5_IRQn = 21,
- PORT0_6_IRQn = 22,
- PORT0_7_IRQn = 23,
- PORT0_8_IRQn = 24,
- PORT0_9_IRQn = 25,
- PORT0_10_IRQn = 26,
- PORT0_11_IRQn = 27,
- PORT0_12_IRQn = 28,
- PORT0_13_IRQn = 29,
- PORT0_14_IRQn = 30,
- PORT0_15_IRQn = 31,
+/****** CMSDK Specific Interrupt Numbers *********************************************************/
+ UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
+ UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
+ UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
+ UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
+ UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
+ UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
+ PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
+ PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
+ TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
+ SPI_IRQn = 11, /*!< SPI Interrupt */
+ UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
+ ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
+ I2S_IRQn = 14, /*!< I2S Interrupt */
+ TSC_IRQn = 15, /*!< Touch Screen Interrupt */
+ PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
+ PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
+ UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
+ UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
+ UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
+ UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
+ ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
+ SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
+ PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
+ PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
+ PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
+ PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
+ PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
+ PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
+ PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
+ PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
} IRQn_Type;
@@ -285,23 +258,23 @@
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
- // <o.7> TimerEn: Timer Enable
- // <o.6> TimerMode: Timer Mode
- // <0=> Freerunning-mode
- // <1=> Periodic mode
- // <o.5> IntEnable: Interrupt Enable
- // <o.2..3> TimerPre: Timer Prescale
- // <0=> / 1
- // <1=> / 16
- // <2=> / 256
- // <3=> Undefined!
- // <o.1> TimerSize: Timer Size
- // <0=> 16-bit counter
- // <1=> 32-bit counter
- // <o.0> OneShot: One-shoot mode
- // <0=> Wrapping mode
- // <1=> One-shot mode
- // </h>
+ /* <o.7> TimerEn: Timer Enable */
+ /* <o.6> TimerMode: Timer Mode */
+ /* <0=> Freerunning-mode */
+ /* <1=> Periodic mode */
+ /* <o.5> IntEnable: Interrupt Enable */
+ /* <o.2..3> TimerPre: Timer Prescale */
+ /* <0=> / 1 */
+ /* <1=> / 16 */
+ /* <2=> / 256 */
+ /* <3=> Undefined! */
+ /* <o.1> TimerSize: Timer Size */
+ /* <0=> 16-bit counter */
+ /* <1=> 32-bit counter */
+ /* <o.0> OneShot: One-shoot mode */
+ /* <0=> Wrapping mode */
+ /* <1=> One-shot mode */
+ /* </h> */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
@@ -310,23 +283,23 @@
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
- // <o.7> TimerEn: Timer Enable
- // <o.6> TimerMode: Timer Mode
- // <0=> Freerunning-mode
- // <1=> Periodic mode
- // <o.5> IntEnable: Interrupt Enable
- // <o.2..3> TimerPre: Timer Prescale
- // <0=> / 1
- // <1=> / 16
- // <2=> / 256
- // <3=> Undefined!
- // <o.1> TimerSize: Timer Size
- // <0=> 16-bit counter
- // <1=> 32-bit counter
- // <o.0> OneShot: One-shoot mode
- // <0=> Wrapping mode
- // <1=> One-shot mode
- // </h>
+ /* <o.7> TimerEn: Timer Enable */
+ /* <o.6> TimerMode: Timer Mode */
+ /* <0=> Freerunning-mode */
+ /* <1=> Periodic mode */
+ /* <o.5> IntEnable: Interrupt Enable */
+ /* <o.2..3> TimerPre: Timer Prescale */
+ /* <0=> / 1 */
+ /* <1=> / 16 */
+ /* <2=> / 256 */
+ /* <3=> Undefined! */
+ /* <o.1> TimerSize: Timer Size */
+ /* <0=> 16-bit counter */
+ /* <1=> 32-bit counter */
+ /* <o.0> OneShot: One-shoot mode */
+ /* <0=> Wrapping mode */
+ /* <1=> One-shot mode */
+ /* </h> */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
@@ -413,23 +386,23 @@
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
- // <o.7> TimerEn: Timer Enable
- // <o.6> TimerMode: Timer Mode
- // <0=> Freerunning-mode
- // <1=> Periodic mode
- // <o.5> IntEnable: Interrupt Enable
- // <o.2..3> TimerPre: Timer Prescale
- // <0=> / 1
- // <1=> / 16
- // <2=> / 256
- // <3=> Undefined!
- // <o.1> TimerSize: Timer Size
- // <0=> 16-bit counter
- // <1=> 32-bit counter
- // <o.0> OneShot: One-shoot mode
- // <0=> Wrapping mode
- // <1=> One-shot mode
- // </h>
+ /* <o.7> TimerEn: Timer Enable */
+ /* <o.6> TimerMode: Timer Mode */
+ /* <0=> Freerunning-mode */
+ /* <1=> Periodic mode */
+ /* <o.5> IntEnable: Interrupt Enable */
+ /* <o.2..3> TimerPre: Timer Prescale */
+ /* <0=> / 1 */
+ /* <1=> / 16 */
+ /* <2=> / 256 */
+ /* <3=> Undefined! */
+ /* <o.1> TimerSize: Timer Size */
+ /* <0=> 16-bit counter */
+ /* <1=> 32-bit counter */
+ /* <o.0> OneShot: One-shoot mode */
+ /* <0=> Wrapping mode */
+ /* <1=> One-shot mode */
+ /* </h> */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
@@ -1146,9 +1119,9 @@
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
- // <o.1> RESEN: Reset enable
- // <o.0> INTEN: Interrupt enable
- // </h>
+ /* <o.1> RESEN: Reset enable */
+ /* <o.0> INTEN: Interrupt enable */
+ /* </h> */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
@@ -1278,8 +1251,9 @@
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
-//#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL) //only used in extended version
+#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
+#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
@@ -1301,9 +1275,10 @@
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
-//#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) //only used in extended version
-#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
-#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
+#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
+#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
+#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
+#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )