mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

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Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h@80:bdf1132a57cf, 2016-03-02 (annotated)

Committer:: mbed_official
Date:: Wed Mar 02 14:30:11 2016 +0000
Revision:: 80:bdf1132a57cf
Parent:: 0:9b334a45a8ff
Child:: 144:ef7eb2e8f9f7

Synchronized with git revision de3b14ec9234d586b155fd24badc22775489a3dc

Full URL: https://github.com/mbedmicro/mbed/commit/de3b14ec9234d586b155fd24badc22775489a3dc/

latest changes to add arduino support, plus fixes for IOTSS BEID

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/* MPS2 CMSIS Library
bogdanm	0:9b334a45a8ff	2	*
mbed_official	80:bdf1132a57cf	3	* Copyright (c) 2006-2016 ARM Limited
bogdanm	0:9b334a45a8ff	4	* All rights reserved.
mbed_official	80:bdf1132a57cf	5	*
mbed_official	80:bdf1132a57cf	6	* Redistribution and use in source and binary forms, with or without
bogdanm	0:9b334a45a8ff	7	* modification, are permitted provided that the following conditions are met:
mbed_official	80:bdf1132a57cf	8	*
mbed_official	80:bdf1132a57cf	9	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	10	* this list of conditions and the following disclaimer.
mbed_official	80:bdf1132a57cf	11	*
mbed_official	80:bdf1132a57cf	12	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	80:bdf1132a57cf	13	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	14	* and/or other materials provided with the distribution.
mbed_official	80:bdf1132a57cf	15	*
mbed_official	80:bdf1132a57cf	16	* 3. Neither the name of the copyright holder nor the names of its contributors
mbed_official	80:bdf1132a57cf	17	* may be used to endorse or promote products derived from this software without
bogdanm	0:9b334a45a8ff	18	* specific prior written permission.
mbed_official	80:bdf1132a57cf	19	*
mbed_official	80:bdf1132a57cf	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	80:bdf1132a57cf	21	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	80:bdf1132a57cf	22	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official	80:bdf1132a57cf	23	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
mbed_official	80:bdf1132a57cf	24	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official	80:bdf1132a57cf	25	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official	80:bdf1132a57cf	26	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official	80:bdf1132a57cf	27	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official	80:bdf1132a57cf	28	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official	80:bdf1132a57cf	29	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official	80:bdf1132a57cf	30	* POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	31	*******************************************************************************
bogdanm	0:9b334a45a8ff	32	* @file CMSDK_CM4.h
bogdanm	0:9b334a45a8ff	33	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
bogdanm	0:9b334a45a8ff	34	* Device CMSDK_CM4
bogdanm	0:9b334a45a8ff	35	*
bogdanm	0:9b334a45a8ff	36	*******************************************************************************/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38
bogdanm	0:9b334a45a8ff	39	#ifndef CMSDK_CM4_H
bogdanm	0:9b334a45a8ff	40	#define CMSDK_CM4_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
mbed_official	80:bdf1132a57cf	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46
mbed_official	80:bdf1132a57cf	47	/* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	typedef enum IRQn
bogdanm	0:9b334a45a8ff	50	{
mbed_official	80:bdf1132a57cf	51	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
mbed_official	80:bdf1132a57cf	52	NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
mbed_official	80:bdf1132a57cf	53	HardFault_IRQn = -13, /* 3 HardFault Interrupt */
mbed_official	80:bdf1132a57cf	54	MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
mbed_official	80:bdf1132a57cf	55	BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
mbed_official	80:bdf1132a57cf	56	UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
mbed_official	80:bdf1132a57cf	57	SVCall_IRQn = -5, /* 11 SV Call Interrupt */
mbed_official	80:bdf1132a57cf	58	DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
mbed_official	80:bdf1132a57cf	59	PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
mbed_official	80:bdf1132a57cf	60	SysTick_IRQn = -1, /* 15 System Tick Interrupt */
bogdanm	0:9b334a45a8ff	61
mbed_official	80:bdf1132a57cf	62	/**** CMSDK Specific Interrupt Numbers *******************************************************/
mbed_official	80:bdf1132a57cf	63	UARTRX0_IRQn = 0, /!< UART 0 RX Interrupt /
mbed_official	80:bdf1132a57cf	64	UARTTX0_IRQn = 1, /!< UART 0 TX Interrupt /
mbed_official	80:bdf1132a57cf	65	UARTRX1_IRQn = 2, /!< UART 1 RX Interrupt /
mbed_official	80:bdf1132a57cf	66	UARTTX1_IRQn = 3, /!< UART 1 TX Interrupt /
mbed_official	80:bdf1132a57cf	67	UARTRX2_IRQn = 4, /!< UART 2 RX Interrupt /
mbed_official	80:bdf1132a57cf	68	UARTTX2_IRQn = 5, /!< UART 2 TX Interrupt /
mbed_official	80:bdf1132a57cf	69	PORT0_ALL_IRQn = 6, /!< Port 0 combined Interrupt /
mbed_official	80:bdf1132a57cf	70	PORT1_ALL_IRQn = 7, /!< Port 1 combined Interrupt /
mbed_official	80:bdf1132a57cf	71	TIMER0_IRQn = 8, /!< TIMER 0 Interrupt /
mbed_official	80:bdf1132a57cf	72	TIMER1_IRQn = 9, /!< TIMER 1 Interrupt /
mbed_official	80:bdf1132a57cf	73	DUALTIMER_IRQn = 10, /!< Dual Timer Interrupt /
mbed_official	80:bdf1132a57cf	74	SPI_IRQn = 11, /!< SPI Interrupt /
mbed_official	80:bdf1132a57cf	75	UARTOVF_IRQn = 12, /!< UART 0,1,2 Overflow Interrupt /
mbed_official	80:bdf1132a57cf	76	ETHERNET_IRQn = 13, /!< Ethernet Interrupt /
mbed_official	80:bdf1132a57cf	77	I2S_IRQn = 14, /!< I2S Interrupt /
mbed_official	80:bdf1132a57cf	78	TSC_IRQn = 15, /!< Touch Screen Interrupt /
mbed_official	80:bdf1132a57cf	79	PORT2_ALL_IRQn = 16, /!< Port 2 combined Interrupt /
mbed_official	80:bdf1132a57cf	80	PORT3_ALL_IRQn = 17, /!< Port 3 combined Interrupt /
mbed_official	80:bdf1132a57cf	81	UARTRX3_IRQn = 18, /!< UART 3 RX Interrupt /
mbed_official	80:bdf1132a57cf	82	UARTTX3_IRQn = 19, /!< UART 3 TX Interrupt /
mbed_official	80:bdf1132a57cf	83	UARTRX4_IRQn = 20, /!< UART 4 RX Interrupt /
mbed_official	80:bdf1132a57cf	84	UARTTX4_IRQn = 21, /!< UART 4 TX Interrupt /
mbed_official	80:bdf1132a57cf	85	ADCSPI_IRQn = 22, /!< SHIELD ADC SPI Interrupt /
mbed_official	80:bdf1132a57cf	86	SHIELDSPI_IRQn = 23, /!< SHIELD SPI Combined Interrupt /
mbed_official	80:bdf1132a57cf	87	PORT0_0_IRQn = 24, /!< GPIO Port 0 pin 0 Interrupt /
mbed_official	80:bdf1132a57cf	88	PORT0_1_IRQn = 25, /!< GPIO Port 0 pin 1 Interrupt /
mbed_official	80:bdf1132a57cf	89	PORT0_2_IRQn = 26, /!< GPIO Port 0 pin 2 Interrupt /
mbed_official	80:bdf1132a57cf	90	PORT0_3_IRQn = 27, /!< GPIO Port 0 pin 3 Interrupt /
mbed_official	80:bdf1132a57cf	91	PORT0_4_IRQn = 28, /!< GPIO Port 0 pin 4 Interrupt /
mbed_official	80:bdf1132a57cf	92	PORT0_5_IRQn = 29, /!< GPIO Port 0 pin 5 Interrupt /
mbed_official	80:bdf1132a57cf	93	PORT0_6_IRQn = 30, /!< GPIO Port 0 pin 6 Interrupt /
mbed_official	80:bdf1132a57cf	94	PORT0_7_IRQn = 31, /!< GPIO Port 0 pin 7 Interrupt /
bogdanm	0:9b334a45a8ff	95	} IRQn_Type;
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	/*
bogdanm	0:9b334a45a8ff	99	* ==========================================================================
bogdanm	0:9b334a45a8ff	100	* ----------- Processor and Core Peripheral Section ------------------------
bogdanm	0:9b334a45a8ff	101	* ==========================================================================
bogdanm	0:9b334a45a8ff	102	*/
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/* Configuration of the Cortex-M4 Processor and Core Peripherals */
bogdanm	0:9b334a45a8ff	105	#define __CM4_REV 0x0001 /!< Core Revision r0p1 /
bogdanm	0:9b334a45a8ff	106	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
bogdanm	0:9b334a45a8ff	107	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	108	#define __MPU_PRESENT 1 /!< MPU present or not /
bogdanm	0:9b334a45a8ff	109	#define __FPU_PRESENT 1 /!< FPU present or not /
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	/@}/ /* end of group CMSDK_CM4_CMSIS */
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm	0:9b334a45a8ff	115	#include "system_CMSDK_CM4.h" /* CMSDK_CM4 System include file */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	/******************************************************************************/
bogdanm	0:9b334a45a8ff	119	/* Device Specific Peripheral registers structures */
bogdanm	0:9b334a45a8ff	120	/******************************************************************************/
bogdanm	0:9b334a45a8ff	121	/** @addtogroup CMSDK_CM4_Peripherals CMSDK_CM4 Peripherals
bogdanm	0:9b334a45a8ff	122	CMSDK_CM4 Device Specific Peripheral registers structures
bogdanm	0:9b334a45a8ff	123	@{
bogdanm	0:9b334a45a8ff	124	*/
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	#if defined ( __CC_ARM )
bogdanm	0:9b334a45a8ff	127	#pragma anon_unions
bogdanm	0:9b334a45a8ff	128	#endif
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	/------------- Universal Asynchronous Receiver Transmitter (UART) -----------/
bogdanm	0:9b334a45a8ff	131	/** @addtogroup CMSDK_UART CMSDK Universal Asynchronous Receiver/Transmitter
bogdanm	0:9b334a45a8ff	132	memory mapped structure for CMSDK_UART
bogdanm	0:9b334a45a8ff	133	@{
bogdanm	0:9b334a45a8ff	134	*/
bogdanm	0:9b334a45a8ff	135	typedef struct
bogdanm	0:9b334a45a8ff	136	{
bogdanm	0:9b334a45a8ff	137	__IO uint32_t DATA; /!< Offset: 0x000 Data Register (R/W) /
bogdanm	0:9b334a45a8ff	138	__IO uint32_t STATE; /!< Offset: 0x004 Status Register (R/W) /
bogdanm	0:9b334a45a8ff	139	__IO uint32_t CTRL; /!< Offset: 0x008 Control Register (R/W) /
bogdanm	0:9b334a45a8ff	140	union {
bogdanm	0:9b334a45a8ff	141	__I uint32_t INTSTATUS; /!< Offset: 0x00C Interrupt Status Register (R/ ) /
bogdanm	0:9b334a45a8ff	142	__O uint32_t INTCLEAR; /!< Offset: 0x00C Interrupt Clear Register ( /W) /
bogdanm	0:9b334a45a8ff	143	};
bogdanm	0:9b334a45a8ff	144	__IO uint32_t BAUDDIV; /!< Offset: 0x010 Baudrate Divider Register (R/W) /
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	} CMSDK_UART_TypeDef;
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148	/* CMSDK_UART DATA Register Definitions */
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150	#define CMSDK_UART_DATA_Pos 0 /!< CMSDK_UART_DATA_Pos: DATA Position /
bogdanm	0:9b334a45a8ff	151	#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /!< CMSDK_UART DATA: DATA Mask /
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	#define CMSDK_UART_STATE_RXOR_Pos 3 /!< CMSDK_UART STATE: RXOR Position /
bogdanm	0:9b334a45a8ff	154	#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /!< CMSDK_UART STATE: RXOR Mask /
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	#define CMSDK_UART_STATE_TXOR_Pos 2 /!< CMSDK_UART STATE: TXOR Position /
bogdanm	0:9b334a45a8ff	157	#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /!< CMSDK_UART STATE: TXOR Mask /
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	#define CMSDK_UART_STATE_RXBF_Pos 1 /!< CMSDK_UART STATE: RXBF Position /
bogdanm	0:9b334a45a8ff	160	#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /!< CMSDK_UART STATE: RXBF Mask /
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	#define CMSDK_UART_STATE_TXBF_Pos 0 /!< CMSDK_UART STATE: TXBF Position /
bogdanm	0:9b334a45a8ff	163	#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /!< CMSDK_UART STATE: TXBF Mask /
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	#define CMSDK_UART_CTRL_HSTM_Pos 6 /!< CMSDK_UART CTRL: HSTM Position /
bogdanm	0:9b334a45a8ff	166	#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /!< CMSDK_UART CTRL: HSTM Mask /
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /!< CMSDK_UART CTRL: RXORIRQEN Position /
bogdanm	0:9b334a45a8ff	169	#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /!< CMSDK_UART CTRL: RXORIRQEN Mask /
bogdanm	0:9b334a45a8ff	170
bogdanm	0:9b334a45a8ff	171	#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /!< CMSDK_UART CTRL: TXORIRQEN Position /
bogdanm	0:9b334a45a8ff	172	#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /!< CMSDK_UART CTRL: TXORIRQEN Mask /
bogdanm	0:9b334a45a8ff	173
bogdanm	0:9b334a45a8ff	174	#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /!< CMSDK_UART CTRL: RXIRQEN Position /
bogdanm	0:9b334a45a8ff	175	#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /!< CMSDK_UART CTRL: RXIRQEN Mask /
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /!< CMSDK_UART CTRL: TXIRQEN Position /
bogdanm	0:9b334a45a8ff	178	#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /!< CMSDK_UART CTRL: TXIRQEN Mask /
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	#define CMSDK_UART_CTRL_RXEN_Pos 1 /!< CMSDK_UART CTRL: RXEN Position /
bogdanm	0:9b334a45a8ff	181	#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /!< CMSDK_UART CTRL: RXEN Mask /
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183	#define CMSDK_UART_CTRL_TXEN_Pos 0 /!< CMSDK_UART CTRL: TXEN Position /
bogdanm	0:9b334a45a8ff	184	#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /!< CMSDK_UART CTRL: TXEN Mask /
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /!< CMSDK_UART CTRL: RXORIRQ Position /
bogdanm	0:9b334a45a8ff	187	#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /!< CMSDK_UART CTRL: RXORIRQ Mask /
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /!< CMSDK_UART CTRL: TXORIRQ Position /
bogdanm	0:9b334a45a8ff	190	#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /!< CMSDK_UART CTRL: TXORIRQ Mask /
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /!< CMSDK_UART CTRL: RXIRQ Position /
bogdanm	0:9b334a45a8ff	193	#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /!< CMSDK_UART CTRL: RXIRQ Mask /
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195	#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /!< CMSDK_UART CTRL: TXIRQ Position /
bogdanm	0:9b334a45a8ff	196	#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /!< CMSDK_UART CTRL: TXIRQ Mask /
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	#define CMSDK_UART_BAUDDIV_Pos 0 /!< CMSDK_UART BAUDDIV: BAUDDIV Position /
bogdanm	0:9b334a45a8ff	199	#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /!< CMSDK_UART BAUDDIV: BAUDDIV Mask /
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/@}/ /* end of group CMSDK_UART */
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	/----------------------------- Timer (TIMER) -------------------------------/
bogdanm	0:9b334a45a8ff	205	/** @addtogroup CMSDK_TIMER CMSDK Timer
bogdanm	0:9b334a45a8ff	206	@{
bogdanm	0:9b334a45a8ff	207	*/
bogdanm	0:9b334a45a8ff	208	typedef struct
bogdanm	0:9b334a45a8ff	209	{
bogdanm	0:9b334a45a8ff	210	__IO uint32_t CTRL; /!< Offset: 0x000 Control Register (R/W) /
bogdanm	0:9b334a45a8ff	211	__IO uint32_t VALUE; /!< Offset: 0x004 Current Value Register (R/W) /
bogdanm	0:9b334a45a8ff	212	__IO uint32_t RELOAD; /!< Offset: 0x008 Reload Value Register (R/W) /
bogdanm	0:9b334a45a8ff	213	union {
bogdanm	0:9b334a45a8ff	214	__I uint32_t INTSTATUS; /!< Offset: 0x00C Interrupt Status Register (R/ ) /
bogdanm	0:9b334a45a8ff	215	__O uint32_t INTCLEAR; /!< Offset: 0x00C Interrupt Clear Register ( /W) /
bogdanm	0:9b334a45a8ff	216	};
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	} CMSDK_TIMER_TypeDef;
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/* CMSDK_TIMER CTRL Register Definitions */
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /!< CMSDK_TIMER CTRL: IRQEN Position /
bogdanm	0:9b334a45a8ff	223	#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /!< CMSDK_TIMER CTRL: IRQEN Mask /
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /!< CMSDK_TIMER CTRL: SELEXTCLK Position /
bogdanm	0:9b334a45a8ff	226	#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /!< CMSDK_TIMER CTRL: SELEXTCLK Mask /
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /!< CMSDK_TIMER CTRL: SELEXTEN Position /
bogdanm	0:9b334a45a8ff	229	#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /!< CMSDK_TIMER CTRL: SELEXTEN Mask /
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	#define CMSDK_TIMER_CTRL_EN_Pos 0 /!< CMSDK_TIMER CTRL: EN Position /
bogdanm	0:9b334a45a8ff	232	#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /!< CMSDK_TIMER CTRL: EN Mask /
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /!< CMSDK_TIMER VALUE: CURRENT Position /
bogdanm	0:9b334a45a8ff	235	#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /!< CMSDK_TIMER VALUE: CURRENT Mask /
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /!< CMSDK_TIMER RELOAD: RELOAD Position /
bogdanm	0:9b334a45a8ff	238	#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /!< CMSDK_TIMER RELOAD: RELOAD Mask /
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	#define CMSDK_TIMER_INTSTATUS_Pos 0 /!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition /
bogdanm	0:9b334a45a8ff	241	#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /!< CMSDK_TIMER INTSTATUS: INTSTATUSMask /
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	#define CMSDK_TIMER_INTCLEAR_Pos 0 /!< CMSDK_TIMER INTCLEAR: INTCLEAR Position /
bogdanm	0:9b334a45a8ff	244	#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask /
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	/@}/ /* end of group CMSDK_TIMER */
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248
bogdanm	0:9b334a45a8ff	249	/------------- Timer (TIM) --------------------------------------------------/
bogdanm	0:9b334a45a8ff	250	// <g> Timer (TIM)
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/** @addtogroup CMSDK_DualTIMER CMSDK Dual Timer
bogdanm	0:9b334a45a8ff	253	@{
bogdanm	0:9b334a45a8ff	254	*/
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	typedef struct
bogdanm	0:9b334a45a8ff	257	{
bogdanm	0:9b334a45a8ff	258	__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
bogdanm	0:9b334a45a8ff	259	__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
bogdanm	0:9b334a45a8ff	260	__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
mbed_official	80:bdf1132a57cf	261	/* <o.7> TimerEn: Timer Enable */
mbed_official	80:bdf1132a57cf	262	/* <o.6> TimerMode: Timer Mode */
mbed_official	80:bdf1132a57cf	263	/* <0=> Freerunning-mode */
mbed_official	80:bdf1132a57cf	264	/* <1=> Periodic mode */
mbed_official	80:bdf1132a57cf	265	/* <o.5> IntEnable: Interrupt Enable */
mbed_official	80:bdf1132a57cf	266	/* <o.2..3> TimerPre: Timer Prescale */
mbed_official	80:bdf1132a57cf	267	/* <0=> / 1 */
mbed_official	80:bdf1132a57cf	268	/* <1=> / 16 */
mbed_official	80:bdf1132a57cf	269	/* <2=> / 256 */
mbed_official	80:bdf1132a57cf	270	/* <3=> Undefined! */
mbed_official	80:bdf1132a57cf	271	/* <o.1> TimerSize: Timer Size */
mbed_official	80:bdf1132a57cf	272	/* <0=> 16-bit counter */
mbed_official	80:bdf1132a57cf	273	/* <1=> 32-bit counter */
mbed_official	80:bdf1132a57cf	274	/* <o.0> OneShot: One-shoot mode */
mbed_official	80:bdf1132a57cf	275	/* <0=> Wrapping mode */
mbed_official	80:bdf1132a57cf	276	/* <1=> One-shot mode */
mbed_official	80:bdf1132a57cf	277	/* </h> */
bogdanm	0:9b334a45a8ff	278	__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
bogdanm	0:9b334a45a8ff	279	__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
bogdanm	0:9b334a45a8ff	280	__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
bogdanm	0:9b334a45a8ff	281	__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
bogdanm	0:9b334a45a8ff	282	uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	283	__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
bogdanm	0:9b334a45a8ff	284	__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
bogdanm	0:9b334a45a8ff	285	__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
mbed_official	80:bdf1132a57cf	286	/* <o.7> TimerEn: Timer Enable */
mbed_official	80:bdf1132a57cf	287	/* <o.6> TimerMode: Timer Mode */
mbed_official	80:bdf1132a57cf	288	/* <0=> Freerunning-mode */
mbed_official	80:bdf1132a57cf	289	/* <1=> Periodic mode */
mbed_official	80:bdf1132a57cf	290	/* <o.5> IntEnable: Interrupt Enable */
mbed_official	80:bdf1132a57cf	291	/* <o.2..3> TimerPre: Timer Prescale */
mbed_official	80:bdf1132a57cf	292	/* <0=> / 1 */
mbed_official	80:bdf1132a57cf	293	/* <1=> / 16 */
mbed_official	80:bdf1132a57cf	294	/* <2=> / 256 */
mbed_official	80:bdf1132a57cf	295	/* <3=> Undefined! */
mbed_official	80:bdf1132a57cf	296	/* <o.1> TimerSize: Timer Size */
mbed_official	80:bdf1132a57cf	297	/* <0=> 16-bit counter */
mbed_official	80:bdf1132a57cf	298	/* <1=> 32-bit counter */
mbed_official	80:bdf1132a57cf	299	/* <o.0> OneShot: One-shoot mode */
mbed_official	80:bdf1132a57cf	300	/* <0=> Wrapping mode */
mbed_official	80:bdf1132a57cf	301	/* <1=> One-shot mode */
mbed_official	80:bdf1132a57cf	302	/* </h> */
bogdanm	0:9b334a45a8ff	303	__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
bogdanm	0:9b334a45a8ff	304	__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
bogdanm	0:9b334a45a8ff	305	__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
bogdanm	0:9b334a45a8ff	306	__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
bogdanm	0:9b334a45a8ff	307	uint32_t RESERVED1[945];
bogdanm	0:9b334a45a8ff	308	__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
bogdanm	0:9b334a45a8ff	309	__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
bogdanm	0:9b334a45a8ff	310	} CMSDK_DUALTIMER_BOTH_TypeDef;
bogdanm	0:9b334a45a8ff	311
bogdanm	0:9b334a45a8ff	312	#define CMSDK_DUALTIMER1_LOAD_Pos 0 /!< CMSDK_DUALTIMER1 LOAD: LOAD Position /
bogdanm	0:9b334a45a8ff	313	#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /!< CMSDK_DUALTIMER1 LOAD: LOAD Mask /
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	#define CMSDK_DUALTIMER1_VALUE_Pos 0 /!< CMSDK_DUALTIMER1 VALUE: VALUE Position /
bogdanm	0:9b334a45a8ff	316	#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /!< CMSDK_DUALTIMER1 VALUE: VALUE Mask /
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position /
bogdanm	0:9b334a45a8ff	319	#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask /
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position /
bogdanm	0:9b334a45a8ff	322	#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask /
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position /
bogdanm	0:9b334a45a8ff	325	#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask /
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position /
bogdanm	0:9b334a45a8ff	328	#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask /
bogdanm	0:9b334a45a8ff	329
bogdanm	0:9b334a45a8ff	330	#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position /
bogdanm	0:9b334a45a8ff	331	#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask /
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position /
bogdanm	0:9b334a45a8ff	334	#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask /
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /!< CMSDK_DUALTIMER1 INTCLR: INT Clear Position /
bogdanm	0:9b334a45a8ff	337	#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /!< CMSDK_DUALTIMER1 INTCLR: INT Clear Mask /
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339	#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position /
bogdanm	0:9b334a45a8ff	340	#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask /
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position /
bogdanm	0:9b334a45a8ff	343	#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask /
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /!< CMSDK_DUALTIMER1 BGLOAD: Background Load Position /
bogdanm	0:9b334a45a8ff	346	#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /!< CMSDK_DUALTIMER1 BGLOAD: Background Load Mask /
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	#define CMSDK_DUALTIMER2_LOAD_Pos 0 /!< CMSDK_DUALTIMER2 LOAD: LOAD Position /
bogdanm	0:9b334a45a8ff	349	#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /!< CMSDK_DUALTIMER2 LOAD: LOAD Mask /
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	#define CMSDK_DUALTIMER2_VALUE_Pos 0 /!< CMSDK_DUALTIMER2 VALUE: VALUE Position /
bogdanm	0:9b334a45a8ff	352	#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /!< CMSDK_DUALTIMER2 VALUE: VALUE Mask /
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position /
bogdanm	0:9b334a45a8ff	355	#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask /
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position /
bogdanm	0:9b334a45a8ff	358	#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask /
bogdanm	0:9b334a45a8ff	359
bogdanm	0:9b334a45a8ff	360	#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position /
bogdanm	0:9b334a45a8ff	361	#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask /
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position /
bogdanm	0:9b334a45a8ff	364	#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask /
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366	#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position /
bogdanm	0:9b334a45a8ff	367	#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask /
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position /
bogdanm	0:9b334a45a8ff	370	#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask /
bogdanm	0:9b334a45a8ff	371
bogdanm	0:9b334a45a8ff	372	#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /!< CMSDK_DUALTIMER2 INTCLR: INT Clear Position /
bogdanm	0:9b334a45a8ff	373	#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /!< CMSDK_DUALTIMER2 INTCLR: INT Clear Mask /
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position /
bogdanm	0:9b334a45a8ff	376	#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask /
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position /
bogdanm	0:9b334a45a8ff	379	#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask /
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position /
bogdanm	0:9b334a45a8ff	382	#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask /
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	typedef struct
bogdanm	0:9b334a45a8ff	385	{
bogdanm	0:9b334a45a8ff	386	__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
bogdanm	0:9b334a45a8ff	387	__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
bogdanm	0:9b334a45a8ff	388	__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
mbed_official	80:bdf1132a57cf	389	/* <o.7> TimerEn: Timer Enable */
mbed_official	80:bdf1132a57cf	390	/* <o.6> TimerMode: Timer Mode */
mbed_official	80:bdf1132a57cf	391	/* <0=> Freerunning-mode */
mbed_official	80:bdf1132a57cf	392	/* <1=> Periodic mode */
mbed_official	80:bdf1132a57cf	393	/* <o.5> IntEnable: Interrupt Enable */
mbed_official	80:bdf1132a57cf	394	/* <o.2..3> TimerPre: Timer Prescale */
mbed_official	80:bdf1132a57cf	395	/* <0=> / 1 */
mbed_official	80:bdf1132a57cf	396	/* <1=> / 16 */
mbed_official	80:bdf1132a57cf	397	/* <2=> / 256 */
mbed_official	80:bdf1132a57cf	398	/* <3=> Undefined! */
mbed_official	80:bdf1132a57cf	399	/* <o.1> TimerSize: Timer Size */
mbed_official	80:bdf1132a57cf	400	/* <0=> 16-bit counter */
mbed_official	80:bdf1132a57cf	401	/* <1=> 32-bit counter */
mbed_official	80:bdf1132a57cf	402	/* <o.0> OneShot: One-shoot mode */
mbed_official	80:bdf1132a57cf	403	/* <0=> Wrapping mode */
mbed_official	80:bdf1132a57cf	404	/* <1=> One-shot mode */
mbed_official	80:bdf1132a57cf	405	/* </h> */
bogdanm	0:9b334a45a8ff	406	__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
bogdanm	0:9b334a45a8ff	407	__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
bogdanm	0:9b334a45a8ff	408	__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
bogdanm	0:9b334a45a8ff	409	__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
bogdanm	0:9b334a45a8ff	410	} CMSDK_DUALTIMER_SINGLE_TypeDef;
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	#define CMSDK_DUALTIMER_LOAD_Pos 0 /!< CMSDK_DUALTIMER LOAD: LOAD Position /
bogdanm	0:9b334a45a8ff	413	#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /!< CMSDK_DUALTIMER LOAD: LOAD Mask /
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	#define CMSDK_DUALTIMER_VALUE_Pos 0 /!< CMSDK_DUALTIMER VALUE: VALUE Position /
bogdanm	0:9b334a45a8ff	416	#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /!< CMSDK_DUALTIMER VALUE: VALUE Mask /
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position /
bogdanm	0:9b334a45a8ff	419	#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask /
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position /
bogdanm	0:9b334a45a8ff	422	#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask /
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position /
bogdanm	0:9b334a45a8ff	425	#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask /
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position /
bogdanm	0:9b334a45a8ff	428	#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask /
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position /
bogdanm	0:9b334a45a8ff	431	#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask /
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position /
bogdanm	0:9b334a45a8ff	434	#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask /
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	#define CMSDK_DUALTIMER_INTCLR_Pos 0 /!< CMSDK_DUALTIMER INTCLR: INT Clear Position /
bogdanm	0:9b334a45a8ff	437	#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /!< CMSDK_DUALTIMER INTCLR: INT Clear Mask /
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position /
bogdanm	0:9b334a45a8ff	440	#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask /
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position /
bogdanm	0:9b334a45a8ff	443	#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask /
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /!< CMSDK_DUALTIMER BGLOAD: Background Load Position /
bogdanm	0:9b334a45a8ff	446	#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /!< CMSDK_DUALTIMER BGLOAD: Background Load Mask /
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/@}/ /* end of group CMSDK_DualTIMER */
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	/-------------------- General Purpose Input Output (GPIO) -------------------/
bogdanm	0:9b334a45a8ff	452	/** @addtogroup CMSDK_GPIO CMSDK GPIO
bogdanm	0:9b334a45a8ff	453	@{
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455	typedef struct
bogdanm	0:9b334a45a8ff	456	{
bogdanm	0:9b334a45a8ff	457	__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
bogdanm	0:9b334a45a8ff	458	__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
bogdanm	0:9b334a45a8ff	459	uint32_t RESERVED0[2];
bogdanm	0:9b334a45a8ff	460	__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
bogdanm	0:9b334a45a8ff	461	__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
bogdanm	0:9b334a45a8ff	462	__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
bogdanm	0:9b334a45a8ff	463	__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
bogdanm	0:9b334a45a8ff	464	__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
bogdanm	0:9b334a45a8ff	465	__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
bogdanm	0:9b334a45a8ff	466	__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
bogdanm	0:9b334a45a8ff	467	__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
bogdanm	0:9b334a45a8ff	468	__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
bogdanm	0:9b334a45a8ff	469	__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
bogdanm	0:9b334a45a8ff	470	union {
bogdanm	0:9b334a45a8ff	471	__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
bogdanm	0:9b334a45a8ff	472	__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
bogdanm	0:9b334a45a8ff	473	};
bogdanm	0:9b334a45a8ff	474	uint32_t RESERVED1[241];
bogdanm	0:9b334a45a8ff	475	__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
bogdanm	0:9b334a45a8ff	476	__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
bogdanm	0:9b334a45a8ff	477	} CMSDK_GPIO_TypeDef;
bogdanm	0:9b334a45a8ff	478
bogdanm	0:9b334a45a8ff	479	#define CMSDK_GPIO_DATA_Pos 0 /!< CMSDK_GPIO DATA: DATA Position /
bogdanm	0:9b334a45a8ff	480	#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /!< CMSDK_GPIO DATA: DATA Mask /
bogdanm	0:9b334a45a8ff	481
bogdanm	0:9b334a45a8ff	482	#define CMSDK_GPIO_DATAOUT_Pos 0 /!< CMSDK_GPIO DATAOUT: DATAOUT Position /
bogdanm	0:9b334a45a8ff	483	#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /!< CMSDK_GPIO DATAOUT: DATAOUT Mask /
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	#define CMSDK_GPIO_OUTENSET_Pos 0 /!< CMSDK_GPIO OUTEN: OUTEN Position /
bogdanm	0:9b334a45a8ff	486	#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /!< CMSDK_GPIO OUTEN: OUTEN Mask /
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	#define CMSDK_GPIO_OUTENCLR_Pos 0 /!< CMSDK_GPIO OUTEN: OUTEN Position /
bogdanm	0:9b334a45a8ff	489	#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /!< CMSDK_GPIO OUTEN: OUTEN Mask /
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /!< CMSDK_GPIO ALTFUNC: ALTFUNC Position /
bogdanm	0:9b334a45a8ff	492	#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask /
bogdanm	0:9b334a45a8ff	493
bogdanm	0:9b334a45a8ff	494	#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /!< CMSDK_GPIO ALTFUNC: ALTFUNC Position /
bogdanm	0:9b334a45a8ff	495	#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask /
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	#define CMSDK_GPIO_INTENSET_Pos 0 /!< CMSDK_GPIO INTEN: INTEN Position /
bogdanm	0:9b334a45a8ff	498	#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /!< CMSDK_GPIO INTEN: INTEN Mask /
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	#define CMSDK_GPIO_INTENCLR_Pos 0 /!< CMSDK_GPIO INTEN: INTEN Position /
bogdanm	0:9b334a45a8ff	501	#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /!< CMSDK_GPIO INTEN: INTEN Mask /
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	#define CMSDK_GPIO_INTTYPESET_Pos 0 /!< CMSDK_GPIO INTTYPE: INTTYPE Position /
bogdanm	0:9b334a45a8ff	504	#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /!< CMSDK_GPIO INTTYPE: INTTYPE Mask /
bogdanm	0:9b334a45a8ff	505
bogdanm	0:9b334a45a8ff	506	#define CMSDK_GPIO_INTTYPECLR_Pos 0 /!< CMSDK_GPIO INTTYPE: INTTYPE Position /
bogdanm	0:9b334a45a8ff	507	#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /!< CMSDK_GPIO INTTYPE: INTTYPE Mask /
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	#define CMSDK_GPIO_INTPOLSET_Pos 0 /!< CMSDK_GPIO INTPOL: INTPOL Position /
bogdanm	0:9b334a45a8ff	510	#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /!< CMSDK_GPIO INTPOL: INTPOL Mask /
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	#define CMSDK_GPIO_INTPOLCLR_Pos 0 /!< CMSDK_GPIO INTPOL: INTPOL Position /
bogdanm	0:9b334a45a8ff	513	#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /!< CMSDK_GPIO INTPOL: INTPOL Mask /
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	#define CMSDK_GPIO_INTSTATUS_Pos 0 /!< CMSDK_GPIO INTSTATUS: INTSTATUS Position /
bogdanm	0:9b334a45a8ff	516	#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask /
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	#define CMSDK_GPIO_INTCLEAR_Pos 0 /!< CMSDK_GPIO INTCLEAR: INTCLEAR Position /
bogdanm	0:9b334a45a8ff	519	#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask /
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position /
bogdanm	0:9b334a45a8ff	522	#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask /
bogdanm	0:9b334a45a8ff	523
bogdanm	0:9b334a45a8ff	524	#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position /
bogdanm	0:9b334a45a8ff	525	#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask /
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/@}/ /* end of group CMSDK_GPIO */
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/------------- System Control (SYSCON) --------------------------------------/
bogdanm	0:9b334a45a8ff	531	/** @addtogroup CMSDK_SYSCON CMSDK System Control
bogdanm	0:9b334a45a8ff	532	@{
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534	typedef struct
bogdanm	0:9b334a45a8ff	535	{
bogdanm	0:9b334a45a8ff	536	__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
bogdanm	0:9b334a45a8ff	537	__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
bogdanm	0:9b334a45a8ff	538	__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
bogdanm	0:9b334a45a8ff	539	__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
bogdanm	0:9b334a45a8ff	540	__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
bogdanm	0:9b334a45a8ff	541	} CMSDK_SYSCON_TypeDef;
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	#define CMSDK_SYSCON_REMAP_Pos 0
bogdanm	0:9b334a45a8ff	544	#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /!< CMSDK_SYSCON MEME_CTRL: REMAP Mask /
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
bogdanm	0:9b334a45a8ff	547	#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /!< CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask /
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
bogdanm	0:9b334a45a8ff	550	#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /!< CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask /
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
bogdanm	0:9b334a45a8ff	553	#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /!< CMSDK_SYSCON EMICTRL: SIZE Mask /
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
bogdanm	0:9b334a45a8ff	556	#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /!< CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask /
bogdanm	0:9b334a45a8ff	557
bogdanm	0:9b334a45a8ff	558	#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
bogdanm	0:9b334a45a8ff	559	#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /!< CMSDK_SYSCON EMICTRL: WRITECYCLE Mask /
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
bogdanm	0:9b334a45a8ff	562	#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /!< CMSDK_SYSCON EMICTRL: READCYCLE Mask /
bogdanm	0:9b334a45a8ff	563
bogdanm	0:9b334a45a8ff	564	#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
bogdanm	0:9b334a45a8ff	565	#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /!< CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask /
bogdanm	0:9b334a45a8ff	566
bogdanm	0:9b334a45a8ff	567	#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
bogdanm	0:9b334a45a8ff	568	#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /!< CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask /
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
bogdanm	0:9b334a45a8ff	571	#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /!< CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask /
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	/@}/ /* end of group CMSDK_SYSCON */
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/------------- PL230 uDMA (PL230) --------------------------------------/
bogdanm	0:9b334a45a8ff	576	/** @addtogroup CMSDK_PL230 CMSDK uDMA controller
bogdanm	0:9b334a45a8ff	577	@{
bogdanm	0:9b334a45a8ff	578	*/
bogdanm	0:9b334a45a8ff	579	typedef struct
bogdanm	0:9b334a45a8ff	580	{
bogdanm	0:9b334a45a8ff	581	__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
bogdanm	0:9b334a45a8ff	582	__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
bogdanm	0:9b334a45a8ff	583	__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
bogdanm	0:9b334a45a8ff	584	__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
bogdanm	0:9b334a45a8ff	585	__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
bogdanm	0:9b334a45a8ff	586	__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
bogdanm	0:9b334a45a8ff	587	__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
bogdanm	0:9b334a45a8ff	588	__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
bogdanm	0:9b334a45a8ff	589	__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
bogdanm	0:9b334a45a8ff	590	__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
bogdanm	0:9b334a45a8ff	591	__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
bogdanm	0:9b334a45a8ff	592	__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
bogdanm	0:9b334a45a8ff	593	__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
bogdanm	0:9b334a45a8ff	594	__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
bogdanm	0:9b334a45a8ff	595	__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
bogdanm	0:9b334a45a8ff	596	__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
bogdanm	0:9b334a45a8ff	597	uint32_t RESERVED0[3];
bogdanm	0:9b334a45a8ff	598	__IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	} CMSDK_PL230_TypeDef;
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	#define PL230_DMA_CHNL_BITS 0
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /!< CMSDK_PL230 DMA STATUS: MSTREN Position /
bogdanm	0:9b334a45a8ff	605	#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /!< CMSDK_PL230 DMA STATUS: MSTREN Mask /
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /!< CMSDK_PL230 DMA STATUS: STATE Position /
bogdanm	0:9b334a45a8ff	608	#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /!< CMSDK_PL230 DMA STATUS: STATE Mask /
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position /
bogdanm	0:9b334a45a8ff	611	#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask /
bogdanm	0:9b334a45a8ff	612
bogdanm	0:9b334a45a8ff	613	#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /!< CMSDK_PL230 DMA STATUS: TEST_STATUS Position /
bogdanm	0:9b334a45a8ff	614	#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /!< CMSDK_PL230 DMA STATUS: TEST_STATUS Mask /
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /!< CMSDK_PL230 DMA CFG: MSTREN Position /
bogdanm	0:9b334a45a8ff	617	#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /!< CMSDK_PL230 DMA CFG: MSTREN Mask /
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /!< CMSDK_PL230 DMA CFG: CPCCACHE Position /
bogdanm	0:9b334a45a8ff	620	#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /!< CMSDK_PL230 DMA CFG: CPCCACHE Mask /
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /!< CMSDK_PL230 DMA CFG: CPCBUF Position /
bogdanm	0:9b334a45a8ff	623	#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /!< CMSDK_PL230 DMA CFG: CPCBUF Mask /
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /!< CMSDK_PL230 DMA CFG: CPCPRIV Position /
bogdanm	0:9b334a45a8ff	626	#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /!< CMSDK_PL230 DMA CFG: CPCPRIV Mask /
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /!< CMSDK_PL230 STATUS: BASE_PTR Position /
bogdanm	0:9b334a45a8ff	629	#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /!< CMSDK_PL230 STATUS: BASE_PTR Mask /
bogdanm	0:9b334a45a8ff	630
bogdanm	0:9b334a45a8ff	631	#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /!< CMSDK_PL230 STATUS: MSTREN Position /
bogdanm	0:9b334a45a8ff	632	#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /!< CMSDK_PL230 STATUS: MSTREN Mask /
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position /
bogdanm	0:9b334a45a8ff	635	#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask /
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position /
bogdanm	0:9b334a45a8ff	638	#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask /
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /!< CMSDK_PL230 CHNL_USEBURST: SET Position /
bogdanm	0:9b334a45a8ff	641	#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /!< CMSDK_PL230 CHNL_USEBURST: SET Mask /
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /!< CMSDK_PL230 CHNL_USEBURST: CLR Position /
bogdanm	0:9b334a45a8ff	644	#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /!< CMSDK_PL230 CHNL_USEBURST: CLR Mask /
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /!< CMSDK_PL230 CHNL_REQ_MASK: SET Position /
bogdanm	0:9b334a45a8ff	647	#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /!< CMSDK_PL230 CHNL_REQ_MASK: SET Mask /
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /!< CMSDK_PL230 CHNL_REQ_MASK: CLR Position /
bogdanm	0:9b334a45a8ff	650	#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /!< CMSDK_PL230 CHNL_REQ_MASK: CLR Mask /
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /!< CMSDK_PL230 CHNL_ENABLE: SET Position /
bogdanm	0:9b334a45a8ff	653	#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /!< CMSDK_PL230 CHNL_ENABLE: SET Mask /
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /!< CMSDK_PL230 CHNL_ENABLE: CLR Position /
bogdanm	0:9b334a45a8ff	656	#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /!< CMSDK_PL230 CHNL_ENABLE: CLR Mask /
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /!< CMSDK_PL230 CHNL_PRI_ALT: SET Position /
bogdanm	0:9b334a45a8ff	659	#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /!< CMSDK_PL230 CHNL_PRI_ALT: SET Mask /
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /!< CMSDK_PL230 CHNL_PRI_ALT: CLR Position /
bogdanm	0:9b334a45a8ff	662	#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /!< CMSDK_PL230 CHNL_PRI_ALT: CLR Mask /
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /!< CMSDK_PL230 CHNL_PRIORITY: SET Position /
bogdanm	0:9b334a45a8ff	665	#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /!< CMSDK_PL230 CHNL_PRIORITY: SET Mask /
bogdanm	0:9b334a45a8ff	666
bogdanm	0:9b334a45a8ff	667	#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /!< CMSDK_PL230 CHNL_PRIORITY: CLR Position /
bogdanm	0:9b334a45a8ff	668	#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /!< CMSDK_PL230 CHNL_PRIORITY: CLR Mask /
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	#define CMSDK_PL230_ERR_CLR_Pos 0 /!< CMSDK_PL230 ERR: CLR Position /
bogdanm	0:9b334a45a8ff	671	#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /!< CMSDK_PL230 ERR: CLR Mask /
bogdanm	0:9b334a45a8ff	672
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	/@}/ /* end of group CMSDK_PL230 */
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/------------- PrimeCell UART (PL110) --------------------------------------/
bogdanm	0:9b334a45a8ff	678	/** @addtogroup CMSDK_PL110 CMSDK PrimeCell UART
bogdanm	0:9b334a45a8ff	679	@{
bogdanm	0:9b334a45a8ff	680	*/
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	typedef struct
bogdanm	0:9b334a45a8ff	683	{
bogdanm	0:9b334a45a8ff	684	__IO uint32_t UARTDR; // <h> Data
bogdanm	0:9b334a45a8ff	685	// <o.11> OE: Overrun error <r>
bogdanm	0:9b334a45a8ff	686	// <o.10> BE: Break error <r>
bogdanm	0:9b334a45a8ff	687	// <o.9> PE: Parity error <r>
bogdanm	0:9b334a45a8ff	688	// <o.8> FE: Framing error <r>
bogdanm	0:9b334a45a8ff	689	// <o.0..7> DATA: Received or Transmitting data (0..255)
bogdanm	0:9b334a45a8ff	690	// </h>
bogdanm	0:9b334a45a8ff	691	union {
bogdanm	0:9b334a45a8ff	692	__I uint32_t UARTRSR; // <h> Receive Status <r>
bogdanm	0:9b334a45a8ff	693	// <o.3> OE: Overrun error <r>
bogdanm	0:9b334a45a8ff	694	// <o.2> BE: Break error <r>
bogdanm	0:9b334a45a8ff	695	// <o.1> PE: Parity error <r>
bogdanm	0:9b334a45a8ff	696	// <o.0> FE: Framing error <r>
bogdanm	0:9b334a45a8ff	697	// </h>
bogdanm	0:9b334a45a8ff	698	__O uint32_t UARTECR; // <h> Error Clear <w>
bogdanm	0:9b334a45a8ff	699	// <o.3> OE: Overrun error <w>
bogdanm	0:9b334a45a8ff	700	// <o.2> BE: Break error <w>
bogdanm	0:9b334a45a8ff	701	// <o.1> PE: Parity error <w>
bogdanm	0:9b334a45a8ff	702	// <o.0> FE: Framing error <w>
bogdanm	0:9b334a45a8ff	703	// </h>
bogdanm	0:9b334a45a8ff	704	};
bogdanm	0:9b334a45a8ff	705	uint32_t RESERVED0[4];
bogdanm	0:9b334a45a8ff	706	__IO uint32_t UARTFR; // <h> Flags <r>
bogdanm	0:9b334a45a8ff	707	// <o.8> RI: Ring indicator <r>
bogdanm	0:9b334a45a8ff	708	// <o.7> TXFE: Transmit FIFO empty <r>
bogdanm	0:9b334a45a8ff	709	// <o.6> RXFF: Receive FIFO full <r>
bogdanm	0:9b334a45a8ff	710	// <o.5> TXFF: Transmit FIFO full <r>
bogdanm	0:9b334a45a8ff	711	// <o.4> RXFE: Receive FIFO empty <r>
bogdanm	0:9b334a45a8ff	712	// <o.3> BUSY: UART busy <r>
bogdanm	0:9b334a45a8ff	713	// <o.2> DCD: Data carrier detect <r>
bogdanm	0:9b334a45a8ff	714	// <o.1> DSR: Data set ready <r>
bogdanm	0:9b334a45a8ff	715	// <o.0> CTS: Clear to send <r>
bogdanm	0:9b334a45a8ff	716	// </h>
bogdanm	0:9b334a45a8ff	717	uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	718	__IO uint32_t UARTILPR; // <h> IrDA Low-power Counter
bogdanm	0:9b334a45a8ff	719	// <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255)
bogdanm	0:9b334a45a8ff	720	// </h>
bogdanm	0:9b334a45a8ff	721	__IO uint32_t UARTIBRD; // <h> Integer Baud Rate
bogdanm	0:9b334a45a8ff	722	// <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535)
bogdanm	0:9b334a45a8ff	723	// </h>
bogdanm	0:9b334a45a8ff	724	__IO uint32_t UARTFBRD; // <h> Fractional Baud Rate
bogdanm	0:9b334a45a8ff	725	// <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63)
bogdanm	0:9b334a45a8ff	726	// </h>
bogdanm	0:9b334a45a8ff	727	__IO uint32_t UARTLCR_H; // <h> Line Control
bogdanm	0:9b334a45a8ff	728	// <o.8> SPS: Stick parity select
bogdanm	0:9b334a45a8ff	729	// <o.5..6> WLEN: Word length
bogdanm	0:9b334a45a8ff	730	// <0=> 5 bits
bogdanm	0:9b334a45a8ff	731	// <1=> 6 bits
bogdanm	0:9b334a45a8ff	732	// <2=> 7 bits
bogdanm	0:9b334a45a8ff	733	// <3=> 8 bits
bogdanm	0:9b334a45a8ff	734	// <o.4> FEN: Enable FIFOs
bogdanm	0:9b334a45a8ff	735	// <o.3> STP2: Two stop bits select
bogdanm	0:9b334a45a8ff	736	// <o.2> EPS: Even parity select
bogdanm	0:9b334a45a8ff	737	// <o.1> PEN: Parity enable
bogdanm	0:9b334a45a8ff	738	// <o.0> BRK: Send break
bogdanm	0:9b334a45a8ff	739	// </h>
bogdanm	0:9b334a45a8ff	740	__IO uint32_t UARTCR; // <h> Control
bogdanm	0:9b334a45a8ff	741	// <o.15> CTSEn: CTS hardware flow control enable
bogdanm	0:9b334a45a8ff	742	// <o.14> RTSEn: RTS hardware flow control enable
bogdanm	0:9b334a45a8ff	743	// <o.13> Out2: Complement of Out2 modem status output
bogdanm	0:9b334a45a8ff	744	// <o.12> Out1: Complement of Out1 modem status output
bogdanm	0:9b334a45a8ff	745	// <o.11> RTS: Request to send
bogdanm	0:9b334a45a8ff	746	// <o.10> DTR: Data transmit ready
bogdanm	0:9b334a45a8ff	747	// <o.9> RXE: Receive enable
bogdanm	0:9b334a45a8ff	748	// <o.8> TXE: Transmit enable
bogdanm	0:9b334a45a8ff	749	// <o.7> LBE: Loop-back enable
bogdanm	0:9b334a45a8ff	750	// <o.2> SIRLP: IrDA SIR low power mode
bogdanm	0:9b334a45a8ff	751	// <o.1> SIREN: SIR enable
bogdanm	0:9b334a45a8ff	752	// <o.0> UARTEN: UART enable
bogdanm	0:9b334a45a8ff	753	// </h>
bogdanm	0:9b334a45a8ff	754	__IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select
bogdanm	0:9b334a45a8ff	755	// <o.3..5> RXIFLSEL: Receive interrupt FIFO level select
bogdanm	0:9b334a45a8ff	756	// <0=> >= 1/8 full
bogdanm	0:9b334a45a8ff	757	// <1=> >= 1/4 full
bogdanm	0:9b334a45a8ff	758	// <2=> >= 1/2 full
bogdanm	0:9b334a45a8ff	759	// <3=> >= 3/4 full
bogdanm	0:9b334a45a8ff	760	// <4=> >= 7/8 full
bogdanm	0:9b334a45a8ff	761	// <5=> reserved
bogdanm	0:9b334a45a8ff	762	// <6=> reserved
bogdanm	0:9b334a45a8ff	763	// <7=> reserved
bogdanm	0:9b334a45a8ff	764	// <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select
bogdanm	0:9b334a45a8ff	765	// <0=> <= 1/8 full
bogdanm	0:9b334a45a8ff	766	// <1=> <= 1/4 full
bogdanm	0:9b334a45a8ff	767	// <2=> <= 1/2 full
bogdanm	0:9b334a45a8ff	768	// <3=> <= 3/4 full
bogdanm	0:9b334a45a8ff	769	// <4=> <= 7/8 full
bogdanm	0:9b334a45a8ff	770	// <5=> reserved
bogdanm	0:9b334a45a8ff	771	// <6=> reserved
bogdanm	0:9b334a45a8ff	772	// <7=> reserved
bogdanm	0:9b334a45a8ff	773	// </h>
bogdanm	0:9b334a45a8ff	774	__IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear
bogdanm	0:9b334a45a8ff	775	// <o.10> OEIM: Overrun error interrupt mask
bogdanm	0:9b334a45a8ff	776	// <o.9> BEIM: Break error interrupt mask
bogdanm	0:9b334a45a8ff	777	// <o.8> PEIM: Parity error interrupt mask
bogdanm	0:9b334a45a8ff	778	// <o.7> FEIM: Framing error interrupt mask
bogdanm	0:9b334a45a8ff	779	// <o.6> RTIM: Receive interrupt mask
bogdanm	0:9b334a45a8ff	780	// <o.5> TXIM: Transmit interrupt mask
bogdanm	0:9b334a45a8ff	781	// <o.4> RXIM: Receive interrupt mask
bogdanm	0:9b334a45a8ff	782	// <o.3> DSRMIM: nUARTDSR modem interrupt mask
bogdanm	0:9b334a45a8ff	783	// <o.2> DCDMIM: nUARTDCD modem interrupt mask
bogdanm	0:9b334a45a8ff	784	// <o.1> CTSMIM: nUARTCTS modem interrupt mask
bogdanm	0:9b334a45a8ff	785	// <o.0> RIMIM: nUARTRI modem interrupt mask
bogdanm	0:9b334a45a8ff	786	// </h>
bogdanm	0:9b334a45a8ff	787	__IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r>
bogdanm	0:9b334a45a8ff	788	// <o.10> OERIS: Overrun error interrupt status <r>
bogdanm	0:9b334a45a8ff	789	// <o.9> BERIS: Break error interrupt status <r>
bogdanm	0:9b334a45a8ff	790	// <o.8> PERIS: Parity error interrupt status <r>
bogdanm	0:9b334a45a8ff	791	// <o.7> FERIS: Framing error interrupt status <r>
bogdanm	0:9b334a45a8ff	792	// <o.6> RTRIS: Receive timeout interrupt status <r>
bogdanm	0:9b334a45a8ff	793	// <o.5> TXRIS: Transmit interrupt status <r>
bogdanm	0:9b334a45a8ff	794	// <o.4> RXRIS: Receive interrupt status <r>
bogdanm	0:9b334a45a8ff	795	// <o.3> DSRRMIS: nUARTDSR modem interrupt status <r>
bogdanm	0:9b334a45a8ff	796	// <o.2> DCDRMIS: nUARTDCD modem interrupt status <r>
bogdanm	0:9b334a45a8ff	797	// <o.1> CTSRMIS: nUARTCTS modem interrupt status <r>
bogdanm	0:9b334a45a8ff	798	// <o.0> RIRMIS: nUARTRI modem interrupt status <r>
bogdanm	0:9b334a45a8ff	799	// </h>
bogdanm	0:9b334a45a8ff	800	__IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r>
bogdanm	0:9b334a45a8ff	801	// <o.10> OEMIS: Overrun error masked interrupt status <r>
bogdanm	0:9b334a45a8ff	802	// <o.9> BEMIS: Break error masked interrupt status <r>
bogdanm	0:9b334a45a8ff	803	// <o.8> PEMIS: Parity error masked interrupt status <r>
bogdanm	0:9b334a45a8ff	804	// <o.7> FEMIS: Framing error masked interrupt status <r>
bogdanm	0:9b334a45a8ff	805	// <o.6> RTMIS: Receive timeout masked interrupt status <r>
bogdanm	0:9b334a45a8ff	806	// <o.5> TXMIS: Transmit masked interrupt status <r>
bogdanm	0:9b334a45a8ff	807	// <o.4> RXMIS: Receive masked interrupt status <r>
bogdanm	0:9b334a45a8ff	808	// <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r>
bogdanm	0:9b334a45a8ff	809	// <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r>
bogdanm	0:9b334a45a8ff	810	// <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r>
bogdanm	0:9b334a45a8ff	811	// <o.0> RIMMIS: nUARTRI modem masked interrupt status <r>
bogdanm	0:9b334a45a8ff	812	// </h>
bogdanm	0:9b334a45a8ff	813	__O uint32_t UARTICR; // <h> Interrupt Clear <w>
bogdanm	0:9b334a45a8ff	814	// <o.10> OEIC: Overrun error interrupt clear <w>
bogdanm	0:9b334a45a8ff	815	// <o.9> BEIC: Break error interrupt clear <w>
bogdanm	0:9b334a45a8ff	816	// <o.8> PEIC: Parity error interrupt clear <w>
bogdanm	0:9b334a45a8ff	817	// <o.7> FEIC: Framing error interrupt clear <w>
bogdanm	0:9b334a45a8ff	818	// <o.6> RTIC: Receive timeout interrupt clear <w>
bogdanm	0:9b334a45a8ff	819	// <o.5> TXIC: Transmit interrupt clear <w>
bogdanm	0:9b334a45a8ff	820	// <o.4> RXIC: Receive interrupt clear <w>
bogdanm	0:9b334a45a8ff	821	// <o.3> DSRMIC: nUARTDSR modem interrupt clear <w>
bogdanm	0:9b334a45a8ff	822	// <o.2> DCDMIC: nUARTDCD modem interrupt clear <w>
bogdanm	0:9b334a45a8ff	823	// <o.1> CTSMIC: nUARTCTS modem interrupt clear <w>
bogdanm	0:9b334a45a8ff	824	// <o.0> RIMIC: nUARTRI modem interrupt clear <w>
bogdanm	0:9b334a45a8ff	825	// </h>
bogdanm	0:9b334a45a8ff	826	__IO uint32_t UARTDMACR; // <h> DMA Control
bogdanm	0:9b334a45a8ff	827	// <o.2> DMAONERR: DMA on error
bogdanm	0:9b334a45a8ff	828	// <o.1> TXDMAE: Transmit DMA enable
bogdanm	0:9b334a45a8ff	829	// <o.0> RXDMAE: Receive DMA enable
bogdanm	0:9b334a45a8ff	830	// </h>
bogdanm	0:9b334a45a8ff	831	} PL110_UART_TypeDef;
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	#define CMSDK_PL110_DATAOVRRUN_Pos 11 /!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position /
bogdanm	0:9b334a45a8ff	834	#define CMSDK_PL110_DATAOVRRUN_Msk (0x1ul << CMSDK_PL110_DATAOVRRUN_Pos) /!< CMSDK_PL110 DATAOVRRUN: Data Overrun Mask /
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	#define CMSDK_PL110_DATABREAKERR_Pos 10 /!< CMSDK_PL110 DATABREAKERR: Data Break Error Position /
bogdanm	0:9b334a45a8ff	837	#define CMSDK_PL110_DATABREAKERR_Msk (0x1ul << CMSDK_PL110_DATABREAKERR_Pos) /!< CMSDK_PL110 DATABREAKERR: Data Break Error Mask /
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	#define CMSDK_PL110_DATAPARITYERR_Pos 9 /!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Position /
bogdanm	0:9b334a45a8ff	840	#define CMSDK_PL110_DATAPARITYERR_Msk (0x1ul << CMSDK_PL110_DATAPARITYERR_Pos) /!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Mask /
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	#define CMSDK_PL110_DATAFRAMEERR_Pos 8 /!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Position /
bogdanm	0:9b334a45a8ff	843	#define CMSDK_PL110_DATAFRAMEERR_Msk (0x1ul << CMSDK_PL110_DATAFRAMEERR_Pos) /!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Mask /
bogdanm	0:9b334a45a8ff	844
bogdanm	0:9b334a45a8ff	845	#define CMSDK_PL110_RECOVRRUN_Pos 3 /!< CMSDK_PL110 RECOVRRUN: Receive Overrun Position /
bogdanm	0:9b334a45a8ff	846	#define CMSDK_PL110_RECOVRRUN_Msk (0x1ul << CMSDK_PL110_RECOVRRUN_Pos) /!< CMSDK_PL110 RECOVRRUN: Receive Overrun Mask /
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	#define CMSDK_PL110_RECBREAKERR_Pos 2 /!< CMSDK_PL110 RECBREAKERR: Receive Break Error Position /
bogdanm	0:9b334a45a8ff	849	#define CMSDK_PL110_RECBREAKERR_Msk (0x1ul << CMSDK_PL110_RECBREAKERR_Pos) /!< CMSDK_PL110 RECBREAKERR: Receive Break Error Mask /
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	#define CMSDK_PL110_RECPARITYERR_Pos 1 /!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Position /
bogdanm	0:9b334a45a8ff	852	#define CMSDK_PL110_RECPARITYERR_Msk (0x1ul << CMSDK_PL110_RECPARITYERR_Pos) /!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Mask /
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	#define CMSDK_PL110_RECFRAMEERR_Pos 0 /!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Position /
bogdanm	0:9b334a45a8ff	855	#define CMSDK_PL110_RECFRAMEERR_Msk (0x1ul << CMSDK_PL110_RECFRAMEERR_Pos) /!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Mask /
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	#define CMSDK_PL110_ERRCLROVRRUN_Pos 3 /!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Position /
bogdanm	0:9b334a45a8ff	858	#define CMSDK_PL110_ERRCLROVRRUN_Msk (0x1ul << CMSDK_PL110_ERRCLROVRRUN_Pos) /!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Mask /
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	#define CMSDK_PL110_ERRCLRBREAKERR_Pos 2 /!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Position /
bogdanm	0:9b334a45a8ff	861	#define CMSDK_PL110_ERRCLRBREAKERR_Msk (0x1ul << CMSDK_PL110_ERRCLRBREAKERR_Pos) /!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Mask /
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863	#define CMSDK_PL110_ERRCLRPARITYERR_Pos 1 /!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Position /
bogdanm	0:9b334a45a8ff	864	#define CMSDK_PL110_ERRCLRPARITYERR_Msk (0x1ul << CMSDK_PL110_ERRCLRPARITYERR_Pos) /!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Mask /
bogdanm	0:9b334a45a8ff	865
bogdanm	0:9b334a45a8ff	866	#define CMSDK_PL110_ERRCLRFRAMEERR_Pos 0 /!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Position /
bogdanm	0:9b334a45a8ff	867	#define CMSDK_PL110_ERRCLRFRAMEERR_Msk (0x1ul << CMSDK_PL110_ERRCLRFRAMEERR_Pos) /!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Mask /
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	#define CMSDK_PL110_FLAG_RINGIND_Pos 8 /!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Position /
bogdanm	0:9b334a45a8ff	870	#define CMSDK_PL110_FLAG_RINGIND_Msk (0x1ul << CMSDK_PL110_FLAG_RINGIND_Pos) /!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Mask /
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	#define CMSDK_PL110_FLAG_TXFEMPTY_Pos 7 /!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Position /
bogdanm	0:9b334a45a8ff	873	#define CMSDK_PL110_FLAG_TXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_TXFEMPTY_Pos) /!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Mask /
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	#define CMSDK_PL110_FLAG_RXFFULL_Pos 6 /!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Position /
bogdanm	0:9b334a45a8ff	876	#define CMSDK_PL110_FLAG_RXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_RXFFULL_Pos) /!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Mask /
bogdanm	0:9b334a45a8ff	877
bogdanm	0:9b334a45a8ff	878	#define CMSDK_PL110_FLAG_TXFFULL_Pos 5 /!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Position /
bogdanm	0:9b334a45a8ff	879	#define CMSDK_PL110_FLAG_TXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_TXFFULL_Pos) /!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Mask /
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	#define CMSDK_PL110_FLAG_RXFEMPTY_Pos 4 /!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Position /
bogdanm	0:9b334a45a8ff	882	#define CMSDK_PL110_FLAG_RXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_RXFEMPTY_Pos) /!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Mask /
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	#define CMSDK_PL110_FLAG_UARTBUSY_Pos 3 /!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Position /
bogdanm	0:9b334a45a8ff	885	#define CMSDK_PL110_FLAG_UARTBUSY_Msk (0x1ul << CMSDK_PL110_FLAG_UARTBUSY_Pos) /!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Mask /
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	#define CMSDK_PL110_FLAG_CARRIERDETECT_Pos 2 /!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Position /
bogdanm	0:9b334a45a8ff	888	#define CMSDK_PL110_FLAG_CARRIERDETECT_Msk (0x1ul << CMSDK_PL110_FLAG_CARRIERDETECT_Pos) /!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Mask /
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	#define CMSDK_PL110_FLAG_DATASETREADY_Pos 1 /!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Position /
bogdanm	0:9b334a45a8ff	891	#define CMSDK_PL110_FLAG_DATASETREADY_Msk (0x1ul << CMSDK_PL110_FLAG_DATASETREADY_Pos) /!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Mask /
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	#define CMSDK_PL110_FLAG_CLR2SEND_Pos 0 /!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Position /
bogdanm	0:9b334a45a8ff	894	#define CMSDK_PL110_FLAG_CLR2SEND_Msk (0x1ul << CMSDK_PL110_FLAG_CLR2SEND_Pos) /!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Mask /
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	#define CMSDK_PL110_IRDALOWPOWERCOUNT_Pos 0 /!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Position /
bogdanm	0:9b334a45a8ff	897	#define CMSDK_PL110_IRDALOWPOWERCOUNT_Msk (0xFFul << CMSDK_PL110_IRDALOWPOWERCOUNT_Pos) /!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Mask /
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	#define CMSDK_PL110_INTDIVIDER_Pos 0 /!< CMSDK_PL110 INTDIVIDER: Integer Divider Position /
bogdanm	0:9b334a45a8ff	900	#define CMSDK_PL110_INTDIVIDER_Msk (0xFFFFul << CMSDK_PL110_INTDIVIDER_Pos) /!< CMSDK_PL110 INTDIVIDER: Integer Divider Mask /
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	#define CMSDK_PL110_FRACTDIVIDER_Pos 0 /!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Position /
bogdanm	0:9b334a45a8ff	903	#define CMSDK_PL110_FRACTDIVIDER_Msk (0x3Ful << CMSDK_PL110_FRACTDIVIDER_Pos) /!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Mask /
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	#define CMSDK_PL110_STICKPARITYSEL_Pos 8 /!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Position /
bogdanm	0:9b334a45a8ff	906	#define CMSDK_PL110_STICKPARITYSEL_Msk (0x1ul << CMSDK_PL110_STICKPARITYSEL_Pos) /!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Mask /
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	#define CMSDK_PL110_WORDLEN_Pos 5 /!< CMSDK_PL110 WORDLEN: Word Length Select Position /
bogdanm	0:9b334a45a8ff	909	#define CMSDK_PL110_WORDLEN_Msk (0x3ul << CMSDK_PL110_WORDLEN_Pos) /!< CMSDK_PL110 WORDLEN: Word Length Select Mask /
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	#define CMSDK_PL110_ENFIFOS_Pos 4 /!< CMSDK_PL110 ENFIFOS: Enable FIFOs Position /
bogdanm	0:9b334a45a8ff	912	#define CMSDK_PL110_ENFIFOS_Msk (0x1ul << CMSDK_PL110_ENFIFOS_Pos) /!< CMSDK_PL110 ENFIFOS: Enable FIFOs Mask /
bogdanm	0:9b334a45a8ff	913
bogdanm	0:9b334a45a8ff	914	#define CMSDK_PL110_2STOPBITS_Pos 3 /!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Position /
bogdanm	0:9b334a45a8ff	915	#define CMSDK_PL110_2STOPBITS_Msk (0x1ul << CMSDK_PL110_2STOPBITS_Pos) /!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Mask /
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	#define CMSDK_PL110_EVENPARITY_Pos 2 /!< CMSDK_PL110 EVENPARITY: Even Parity Select Position /
bogdanm	0:9b334a45a8ff	918	#define CMSDK_PL110_EVENPARITY_Msk (0x1ul << CMSDK_PL110_EVENPARITY_Pos) /!< CMSDK_PL110 EVENPARITY: Even Parity Select Mask /
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	#define CMSDK_PL110_PARITYEN_Pos 1 /!< CMSDK_PL110 PARITYEN: Parity Enable Position /
bogdanm	0:9b334a45a8ff	921	#define CMSDK_PL110_PARITYEN_Msk (0x1ul << CMSDK_PL110_PARITYEN_Pos) /!< CMSDK_PL110 PARITYEN: Parity Enable Mask /
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	#define CMSDK_PL110_SENDBREAK_Pos 0 /!< CMSDK_PL110 SENDBREAK: Send Break Position /
bogdanm	0:9b334a45a8ff	924	#define CMSDK_PL110_SENDBREAK_Msk (0x1ul << CMSDK_PL110_SENDBREAK_Pos) /!< CMSDK_PL110 SENDBREAK: Send Break Mask /
bogdanm	0:9b334a45a8ff	925
bogdanm	0:9b334a45a8ff	926	#define CMSDK_PL110_CTS_FLOWCTRL_Pos 15 /!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Position /
bogdanm	0:9b334a45a8ff	927	#define CMSDK_PL110_CTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_CTS_FLOWCTRL_Pos) /!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Mask /
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	#define CMSDK_PL110_RTS_FLOWCTRL_Pos 14 /!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Position /
bogdanm	0:9b334a45a8ff	930	#define CMSDK_PL110_RTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_RTS_FLOWCTRL_Pos) /!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Mask /
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	#define CMSDK_PL110_OUT2_Pos 13 /!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Position /
bogdanm	0:9b334a45a8ff	933	#define CMSDK_PL110_OUT2_Msk (0x1ul << CMSDK_PL110_OUT2_Pos) /!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Mask /
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	#define CMSDK_PL110_OUT1_Pos 12 /!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Position /
bogdanm	0:9b334a45a8ff	936	#define CMSDK_PL110_OUT1_Msk (0x1ul << CMSDK_PL110_OUT1_Pos) /!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Mask /
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	#define CMSDK_PL110_REQ2SEND_Pos 11 /!< CMSDK_PL110 REQ2SEND: Request To Send Position /
bogdanm	0:9b334a45a8ff	939	#define CMSDK_PL110_REQ2SEND_Msk (0x1ul << CMSDK_PL110_REQ2SEND_Pos) /!< CMSDK_PL110 REQ2SEND: Request To Send Mask /
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	#define CMSDK_PL110_DATATRANSREADY_Pos 10 /!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Position /
bogdanm	0:9b334a45a8ff	942	#define CMSDK_PL110_DATATRANSREADY_Msk (0x1ul << CMSDK_PL110_DATATRANSREADY_Pos) /!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Mask /
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	#define CMSDK_PL110_RXEN_Pos 9 /!< CMSDK_PL110 RXEN: Receive Enable Position /
bogdanm	0:9b334a45a8ff	945	#define CMSDK_PL110_RXEN_Msk (0x1ul << CMSDK_PL110_RXEN_Pos) /!< CMSDK_PL110 RXEN: Receive Enable Mask /
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	#define CMSDK_PL110_TXEN_Pos 8 /!< CMSDK_PL110 TXEN: Transmit Enable Position /
bogdanm	0:9b334a45a8ff	948	#define CMSDK_PL110_TXEN_Msk (0x1ul << CMSDK_PL110_TXEN_Pos) /!< CMSDK_PL110 TXEN: Transmit Enable Mask /
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	#define CMSDK_PL110_LOOPBACKEN_Pos 7 /!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Position /
bogdanm	0:9b334a45a8ff	951	#define CMSDK_PL110_LOOPBACKEN_Msk (0x1ul << CMSDK_PL110_LOOPBACKEN_Pos) /!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Mask /
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	#define CMSDK_PL110_IRDASIRLPM_Pos 2 /!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Position /
bogdanm	0:9b334a45a8ff	954	#define CMSDK_PL110_IRDASIRLPM_Msk (0x1ul << CMSDK_PL110_IRDASIRLPM_Pos) /!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Mask /
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	#define CMSDK_PL110_SIREN_Pos 1 /!< CMSDK_PL110 SIREN: SIR Enable Position /
bogdanm	0:9b334a45a8ff	957	#define CMSDK_PL110_SIREN_Msk (0x1ul << CMSDK_PL110_SIREN_Pos) /!< CMSDK_PL110 SIREN: SIR Enable Mask /
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	#define CMSDK_PL110_UARTEN_Pos 0 /!< CMSDK_PL110 UARTEN: UART Enable Position /
bogdanm	0:9b334a45a8ff	960	#define CMSDK_PL110_UARTEN_Msk (0x1ul << CMSDK_PL110_UARTEN_Pos) /!< CMSDK_PL110 UARTEN: UART Enable Mask /
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	#define CMSDK_PL110_RECINTFIFOLEVEL_Pos 3 /!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Position /
bogdanm	0:9b334a45a8ff	963	#define CMSDK_PL110_RECINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_RECINTFIFOLEVEL_Pos) /!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Mask /
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	#define CMSDK_PL110_TRANSINTFIFOLEVEL_Pos 0 /!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Position /
bogdanm	0:9b334a45a8ff	966	#define CMSDK_PL110_TRANSINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_TRANSINTFIFOLEVEL_Pos) /!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Mask /
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos 10 /!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Position /
bogdanm	0:9b334a45a8ff	969	#define CMSDK_PL110_SETMASK_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos) /!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Mask /
bogdanm	0:9b334a45a8ff	970
bogdanm	0:9b334a45a8ff	971	#define CMSDK_PL110_SETMASK_BREAKERRINT_Pos 9 /!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Position /
bogdanm	0:9b334a45a8ff	972	#define CMSDK_PL110_SETMASK_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_BREAKERRINT_Pos) /!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Mask /
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	#define CMSDK_PL110_SETMASK_PARITYERRINT_Pos 8 /!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Position /
bogdanm	0:9b334a45a8ff	975	#define CMSDK_PL110_SETMASK_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_PARITYERRINT_Pos) /!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Mask /
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	#define CMSDK_PL110_SETMASK_FRAMEERRINT_Pos 7 /!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Position /
bogdanm	0:9b334a45a8ff	978	#define CMSDK_PL110_SETMASK_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_FRAMEERRINT_Pos) /!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Mask /
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980	#define CMSDK_PL110_SETMASK_RECTRANSINT_Pos 6 /!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Position /
bogdanm	0:9b334a45a8ff	981	#define CMSDK_PL110_SETMASK_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECTRANSINT_Pos) /!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Mask /
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	#define CMSDK_PL110_SETMASK_TRANSINT_Pos 5 /!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Position /
bogdanm	0:9b334a45a8ff	984	#define CMSDK_PL110_SETMASK_TRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_TRANSINT_Pos) /!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Mask /
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	#define CMSDK_PL110_SETMASK_RECINT_Pos 4 /!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Position /
bogdanm	0:9b334a45a8ff	987	#define CMSDK_PL110_SETMASK_RECINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECINT_Pos) /!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Mask /
bogdanm	0:9b334a45a8ff	988
bogdanm	0:9b334a45a8ff	989	#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Pos 3 /!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Position /
bogdanm	0:9b334a45a8ff	990	#define CMSDK_PL110_SETMASK_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UARTD_SRMODINT_Pos) /!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Mask /
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos 2 /!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Position /
bogdanm	0:9b334a45a8ff	993	#define CMSDK_PL110_SETMASK_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos) /!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Mask /
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos 1 /!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Position /
bogdanm	0:9b334a45a8ff	996	#define CMSDK_PL110_SETMASK_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos) /!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Mask /
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	#define CMSDK_PL110_SETMASK_UART_RIMODINT_Pos 0 /!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Position /
bogdanm	0:9b334a45a8ff	999	#define CMSDK_PL110_SETMASK_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_RIMODINT_Pos) /!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Mask /
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001	#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos 10 /!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask Position /
bogdanm	0:9b334a45a8ff	1002	#define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos 9 /!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask Position /
bogdanm	0:9b334a45a8ff	1005	#define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos 8 /!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask Position /
bogdanm	0:9b334a45a8ff	1008	#define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos 7 /!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask Position /
bogdanm	0:9b334a45a8ff	1011	#define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos 6 /!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Position /
bogdanm	0:9b334a45a8ff	1014	#define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Mask /
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos 5 /!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Position /
bogdanm	0:9b334a45a8ff	1017	#define CMSDK_PL110_RAWINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Mask /
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019	#define CMSDK_PL110_RAWINTSTAT_RECINT_Pos 4 /!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Position /
bogdanm	0:9b334a45a8ff	1020	#define CMSDK_PL110_RAWINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Mask /
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Pos 3 /!< CMSDK_PL110 RAWINTSTAT_UART_DSRMODINT: Raw Data Set Ready Int Status Position /
bogdanm	0:9b334a45a8ff	1023	#define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UARTD_SRMODINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_UARTD_SRMODINT: Raw Data Set Ready Int Status Mask /
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos 2 /!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Position /
bogdanm	0:9b334a45a8ff	1026	#define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Mask /
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos 1 /!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Position /
bogdanm	0:9b334a45a8ff	1029	#define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Mask /
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031	#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos 0 /!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Position /
bogdanm	0:9b334a45a8ff	1032	#define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos) /!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Mask /
bogdanm	0:9b334a45a8ff	1033
bogdanm	0:9b334a45a8ff	1034	#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos 10 /!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Position /
bogdanm	0:9b334a45a8ff	1035	#define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos 9 /!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Position /
bogdanm	0:9b334a45a8ff	1038	#define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos 8 /!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Position /
bogdanm	0:9b334a45a8ff	1041	#define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos 7 /!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Position /
bogdanm	0:9b334a45a8ff	1044	#define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Mask /
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos 6 /!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Position /
bogdanm	0:9b334a45a8ff	1047	#define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Mask /
bogdanm	0:9b334a45a8ff	1048
bogdanm	0:9b334a45a8ff	1049	#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos 5 /!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Position /
bogdanm	0:9b334a45a8ff	1050	#define CMSDK_PL110_MSKINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Mask /
bogdanm	0:9b334a45a8ff	1051
bogdanm	0:9b334a45a8ff	1052	#define CMSDK_PL110_MSKINTSTAT_RECINT_Pos 4 /!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Position /
bogdanm	0:9b334a45a8ff	1053	#define CMSDK_PL110_MSKINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Mask /
bogdanm	0:9b334a45a8ff	1054
bogdanm	0:9b334a45a8ff	1055	#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Pos 3 /!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Position /
bogdanm	0:9b334a45a8ff	1056	#define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UARTD_SRMODINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Mask /
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos 2 /!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Position /
bogdanm	0:9b334a45a8ff	1059	#define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Mask /
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos 1 /!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Position /
bogdanm	0:9b334a45a8ff	1062	#define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Mask /
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos 0 /!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Position /
bogdanm	0:9b334a45a8ff	1065	#define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos) /!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Mask /
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos 10 /!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Position /
bogdanm	0:9b334a45a8ff	1068	#define CMSDK_PL110_INTCLR_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos) /!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Mask /
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	#define CMSDK_PL110_INTCLR_BREAKERRINT_Pos 9 /!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Position /
bogdanm	0:9b334a45a8ff	1071	#define CMSDK_PL110_INTCLR_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_BREAKERRINT_Pos) /!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Mask /
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	#define CMSDK_PL110_INTCLR_PARITYERRINT_Pos 8 /!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Position /
bogdanm	0:9b334a45a8ff	1074	#define CMSDK_PL110_INTCLR_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_PARITYERRINT_Pos) /!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Mask /
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	#define CMSDK_PL110_INTCLR_FRAMEERRINT_Pos 7 /!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Position /
bogdanm	0:9b334a45a8ff	1077	#define CMSDK_PL110_INTCLR_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_FRAMEERRINT_Pos) /!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Mask /
bogdanm	0:9b334a45a8ff	1078
bogdanm	0:9b334a45a8ff	1079	#define CMSDK_PL110_INTCLR_RECTRANSINT_Pos 6 /!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Position /
bogdanm	0:9b334a45a8ff	1080	#define CMSDK_PL110_INTCLR_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECTRANSINT_Pos) /!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Mask /
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	#define CMSDK_PL110_INTCLR_TRANSINT_Pos 5 /!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Position /
bogdanm	0:9b334a45a8ff	1083	#define CMSDK_PL110_INTCLR_TRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_TRANSINT_Pos) /!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Mask /
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	#define CMSDK_PL110_INTCLR_RECINT_Pos 4 /!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Position /
bogdanm	0:9b334a45a8ff	1086	#define CMSDK_PL110_INTCLR_RECINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECINT_Pos) /!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Mask /
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Pos 3 /!< CMSDK_PL110 INTCLR_UART_DSRMODINT: Clear Data Carrier Detect Int Position /
bogdanm	0:9b334a45a8ff	1089	#define CMSDK_PL110_INTCLR_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UARTD_SRMODINT_Pos) /!< CMSDK_PL110 INTCLR_UARTD_SRMODINT: Clear Data Carrier Detect Int Mask /
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos 2 /!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Position /
bogdanm	0:9b334a45a8ff	1092	#define CMSDK_PL110_INTCLR_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos) /!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Mask /
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos 1 /!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Position /
bogdanm	0:9b334a45a8ff	1095	#define CMSDK_PL110_INTCLR_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos) /!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Mask /
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	#define CMSDK_PL110_INTCLR_UART_RIMODINT_Pos 0 /!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Position /
bogdanm	0:9b334a45a8ff	1098	#define CMSDK_PL110_INTCLR_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_RIMODINT_Pos) /!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Mask /
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	#define CMSDK_PL110_DMA_ERR_Pos 2 /!< CMSDK_PL110 DMA_ERR: DMA Error Position /
bogdanm	0:9b334a45a8ff	1101	#define CMSDK_PL110_DMA_ERR_Msk (0x1ul << CMSDK_PL110_DMA_ERR_Pos) /!< CMSDK_PL110 DMA_ERR: DMA Error Mask /
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	#define CMSDK_PL110_DMA_TRANS_EN_Pos 1 /!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Position /
bogdanm	0:9b334a45a8ff	1104	#define CMSDK_PL110_DMA_TRANS_EN_Msk (0x1ul << CMSDK_PL110_DMA_TRANS_EN_Pos) /!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Mask /
bogdanm	0:9b334a45a8ff	1105
bogdanm	0:9b334a45a8ff	1106	#define CMSDK_PL110_DMA_REC_EN_Pos 0 /!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Position /
bogdanm	0:9b334a45a8ff	1107	#define CMSDK_PL110_DMA_REC_EN_Msk (0x1ul << CMSDK_PL110_DMA_REC_EN_Pos) /!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Mask /
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	/@}/ /* end of group CMSDK_PL110 */
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/------------------- Watchdog ----------------------------------------------/
bogdanm	0:9b334a45a8ff	1113	/** @addtogroup CMSDK_Watchdog CMSDK Watchdog
bogdanm	0:9b334a45a8ff	1114	@{
bogdanm	0:9b334a45a8ff	1115	*/
bogdanm	0:9b334a45a8ff	1116	typedef struct
bogdanm	0:9b334a45a8ff	1117	{
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
bogdanm	0:9b334a45a8ff	1120	__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
bogdanm	0:9b334a45a8ff	1121	__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
mbed_official	80:bdf1132a57cf	1122	/* <o.1> RESEN: Reset enable */
mbed_official	80:bdf1132a57cf	1123	/* <o.0> INTEN: Interrupt enable */
mbed_official	80:bdf1132a57cf	1124	/* </h> */
bogdanm	0:9b334a45a8ff	1125	__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
bogdanm	0:9b334a45a8ff	1126	__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
bogdanm	0:9b334a45a8ff	1127	__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
bogdanm	0:9b334a45a8ff	1128	uint32_t RESERVED0[762];
bogdanm	0:9b334a45a8ff	1129	__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
bogdanm	0:9b334a45a8ff	1130	uint32_t RESERVED1[191];
bogdanm	0:9b334a45a8ff	1131	__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
bogdanm	0:9b334a45a8ff	1132	__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
bogdanm	0:9b334a45a8ff	1133	}CMSDK_WATCHDOG_TypeDef;
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	#define CMSDK_Watchdog_LOAD_Pos 0 /!< CMSDK_Watchdog LOAD: LOAD Position /
bogdanm	0:9b334a45a8ff	1136	#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /!< CMSDK_Watchdog LOAD: LOAD Mask /
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	#define CMSDK_Watchdog_VALUE_Pos 0 /!< CMSDK_Watchdog VALUE: VALUE Position /
bogdanm	0:9b334a45a8ff	1139	#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /!< CMSDK_Watchdog VALUE: VALUE Mask /
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position /
bogdanm	0:9b334a45a8ff	1142	#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask /
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position /
bogdanm	0:9b334a45a8ff	1145	#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask /
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	#define CMSDK_Watchdog_INTCLR_Pos 0 /!< CMSDK_Watchdog INTCLR: Int Clear Position /
bogdanm	0:9b334a45a8ff	1148	#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /!< CMSDK_Watchdog INTCLR: Int Clear Mask /
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position /
bogdanm	0:9b334a45a8ff	1151	#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask /
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position /
bogdanm	0:9b334a45a8ff	1154	#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask /
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	#define CMSDK_Watchdog_LOCK_Pos 0 /!< CMSDK_Watchdog LOCK: LOCK Position /
bogdanm	0:9b334a45a8ff	1157	#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /!< CMSDK_Watchdog LOCK: LOCK Mask /
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position /
bogdanm	0:9b334a45a8ff	1160	#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask /
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position /
bogdanm	0:9b334a45a8ff	1163	#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask /
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/@}/ /* end of group CMSDK_Watchdog */
bogdanm	0:9b334a45a8ff	1166
bogdanm	0:9b334a45a8ff	1167	/------------------- PrimeCell APB GPIO --------------------------------------/
bogdanm	0:9b334a45a8ff	1168	/** @addtogroup CMSDK_PL061 CMSDK APB GPIO
bogdanm	0:9b334a45a8ff	1169	@{
bogdanm	0:9b334a45a8ff	1170	*/
bogdanm	0:9b334a45a8ff	1171	typedef struct
bogdanm	0:9b334a45a8ff	1172	{
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	__IO uint32_t DATA[256];
bogdanm	0:9b334a45a8ff	1175	__IO uint32_t DIR;
bogdanm	0:9b334a45a8ff	1176	__IO uint32_t INTSENSE;
bogdanm	0:9b334a45a8ff	1177	__IO uint32_t INTBOTHEDGE;
bogdanm	0:9b334a45a8ff	1178	__IO uint32_t INTEVENT;
bogdanm	0:9b334a45a8ff	1179	__IO uint32_t INTMASK;
bogdanm	0:9b334a45a8ff	1180	__O uint32_t RAWINTSTAT;
bogdanm	0:9b334a45a8ff	1181	__O uint32_t MASKINTSTAT;
bogdanm	0:9b334a45a8ff	1182	__I uint32_t INTCLR;
bogdanm	0:9b334a45a8ff	1183	__IO uint32_t MODECTRL;
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	}APBGPIO_TypeDef;
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	#define CMSDK_PL061_DATA_Pos 0 /!< CMSDK_PL061 DATA: DATA Position /
bogdanm	0:9b334a45a8ff	1188	#define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /!< CMSDK_PL061 DATA: DATA Mask /
bogdanm	0:9b334a45a8ff	1189
bogdanm	0:9b334a45a8ff	1190	#define CMSDK_PL061_DIR_Pos 0 /!< CMSDK_PL061 DIR: Data Direction Position /
bogdanm	0:9b334a45a8ff	1191	#define CMSDK_PL061_DIR_Msk (0x1ul << CMSDK_PL061_DIR_Pos) /!< CMSDK_PL061 DIR: Data Direction Mask /
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	#define CMSDK_PL061_INTSENSE_Pos 0 /!< CMSDK_PL061 INTSENSE: INT SENSE Position /
bogdanm	0:9b334a45a8ff	1194	#define CMSDK_PL061_INTSENSE_Msk (0x1ul << CMSDK_PL061_INTSENSE_Pos) /!< CMSDK_PL061 INTSENSE: INT SENSE Mask /
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	#define CMSDK_PL061_INTBOTHEDGE_Pos 0 /!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Position /
bogdanm	0:9b334a45a8ff	1197	#define CMSDK_PL061_INTBOTHEDGE_Msk (0x1ul << CMSDK_PL061_INTBOTHEDGE_Pos) /!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Mask /
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	#define CMSDK_PL061_INTEVENT_Pos 0 /!< CMSDK_PL061 INTEVENT: INT EVENT Position /
bogdanm	0:9b334a45a8ff	1200	#define CMSDK_PL061_INTEVENT_Msk (0x1ul << CMSDK_PL061_INTEVENT_Pos) /!< CMSDK_PL061 INTEVENT: INT EVENT Mask /
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	#define CMSDK_PL061_INTMASK_Pos 0 /!< CMSDK_PL061 INTMASK: INT MASK Position /
bogdanm	0:9b334a45a8ff	1203	#define CMSDK_PL061_INTMASK_Msk (0x1ul << CMSDK_PL061_INTMASK_Pos) /!< CMSDK_PL061 INTMASK: INT MASK Mask /
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	#define CMSDK_PL061_RAWINTSTAT_Pos 0 /!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Position /
bogdanm	0:9b334a45a8ff	1206	#define CMSDK_PL061_RAWINTSTAT_Msk (0x1ul << CMSDK_PL061_RAWINTSTAT_Pos) /!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Mask /
bogdanm	0:9b334a45a8ff	1207
bogdanm	0:9b334a45a8ff	1208	#define CMSDK_PL061_MASKINTSTAT_Pos 0 /!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Position /
bogdanm	0:9b334a45a8ff	1209	#define CMSDK_PL061_MASKINTSTAT_Msk (0x1ul << CMSDK_PL061_MASKINTSTAT_Pos) /!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Mask /
bogdanm	0:9b334a45a8ff	1210
bogdanm	0:9b334a45a8ff	1211	#define CMSDK_PL061_INTCLR_Pos 0 /!< CMSDK_PL061 INTCLR: Int Clear Position /
bogdanm	0:9b334a45a8ff	1212	#define CMSDK_PL061_INTCLR_Msk (0x1ul << CMSDK_PL061_INTCLR_Pos) /!< CMSDK_PL061 INTCLR: Int Clear Mask /
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	#define CMSDK_PL061_MODECTRL_HWEN_Pos 0 /!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Position /
bogdanm	0:9b334a45a8ff	1215	#define CMSDK_PL061_MODECTRL_HWEN_Msk (0x1ul << CMSDK_PL061_MODECTRL_HWEN_Pos) /!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Mask /
bogdanm	0:9b334a45a8ff	1216
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/@}/ /* end of group CMSDK_PL061 */
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221	#if defined ( __CC_ARM )
bogdanm	0:9b334a45a8ff	1222	#pragma no_anon_unions
bogdanm	0:9b334a45a8ff	1223	#endif
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/@}/ /* end of group CMSDK_CM4_Peripherals */
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227
bogdanm	0:9b334a45a8ff	1228	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1229	/* Peripheral memory map */
bogdanm	0:9b334a45a8ff	1230	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1231	/** @addtogroup CMSDK_CM4_MemoryMap CMSDK_CM4 Memory Mapping
bogdanm	0:9b334a45a8ff	1232	@{
bogdanm	0:9b334a45a8ff	1233	*/
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	/* Peripheral and SRAM base address */
bogdanm	0:9b334a45a8ff	1236	#define CMSDK_FLASH_BASE (0x00000000UL) /!< (FLASH ) Base Address /
bogdanm	0:9b334a45a8ff	1237	#define CMSDK_SRAM_BASE (0x20000000UL) /!< (SRAM ) Base Address /
bogdanm	0:9b334a45a8ff	1238	#define CMSDK_PERIPH_BASE (0x40000000UL) /!< (Peripheral) Base Address /
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/* Base addresses */
bogdanm	0:9b334a45a8ff	1241	#define CMSDK_RAM_BASE (0x20000000UL)
bogdanm	0:9b334a45a8ff	1242	#define CMSDK_APB_BASE (0x40000000UL)
bogdanm	0:9b334a45a8ff	1243	#define CMSDK_AHB_BASE (0x40010000UL)
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/* APB peripherals */
bogdanm	0:9b334a45a8ff	1246	#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
bogdanm	0:9b334a45a8ff	1247	#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
bogdanm	0:9b334a45a8ff	1248	#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
bogdanm	0:9b334a45a8ff	1249	#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
bogdanm	0:9b334a45a8ff	1250	#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
bogdanm	0:9b334a45a8ff	1251	#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
bogdanm	0:9b334a45a8ff	1252	#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
bogdanm	0:9b334a45a8ff	1253	#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
mbed_official	80:bdf1132a57cf	1254	#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
bogdanm	0:9b334a45a8ff	1255	#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
mbed_official	80:bdf1132a57cf	1256	#define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
bogdanm	0:9b334a45a8ff	1257	#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/* AHB peripherals */
bogdanm	0:9b334a45a8ff	1260	#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
bogdanm	0:9b334a45a8ff	1261	#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
bogdanm	0:9b334a45a8ff	1262	#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
bogdanm	0:9b334a45a8ff	1263	#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
bogdanm	0:9b334a45a8ff	1264	#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
bogdanm	0:9b334a45a8ff	1265	/@}/ /* end of group CMSDK_CM4_MemoryMap */
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1269	/* Peripheral declaration */
bogdanm	0:9b334a45a8ff	1270	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1271	/** @addtogroup CMSDK_CM4_PeripheralDecl CMSDK_CM4 Peripheral Declaration
bogdanm	0:9b334a45a8ff	1272	@{
bogdanm	0:9b334a45a8ff	1273	*/
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
bogdanm	0:9b334a45a8ff	1276	#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
bogdanm	0:9b334a45a8ff	1277	#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
mbed_official	80:bdf1132a57cf	1278	#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
mbed_official	80:bdf1132a57cf	1279	#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
mbed_official	80:bdf1132a57cf	1280	#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
mbed_official	80:bdf1132a57cf	1281	#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
bogdanm	0:9b334a45a8ff	1282	#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
bogdanm	0:9b334a45a8ff	1283	#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
bogdanm	0:9b334a45a8ff	1284	#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
bogdanm	0:9b334a45a8ff	1285	#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
bogdanm	0:9b334a45a8ff	1286	#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
bogdanm	0:9b334a45a8ff	1287	#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
bogdanm	0:9b334a45a8ff	1288	#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
bogdanm	0:9b334a45a8ff	1289	#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
bogdanm	0:9b334a45a8ff	1290	#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
bogdanm	0:9b334a45a8ff	1291	#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
bogdanm	0:9b334a45a8ff	1292	/@}/ /* end of group CMSDK_CM4_PeripheralDecl */
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294	/@}/ /* end of group CMSDK_CM4_Definitions */
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1297	}
bogdanm	0:9b334a45a8ff	1298	#endif
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	#endif /* CMSDK_CM4_H */

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h@80:bdf1132a57cf, 2016-03-02 (annotated)

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