added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 50:a417edff4437
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file em_ebi.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @brief External Bus Interface (EBI) Peripheral API |
<> | 144:ef7eb2e8f9f7 | 4 | * @version 4.2.1 |
<> | 144:ef7eb2e8f9f7 | 5 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 6 | * @section License |
<> | 144:ef7eb2e8f9f7 | 7 | * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b> |
<> | 144:ef7eb2e8f9f7 | 8 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Permission is granted to anyone to use this software for any purpose, |
<> | 144:ef7eb2e8f9f7 | 11 | * including commercial applications, and to alter it and redistribute it |
<> | 144:ef7eb2e8f9f7 | 12 | * freely, subject to the following restrictions: |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 144:ef7eb2e8f9f7 | 15 | * claim that you wrote the original software. |
<> | 144:ef7eb2e8f9f7 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 144:ef7eb2e8f9f7 | 17 | * misrepresented as being the original software. |
<> | 144:ef7eb2e8f9f7 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 144:ef7eb2e8f9f7 | 19 | * |
<> | 144:ef7eb2e8f9f7 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
<> | 144:ef7eb2e8f9f7 | 21 | * obligation to support this Software. Silicon Labs is providing the |
<> | 144:ef7eb2e8f9f7 | 22 | * Software "AS IS", with no express or implied warranties of any kind, |
<> | 144:ef7eb2e8f9f7 | 23 | * including, but not limited to, any implied warranties of merchantability |
<> | 144:ef7eb2e8f9f7 | 24 | * or fitness for any particular purpose or warranties against infringement |
<> | 144:ef7eb2e8f9f7 | 25 | * of any proprietary rights of a third party. |
<> | 144:ef7eb2e8f9f7 | 26 | * |
<> | 144:ef7eb2e8f9f7 | 27 | * Silicon Labs will not be liable for any consequential, incidental, or |
<> | 144:ef7eb2e8f9f7 | 28 | * special damages, or any other relief, or for any claim by any third party, |
<> | 144:ef7eb2e8f9f7 | 29 | * arising from your use of this Software. |
<> | 144:ef7eb2e8f9f7 | 30 | * |
<> | 144:ef7eb2e8f9f7 | 31 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | #include "em_ebi.h" |
<> | 144:ef7eb2e8f9f7 | 34 | #if defined(EBI_COUNT) && (EBI_COUNT > 0) |
<> | 144:ef7eb2e8f9f7 | 35 | #include "em_assert.h" |
<> | 144:ef7eb2e8f9f7 | 36 | #include "em_bus.h" |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 39 | * @addtogroup EM_Library |
<> | 144:ef7eb2e8f9f7 | 40 | * @{ |
<> | 144:ef7eb2e8f9f7 | 41 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 44 | * @addtogroup EBI |
<> | 144:ef7eb2e8f9f7 | 45 | * @brief EBI External Bus Interface (EBI) Peripheral API |
<> | 144:ef7eb2e8f9f7 | 46 | * @{ |
<> | 144:ef7eb2e8f9f7 | 47 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 50 | * @brief |
<> | 144:ef7eb2e8f9f7 | 51 | * Configure and enable External Bus Interface |
<> | 144:ef7eb2e8f9f7 | 52 | * |
<> | 144:ef7eb2e8f9f7 | 53 | * @param[in] ebiInit |
<> | 144:ef7eb2e8f9f7 | 54 | * EBI configuration structure |
<> | 144:ef7eb2e8f9f7 | 55 | * |
<> | 144:ef7eb2e8f9f7 | 56 | * @note |
<> | 144:ef7eb2e8f9f7 | 57 | * GPIO lines must be configured as PUSH_PULL for correct operation |
<> | 144:ef7eb2e8f9f7 | 58 | * GPIO and EBI clocks must be enabled in the CMU |
<> | 144:ef7eb2e8f9f7 | 59 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 60 | void EBI_Init(const EBI_Init_TypeDef *ebiInit) |
<> | 144:ef7eb2e8f9f7 | 61 | { |
<> | 144:ef7eb2e8f9f7 | 62 | uint32_t ctrl = EBI->CTRL; |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 65 | /* Enable Independent Timing for devices that supports it */ |
<> | 144:ef7eb2e8f9f7 | 66 | ctrl |= EBI_CTRL_ITS; |
<> | 144:ef7eb2e8f9f7 | 67 | |
<> | 144:ef7eb2e8f9f7 | 68 | /* Set polarity of address ready */ |
<> | 144:ef7eb2e8f9f7 | 69 | EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity); |
<> | 144:ef7eb2e8f9f7 | 70 | /* Set polarity of address latch enable */ |
<> | 144:ef7eb2e8f9f7 | 71 | EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity); |
<> | 144:ef7eb2e8f9f7 | 72 | /* Set polarity of write enable */ |
<> | 144:ef7eb2e8f9f7 | 73 | EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity); |
<> | 144:ef7eb2e8f9f7 | 74 | /* Set polarity of read enable */ |
<> | 144:ef7eb2e8f9f7 | 75 | EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity); |
<> | 144:ef7eb2e8f9f7 | 76 | /* Set polarity of chip select lines */ |
<> | 144:ef7eb2e8f9f7 | 77 | EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity); |
<> | 144:ef7eb2e8f9f7 | 78 | /* Set polarity of byte lane line */ |
<> | 144:ef7eb2e8f9f7 | 79 | EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity); |
<> | 144:ef7eb2e8f9f7 | 80 | #else |
<> | 144:ef7eb2e8f9f7 | 81 | /* Set polarity of address ready */ |
<> | 144:ef7eb2e8f9f7 | 82 | EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity); |
<> | 144:ef7eb2e8f9f7 | 83 | /* Set polarity of address latch enable */ |
<> | 144:ef7eb2e8f9f7 | 84 | EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity); |
<> | 144:ef7eb2e8f9f7 | 85 | /* Set polarity of write enable */ |
<> | 144:ef7eb2e8f9f7 | 86 | EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity); |
<> | 144:ef7eb2e8f9f7 | 87 | /* Set polarity of read enable */ |
<> | 144:ef7eb2e8f9f7 | 88 | EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity); |
<> | 144:ef7eb2e8f9f7 | 89 | /* Set polarity of chip select lines */ |
<> | 144:ef7eb2e8f9f7 | 90 | EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity); |
<> | 144:ef7eb2e8f9f7 | 91 | #endif |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | /* Configure EBI mode and control settings */ |
<> | 144:ef7eb2e8f9f7 | 94 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 95 | if (ebiInit->banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 96 | { |
<> | 144:ef7eb2e8f9f7 | 97 | ctrl &= ~(_EBI_CTRL_MODE_MASK |
<> | 144:ef7eb2e8f9f7 | 98 | | _EBI_CTRL_ARDYEN_MASK |
<> | 144:ef7eb2e8f9f7 | 99 | | _EBI_CTRL_ARDYTODIS_MASK |
<> | 144:ef7eb2e8f9f7 | 100 | | _EBI_CTRL_BL_MASK |
<> | 144:ef7eb2e8f9f7 | 101 | | _EBI_CTRL_NOIDLE_MASK |
<> | 144:ef7eb2e8f9f7 | 102 | | _EBI_CTRL_BANK0EN_MASK); |
<> | 144:ef7eb2e8f9f7 | 103 | ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 104 | ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 105 | ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 106 | ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 107 | ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 108 | if ( ebiInit->enable) |
<> | 144:ef7eb2e8f9f7 | 109 | { |
<> | 144:ef7eb2e8f9f7 | 110 | ctrl |= EBI_CTRL_BANK0EN; |
<> | 144:ef7eb2e8f9f7 | 111 | } |
<> | 144:ef7eb2e8f9f7 | 112 | } |
<> | 144:ef7eb2e8f9f7 | 113 | if (ebiInit->banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 114 | { |
<> | 144:ef7eb2e8f9f7 | 115 | ctrl &= ~(_EBI_CTRL_BL1_MASK |
<> | 144:ef7eb2e8f9f7 | 116 | | _EBI_CTRL_MODE1_MASK |
<> | 144:ef7eb2e8f9f7 | 117 | | _EBI_CTRL_ARDY1EN_MASK |
<> | 144:ef7eb2e8f9f7 | 118 | | _EBI_CTRL_ARDYTO1DIS_MASK |
<> | 144:ef7eb2e8f9f7 | 119 | | _EBI_CTRL_NOIDLE1_MASK |
<> | 144:ef7eb2e8f9f7 | 120 | | _EBI_CTRL_BANK1EN_MASK); |
<> | 144:ef7eb2e8f9f7 | 121 | ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 122 | ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 123 | ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 124 | ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 125 | ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 126 | if ( ebiInit->enable) |
<> | 144:ef7eb2e8f9f7 | 127 | { |
<> | 144:ef7eb2e8f9f7 | 128 | ctrl |= EBI_CTRL_BANK1EN; |
<> | 144:ef7eb2e8f9f7 | 129 | } |
<> | 144:ef7eb2e8f9f7 | 130 | } |
<> | 144:ef7eb2e8f9f7 | 131 | if (ebiInit->banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 132 | { |
<> | 144:ef7eb2e8f9f7 | 133 | ctrl &= ~(_EBI_CTRL_BL2_MASK |
<> | 144:ef7eb2e8f9f7 | 134 | | _EBI_CTRL_MODE2_MASK |
<> | 144:ef7eb2e8f9f7 | 135 | | _EBI_CTRL_ARDY2EN_MASK |
<> | 144:ef7eb2e8f9f7 | 136 | | _EBI_CTRL_ARDYTO2DIS_MASK |
<> | 144:ef7eb2e8f9f7 | 137 | | _EBI_CTRL_NOIDLE2_MASK |
<> | 144:ef7eb2e8f9f7 | 138 | | _EBI_CTRL_BANK2EN_MASK); |
<> | 144:ef7eb2e8f9f7 | 139 | ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 140 | ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 141 | ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 142 | ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 143 | ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 144 | if ( ebiInit->enable) |
<> | 144:ef7eb2e8f9f7 | 145 | { |
<> | 144:ef7eb2e8f9f7 | 146 | ctrl |= EBI_CTRL_BANK2EN; |
<> | 144:ef7eb2e8f9f7 | 147 | } |
<> | 144:ef7eb2e8f9f7 | 148 | } |
<> | 144:ef7eb2e8f9f7 | 149 | if (ebiInit->banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 150 | { |
<> | 144:ef7eb2e8f9f7 | 151 | ctrl &= ~(_EBI_CTRL_BL3_MASK |
<> | 144:ef7eb2e8f9f7 | 152 | | _EBI_CTRL_MODE3_MASK |
<> | 144:ef7eb2e8f9f7 | 153 | | _EBI_CTRL_ARDY3EN_MASK |
<> | 144:ef7eb2e8f9f7 | 154 | | _EBI_CTRL_ARDYTO3DIS_MASK |
<> | 144:ef7eb2e8f9f7 | 155 | | _EBI_CTRL_NOIDLE3_MASK |
<> | 144:ef7eb2e8f9f7 | 156 | | _EBI_CTRL_BANK3EN_MASK); |
<> | 144:ef7eb2e8f9f7 | 157 | ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 158 | ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 159 | ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 160 | ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 161 | ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 162 | if ( ebiInit->enable) |
<> | 144:ef7eb2e8f9f7 | 163 | { |
<> | 144:ef7eb2e8f9f7 | 164 | ctrl |= EBI_CTRL_BANK3EN; |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | } |
<> | 144:ef7eb2e8f9f7 | 167 | #else |
<> | 144:ef7eb2e8f9f7 | 168 | ctrl &= ~(_EBI_CTRL_MODE_MASK |
<> | 144:ef7eb2e8f9f7 | 169 | | _EBI_CTRL_ARDYEN_MASK |
<> | 144:ef7eb2e8f9f7 | 170 | | _EBI_CTRL_ARDYTODIS_MASK |
<> | 144:ef7eb2e8f9f7 | 171 | | _EBI_CTRL_BANK0EN_MASK |
<> | 144:ef7eb2e8f9f7 | 172 | | _EBI_CTRL_BANK1EN_MASK |
<> | 144:ef7eb2e8f9f7 | 173 | | _EBI_CTRL_BANK2EN_MASK |
<> | 144:ef7eb2e8f9f7 | 174 | | _EBI_CTRL_BANK3EN_MASK); |
<> | 144:ef7eb2e8f9f7 | 175 | if ( ebiInit->enable) |
<> | 144:ef7eb2e8f9f7 | 176 | { |
<> | 144:ef7eb2e8f9f7 | 177 | if ( ebiInit->banks & EBI_BANK0 ) |
<> | 144:ef7eb2e8f9f7 | 178 | { |
<> | 144:ef7eb2e8f9f7 | 179 | ctrl |= EBI_CTRL_BANK0EN; |
<> | 144:ef7eb2e8f9f7 | 180 | } |
<> | 144:ef7eb2e8f9f7 | 181 | if ( ebiInit->banks & EBI_BANK1 ) |
<> | 144:ef7eb2e8f9f7 | 182 | { |
<> | 144:ef7eb2e8f9f7 | 183 | ctrl |= EBI_CTRL_BANK1EN; |
<> | 144:ef7eb2e8f9f7 | 184 | } |
<> | 144:ef7eb2e8f9f7 | 185 | if ( ebiInit->banks & EBI_BANK2 ) |
<> | 144:ef7eb2e8f9f7 | 186 | { |
<> | 144:ef7eb2e8f9f7 | 187 | ctrl |= EBI_CTRL_BANK2EN; |
<> | 144:ef7eb2e8f9f7 | 188 | } |
<> | 144:ef7eb2e8f9f7 | 189 | if ( ebiInit->banks & EBI_BANK3 ) |
<> | 144:ef7eb2e8f9f7 | 190 | { |
<> | 144:ef7eb2e8f9f7 | 191 | ctrl |= EBI_CTRL_BANK3EN; |
<> | 144:ef7eb2e8f9f7 | 192 | } |
<> | 144:ef7eb2e8f9f7 | 193 | } |
<> | 144:ef7eb2e8f9f7 | 194 | ctrl |= ebiInit->mode; |
<> | 144:ef7eb2e8f9f7 | 195 | ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 196 | ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 197 | #endif |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | /* Configure timing */ |
<> | 144:ef7eb2e8f9f7 | 200 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 201 | EBI_BankReadTimingSet(ebiInit->banks, |
<> | 144:ef7eb2e8f9f7 | 202 | ebiInit->readSetupCycles, |
<> | 144:ef7eb2e8f9f7 | 203 | ebiInit->readStrobeCycles, |
<> | 144:ef7eb2e8f9f7 | 204 | ebiInit->readHoldCycles); |
<> | 144:ef7eb2e8f9f7 | 205 | EBI_BankReadTimingConfig(ebiInit->banks, |
<> | 144:ef7eb2e8f9f7 | 206 | ebiInit->readPageMode, |
<> | 144:ef7eb2e8f9f7 | 207 | ebiInit->readPrefetch, |
<> | 144:ef7eb2e8f9f7 | 208 | ebiInit->readHalfRE); |
<> | 144:ef7eb2e8f9f7 | 209 | EBI_BankWriteTimingSet(ebiInit->banks, |
<> | 144:ef7eb2e8f9f7 | 210 | ebiInit->writeSetupCycles, |
<> | 144:ef7eb2e8f9f7 | 211 | ebiInit->writeStrobeCycles, |
<> | 144:ef7eb2e8f9f7 | 212 | ebiInit->writeHoldCycles); |
<> | 144:ef7eb2e8f9f7 | 213 | EBI_BankWriteTimingConfig(ebiInit->banks, |
<> | 144:ef7eb2e8f9f7 | 214 | ebiInit->writeBufferDisable, |
<> | 144:ef7eb2e8f9f7 | 215 | ebiInit->writeHalfWE); |
<> | 144:ef7eb2e8f9f7 | 216 | EBI_BankAddressTimingSet(ebiInit->banks, |
<> | 144:ef7eb2e8f9f7 | 217 | ebiInit->addrSetupCycles, |
<> | 144:ef7eb2e8f9f7 | 218 | ebiInit->addrHoldCycles); |
<> | 144:ef7eb2e8f9f7 | 219 | EBI_BankAddressTimingConfig(ebiInit->banks, |
<> | 144:ef7eb2e8f9f7 | 220 | ebiInit->addrHalfALE); |
<> | 144:ef7eb2e8f9f7 | 221 | #else |
<> | 144:ef7eb2e8f9f7 | 222 | EBI_ReadTimingSet(ebiInit->readSetupCycles, |
<> | 144:ef7eb2e8f9f7 | 223 | ebiInit->readStrobeCycles, |
<> | 144:ef7eb2e8f9f7 | 224 | ebiInit->readHoldCycles); |
<> | 144:ef7eb2e8f9f7 | 225 | EBI_WriteTimingSet(ebiInit->writeSetupCycles, |
<> | 144:ef7eb2e8f9f7 | 226 | ebiInit->writeStrobeCycles, |
<> | 144:ef7eb2e8f9f7 | 227 | ebiInit->writeHoldCycles); |
<> | 144:ef7eb2e8f9f7 | 228 | EBI_AddressTimingSet(ebiInit->addrSetupCycles, |
<> | 144:ef7eb2e8f9f7 | 229 | ebiInit->addrHoldCycles); |
<> | 144:ef7eb2e8f9f7 | 230 | #endif |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | /* Activate new configuration */ |
<> | 144:ef7eb2e8f9f7 | 233 | EBI->CTRL = ctrl; |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | /* Configure Adress Latch Enable */ |
<> | 144:ef7eb2e8f9f7 | 236 | switch (ebiInit->mode) |
<> | 144:ef7eb2e8f9f7 | 237 | { |
<> | 144:ef7eb2e8f9f7 | 238 | case ebiModeD16A16ALE: |
<> | 144:ef7eb2e8f9f7 | 239 | case ebiModeD8A24ALE: |
<> | 144:ef7eb2e8f9f7 | 240 | /* Address Latch Enable */ |
<> | 144:ef7eb2e8f9f7 | 241 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 242 | break; |
<> | 144:ef7eb2e8f9f7 | 243 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 244 | case ebiModeD16: |
<> | 144:ef7eb2e8f9f7 | 245 | #endif |
<> | 144:ef7eb2e8f9f7 | 246 | case ebiModeD8A8: |
<> | 144:ef7eb2e8f9f7 | 247 | /* Make sure Address Latch is disabled */ |
<> | 144:ef7eb2e8f9f7 | 248 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0); |
<> | 144:ef7eb2e8f9f7 | 249 | break; |
<> | 144:ef7eb2e8f9f7 | 250 | } |
<> | 144:ef7eb2e8f9f7 | 251 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 252 | /* Limit pin enable */ |
<> | 144:ef7eb2e8f9f7 | 253 | EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow; |
<> | 144:ef7eb2e8f9f7 | 254 | EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh; |
<> | 144:ef7eb2e8f9f7 | 255 | /* Location */ |
<> | 144:ef7eb2e8f9f7 | 256 | EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location; |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /* Enable EBI BL pin if necessary */ |
<> | 144:ef7eb2e8f9f7 | 259 | if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK)) |
<> | 144:ef7eb2e8f9f7 | 260 | { |
<> | 144:ef7eb2e8f9f7 | 261 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable); |
<> | 144:ef7eb2e8f9f7 | 262 | } |
<> | 144:ef7eb2e8f9f7 | 263 | #endif |
<> | 144:ef7eb2e8f9f7 | 264 | /* Enable EBI pins EBI_WEn and EBI_REn */ |
<> | 144:ef7eb2e8f9f7 | 265 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 266 | |
<> | 144:ef7eb2e8f9f7 | 267 | /* Enable chip select lines */ |
<> | 144:ef7eb2e8f9f7 | 268 | EBI_ChipSelectEnable(ebiInit->csLines, true); |
<> | 144:ef7eb2e8f9f7 | 269 | } |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | |
<> | 144:ef7eb2e8f9f7 | 272 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 273 | * @brief |
<> | 144:ef7eb2e8f9f7 | 274 | * Disable External Bus Interface |
<> | 144:ef7eb2e8f9f7 | 275 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 276 | void EBI_Disable(void) |
<> | 144:ef7eb2e8f9f7 | 277 | { |
<> | 144:ef7eb2e8f9f7 | 278 | /* Disable pins */ |
<> | 144:ef7eb2e8f9f7 | 279 | EBI->ROUTE = _EBI_ROUTE_RESETVALUE; |
<> | 144:ef7eb2e8f9f7 | 280 | /* Disable banks */ |
<> | 144:ef7eb2e8f9f7 | 281 | EBI->CTRL = _EBI_CTRL_RESETVALUE; |
<> | 144:ef7eb2e8f9f7 | 282 | } |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 286 | * @brief |
<> | 144:ef7eb2e8f9f7 | 287 | * Enable or disable EBI Bank |
<> | 144:ef7eb2e8f9f7 | 288 | * |
<> | 144:ef7eb2e8f9f7 | 289 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 290 | * Banks to reconfigure, mask of EBI_BANK<n> flags |
<> | 144:ef7eb2e8f9f7 | 291 | * |
<> | 144:ef7eb2e8f9f7 | 292 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 293 | * True to enable, false to disable |
<> | 144:ef7eb2e8f9f7 | 294 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 295 | void EBI_BankEnable(uint32_t banks, bool enable) |
<> | 144:ef7eb2e8f9f7 | 296 | { |
<> | 144:ef7eb2e8f9f7 | 297 | if (banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 298 | { |
<> | 144:ef7eb2e8f9f7 | 299 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | if (banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 302 | { |
<> | 144:ef7eb2e8f9f7 | 303 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 304 | } |
<> | 144:ef7eb2e8f9f7 | 305 | if (banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 306 | { |
<> | 144:ef7eb2e8f9f7 | 307 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 308 | } |
<> | 144:ef7eb2e8f9f7 | 309 | if (banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 310 | { |
<> | 144:ef7eb2e8f9f7 | 311 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 312 | } |
<> | 144:ef7eb2e8f9f7 | 313 | } |
<> | 144:ef7eb2e8f9f7 | 314 | |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 317 | * @brief |
<> | 144:ef7eb2e8f9f7 | 318 | * Return base address of EBI bank |
<> | 144:ef7eb2e8f9f7 | 319 | * |
<> | 144:ef7eb2e8f9f7 | 320 | * @param[in] bank |
<> | 144:ef7eb2e8f9f7 | 321 | * Bank to return start address for |
<> | 144:ef7eb2e8f9f7 | 322 | * |
<> | 144:ef7eb2e8f9f7 | 323 | * @return |
<> | 144:ef7eb2e8f9f7 | 324 | * Absolute address of bank |
<> | 144:ef7eb2e8f9f7 | 325 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 326 | uint32_t EBI_BankAddress(uint32_t bank) |
<> | 144:ef7eb2e8f9f7 | 327 | { |
<> | 144:ef7eb2e8f9f7 | 328 | #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 329 | if(EBI->CTRL & EBI_CTRL_ALTMAP) |
<> | 144:ef7eb2e8f9f7 | 330 | { |
<> | 144:ef7eb2e8f9f7 | 331 | switch (bank) |
<> | 144:ef7eb2e8f9f7 | 332 | { |
<> | 144:ef7eb2e8f9f7 | 333 | case EBI_BANK0: |
<> | 144:ef7eb2e8f9f7 | 334 | return(EBI_MEM_BASE); |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | case EBI_BANK1: |
<> | 144:ef7eb2e8f9f7 | 337 | return(EBI_MEM_BASE + 0x10000000UL); |
<> | 144:ef7eb2e8f9f7 | 338 | |
<> | 144:ef7eb2e8f9f7 | 339 | case EBI_BANK2: |
<> | 144:ef7eb2e8f9f7 | 340 | return(EBI_MEM_BASE + 0x20000000UL); |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | case EBI_BANK3: |
<> | 144:ef7eb2e8f9f7 | 343 | return(EBI_MEM_BASE + 0x30000000UL); |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | default: |
<> | 144:ef7eb2e8f9f7 | 346 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 347 | break; |
<> | 144:ef7eb2e8f9f7 | 348 | } |
<> | 144:ef7eb2e8f9f7 | 349 | } |
<> | 144:ef7eb2e8f9f7 | 350 | #endif |
<> | 144:ef7eb2e8f9f7 | 351 | switch (bank) |
<> | 144:ef7eb2e8f9f7 | 352 | { |
<> | 144:ef7eb2e8f9f7 | 353 | case EBI_BANK0: |
<> | 144:ef7eb2e8f9f7 | 354 | return(EBI_MEM_BASE); |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | case EBI_BANK1: |
<> | 144:ef7eb2e8f9f7 | 357 | return(EBI_MEM_BASE + 0x04000000UL); |
<> | 144:ef7eb2e8f9f7 | 358 | |
<> | 144:ef7eb2e8f9f7 | 359 | case EBI_BANK2: |
<> | 144:ef7eb2e8f9f7 | 360 | return(EBI_MEM_BASE + 0x08000000UL); |
<> | 144:ef7eb2e8f9f7 | 361 | |
<> | 144:ef7eb2e8f9f7 | 362 | case EBI_BANK3: |
<> | 144:ef7eb2e8f9f7 | 363 | return(EBI_MEM_BASE + 0x0C000000UL); |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | default: |
<> | 144:ef7eb2e8f9f7 | 366 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 367 | break; |
<> | 144:ef7eb2e8f9f7 | 368 | } |
<> | 144:ef7eb2e8f9f7 | 369 | return 0; |
<> | 144:ef7eb2e8f9f7 | 370 | } |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | |
<> | 144:ef7eb2e8f9f7 | 373 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 374 | * @brief |
<> | 144:ef7eb2e8f9f7 | 375 | * Enable or disable EBI Chip Select |
<> | 144:ef7eb2e8f9f7 | 376 | * |
<> | 144:ef7eb2e8f9f7 | 377 | * @param[in] cs |
<> | 144:ef7eb2e8f9f7 | 378 | * ChipSelect lines to reconfigure, mask of EBI_CS<n> flags |
<> | 144:ef7eb2e8f9f7 | 379 | * |
<> | 144:ef7eb2e8f9f7 | 380 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 381 | * True to enable, false to disable |
<> | 144:ef7eb2e8f9f7 | 382 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 383 | void EBI_ChipSelectEnable(uint32_t cs, bool enable) |
<> | 144:ef7eb2e8f9f7 | 384 | { |
<> | 144:ef7eb2e8f9f7 | 385 | if (cs & EBI_CS0) |
<> | 144:ef7eb2e8f9f7 | 386 | { |
<> | 144:ef7eb2e8f9f7 | 387 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 388 | } |
<> | 144:ef7eb2e8f9f7 | 389 | if (cs & EBI_CS1) |
<> | 144:ef7eb2e8f9f7 | 390 | { |
<> | 144:ef7eb2e8f9f7 | 391 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 392 | } |
<> | 144:ef7eb2e8f9f7 | 393 | if (cs & EBI_CS2) |
<> | 144:ef7eb2e8f9f7 | 394 | { |
<> | 144:ef7eb2e8f9f7 | 395 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 396 | } |
<> | 144:ef7eb2e8f9f7 | 397 | if (cs & EBI_CS3) |
<> | 144:ef7eb2e8f9f7 | 398 | { |
<> | 144:ef7eb2e8f9f7 | 399 | BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 400 | } |
<> | 144:ef7eb2e8f9f7 | 401 | } |
<> | 144:ef7eb2e8f9f7 | 402 | |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 405 | * @brief |
<> | 144:ef7eb2e8f9f7 | 406 | * Configure EBI pin polarity |
<> | 144:ef7eb2e8f9f7 | 407 | * |
<> | 144:ef7eb2e8f9f7 | 408 | * @param[in] line |
<> | 144:ef7eb2e8f9f7 | 409 | * Which pin/line to configure |
<> | 144:ef7eb2e8f9f7 | 410 | * |
<> | 144:ef7eb2e8f9f7 | 411 | * @param[in] polarity |
<> | 144:ef7eb2e8f9f7 | 412 | * Active high, or active low |
<> | 144:ef7eb2e8f9f7 | 413 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 414 | void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity) |
<> | 144:ef7eb2e8f9f7 | 415 | { |
<> | 144:ef7eb2e8f9f7 | 416 | switch (line) |
<> | 144:ef7eb2e8f9f7 | 417 | { |
<> | 144:ef7eb2e8f9f7 | 418 | case ebiLineARDY: |
<> | 144:ef7eb2e8f9f7 | 419 | BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 420 | break; |
<> | 144:ef7eb2e8f9f7 | 421 | case ebiLineALE: |
<> | 144:ef7eb2e8f9f7 | 422 | BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 423 | break; |
<> | 144:ef7eb2e8f9f7 | 424 | case ebiLineWE: |
<> | 144:ef7eb2e8f9f7 | 425 | BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 426 | break; |
<> | 144:ef7eb2e8f9f7 | 427 | case ebiLineRE: |
<> | 144:ef7eb2e8f9f7 | 428 | BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 429 | break; |
<> | 144:ef7eb2e8f9f7 | 430 | case ebiLineCS: |
<> | 144:ef7eb2e8f9f7 | 431 | BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 432 | break; |
<> | 144:ef7eb2e8f9f7 | 433 | #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 434 | case ebiLineBL: |
<> | 144:ef7eb2e8f9f7 | 435 | BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 436 | break; |
<> | 144:ef7eb2e8f9f7 | 437 | case ebiLineTFTVSync: |
<> | 144:ef7eb2e8f9f7 | 438 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 439 | break; |
<> | 144:ef7eb2e8f9f7 | 440 | case ebiLineTFTHSync: |
<> | 144:ef7eb2e8f9f7 | 441 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 442 | break; |
<> | 144:ef7eb2e8f9f7 | 443 | case ebiLineTFTDataEn: |
<> | 144:ef7eb2e8f9f7 | 444 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 445 | break; |
<> | 144:ef7eb2e8f9f7 | 446 | case ebiLineTFTDClk: |
<> | 144:ef7eb2e8f9f7 | 447 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 448 | break; |
<> | 144:ef7eb2e8f9f7 | 449 | case ebiLineTFTCS: |
<> | 144:ef7eb2e8f9f7 | 450 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 451 | break; |
<> | 144:ef7eb2e8f9f7 | 452 | #endif |
<> | 144:ef7eb2e8f9f7 | 453 | default: |
<> | 144:ef7eb2e8f9f7 | 454 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 455 | break; |
<> | 144:ef7eb2e8f9f7 | 456 | } |
<> | 144:ef7eb2e8f9f7 | 457 | } |
<> | 144:ef7eb2e8f9f7 | 458 | |
<> | 144:ef7eb2e8f9f7 | 459 | |
<> | 144:ef7eb2e8f9f7 | 460 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 461 | * @brief |
<> | 144:ef7eb2e8f9f7 | 462 | * Configure timing values of read bus accesses |
<> | 144:ef7eb2e8f9f7 | 463 | * |
<> | 144:ef7eb2e8f9f7 | 464 | * @param[in] setupCycles |
<> | 144:ef7eb2e8f9f7 | 465 | * Number of clock cycles for address setup before REn is asserted |
<> | 144:ef7eb2e8f9f7 | 466 | * |
<> | 144:ef7eb2e8f9f7 | 467 | * @param[in] strobeCycles |
<> | 144:ef7eb2e8f9f7 | 468 | * The number of cycles the REn is held active. After the specified number of |
<> | 144:ef7eb2e8f9f7 | 469 | * cycles, data is read. If set to 0, 1 cycle is inserted by HW |
<> | 144:ef7eb2e8f9f7 | 470 | * |
<> | 144:ef7eb2e8f9f7 | 471 | * @param[in] holdCycles |
<> | 144:ef7eb2e8f9f7 | 472 | * The number of cycles CSn is held active after the REn is dessarted |
<> | 144:ef7eb2e8f9f7 | 473 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 474 | void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles) |
<> | 144:ef7eb2e8f9f7 | 475 | { |
<> | 144:ef7eb2e8f9f7 | 476 | uint32_t readTiming; |
<> | 144:ef7eb2e8f9f7 | 477 | |
<> | 144:ef7eb2e8f9f7 | 478 | /* Check that timings are within limits */ |
<> | 144:ef7eb2e8f9f7 | 479 | EFM_ASSERT(setupCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 480 | EFM_ASSERT(strobeCycles < 16); |
<> | 144:ef7eb2e8f9f7 | 481 | EFM_ASSERT(holdCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | /* Configure timing values */ |
<> | 144:ef7eb2e8f9f7 | 484 | readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 485 | | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 486 | | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 487 | |
<> | 144:ef7eb2e8f9f7 | 488 | |
<> | 144:ef7eb2e8f9f7 | 489 | EBI->RDTIMING = (EBI->RDTIMING |
<> | 144:ef7eb2e8f9f7 | 490 | & ~(_EBI_RDTIMING_RDSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 491 | | _EBI_RDTIMING_RDSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 492 | | _EBI_RDTIMING_RDHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 493 | | readTiming; |
<> | 144:ef7eb2e8f9f7 | 494 | } |
<> | 144:ef7eb2e8f9f7 | 495 | |
<> | 144:ef7eb2e8f9f7 | 496 | |
<> | 144:ef7eb2e8f9f7 | 497 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 498 | * @brief |
<> | 144:ef7eb2e8f9f7 | 499 | * Configure timing values of write bus accesses |
<> | 144:ef7eb2e8f9f7 | 500 | * |
<> | 144:ef7eb2e8f9f7 | 501 | * @param[in] setupCycles |
<> | 144:ef7eb2e8f9f7 | 502 | * Number of clock cycles for address setup before WEn is asserted |
<> | 144:ef7eb2e8f9f7 | 503 | * |
<> | 144:ef7eb2e8f9f7 | 504 | * @param[in] strobeCycles |
<> | 144:ef7eb2e8f9f7 | 505 | * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW |
<> | 144:ef7eb2e8f9f7 | 506 | * |
<> | 144:ef7eb2e8f9f7 | 507 | * @param[in] holdCycles |
<> | 144:ef7eb2e8f9f7 | 508 | * Number of cycles CSn is held active after the WEn is deasserted |
<> | 144:ef7eb2e8f9f7 | 509 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 510 | void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles) |
<> | 144:ef7eb2e8f9f7 | 511 | { |
<> | 144:ef7eb2e8f9f7 | 512 | uint32_t writeTiming; |
<> | 144:ef7eb2e8f9f7 | 513 | |
<> | 144:ef7eb2e8f9f7 | 514 | /* Check that timings are within limits */ |
<> | 144:ef7eb2e8f9f7 | 515 | EFM_ASSERT(setupCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 516 | EFM_ASSERT(strobeCycles < 16); |
<> | 144:ef7eb2e8f9f7 | 517 | EFM_ASSERT(holdCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 518 | |
<> | 144:ef7eb2e8f9f7 | 519 | /* Configure timing values */ |
<> | 144:ef7eb2e8f9f7 | 520 | writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 521 | | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 522 | | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 523 | |
<> | 144:ef7eb2e8f9f7 | 524 | EBI->WRTIMING = (EBI->WRTIMING |
<> | 144:ef7eb2e8f9f7 | 525 | & ~(_EBI_WRTIMING_WRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 526 | | _EBI_WRTIMING_WRSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 527 | | _EBI_WRTIMING_WRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 528 | | writeTiming; |
<> | 144:ef7eb2e8f9f7 | 529 | } |
<> | 144:ef7eb2e8f9f7 | 530 | |
<> | 144:ef7eb2e8f9f7 | 531 | |
<> | 144:ef7eb2e8f9f7 | 532 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 533 | * @brief |
<> | 144:ef7eb2e8f9f7 | 534 | * Configure timing values of address latch bus accesses |
<> | 144:ef7eb2e8f9f7 | 535 | * |
<> | 144:ef7eb2e8f9f7 | 536 | * @param[in] setupCycles |
<> | 144:ef7eb2e8f9f7 | 537 | * Sets the number of cycles the address is held after ALE is asserted |
<> | 144:ef7eb2e8f9f7 | 538 | * |
<> | 144:ef7eb2e8f9f7 | 539 | * @param[in] holdCycles |
<> | 144:ef7eb2e8f9f7 | 540 | * Sets the number of cycles the address is driven onto the ADDRDAT bus before |
<> | 144:ef7eb2e8f9f7 | 541 | * ALE is asserted. If set 0, 1 cycle is inserted by HW |
<> | 144:ef7eb2e8f9f7 | 542 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 543 | void EBI_AddressTimingSet(int setupCycles, int holdCycles) |
<> | 144:ef7eb2e8f9f7 | 544 | { |
<> | 144:ef7eb2e8f9f7 | 545 | uint32_t addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 546 | |
<> | 144:ef7eb2e8f9f7 | 547 | /* Check that timing values are within limits */ |
<> | 144:ef7eb2e8f9f7 | 548 | EFM_ASSERT(setupCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 549 | EFM_ASSERT(holdCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /* Configure address latch timing values */ |
<> | 144:ef7eb2e8f9f7 | 552 | addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 553 | | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 554 | |
<> | 144:ef7eb2e8f9f7 | 555 | EBI->ADDRTIMING = (EBI->ADDRTIMING |
<> | 144:ef7eb2e8f9f7 | 556 | & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 557 | | _EBI_ADDRTIMING_ADDRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 558 | | addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 559 | } |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 562 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 563 | * @brief |
<> | 144:ef7eb2e8f9f7 | 564 | * Configure and initialize TFT Direct Drive |
<> | 144:ef7eb2e8f9f7 | 565 | * |
<> | 144:ef7eb2e8f9f7 | 566 | * @param[in] ebiTFTInit |
<> | 144:ef7eb2e8f9f7 | 567 | * TFT Initialization structure |
<> | 144:ef7eb2e8f9f7 | 568 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 569 | void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit) |
<> | 144:ef7eb2e8f9f7 | 570 | { |
<> | 144:ef7eb2e8f9f7 | 571 | uint32_t ctrl; |
<> | 144:ef7eb2e8f9f7 | 572 | |
<> | 144:ef7eb2e8f9f7 | 573 | /* Configure base address for frame buffer offset to EBI bank */ |
<> | 144:ef7eb2e8f9f7 | 574 | EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset); |
<> | 144:ef7eb2e8f9f7 | 575 | |
<> | 144:ef7eb2e8f9f7 | 576 | /* Configure display size and porch areas */ |
<> | 144:ef7eb2e8f9f7 | 577 | EBI_TFTSizeSet(ebiTFTInit->hsize, |
<> | 144:ef7eb2e8f9f7 | 578 | ebiTFTInit->vsize); |
<> | 144:ef7eb2e8f9f7 | 579 | EBI_TFTHPorchSet(ebiTFTInit->hPorchFront, |
<> | 144:ef7eb2e8f9f7 | 580 | ebiTFTInit->hPorchBack, |
<> | 144:ef7eb2e8f9f7 | 581 | ebiTFTInit->hPulseWidth); |
<> | 144:ef7eb2e8f9f7 | 582 | EBI_TFTVPorchSet(ebiTFTInit->vPorchFront, |
<> | 144:ef7eb2e8f9f7 | 583 | ebiTFTInit->vPorchBack, |
<> | 144:ef7eb2e8f9f7 | 584 | ebiTFTInit->vPulseWidth); |
<> | 144:ef7eb2e8f9f7 | 585 | |
<> | 144:ef7eb2e8f9f7 | 586 | /* Configure timing settings */ |
<> | 144:ef7eb2e8f9f7 | 587 | EBI_TFTTimingSet(ebiTFTInit->dclkPeriod, |
<> | 144:ef7eb2e8f9f7 | 588 | ebiTFTInit->startPosition, |
<> | 144:ef7eb2e8f9f7 | 589 | ebiTFTInit->setupCycles, |
<> | 144:ef7eb2e8f9f7 | 590 | ebiTFTInit->holdCycles); |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | /* Configure line polarity settings */ |
<> | 144:ef7eb2e8f9f7 | 593 | EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity); |
<> | 144:ef7eb2e8f9f7 | 594 | EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity); |
<> | 144:ef7eb2e8f9f7 | 595 | EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity); |
<> | 144:ef7eb2e8f9f7 | 596 | EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity); |
<> | 144:ef7eb2e8f9f7 | 597 | EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity); |
<> | 144:ef7eb2e8f9f7 | 598 | |
<> | 144:ef7eb2e8f9f7 | 599 | /* Main control, EBI bank select, mask and blending configuration */ |
<> | 144:ef7eb2e8f9f7 | 600 | ctrl = (uint32_t)ebiTFTInit->bank |
<> | 144:ef7eb2e8f9f7 | 601 | | (uint32_t)ebiTFTInit->width |
<> | 144:ef7eb2e8f9f7 | 602 | | (uint32_t)ebiTFTInit->colSrc |
<> | 144:ef7eb2e8f9f7 | 603 | | (uint32_t)ebiTFTInit->interleave |
<> | 144:ef7eb2e8f9f7 | 604 | | (uint32_t)ebiTFTInit->fbTrigger |
<> | 144:ef7eb2e8f9f7 | 605 | | (uint32_t)(ebiTFTInit->shiftDClk == true |
<> | 144:ef7eb2e8f9f7 | 606 | ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0) |
<> | 144:ef7eb2e8f9f7 | 607 | | (uint32_t)ebiTFTInit->maskBlend |
<> | 144:ef7eb2e8f9f7 | 608 | | (uint32_t)ebiTFTInit->driveMode; |
<> | 144:ef7eb2e8f9f7 | 609 | |
<> | 144:ef7eb2e8f9f7 | 610 | EBI->TFTCTRL = ctrl; |
<> | 144:ef7eb2e8f9f7 | 611 | |
<> | 144:ef7eb2e8f9f7 | 612 | /* Enable TFT pins */ |
<> | 144:ef7eb2e8f9f7 | 613 | if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled) |
<> | 144:ef7eb2e8f9f7 | 614 | { |
<> | 144:ef7eb2e8f9f7 | 615 | EBI->ROUTE |= EBI_ROUTE_TFTPEN; |
<> | 144:ef7eb2e8f9f7 | 616 | } |
<> | 144:ef7eb2e8f9f7 | 617 | } |
<> | 144:ef7eb2e8f9f7 | 618 | |
<> | 144:ef7eb2e8f9f7 | 619 | |
<> | 144:ef7eb2e8f9f7 | 620 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 621 | * @brief |
<> | 144:ef7eb2e8f9f7 | 622 | * Configure and initialize TFT size settings |
<> | 144:ef7eb2e8f9f7 | 623 | * |
<> | 144:ef7eb2e8f9f7 | 624 | * @param[in] horizontal |
<> | 144:ef7eb2e8f9f7 | 625 | * TFT display horizontal size in pixels |
<> | 144:ef7eb2e8f9f7 | 626 | * @param[in] vertical |
<> | 144:ef7eb2e8f9f7 | 627 | * TFT display vertical size in pixels |
<> | 144:ef7eb2e8f9f7 | 628 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 629 | void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical) |
<> | 144:ef7eb2e8f9f7 | 630 | { |
<> | 144:ef7eb2e8f9f7 | 631 | EFM_ASSERT((horizontal-1) < 1024); |
<> | 144:ef7eb2e8f9f7 | 632 | EFM_ASSERT((vertical-1) < 1024); |
<> | 144:ef7eb2e8f9f7 | 633 | |
<> | 144:ef7eb2e8f9f7 | 634 | EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 635 | | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 636 | } |
<> | 144:ef7eb2e8f9f7 | 637 | |
<> | 144:ef7eb2e8f9f7 | 638 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 639 | * @brief |
<> | 144:ef7eb2e8f9f7 | 640 | * Configure and initialize Horizontal Porch Settings |
<> | 144:ef7eb2e8f9f7 | 641 | * |
<> | 144:ef7eb2e8f9f7 | 642 | * @param[in] front |
<> | 144:ef7eb2e8f9f7 | 643 | * Horizontal front porch size in pixels |
<> | 144:ef7eb2e8f9f7 | 644 | * @param[in] back |
<> | 144:ef7eb2e8f9f7 | 645 | * Horizontal back porch size in pixels |
<> | 144:ef7eb2e8f9f7 | 646 | * @param[in] pulseWidth |
<> | 144:ef7eb2e8f9f7 | 647 | * Horizontal synchronization pulse width. Set to required -1. |
<> | 144:ef7eb2e8f9f7 | 648 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 649 | void EBI_TFTHPorchSet(int front, int back, int pulseWidth) |
<> | 144:ef7eb2e8f9f7 | 650 | { |
<> | 144:ef7eb2e8f9f7 | 651 | EFM_ASSERT(front < 256); |
<> | 144:ef7eb2e8f9f7 | 652 | EFM_ASSERT(back < 256); |
<> | 144:ef7eb2e8f9f7 | 653 | EFM_ASSERT((pulseWidth-1) < 128); |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 656 | | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 657 | | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 658 | } |
<> | 144:ef7eb2e8f9f7 | 659 | |
<> | 144:ef7eb2e8f9f7 | 660 | |
<> | 144:ef7eb2e8f9f7 | 661 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 662 | * @brief |
<> | 144:ef7eb2e8f9f7 | 663 | * Configure Vertical Porch Settings |
<> | 144:ef7eb2e8f9f7 | 664 | * |
<> | 144:ef7eb2e8f9f7 | 665 | * @param[in] front |
<> | 144:ef7eb2e8f9f7 | 666 | * Vertical front porch size in pixels |
<> | 144:ef7eb2e8f9f7 | 667 | * @param[in] back |
<> | 144:ef7eb2e8f9f7 | 668 | * Vertical back porch size in pixels |
<> | 144:ef7eb2e8f9f7 | 669 | * @param[in] pulseWidth |
<> | 144:ef7eb2e8f9f7 | 670 | * Vertical synchronization pulse width. Set to required -1. |
<> | 144:ef7eb2e8f9f7 | 671 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 672 | void EBI_TFTVPorchSet(int front, int back, int pulseWidth) |
<> | 144:ef7eb2e8f9f7 | 673 | { |
<> | 144:ef7eb2e8f9f7 | 674 | EFM_ASSERT(front < 256); |
<> | 144:ef7eb2e8f9f7 | 675 | EFM_ASSERT(back < 256); |
<> | 144:ef7eb2e8f9f7 | 676 | EFM_ASSERT((pulseWidth-1) < 128); |
<> | 144:ef7eb2e8f9f7 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 679 | | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 680 | | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 681 | } |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | |
<> | 144:ef7eb2e8f9f7 | 684 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 685 | * @brief |
<> | 144:ef7eb2e8f9f7 | 686 | * Configure TFT Direct Drive Timing Settings |
<> | 144:ef7eb2e8f9f7 | 687 | * |
<> | 144:ef7eb2e8f9f7 | 688 | * @param[in] dclkPeriod |
<> | 144:ef7eb2e8f9f7 | 689 | * DCLK period in internal cycles |
<> | 144:ef7eb2e8f9f7 | 690 | * |
<> | 144:ef7eb2e8f9f7 | 691 | * @param[in] start |
<> | 144:ef7eb2e8f9f7 | 692 | * Starting position of external direct drive, relative to DCLK inactive edge |
<> | 144:ef7eb2e8f9f7 | 693 | * |
<> | 144:ef7eb2e8f9f7 | 694 | * @param[in] setup |
<> | 144:ef7eb2e8f9f7 | 695 | * Number of cycles RGB data is driven before active edge of DCLK |
<> | 144:ef7eb2e8f9f7 | 696 | * |
<> | 144:ef7eb2e8f9f7 | 697 | * @param[in] hold |
<> | 144:ef7eb2e8f9f7 | 698 | * Number of cycles RGB data is held after active edge of DCLK |
<> | 144:ef7eb2e8f9f7 | 699 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 700 | void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold) |
<> | 144:ef7eb2e8f9f7 | 701 | { |
<> | 144:ef7eb2e8f9f7 | 702 | EFM_ASSERT(dclkPeriod < 2048); |
<> | 144:ef7eb2e8f9f7 | 703 | EFM_ASSERT(start < 2048); |
<> | 144:ef7eb2e8f9f7 | 704 | EFM_ASSERT(setup < 4); |
<> | 144:ef7eb2e8f9f7 | 705 | EFM_ASSERT(hold < 4); |
<> | 144:ef7eb2e8f9f7 | 706 | |
<> | 144:ef7eb2e8f9f7 | 707 | EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 708 | | (start << _EBI_TFTTIMING_TFTSTART_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 709 | | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 710 | | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 711 | } |
<> | 144:ef7eb2e8f9f7 | 712 | #endif |
<> | 144:ef7eb2e8f9f7 | 713 | |
<> | 144:ef7eb2e8f9f7 | 714 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 715 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 716 | * @brief |
<> | 144:ef7eb2e8f9f7 | 717 | * Configure read operation parameters for selected bank |
<> | 144:ef7eb2e8f9f7 | 718 | * |
<> | 144:ef7eb2e8f9f7 | 719 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 720 | * Mask of memory bank(s) to configure write timing for |
<> | 144:ef7eb2e8f9f7 | 721 | * |
<> | 144:ef7eb2e8f9f7 | 722 | * @param[in] pageMode |
<> | 144:ef7eb2e8f9f7 | 723 | * Enables or disables half cycle WE strobe in last strobe cycle |
<> | 144:ef7eb2e8f9f7 | 724 | * |
<> | 144:ef7eb2e8f9f7 | 725 | * @param[in] prefetch |
<> | 144:ef7eb2e8f9f7 | 726 | * Enables or disables half cycle WE strobe in last strobe cycle |
<> | 144:ef7eb2e8f9f7 | 727 | * |
<> | 144:ef7eb2e8f9f7 | 728 | * @param[in] halfRE |
<> | 144:ef7eb2e8f9f7 | 729 | * Enables or disables half cycle WE strobe in last strobe cycle |
<> | 144:ef7eb2e8f9f7 | 730 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 731 | void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE) |
<> | 144:ef7eb2e8f9f7 | 732 | { |
<> | 144:ef7eb2e8f9f7 | 733 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 734 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | /* Configure read operation parameters */ |
<> | 144:ef7eb2e8f9f7 | 737 | if( banks & EBI_BANK0 ) |
<> | 144:ef7eb2e8f9f7 | 738 | { |
<> | 144:ef7eb2e8f9f7 | 739 | BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode); |
<> | 144:ef7eb2e8f9f7 | 740 | BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch); |
<> | 144:ef7eb2e8f9f7 | 741 | BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE); |
<> | 144:ef7eb2e8f9f7 | 742 | } |
<> | 144:ef7eb2e8f9f7 | 743 | if( banks & EBI_BANK1 ) |
<> | 144:ef7eb2e8f9f7 | 744 | { |
<> | 144:ef7eb2e8f9f7 | 745 | BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode); |
<> | 144:ef7eb2e8f9f7 | 746 | BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch); |
<> | 144:ef7eb2e8f9f7 | 747 | BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE); |
<> | 144:ef7eb2e8f9f7 | 748 | } |
<> | 144:ef7eb2e8f9f7 | 749 | if( banks & EBI_BANK2 ) |
<> | 144:ef7eb2e8f9f7 | 750 | { |
<> | 144:ef7eb2e8f9f7 | 751 | BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode); |
<> | 144:ef7eb2e8f9f7 | 752 | BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch); |
<> | 144:ef7eb2e8f9f7 | 753 | BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE); |
<> | 144:ef7eb2e8f9f7 | 754 | } |
<> | 144:ef7eb2e8f9f7 | 755 | if( banks & EBI_BANK3 ) |
<> | 144:ef7eb2e8f9f7 | 756 | { |
<> | 144:ef7eb2e8f9f7 | 757 | BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode); |
<> | 144:ef7eb2e8f9f7 | 758 | BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch); |
<> | 144:ef7eb2e8f9f7 | 759 | BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE); |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | } |
<> | 144:ef7eb2e8f9f7 | 762 | |
<> | 144:ef7eb2e8f9f7 | 763 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 764 | * @brief |
<> | 144:ef7eb2e8f9f7 | 765 | * Configure timing values of read bus accesses |
<> | 144:ef7eb2e8f9f7 | 766 | * |
<> | 144:ef7eb2e8f9f7 | 767 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 768 | * Mask of memory bank(s) to configure timing for |
<> | 144:ef7eb2e8f9f7 | 769 | * |
<> | 144:ef7eb2e8f9f7 | 770 | * @param[in] setupCycles |
<> | 144:ef7eb2e8f9f7 | 771 | * Number of clock cycles for address setup before REn is asserted |
<> | 144:ef7eb2e8f9f7 | 772 | * |
<> | 144:ef7eb2e8f9f7 | 773 | * @param[in] strobeCycles |
<> | 144:ef7eb2e8f9f7 | 774 | * The number of cycles the REn is held active. After the specified number of |
<> | 144:ef7eb2e8f9f7 | 775 | * cycles, data is read. If set to 0, 1 cycle is inserted by HW |
<> | 144:ef7eb2e8f9f7 | 776 | * |
<> | 144:ef7eb2e8f9f7 | 777 | * @param[in] holdCycles |
<> | 144:ef7eb2e8f9f7 | 778 | * The number of cycles CSn is held active after the REn is dessarted |
<> | 144:ef7eb2e8f9f7 | 779 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 780 | void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles) |
<> | 144:ef7eb2e8f9f7 | 781 | { |
<> | 144:ef7eb2e8f9f7 | 782 | uint32_t readTiming; |
<> | 144:ef7eb2e8f9f7 | 783 | |
<> | 144:ef7eb2e8f9f7 | 784 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 785 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 786 | |
<> | 144:ef7eb2e8f9f7 | 787 | /* Check that timings are within limits */ |
<> | 144:ef7eb2e8f9f7 | 788 | EFM_ASSERT(setupCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 789 | EFM_ASSERT(strobeCycles < 64); |
<> | 144:ef7eb2e8f9f7 | 790 | EFM_ASSERT(holdCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | /* Configure timing values */ |
<> | 144:ef7eb2e8f9f7 | 793 | readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 794 | | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 795 | | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | if (banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 798 | { |
<> | 144:ef7eb2e8f9f7 | 799 | EBI->RDTIMING = (EBI->RDTIMING |
<> | 144:ef7eb2e8f9f7 | 800 | & ~(_EBI_RDTIMING_RDSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 801 | | _EBI_RDTIMING_RDSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 802 | | _EBI_RDTIMING_RDHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 803 | | readTiming; |
<> | 144:ef7eb2e8f9f7 | 804 | } |
<> | 144:ef7eb2e8f9f7 | 805 | if (banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 806 | { |
<> | 144:ef7eb2e8f9f7 | 807 | EBI->RDTIMING1 = (EBI->RDTIMING1 |
<> | 144:ef7eb2e8f9f7 | 808 | & ~(_EBI_RDTIMING1_RDSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 809 | | _EBI_RDTIMING1_RDSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 810 | | _EBI_RDTIMING1_RDHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 811 | | readTiming; |
<> | 144:ef7eb2e8f9f7 | 812 | } |
<> | 144:ef7eb2e8f9f7 | 813 | if (banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 814 | { |
<> | 144:ef7eb2e8f9f7 | 815 | EBI->RDTIMING2 = (EBI->RDTIMING2 |
<> | 144:ef7eb2e8f9f7 | 816 | & ~(_EBI_RDTIMING2_RDSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 817 | | _EBI_RDTIMING2_RDSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 818 | | _EBI_RDTIMING2_RDHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 819 | | readTiming; |
<> | 144:ef7eb2e8f9f7 | 820 | } |
<> | 144:ef7eb2e8f9f7 | 821 | if (banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 822 | { |
<> | 144:ef7eb2e8f9f7 | 823 | EBI->RDTIMING3 = (EBI->RDTIMING3 |
<> | 144:ef7eb2e8f9f7 | 824 | & ~(_EBI_RDTIMING3_RDSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 825 | | _EBI_RDTIMING3_RDSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 826 | | _EBI_RDTIMING3_RDHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 827 | | readTiming; |
<> | 144:ef7eb2e8f9f7 | 828 | } |
<> | 144:ef7eb2e8f9f7 | 829 | } |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | |
<> | 144:ef7eb2e8f9f7 | 832 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 833 | * @brief |
<> | 144:ef7eb2e8f9f7 | 834 | * Configure write operation parameters for selected bank |
<> | 144:ef7eb2e8f9f7 | 835 | * |
<> | 144:ef7eb2e8f9f7 | 836 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 837 | * Mask of memory bank(s) to configure write timing for |
<> | 144:ef7eb2e8f9f7 | 838 | * |
<> | 144:ef7eb2e8f9f7 | 839 | * @param[in] writeBufDisable |
<> | 144:ef7eb2e8f9f7 | 840 | * If true, disable the write buffer |
<> | 144:ef7eb2e8f9f7 | 841 | * |
<> | 144:ef7eb2e8f9f7 | 842 | * @param[in] halfWE |
<> | 144:ef7eb2e8f9f7 | 843 | * Enables or disables half cycle WE strobe in last strobe cycle |
<> | 144:ef7eb2e8f9f7 | 844 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 845 | void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE) |
<> | 144:ef7eb2e8f9f7 | 846 | { |
<> | 144:ef7eb2e8f9f7 | 847 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 848 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 849 | |
<> | 144:ef7eb2e8f9f7 | 850 | /* Configure write operation parameters */ |
<> | 144:ef7eb2e8f9f7 | 851 | if( banks & EBI_BANK0 ) |
<> | 144:ef7eb2e8f9f7 | 852 | { |
<> | 144:ef7eb2e8f9f7 | 853 | BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable); |
<> | 144:ef7eb2e8f9f7 | 854 | BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE); |
<> | 144:ef7eb2e8f9f7 | 855 | } |
<> | 144:ef7eb2e8f9f7 | 856 | if( banks & EBI_BANK1 ) |
<> | 144:ef7eb2e8f9f7 | 857 | { |
<> | 144:ef7eb2e8f9f7 | 858 | BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable); |
<> | 144:ef7eb2e8f9f7 | 859 | BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE); |
<> | 144:ef7eb2e8f9f7 | 860 | } |
<> | 144:ef7eb2e8f9f7 | 861 | if( banks & EBI_BANK2 ) |
<> | 144:ef7eb2e8f9f7 | 862 | { |
<> | 144:ef7eb2e8f9f7 | 863 | BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable); |
<> | 144:ef7eb2e8f9f7 | 864 | BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE); |
<> | 144:ef7eb2e8f9f7 | 865 | } |
<> | 144:ef7eb2e8f9f7 | 866 | if( banks & EBI_BANK3 ) |
<> | 144:ef7eb2e8f9f7 | 867 | { |
<> | 144:ef7eb2e8f9f7 | 868 | BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable); |
<> | 144:ef7eb2e8f9f7 | 869 | BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE); |
<> | 144:ef7eb2e8f9f7 | 870 | } |
<> | 144:ef7eb2e8f9f7 | 871 | } |
<> | 144:ef7eb2e8f9f7 | 872 | |
<> | 144:ef7eb2e8f9f7 | 873 | |
<> | 144:ef7eb2e8f9f7 | 874 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 875 | * @brief |
<> | 144:ef7eb2e8f9f7 | 876 | * Configure timing values of write bus accesses |
<> | 144:ef7eb2e8f9f7 | 877 | * |
<> | 144:ef7eb2e8f9f7 | 878 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 879 | * Mask of memory bank(s) to configure write timing for |
<> | 144:ef7eb2e8f9f7 | 880 | * |
<> | 144:ef7eb2e8f9f7 | 881 | * @param[in] setupCycles |
<> | 144:ef7eb2e8f9f7 | 882 | * Number of clock cycles for address setup before WEn is asserted |
<> | 144:ef7eb2e8f9f7 | 883 | * |
<> | 144:ef7eb2e8f9f7 | 884 | * @param[in] strobeCycles |
<> | 144:ef7eb2e8f9f7 | 885 | * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW |
<> | 144:ef7eb2e8f9f7 | 886 | * |
<> | 144:ef7eb2e8f9f7 | 887 | * @param[in] holdCycles |
<> | 144:ef7eb2e8f9f7 | 888 | * Number of cycles CSn is held active after the WEn is deasserted |
<> | 144:ef7eb2e8f9f7 | 889 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 890 | void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles) |
<> | 144:ef7eb2e8f9f7 | 891 | { |
<> | 144:ef7eb2e8f9f7 | 892 | uint32_t writeTiming; |
<> | 144:ef7eb2e8f9f7 | 893 | |
<> | 144:ef7eb2e8f9f7 | 894 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 895 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 896 | |
<> | 144:ef7eb2e8f9f7 | 897 | /* Check that timings are within limits */ |
<> | 144:ef7eb2e8f9f7 | 898 | EFM_ASSERT(setupCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 899 | EFM_ASSERT(strobeCycles < 64); |
<> | 144:ef7eb2e8f9f7 | 900 | EFM_ASSERT(holdCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 901 | |
<> | 144:ef7eb2e8f9f7 | 902 | /* Configure timing values */ |
<> | 144:ef7eb2e8f9f7 | 903 | writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 904 | | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 905 | | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | if (banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 908 | { |
<> | 144:ef7eb2e8f9f7 | 909 | EBI->WRTIMING = (EBI->WRTIMING |
<> | 144:ef7eb2e8f9f7 | 910 | & ~(_EBI_WRTIMING_WRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 911 | | _EBI_WRTIMING_WRSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 912 | | _EBI_WRTIMING_WRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 913 | | writeTiming; |
<> | 144:ef7eb2e8f9f7 | 914 | } |
<> | 144:ef7eb2e8f9f7 | 915 | if (banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 916 | { |
<> | 144:ef7eb2e8f9f7 | 917 | EBI->WRTIMING1 = (EBI->WRTIMING1 |
<> | 144:ef7eb2e8f9f7 | 918 | & ~(_EBI_WRTIMING1_WRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 919 | | _EBI_WRTIMING1_WRSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 920 | | _EBI_WRTIMING1_WRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 921 | | writeTiming; |
<> | 144:ef7eb2e8f9f7 | 922 | } |
<> | 144:ef7eb2e8f9f7 | 923 | if (banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 924 | { |
<> | 144:ef7eb2e8f9f7 | 925 | EBI->WRTIMING2 = (EBI->WRTIMING2 |
<> | 144:ef7eb2e8f9f7 | 926 | & ~(_EBI_WRTIMING2_WRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 927 | | _EBI_WRTIMING2_WRSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 928 | | _EBI_WRTIMING2_WRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 929 | | writeTiming; |
<> | 144:ef7eb2e8f9f7 | 930 | } |
<> | 144:ef7eb2e8f9f7 | 931 | if (banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 932 | { |
<> | 144:ef7eb2e8f9f7 | 933 | EBI->WRTIMING3 = (EBI->WRTIMING3 |
<> | 144:ef7eb2e8f9f7 | 934 | & ~(_EBI_WRTIMING3_WRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 935 | | _EBI_WRTIMING3_WRSTRB_MASK |
<> | 144:ef7eb2e8f9f7 | 936 | | _EBI_WRTIMING3_WRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 937 | | writeTiming; |
<> | 144:ef7eb2e8f9f7 | 938 | } |
<> | 144:ef7eb2e8f9f7 | 939 | } |
<> | 144:ef7eb2e8f9f7 | 940 | |
<> | 144:ef7eb2e8f9f7 | 941 | |
<> | 144:ef7eb2e8f9f7 | 942 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 943 | * @brief |
<> | 144:ef7eb2e8f9f7 | 944 | * Configure address operation parameters for selected bank |
<> | 144:ef7eb2e8f9f7 | 945 | * |
<> | 144:ef7eb2e8f9f7 | 946 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 947 | * Mask of memory bank(s) to configure write timing for |
<> | 144:ef7eb2e8f9f7 | 948 | * |
<> | 144:ef7eb2e8f9f7 | 949 | * @param[in] halfALE |
<> | 144:ef7eb2e8f9f7 | 950 | * Enables or disables half cycle ALE strobe in last strobe cycle |
<> | 144:ef7eb2e8f9f7 | 951 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 952 | void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE) |
<> | 144:ef7eb2e8f9f7 | 953 | { |
<> | 144:ef7eb2e8f9f7 | 954 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 955 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 956 | |
<> | 144:ef7eb2e8f9f7 | 957 | if( banks & EBI_BANK0 ) |
<> | 144:ef7eb2e8f9f7 | 958 | { |
<> | 144:ef7eb2e8f9f7 | 959 | BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE); |
<> | 144:ef7eb2e8f9f7 | 960 | } |
<> | 144:ef7eb2e8f9f7 | 961 | if( banks & EBI_BANK1 ) |
<> | 144:ef7eb2e8f9f7 | 962 | { |
<> | 144:ef7eb2e8f9f7 | 963 | BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE); |
<> | 144:ef7eb2e8f9f7 | 964 | } |
<> | 144:ef7eb2e8f9f7 | 965 | if( banks & EBI_BANK2 ) |
<> | 144:ef7eb2e8f9f7 | 966 | { |
<> | 144:ef7eb2e8f9f7 | 967 | BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE); |
<> | 144:ef7eb2e8f9f7 | 968 | } |
<> | 144:ef7eb2e8f9f7 | 969 | if( banks & EBI_BANK3 ) |
<> | 144:ef7eb2e8f9f7 | 970 | { |
<> | 144:ef7eb2e8f9f7 | 971 | BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE); |
<> | 144:ef7eb2e8f9f7 | 972 | } |
<> | 144:ef7eb2e8f9f7 | 973 | } |
<> | 144:ef7eb2e8f9f7 | 974 | |
<> | 144:ef7eb2e8f9f7 | 975 | |
<> | 144:ef7eb2e8f9f7 | 976 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 977 | * @brief |
<> | 144:ef7eb2e8f9f7 | 978 | * Configure timing values of address latch bus accesses |
<> | 144:ef7eb2e8f9f7 | 979 | * |
<> | 144:ef7eb2e8f9f7 | 980 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 981 | * Mask of memory bank(s) to configure address timing for |
<> | 144:ef7eb2e8f9f7 | 982 | * |
<> | 144:ef7eb2e8f9f7 | 983 | * @param[in] setupCycles |
<> | 144:ef7eb2e8f9f7 | 984 | * Sets the number of cycles the address is held after ALE is asserted |
<> | 144:ef7eb2e8f9f7 | 985 | * |
<> | 144:ef7eb2e8f9f7 | 986 | * @param[in] holdCycles |
<> | 144:ef7eb2e8f9f7 | 987 | * Sets the number of cycles the address is driven onto the ADDRDAT bus before |
<> | 144:ef7eb2e8f9f7 | 988 | * ALE is asserted. If set 0, 1 cycle is inserted by HW |
<> | 144:ef7eb2e8f9f7 | 989 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 990 | void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles) |
<> | 144:ef7eb2e8f9f7 | 991 | { |
<> | 144:ef7eb2e8f9f7 | 992 | uint32_t addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 995 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /* Check that timing values are within limits */ |
<> | 144:ef7eb2e8f9f7 | 998 | EFM_ASSERT(setupCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 999 | EFM_ASSERT(holdCycles < 4); |
<> | 144:ef7eb2e8f9f7 | 1000 | |
<> | 144:ef7eb2e8f9f7 | 1001 | /* Configure address latch timing values */ |
<> | 144:ef7eb2e8f9f7 | 1002 | addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 1003 | | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | if (banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 1006 | { |
<> | 144:ef7eb2e8f9f7 | 1007 | EBI->ADDRTIMING = (EBI->ADDRTIMING |
<> | 144:ef7eb2e8f9f7 | 1008 | & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 1009 | | _EBI_ADDRTIMING_ADDRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1010 | | addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 1011 | } |
<> | 144:ef7eb2e8f9f7 | 1012 | if (banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 1013 | { |
<> | 144:ef7eb2e8f9f7 | 1014 | EBI->ADDRTIMING1 = (EBI->ADDRTIMING1 |
<> | 144:ef7eb2e8f9f7 | 1015 | & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 1016 | | _EBI_ADDRTIMING1_ADDRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1017 | | addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 1018 | } |
<> | 144:ef7eb2e8f9f7 | 1019 | if (banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 1020 | { |
<> | 144:ef7eb2e8f9f7 | 1021 | EBI->ADDRTIMING2 = (EBI->ADDRTIMING2 |
<> | 144:ef7eb2e8f9f7 | 1022 | & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 1023 | | _EBI_ADDRTIMING2_ADDRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1024 | | addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 1025 | } |
<> | 144:ef7eb2e8f9f7 | 1026 | if (banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 1027 | { |
<> | 144:ef7eb2e8f9f7 | 1028 | EBI->ADDRTIMING3 = (EBI->ADDRTIMING3 |
<> | 144:ef7eb2e8f9f7 | 1029 | & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK |
<> | 144:ef7eb2e8f9f7 | 1030 | | _EBI_ADDRTIMING3_ADDRHOLD_MASK)) |
<> | 144:ef7eb2e8f9f7 | 1031 | | addressLatchTiming; |
<> | 144:ef7eb2e8f9f7 | 1032 | } |
<> | 144:ef7eb2e8f9f7 | 1033 | } |
<> | 144:ef7eb2e8f9f7 | 1034 | |
<> | 144:ef7eb2e8f9f7 | 1035 | |
<> | 144:ef7eb2e8f9f7 | 1036 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1037 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1038 | * Configure EBI pin polarity for selected bank(s) for devices with individual |
<> | 144:ef7eb2e8f9f7 | 1039 | * timing support |
<> | 144:ef7eb2e8f9f7 | 1040 | * |
<> | 144:ef7eb2e8f9f7 | 1041 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 1042 | * Mask of memory bank(s) to configure polarity for |
<> | 144:ef7eb2e8f9f7 | 1043 | * |
<> | 144:ef7eb2e8f9f7 | 1044 | * @param[in] line |
<> | 144:ef7eb2e8f9f7 | 1045 | * Which pin/line to configure |
<> | 144:ef7eb2e8f9f7 | 1046 | * |
<> | 144:ef7eb2e8f9f7 | 1047 | * @param[in] polarity |
<> | 144:ef7eb2e8f9f7 | 1048 | * Active high, or active low |
<> | 144:ef7eb2e8f9f7 | 1049 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1050 | void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity) |
<> | 144:ef7eb2e8f9f7 | 1051 | { |
<> | 144:ef7eb2e8f9f7 | 1052 | uint32_t bankSet = 0; |
<> | 144:ef7eb2e8f9f7 | 1053 | volatile uint32_t *polRegister = 0; |
<> | 144:ef7eb2e8f9f7 | 1054 | |
<> | 144:ef7eb2e8f9f7 | 1055 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 1056 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 1057 | |
<> | 144:ef7eb2e8f9f7 | 1058 | while (banks) |
<> | 144:ef7eb2e8f9f7 | 1059 | { |
<> | 144:ef7eb2e8f9f7 | 1060 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 1061 | if (banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 1062 | { |
<> | 144:ef7eb2e8f9f7 | 1063 | polRegister = &EBI->POLARITY; |
<> | 144:ef7eb2e8f9f7 | 1064 | bankSet = EBI_BANK0; |
<> | 144:ef7eb2e8f9f7 | 1065 | } |
<> | 144:ef7eb2e8f9f7 | 1066 | if (banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 1067 | { |
<> | 144:ef7eb2e8f9f7 | 1068 | polRegister = &EBI->POLARITY1; |
<> | 144:ef7eb2e8f9f7 | 1069 | bankSet = EBI_BANK1; |
<> | 144:ef7eb2e8f9f7 | 1070 | } |
<> | 144:ef7eb2e8f9f7 | 1071 | if (banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 1072 | { |
<> | 144:ef7eb2e8f9f7 | 1073 | polRegister = &EBI->POLARITY2; |
<> | 144:ef7eb2e8f9f7 | 1074 | bankSet = EBI_BANK2; |
<> | 144:ef7eb2e8f9f7 | 1075 | } |
<> | 144:ef7eb2e8f9f7 | 1076 | if (banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 1077 | { |
<> | 144:ef7eb2e8f9f7 | 1078 | polRegister = &EBI->POLARITY3; |
<> | 144:ef7eb2e8f9f7 | 1079 | bankSet = EBI_BANK3; |
<> | 144:ef7eb2e8f9f7 | 1080 | } |
<> | 144:ef7eb2e8f9f7 | 1081 | #else |
<> | 144:ef7eb2e8f9f7 | 1082 | polRegister = &EBI->POLARITY; |
<> | 144:ef7eb2e8f9f7 | 1083 | banks = 0; |
<> | 144:ef7eb2e8f9f7 | 1084 | #endif |
<> | 144:ef7eb2e8f9f7 | 1085 | |
<> | 144:ef7eb2e8f9f7 | 1086 | /* What line to configure */ |
<> | 144:ef7eb2e8f9f7 | 1087 | switch (line) |
<> | 144:ef7eb2e8f9f7 | 1088 | { |
<> | 144:ef7eb2e8f9f7 | 1089 | case ebiLineARDY: |
<> | 144:ef7eb2e8f9f7 | 1090 | BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1091 | break; |
<> | 144:ef7eb2e8f9f7 | 1092 | case ebiLineALE: |
<> | 144:ef7eb2e8f9f7 | 1093 | BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1094 | break; |
<> | 144:ef7eb2e8f9f7 | 1095 | case ebiLineWE: |
<> | 144:ef7eb2e8f9f7 | 1096 | BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1097 | break; |
<> | 144:ef7eb2e8f9f7 | 1098 | case ebiLineRE: |
<> | 144:ef7eb2e8f9f7 | 1099 | BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1100 | break; |
<> | 144:ef7eb2e8f9f7 | 1101 | case ebiLineCS: |
<> | 144:ef7eb2e8f9f7 | 1102 | BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1103 | break; |
<> | 144:ef7eb2e8f9f7 | 1104 | #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) |
<> | 144:ef7eb2e8f9f7 | 1105 | case ebiLineBL: |
<> | 144:ef7eb2e8f9f7 | 1106 | BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1107 | break; |
<> | 144:ef7eb2e8f9f7 | 1108 | case ebiLineTFTVSync: |
<> | 144:ef7eb2e8f9f7 | 1109 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1110 | break; |
<> | 144:ef7eb2e8f9f7 | 1111 | case ebiLineTFTHSync: |
<> | 144:ef7eb2e8f9f7 | 1112 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1113 | break; |
<> | 144:ef7eb2e8f9f7 | 1114 | case ebiLineTFTDataEn: |
<> | 144:ef7eb2e8f9f7 | 1115 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1116 | break; |
<> | 144:ef7eb2e8f9f7 | 1117 | case ebiLineTFTDClk: |
<> | 144:ef7eb2e8f9f7 | 1118 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1119 | break; |
<> | 144:ef7eb2e8f9f7 | 1120 | case ebiLineTFTCS: |
<> | 144:ef7eb2e8f9f7 | 1121 | BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity); |
<> | 144:ef7eb2e8f9f7 | 1122 | break; |
<> | 144:ef7eb2e8f9f7 | 1123 | #endif |
<> | 144:ef7eb2e8f9f7 | 1124 | default: |
<> | 144:ef7eb2e8f9f7 | 1125 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1126 | break; |
<> | 144:ef7eb2e8f9f7 | 1127 | } |
<> | 144:ef7eb2e8f9f7 | 1128 | banks = banks & ~bankSet; |
<> | 144:ef7eb2e8f9f7 | 1129 | } |
<> | 144:ef7eb2e8f9f7 | 1130 | } |
<> | 144:ef7eb2e8f9f7 | 1131 | |
<> | 144:ef7eb2e8f9f7 | 1132 | |
<> | 144:ef7eb2e8f9f7 | 1133 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1134 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1135 | * Configure Byte Lane Enable for select banks |
<> | 144:ef7eb2e8f9f7 | 1136 | * timing support |
<> | 144:ef7eb2e8f9f7 | 1137 | * |
<> | 144:ef7eb2e8f9f7 | 1138 | * @param[in] banks |
<> | 144:ef7eb2e8f9f7 | 1139 | * Mask of memory bank(s) to configure polarity for |
<> | 144:ef7eb2e8f9f7 | 1140 | * |
<> | 144:ef7eb2e8f9f7 | 1141 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 1142 | * Flag |
<> | 144:ef7eb2e8f9f7 | 1143 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1144 | void EBI_BankByteLaneEnable(uint32_t banks, bool enable) |
<> | 144:ef7eb2e8f9f7 | 1145 | { |
<> | 144:ef7eb2e8f9f7 | 1146 | /* Verify only valid banks are used */ |
<> | 144:ef7eb2e8f9f7 | 1147 | EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0); |
<> | 144:ef7eb2e8f9f7 | 1148 | |
<> | 144:ef7eb2e8f9f7 | 1149 | /* Configure byte lane support for each selected bank */ |
<> | 144:ef7eb2e8f9f7 | 1150 | if (banks & EBI_BANK0) |
<> | 144:ef7eb2e8f9f7 | 1151 | { |
<> | 144:ef7eb2e8f9f7 | 1152 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 1153 | } |
<> | 144:ef7eb2e8f9f7 | 1154 | if (banks & EBI_BANK1) |
<> | 144:ef7eb2e8f9f7 | 1155 | { |
<> | 144:ef7eb2e8f9f7 | 1156 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 1157 | } |
<> | 144:ef7eb2e8f9f7 | 1158 | if (banks & EBI_BANK2) |
<> | 144:ef7eb2e8f9f7 | 1159 | { |
<> | 144:ef7eb2e8f9f7 | 1160 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 1161 | } |
<> | 144:ef7eb2e8f9f7 | 1162 | if (banks & EBI_BANK3) |
<> | 144:ef7eb2e8f9f7 | 1163 | { |
<> | 144:ef7eb2e8f9f7 | 1164 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 1165 | } |
<> | 144:ef7eb2e8f9f7 | 1166 | } |
<> | 144:ef7eb2e8f9f7 | 1167 | |
<> | 144:ef7eb2e8f9f7 | 1168 | |
<> | 144:ef7eb2e8f9f7 | 1169 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1170 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1171 | * Configure Alternate Address Map support |
<> | 144:ef7eb2e8f9f7 | 1172 | * Enables or disables 256MB address range for all banks |
<> | 144:ef7eb2e8f9f7 | 1173 | * |
<> | 144:ef7eb2e8f9f7 | 1174 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 1175 | * Set or clear address map extension |
<> | 144:ef7eb2e8f9f7 | 1176 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1177 | void EBI_AltMapEnable(bool enable) |
<> | 144:ef7eb2e8f9f7 | 1178 | { |
<> | 144:ef7eb2e8f9f7 | 1179 | BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable); |
<> | 144:ef7eb2e8f9f7 | 1180 | } |
<> | 144:ef7eb2e8f9f7 | 1181 | |
<> | 144:ef7eb2e8f9f7 | 1182 | #endif |
<> | 144:ef7eb2e8f9f7 | 1183 | |
<> | 144:ef7eb2e8f9f7 | 1184 | /** @} (end addtogroup EBI) */ |
<> | 144:ef7eb2e8f9f7 | 1185 | /** @} (end addtogroup EM_Library) */ |
<> | 144:ef7eb2e8f9f7 | 1186 | |
<> | 144:ef7eb2e8f9f7 | 1187 | #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */ |