Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c@50:a417edff4437, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 07:45:16 2016 +0000
Revision:
50:a417edff4437
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9



Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/



Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file em_ebi.c
bogdanm 0:9b334a45a8ff 3 * @brief External Bus Interface (EBI) Peripheral API
mbed_official 50:a417edff4437 4 * @version 4.2.1
bogdanm 0:9b334a45a8ff 5 *******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
mbed_official 50:a417edff4437 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 *******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 21 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 22 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 23 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 24 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 25 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 28 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 29 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 ******************************************************************************/
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 #include "em_ebi.h"
bogdanm 0:9b334a45a8ff 34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
bogdanm 0:9b334a45a8ff 35 #include "em_assert.h"
mbed_official 50:a417edff4437 36 #include "em_bus.h"
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 39 * @addtogroup EM_Library
bogdanm 0:9b334a45a8ff 40 * @{
bogdanm 0:9b334a45a8ff 41 ******************************************************************************/
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 44 * @addtogroup EBI
bogdanm 0:9b334a45a8ff 45 * @brief EBI External Bus Interface (EBI) Peripheral API
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 ******************************************************************************/
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 50 * @brief
bogdanm 0:9b334a45a8ff 51 * Configure and enable External Bus Interface
bogdanm 0:9b334a45a8ff 52 *
bogdanm 0:9b334a45a8ff 53 * @param[in] ebiInit
bogdanm 0:9b334a45a8ff 54 * EBI configuration structure
bogdanm 0:9b334a45a8ff 55 *
bogdanm 0:9b334a45a8ff 56 * @note
bogdanm 0:9b334a45a8ff 57 * GPIO lines must be configured as PUSH_PULL for correct operation
bogdanm 0:9b334a45a8ff 58 * GPIO and EBI clocks must be enabled in the CMU
bogdanm 0:9b334a45a8ff 59 ******************************************************************************/
bogdanm 0:9b334a45a8ff 60 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
bogdanm 0:9b334a45a8ff 61 {
bogdanm 0:9b334a45a8ff 62 uint32_t ctrl = EBI->CTRL;
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 65 /* Enable Independent Timing for devices that supports it */
bogdanm 0:9b334a45a8ff 66 ctrl |= EBI_CTRL_ITS;
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /* Set polarity of address ready */
bogdanm 0:9b334a45a8ff 69 EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
bogdanm 0:9b334a45a8ff 70 /* Set polarity of address latch enable */
bogdanm 0:9b334a45a8ff 71 EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
bogdanm 0:9b334a45a8ff 72 /* Set polarity of write enable */
bogdanm 0:9b334a45a8ff 73 EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
bogdanm 0:9b334a45a8ff 74 /* Set polarity of read enable */
bogdanm 0:9b334a45a8ff 75 EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
bogdanm 0:9b334a45a8ff 76 /* Set polarity of chip select lines */
bogdanm 0:9b334a45a8ff 77 EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
bogdanm 0:9b334a45a8ff 78 /* Set polarity of byte lane line */
bogdanm 0:9b334a45a8ff 79 EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
bogdanm 0:9b334a45a8ff 80 #else
bogdanm 0:9b334a45a8ff 81 /* Set polarity of address ready */
bogdanm 0:9b334a45a8ff 82 EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
bogdanm 0:9b334a45a8ff 83 /* Set polarity of address latch enable */
bogdanm 0:9b334a45a8ff 84 EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
bogdanm 0:9b334a45a8ff 85 /* Set polarity of write enable */
bogdanm 0:9b334a45a8ff 86 EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
bogdanm 0:9b334a45a8ff 87 /* Set polarity of read enable */
bogdanm 0:9b334a45a8ff 88 EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
bogdanm 0:9b334a45a8ff 89 /* Set polarity of chip select lines */
bogdanm 0:9b334a45a8ff 90 EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
bogdanm 0:9b334a45a8ff 91 #endif
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /* Configure EBI mode and control settings */
bogdanm 0:9b334a45a8ff 94 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 95 if (ebiInit->banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 96 {
mbed_official 50:a417edff4437 97 ctrl &= ~(_EBI_CTRL_MODE_MASK
mbed_official 50:a417edff4437 98 | _EBI_CTRL_ARDYEN_MASK
mbed_official 50:a417edff4437 99 | _EBI_CTRL_ARDYTODIS_MASK
mbed_official 50:a417edff4437 100 | _EBI_CTRL_BL_MASK
mbed_official 50:a417edff4437 101 | _EBI_CTRL_NOIDLE_MASK
mbed_official 50:a417edff4437 102 | _EBI_CTRL_BANK0EN_MASK);
bogdanm 0:9b334a45a8ff 103 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
bogdanm 0:9b334a45a8ff 104 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
bogdanm 0:9b334a45a8ff 105 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
bogdanm 0:9b334a45a8ff 106 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
bogdanm 0:9b334a45a8ff 107 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
mbed_official 50:a417edff4437 108 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 109 {
bogdanm 0:9b334a45a8ff 110 ctrl |= EBI_CTRL_BANK0EN;
bogdanm 0:9b334a45a8ff 111 }
bogdanm 0:9b334a45a8ff 112 }
bogdanm 0:9b334a45a8ff 113 if (ebiInit->banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 114 {
mbed_official 50:a417edff4437 115 ctrl &= ~(_EBI_CTRL_BL1_MASK
mbed_official 50:a417edff4437 116 | _EBI_CTRL_MODE1_MASK
mbed_official 50:a417edff4437 117 | _EBI_CTRL_ARDY1EN_MASK
mbed_official 50:a417edff4437 118 | _EBI_CTRL_ARDYTO1DIS_MASK
mbed_official 50:a417edff4437 119 | _EBI_CTRL_NOIDLE1_MASK
mbed_official 50:a417edff4437 120 | _EBI_CTRL_BANK1EN_MASK);
bogdanm 0:9b334a45a8ff 121 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
bogdanm 0:9b334a45a8ff 122 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
bogdanm 0:9b334a45a8ff 123 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
bogdanm 0:9b334a45a8ff 124 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
bogdanm 0:9b334a45a8ff 125 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
mbed_official 50:a417edff4437 126 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 127 {
bogdanm 0:9b334a45a8ff 128 ctrl |= EBI_CTRL_BANK1EN;
bogdanm 0:9b334a45a8ff 129 }
bogdanm 0:9b334a45a8ff 130 }
bogdanm 0:9b334a45a8ff 131 if (ebiInit->banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 132 {
mbed_official 50:a417edff4437 133 ctrl &= ~(_EBI_CTRL_BL2_MASK
mbed_official 50:a417edff4437 134 | _EBI_CTRL_MODE2_MASK
mbed_official 50:a417edff4437 135 | _EBI_CTRL_ARDY2EN_MASK
mbed_official 50:a417edff4437 136 | _EBI_CTRL_ARDYTO2DIS_MASK
mbed_official 50:a417edff4437 137 | _EBI_CTRL_NOIDLE2_MASK
mbed_official 50:a417edff4437 138 | _EBI_CTRL_BANK2EN_MASK);
bogdanm 0:9b334a45a8ff 139 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
bogdanm 0:9b334a45a8ff 140 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
bogdanm 0:9b334a45a8ff 141 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
bogdanm 0:9b334a45a8ff 142 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
bogdanm 0:9b334a45a8ff 143 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
mbed_official 50:a417edff4437 144 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 145 {
bogdanm 0:9b334a45a8ff 146 ctrl |= EBI_CTRL_BANK2EN;
bogdanm 0:9b334a45a8ff 147 }
bogdanm 0:9b334a45a8ff 148 }
bogdanm 0:9b334a45a8ff 149 if (ebiInit->banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 150 {
mbed_official 50:a417edff4437 151 ctrl &= ~(_EBI_CTRL_BL3_MASK
mbed_official 50:a417edff4437 152 | _EBI_CTRL_MODE3_MASK
mbed_official 50:a417edff4437 153 | _EBI_CTRL_ARDY3EN_MASK
mbed_official 50:a417edff4437 154 | _EBI_CTRL_ARDYTO3DIS_MASK
mbed_official 50:a417edff4437 155 | _EBI_CTRL_NOIDLE3_MASK
mbed_official 50:a417edff4437 156 | _EBI_CTRL_BANK3EN_MASK);
bogdanm 0:9b334a45a8ff 157 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
bogdanm 0:9b334a45a8ff 158 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
bogdanm 0:9b334a45a8ff 159 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
bogdanm 0:9b334a45a8ff 160 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
bogdanm 0:9b334a45a8ff 161 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
mbed_official 50:a417edff4437 162 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 163 {
bogdanm 0:9b334a45a8ff 164 ctrl |= EBI_CTRL_BANK3EN;
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166 }
bogdanm 0:9b334a45a8ff 167 #else
mbed_official 50:a417edff4437 168 ctrl &= ~(_EBI_CTRL_MODE_MASK
mbed_official 50:a417edff4437 169 | _EBI_CTRL_ARDYEN_MASK
mbed_official 50:a417edff4437 170 | _EBI_CTRL_ARDYTODIS_MASK
mbed_official 50:a417edff4437 171 | _EBI_CTRL_BANK0EN_MASK
mbed_official 50:a417edff4437 172 | _EBI_CTRL_BANK1EN_MASK
mbed_official 50:a417edff4437 173 | _EBI_CTRL_BANK2EN_MASK
mbed_official 50:a417edff4437 174 | _EBI_CTRL_BANK3EN_MASK);
mbed_official 50:a417edff4437 175 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 176 {
bogdanm 0:9b334a45a8ff 177 if ( ebiInit->banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 ctrl |= EBI_CTRL_BANK0EN;
bogdanm 0:9b334a45a8ff 180 }
bogdanm 0:9b334a45a8ff 181 if ( ebiInit->banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 182 {
bogdanm 0:9b334a45a8ff 183 ctrl |= EBI_CTRL_BANK1EN;
bogdanm 0:9b334a45a8ff 184 }
bogdanm 0:9b334a45a8ff 185 if ( ebiInit->banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 186 {
bogdanm 0:9b334a45a8ff 187 ctrl |= EBI_CTRL_BANK2EN;
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189 if ( ebiInit->banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 ctrl |= EBI_CTRL_BANK3EN;
bogdanm 0:9b334a45a8ff 192 }
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194 ctrl |= ebiInit->mode;
bogdanm 0:9b334a45a8ff 195 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
bogdanm 0:9b334a45a8ff 196 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
bogdanm 0:9b334a45a8ff 197 #endif
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /* Configure timing */
bogdanm 0:9b334a45a8ff 200 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 201 EBI_BankReadTimingSet(ebiInit->banks,
bogdanm 0:9b334a45a8ff 202 ebiInit->readSetupCycles,
bogdanm 0:9b334a45a8ff 203 ebiInit->readStrobeCycles,
bogdanm 0:9b334a45a8ff 204 ebiInit->readHoldCycles);
bogdanm 0:9b334a45a8ff 205 EBI_BankReadTimingConfig(ebiInit->banks,
bogdanm 0:9b334a45a8ff 206 ebiInit->readPageMode,
bogdanm 0:9b334a45a8ff 207 ebiInit->readPrefetch,
bogdanm 0:9b334a45a8ff 208 ebiInit->readHalfRE);
bogdanm 0:9b334a45a8ff 209 EBI_BankWriteTimingSet(ebiInit->banks,
bogdanm 0:9b334a45a8ff 210 ebiInit->writeSetupCycles,
bogdanm 0:9b334a45a8ff 211 ebiInit->writeStrobeCycles,
bogdanm 0:9b334a45a8ff 212 ebiInit->writeHoldCycles);
bogdanm 0:9b334a45a8ff 213 EBI_BankWriteTimingConfig(ebiInit->banks,
bogdanm 0:9b334a45a8ff 214 ebiInit->writeBufferDisable,
bogdanm 0:9b334a45a8ff 215 ebiInit->writeHalfWE);
bogdanm 0:9b334a45a8ff 216 EBI_BankAddressTimingSet(ebiInit->banks,
bogdanm 0:9b334a45a8ff 217 ebiInit->addrSetupCycles,
bogdanm 0:9b334a45a8ff 218 ebiInit->addrHoldCycles);
bogdanm 0:9b334a45a8ff 219 EBI_BankAddressTimingConfig(ebiInit->banks,
bogdanm 0:9b334a45a8ff 220 ebiInit->addrHalfALE);
bogdanm 0:9b334a45a8ff 221 #else
bogdanm 0:9b334a45a8ff 222 EBI_ReadTimingSet(ebiInit->readSetupCycles,
bogdanm 0:9b334a45a8ff 223 ebiInit->readStrobeCycles,
bogdanm 0:9b334a45a8ff 224 ebiInit->readHoldCycles);
bogdanm 0:9b334a45a8ff 225 EBI_WriteTimingSet(ebiInit->writeSetupCycles,
bogdanm 0:9b334a45a8ff 226 ebiInit->writeStrobeCycles,
bogdanm 0:9b334a45a8ff 227 ebiInit->writeHoldCycles);
bogdanm 0:9b334a45a8ff 228 EBI_AddressTimingSet(ebiInit->addrSetupCycles,
bogdanm 0:9b334a45a8ff 229 ebiInit->addrHoldCycles);
bogdanm 0:9b334a45a8ff 230 #endif
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /* Activate new configuration */
mbed_official 50:a417edff4437 233 EBI->CTRL = ctrl;
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /* Configure Adress Latch Enable */
bogdanm 0:9b334a45a8ff 236 switch (ebiInit->mode)
bogdanm 0:9b334a45a8ff 237 {
mbed_official 50:a417edff4437 238 case ebiModeD16A16ALE:
mbed_official 50:a417edff4437 239 case ebiModeD8A24ALE:
mbed_official 50:a417edff4437 240 /* Address Latch Enable */
mbed_official 50:a417edff4437 241 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
mbed_official 50:a417edff4437 242 break;
bogdanm 0:9b334a45a8ff 243 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
mbed_official 50:a417edff4437 244 case ebiModeD16:
bogdanm 0:9b334a45a8ff 245 #endif
mbed_official 50:a417edff4437 246 case ebiModeD8A8:
mbed_official 50:a417edff4437 247 /* Make sure Address Latch is disabled */
mbed_official 50:a417edff4437 248 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
mbed_official 50:a417edff4437 249 break;
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 252 /* Limit pin enable */
bogdanm 0:9b334a45a8ff 253 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
bogdanm 0:9b334a45a8ff 254 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
bogdanm 0:9b334a45a8ff 255 /* Location */
bogdanm 0:9b334a45a8ff 256 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /* Enable EBI BL pin if necessary */
bogdanm 0:9b334a45a8ff 259 if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
bogdanm 0:9b334a45a8ff 260 {
mbed_official 50:a417edff4437 261 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263 #endif
bogdanm 0:9b334a45a8ff 264 /* Enable EBI pins EBI_WEn and EBI_REn */
mbed_official 50:a417edff4437 265 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /* Enable chip select lines */
bogdanm 0:9b334a45a8ff 268 EBI_ChipSelectEnable(ebiInit->csLines, true);
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 273 * @brief
bogdanm 0:9b334a45a8ff 274 * Disable External Bus Interface
bogdanm 0:9b334a45a8ff 275 ******************************************************************************/
bogdanm 0:9b334a45a8ff 276 void EBI_Disable(void)
bogdanm 0:9b334a45a8ff 277 {
bogdanm 0:9b334a45a8ff 278 /* Disable pins */
bogdanm 0:9b334a45a8ff 279 EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
bogdanm 0:9b334a45a8ff 280 /* Disable banks */
bogdanm 0:9b334a45a8ff 281 EBI->CTRL = _EBI_CTRL_RESETVALUE;
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 286 * @brief
bogdanm 0:9b334a45a8ff 287 * Enable or disable EBI Bank
bogdanm 0:9b334a45a8ff 288 *
bogdanm 0:9b334a45a8ff 289 * @param[in] banks
bogdanm 0:9b334a45a8ff 290 * Banks to reconfigure, mask of EBI_BANK<n> flags
bogdanm 0:9b334a45a8ff 291 *
bogdanm 0:9b334a45a8ff 292 * @param[in] enable
bogdanm 0:9b334a45a8ff 293 * True to enable, false to disable
bogdanm 0:9b334a45a8ff 294 ******************************************************************************/
bogdanm 0:9b334a45a8ff 295 void EBI_BankEnable(uint32_t banks, bool enable)
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 298 {
mbed_official 50:a417edff4437 299 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 302 {
mbed_official 50:a417edff4437 303 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 306 {
mbed_official 50:a417edff4437 307 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 310 {
mbed_official 50:a417edff4437 311 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 317 * @brief
bogdanm 0:9b334a45a8ff 318 * Return base address of EBI bank
bogdanm 0:9b334a45a8ff 319 *
bogdanm 0:9b334a45a8ff 320 * @param[in] bank
bogdanm 0:9b334a45a8ff 321 * Bank to return start address for
bogdanm 0:9b334a45a8ff 322 *
bogdanm 0:9b334a45a8ff 323 * @return
bogdanm 0:9b334a45a8ff 324 * Absolute address of bank
bogdanm 0:9b334a45a8ff 325 ******************************************************************************/
bogdanm 0:9b334a45a8ff 326 uint32_t EBI_BankAddress(uint32_t bank)
bogdanm 0:9b334a45a8ff 327 {
bogdanm 0:9b334a45a8ff 328 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 329 if(EBI->CTRL & EBI_CTRL_ALTMAP)
bogdanm 0:9b334a45a8ff 330 {
bogdanm 0:9b334a45a8ff 331 switch (bank)
bogdanm 0:9b334a45a8ff 332 {
mbed_official 50:a417edff4437 333 case EBI_BANK0:
mbed_official 50:a417edff4437 334 return(EBI_MEM_BASE);
bogdanm 0:9b334a45a8ff 335
mbed_official 50:a417edff4437 336 case EBI_BANK1:
mbed_official 50:a417edff4437 337 return(EBI_MEM_BASE + 0x10000000UL);
bogdanm 0:9b334a45a8ff 338
mbed_official 50:a417edff4437 339 case EBI_BANK2:
mbed_official 50:a417edff4437 340 return(EBI_MEM_BASE + 0x20000000UL);
bogdanm 0:9b334a45a8ff 341
mbed_official 50:a417edff4437 342 case EBI_BANK3:
mbed_official 50:a417edff4437 343 return(EBI_MEM_BASE + 0x30000000UL);
bogdanm 0:9b334a45a8ff 344
mbed_official 50:a417edff4437 345 default:
mbed_official 50:a417edff4437 346 EFM_ASSERT(0);
mbed_official 50:a417edff4437 347 break;
bogdanm 0:9b334a45a8ff 348 }
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 #endif
bogdanm 0:9b334a45a8ff 351 switch (bank)
bogdanm 0:9b334a45a8ff 352 {
mbed_official 50:a417edff4437 353 case EBI_BANK0:
mbed_official 50:a417edff4437 354 return(EBI_MEM_BASE);
bogdanm 0:9b334a45a8ff 355
mbed_official 50:a417edff4437 356 case EBI_BANK1:
mbed_official 50:a417edff4437 357 return(EBI_MEM_BASE + 0x04000000UL);
bogdanm 0:9b334a45a8ff 358
mbed_official 50:a417edff4437 359 case EBI_BANK2:
mbed_official 50:a417edff4437 360 return(EBI_MEM_BASE + 0x08000000UL);
bogdanm 0:9b334a45a8ff 361
mbed_official 50:a417edff4437 362 case EBI_BANK3:
mbed_official 50:a417edff4437 363 return(EBI_MEM_BASE + 0x0C000000UL);
bogdanm 0:9b334a45a8ff 364
mbed_official 50:a417edff4437 365 default:
mbed_official 50:a417edff4437 366 EFM_ASSERT(0);
mbed_official 50:a417edff4437 367 break;
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369 return 0;
bogdanm 0:9b334a45a8ff 370 }
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 374 * @brief
bogdanm 0:9b334a45a8ff 375 * Enable or disable EBI Chip Select
bogdanm 0:9b334a45a8ff 376 *
bogdanm 0:9b334a45a8ff 377 * @param[in] cs
bogdanm 0:9b334a45a8ff 378 * ChipSelect lines to reconfigure, mask of EBI_CS<n> flags
bogdanm 0:9b334a45a8ff 379 *
bogdanm 0:9b334a45a8ff 380 * @param[in] enable
bogdanm 0:9b334a45a8ff 381 * True to enable, false to disable
bogdanm 0:9b334a45a8ff 382 ******************************************************************************/
bogdanm 0:9b334a45a8ff 383 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 if (cs & EBI_CS0)
bogdanm 0:9b334a45a8ff 386 {
mbed_official 50:a417edff4437 387 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 388 }
bogdanm 0:9b334a45a8ff 389 if (cs & EBI_CS1)
bogdanm 0:9b334a45a8ff 390 {
mbed_official 50:a417edff4437 391 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 392 }
bogdanm 0:9b334a45a8ff 393 if (cs & EBI_CS2)
bogdanm 0:9b334a45a8ff 394 {
mbed_official 50:a417edff4437 395 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 396 }
bogdanm 0:9b334a45a8ff 397 if (cs & EBI_CS3)
bogdanm 0:9b334a45a8ff 398 {
mbed_official 50:a417edff4437 399 BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401 }
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 405 * @brief
bogdanm 0:9b334a45a8ff 406 * Configure EBI pin polarity
bogdanm 0:9b334a45a8ff 407 *
bogdanm 0:9b334a45a8ff 408 * @param[in] line
bogdanm 0:9b334a45a8ff 409 * Which pin/line to configure
bogdanm 0:9b334a45a8ff 410 *
bogdanm 0:9b334a45a8ff 411 * @param[in] polarity
bogdanm 0:9b334a45a8ff 412 * Active high, or active low
bogdanm 0:9b334a45a8ff 413 ******************************************************************************/
bogdanm 0:9b334a45a8ff 414 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
bogdanm 0:9b334a45a8ff 415 {
bogdanm 0:9b334a45a8ff 416 switch (line)
bogdanm 0:9b334a45a8ff 417 {
mbed_official 50:a417edff4437 418 case ebiLineARDY:
mbed_official 50:a417edff4437 419 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 420 break;
mbed_official 50:a417edff4437 421 case ebiLineALE:
mbed_official 50:a417edff4437 422 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 423 break;
mbed_official 50:a417edff4437 424 case ebiLineWE:
mbed_official 50:a417edff4437 425 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 426 break;
mbed_official 50:a417edff4437 427 case ebiLineRE:
mbed_official 50:a417edff4437 428 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 429 break;
mbed_official 50:a417edff4437 430 case ebiLineCS:
mbed_official 50:a417edff4437 431 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 432 break;
bogdanm 0:9b334a45a8ff 433 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
mbed_official 50:a417edff4437 434 case ebiLineBL:
mbed_official 50:a417edff4437 435 BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 436 break;
mbed_official 50:a417edff4437 437 case ebiLineTFTVSync:
mbed_official 50:a417edff4437 438 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 439 break;
mbed_official 50:a417edff4437 440 case ebiLineTFTHSync:
mbed_official 50:a417edff4437 441 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 442 break;
mbed_official 50:a417edff4437 443 case ebiLineTFTDataEn:
mbed_official 50:a417edff4437 444 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 445 break;
mbed_official 50:a417edff4437 446 case ebiLineTFTDClk:
mbed_official 50:a417edff4437 447 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 448 break;
mbed_official 50:a417edff4437 449 case ebiLineTFTCS:
mbed_official 50:a417edff4437 450 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 451 break;
bogdanm 0:9b334a45a8ff 452 #endif
mbed_official 50:a417edff4437 453 default:
mbed_official 50:a417edff4437 454 EFM_ASSERT(0);
mbed_official 50:a417edff4437 455 break;
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 461 * @brief
bogdanm 0:9b334a45a8ff 462 * Configure timing values of read bus accesses
bogdanm 0:9b334a45a8ff 463 *
bogdanm 0:9b334a45a8ff 464 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 465 * Number of clock cycles for address setup before REn is asserted
bogdanm 0:9b334a45a8ff 466 *
bogdanm 0:9b334a45a8ff 467 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 468 * The number of cycles the REn is held active. After the specified number of
bogdanm 0:9b334a45a8ff 469 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 470 *
bogdanm 0:9b334a45a8ff 471 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 472 * The number of cycles CSn is held active after the REn is dessarted
bogdanm 0:9b334a45a8ff 473 ******************************************************************************/
bogdanm 0:9b334a45a8ff 474 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 475 {
bogdanm 0:9b334a45a8ff 476 uint32_t readTiming;
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 479 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 480 EFM_ASSERT(strobeCycles < 16);
bogdanm 0:9b334a45a8ff 481 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /* Configure timing values */
mbed_official 50:a417edff4437 484 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
mbed_official 50:a417edff4437 485 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
mbed_official 50:a417edff4437 486 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488
mbed_official 50:a417edff4437 489 EBI->RDTIMING = (EBI->RDTIMING
mbed_official 50:a417edff4437 490 & ~(_EBI_RDTIMING_RDSETUP_MASK
mbed_official 50:a417edff4437 491 | _EBI_RDTIMING_RDSTRB_MASK
mbed_official 50:a417edff4437 492 | _EBI_RDTIMING_RDHOLD_MASK))
mbed_official 50:a417edff4437 493 | readTiming;
bogdanm 0:9b334a45a8ff 494 }
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 498 * @brief
bogdanm 0:9b334a45a8ff 499 * Configure timing values of write bus accesses
bogdanm 0:9b334a45a8ff 500 *
bogdanm 0:9b334a45a8ff 501 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 502 * Number of clock cycles for address setup before WEn is asserted
bogdanm 0:9b334a45a8ff 503 *
bogdanm 0:9b334a45a8ff 504 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 505 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 506 *
bogdanm 0:9b334a45a8ff 507 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 508 * Number of cycles CSn is held active after the WEn is deasserted
bogdanm 0:9b334a45a8ff 509 ******************************************************************************/
bogdanm 0:9b334a45a8ff 510 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 511 {
bogdanm 0:9b334a45a8ff 512 uint32_t writeTiming;
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 515 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 516 EFM_ASSERT(strobeCycles < 16);
bogdanm 0:9b334a45a8ff 517 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /* Configure timing values */
mbed_official 50:a417edff4437 520 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
mbed_official 50:a417edff4437 521 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
mbed_official 50:a417edff4437 522 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 523
mbed_official 50:a417edff4437 524 EBI->WRTIMING = (EBI->WRTIMING
mbed_official 50:a417edff4437 525 & ~(_EBI_WRTIMING_WRSETUP_MASK
mbed_official 50:a417edff4437 526 | _EBI_WRTIMING_WRSTRB_MASK
mbed_official 50:a417edff4437 527 | _EBI_WRTIMING_WRHOLD_MASK))
mbed_official 50:a417edff4437 528 | writeTiming;
bogdanm 0:9b334a45a8ff 529 }
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 533 * @brief
bogdanm 0:9b334a45a8ff 534 * Configure timing values of address latch bus accesses
bogdanm 0:9b334a45a8ff 535 *
bogdanm 0:9b334a45a8ff 536 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 537 * Sets the number of cycles the address is held after ALE is asserted
bogdanm 0:9b334a45a8ff 538 *
bogdanm 0:9b334a45a8ff 539 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 540 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
bogdanm 0:9b334a45a8ff 541 * ALE is asserted. If set 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 542 ******************************************************************************/
bogdanm 0:9b334a45a8ff 543 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 544 {
bogdanm 0:9b334a45a8ff 545 uint32_t addressLatchTiming;
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* Check that timing values are within limits */
bogdanm 0:9b334a45a8ff 548 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 549 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Configure address latch timing values */
mbed_official 50:a417edff4437 552 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
mbed_official 50:a417edff4437 553 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 554
mbed_official 50:a417edff4437 555 EBI->ADDRTIMING = (EBI->ADDRTIMING
mbed_official 50:a417edff4437 556 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
mbed_official 50:a417edff4437 557 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
mbed_official 50:a417edff4437 558 | addressLatchTiming;
bogdanm 0:9b334a45a8ff 559 }
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 562 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 563 * @brief
bogdanm 0:9b334a45a8ff 564 * Configure and initialize TFT Direct Drive
bogdanm 0:9b334a45a8ff 565 *
bogdanm 0:9b334a45a8ff 566 * @param[in] ebiTFTInit
bogdanm 0:9b334a45a8ff 567 * TFT Initialization structure
bogdanm 0:9b334a45a8ff 568 ******************************************************************************/
bogdanm 0:9b334a45a8ff 569 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 uint32_t ctrl;
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 /* Configure base address for frame buffer offset to EBI bank */
bogdanm 0:9b334a45a8ff 574 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /* Configure display size and porch areas */
bogdanm 0:9b334a45a8ff 577 EBI_TFTSizeSet(ebiTFTInit->hsize,
bogdanm 0:9b334a45a8ff 578 ebiTFTInit->vsize);
bogdanm 0:9b334a45a8ff 579 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
bogdanm 0:9b334a45a8ff 580 ebiTFTInit->hPorchBack,
bogdanm 0:9b334a45a8ff 581 ebiTFTInit->hPulseWidth);
bogdanm 0:9b334a45a8ff 582 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
bogdanm 0:9b334a45a8ff 583 ebiTFTInit->vPorchBack,
bogdanm 0:9b334a45a8ff 584 ebiTFTInit->vPulseWidth);
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /* Configure timing settings */
bogdanm 0:9b334a45a8ff 587 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
bogdanm 0:9b334a45a8ff 588 ebiTFTInit->startPosition,
bogdanm 0:9b334a45a8ff 589 ebiTFTInit->setupCycles,
bogdanm 0:9b334a45a8ff 590 ebiTFTInit->holdCycles);
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /* Configure line polarity settings */
bogdanm 0:9b334a45a8ff 593 EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
bogdanm 0:9b334a45a8ff 594 EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
bogdanm 0:9b334a45a8ff 595 EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
bogdanm 0:9b334a45a8ff 596 EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
bogdanm 0:9b334a45a8ff 597 EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /* Main control, EBI bank select, mask and blending configuration */
mbed_official 50:a417edff4437 600 ctrl = (uint32_t)ebiTFTInit->bank
mbed_official 50:a417edff4437 601 | (uint32_t)ebiTFTInit->width
mbed_official 50:a417edff4437 602 | (uint32_t)ebiTFTInit->colSrc
mbed_official 50:a417edff4437 603 | (uint32_t)ebiTFTInit->interleave
mbed_official 50:a417edff4437 604 | (uint32_t)ebiTFTInit->fbTrigger
mbed_official 50:a417edff4437 605 | (uint32_t)(ebiTFTInit->shiftDClk == true
mbed_official 50:a417edff4437 606 ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
mbed_official 50:a417edff4437 607 | (uint32_t)ebiTFTInit->maskBlend
mbed_official 50:a417edff4437 608 | (uint32_t)ebiTFTInit->driveMode;
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 EBI->TFTCTRL = ctrl;
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 /* Enable TFT pins */
bogdanm 0:9b334a45a8ff 613 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
bogdanm 0:9b334a45a8ff 614 {
mbed_official 50:a417edff4437 615 EBI->ROUTE |= EBI_ROUTE_TFTPEN;
bogdanm 0:9b334a45a8ff 616 }
bogdanm 0:9b334a45a8ff 617 }
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 621 * @brief
bogdanm 0:9b334a45a8ff 622 * Configure and initialize TFT size settings
bogdanm 0:9b334a45a8ff 623 *
bogdanm 0:9b334a45a8ff 624 * @param[in] horizontal
bogdanm 0:9b334a45a8ff 625 * TFT display horizontal size in pixels
bogdanm 0:9b334a45a8ff 626 * @param[in] vertical
bogdanm 0:9b334a45a8ff 627 * TFT display vertical size in pixels
bogdanm 0:9b334a45a8ff 628 ******************************************************************************/
bogdanm 0:9b334a45a8ff 629 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
bogdanm 0:9b334a45a8ff 630 {
bogdanm 0:9b334a45a8ff 631 EFM_ASSERT((horizontal-1) < 1024);
bogdanm 0:9b334a45a8ff 632 EFM_ASSERT((vertical-1) < 1024);
bogdanm 0:9b334a45a8ff 633
mbed_official 50:a417edff4437 634 EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
mbed_official 50:a417edff4437 635 | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
bogdanm 0:9b334a45a8ff 636 }
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 639 * @brief
bogdanm 0:9b334a45a8ff 640 * Configure and initialize Horizontal Porch Settings
bogdanm 0:9b334a45a8ff 641 *
bogdanm 0:9b334a45a8ff 642 * @param[in] front
bogdanm 0:9b334a45a8ff 643 * Horizontal front porch size in pixels
bogdanm 0:9b334a45a8ff 644 * @param[in] back
bogdanm 0:9b334a45a8ff 645 * Horizontal back porch size in pixels
bogdanm 0:9b334a45a8ff 646 * @param[in] pulseWidth
bogdanm 0:9b334a45a8ff 647 * Horizontal synchronization pulse width. Set to required -1.
bogdanm 0:9b334a45a8ff 648 ******************************************************************************/
bogdanm 0:9b334a45a8ff 649 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
bogdanm 0:9b334a45a8ff 650 {
bogdanm 0:9b334a45a8ff 651 EFM_ASSERT(front < 256);
bogdanm 0:9b334a45a8ff 652 EFM_ASSERT(back < 256);
bogdanm 0:9b334a45a8ff 653 EFM_ASSERT((pulseWidth-1) < 128);
bogdanm 0:9b334a45a8ff 654
mbed_official 50:a417edff4437 655 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
mbed_official 50:a417edff4437 656 | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
mbed_official 50:a417edff4437 657 | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 662 * @brief
bogdanm 0:9b334a45a8ff 663 * Configure Vertical Porch Settings
bogdanm 0:9b334a45a8ff 664 *
bogdanm 0:9b334a45a8ff 665 * @param[in] front
bogdanm 0:9b334a45a8ff 666 * Vertical front porch size in pixels
bogdanm 0:9b334a45a8ff 667 * @param[in] back
bogdanm 0:9b334a45a8ff 668 * Vertical back porch size in pixels
bogdanm 0:9b334a45a8ff 669 * @param[in] pulseWidth
bogdanm 0:9b334a45a8ff 670 * Vertical synchronization pulse width. Set to required -1.
bogdanm 0:9b334a45a8ff 671 ******************************************************************************/
bogdanm 0:9b334a45a8ff 672 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 EFM_ASSERT(front < 256);
bogdanm 0:9b334a45a8ff 675 EFM_ASSERT(back < 256);
bogdanm 0:9b334a45a8ff 676 EFM_ASSERT((pulseWidth-1) < 128);
bogdanm 0:9b334a45a8ff 677
mbed_official 50:a417edff4437 678 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
mbed_official 50:a417edff4437 679 | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
mbed_official 50:a417edff4437 680 | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 685 * @brief
bogdanm 0:9b334a45a8ff 686 * Configure TFT Direct Drive Timing Settings
bogdanm 0:9b334a45a8ff 687 *
bogdanm 0:9b334a45a8ff 688 * @param[in] dclkPeriod
bogdanm 0:9b334a45a8ff 689 * DCLK period in internal cycles
bogdanm 0:9b334a45a8ff 690 *
bogdanm 0:9b334a45a8ff 691 * @param[in] start
bogdanm 0:9b334a45a8ff 692 * Starting position of external direct drive, relative to DCLK inactive edge
bogdanm 0:9b334a45a8ff 693 *
bogdanm 0:9b334a45a8ff 694 * @param[in] setup
bogdanm 0:9b334a45a8ff 695 * Number of cycles RGB data is driven before active edge of DCLK
bogdanm 0:9b334a45a8ff 696 *
bogdanm 0:9b334a45a8ff 697 * @param[in] hold
bogdanm 0:9b334a45a8ff 698 * Number of cycles RGB data is held after active edge of DCLK
bogdanm 0:9b334a45a8ff 699 ******************************************************************************/
bogdanm 0:9b334a45a8ff 700 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
bogdanm 0:9b334a45a8ff 701 {
bogdanm 0:9b334a45a8ff 702 EFM_ASSERT(dclkPeriod < 2048);
bogdanm 0:9b334a45a8ff 703 EFM_ASSERT(start < 2048);
bogdanm 0:9b334a45a8ff 704 EFM_ASSERT(setup < 4);
bogdanm 0:9b334a45a8ff 705 EFM_ASSERT(hold < 4);
bogdanm 0:9b334a45a8ff 706
mbed_official 50:a417edff4437 707 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
mbed_official 50:a417edff4437 708 | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
mbed_official 50:a417edff4437 709 | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
mbed_official 50:a417edff4437 710 | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712 #endif
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 715 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 716 * @brief
bogdanm 0:9b334a45a8ff 717 * Configure read operation parameters for selected bank
bogdanm 0:9b334a45a8ff 718 *
bogdanm 0:9b334a45a8ff 719 * @param[in] banks
bogdanm 0:9b334a45a8ff 720 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 721 *
bogdanm 0:9b334a45a8ff 722 * @param[in] pageMode
bogdanm 0:9b334a45a8ff 723 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 724 *
bogdanm 0:9b334a45a8ff 725 * @param[in] prefetch
bogdanm 0:9b334a45a8ff 726 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 727 *
bogdanm 0:9b334a45a8ff 728 * @param[in] halfRE
bogdanm 0:9b334a45a8ff 729 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 730 ******************************************************************************/
bogdanm 0:9b334a45a8ff 731 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
bogdanm 0:9b334a45a8ff 732 {
bogdanm 0:9b334a45a8ff 733 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 734 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 /* Configure read operation parameters */
bogdanm 0:9b334a45a8ff 737 if( banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 738 {
mbed_official 50:a417edff4437 739 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
mbed_official 50:a417edff4437 740 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
mbed_official 50:a417edff4437 741 BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 742 }
bogdanm 0:9b334a45a8ff 743 if( banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 744 {
mbed_official 50:a417edff4437 745 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
mbed_official 50:a417edff4437 746 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
mbed_official 50:a417edff4437 747 BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 748 }
bogdanm 0:9b334a45a8ff 749 if( banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 750 {
mbed_official 50:a417edff4437 751 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
mbed_official 50:a417edff4437 752 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
mbed_official 50:a417edff4437 753 BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 754 }
bogdanm 0:9b334a45a8ff 755 if( banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 756 {
mbed_official 50:a417edff4437 757 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
mbed_official 50:a417edff4437 758 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
mbed_official 50:a417edff4437 759 BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761 }
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 764 * @brief
bogdanm 0:9b334a45a8ff 765 * Configure timing values of read bus accesses
bogdanm 0:9b334a45a8ff 766 *
bogdanm 0:9b334a45a8ff 767 * @param[in] banks
bogdanm 0:9b334a45a8ff 768 * Mask of memory bank(s) to configure timing for
bogdanm 0:9b334a45a8ff 769 *
bogdanm 0:9b334a45a8ff 770 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 771 * Number of clock cycles for address setup before REn is asserted
bogdanm 0:9b334a45a8ff 772 *
bogdanm 0:9b334a45a8ff 773 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 774 * The number of cycles the REn is held active. After the specified number of
bogdanm 0:9b334a45a8ff 775 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 776 *
bogdanm 0:9b334a45a8ff 777 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 778 * The number of cycles CSn is held active after the REn is dessarted
bogdanm 0:9b334a45a8ff 779 ******************************************************************************/
bogdanm 0:9b334a45a8ff 780 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 781 {
bogdanm 0:9b334a45a8ff 782 uint32_t readTiming;
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 785 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 788 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 789 EFM_ASSERT(strobeCycles < 64);
bogdanm 0:9b334a45a8ff 790 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /* Configure timing values */
mbed_official 50:a417edff4437 793 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
mbed_official 50:a417edff4437 794 | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
mbed_official 50:a417edff4437 795 | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 798 {
mbed_official 50:a417edff4437 799 EBI->RDTIMING = (EBI->RDTIMING
mbed_official 50:a417edff4437 800 & ~(_EBI_RDTIMING_RDSETUP_MASK
mbed_official 50:a417edff4437 801 | _EBI_RDTIMING_RDSTRB_MASK
mbed_official 50:a417edff4437 802 | _EBI_RDTIMING_RDHOLD_MASK))
mbed_official 50:a417edff4437 803 | readTiming;
bogdanm 0:9b334a45a8ff 804 }
bogdanm 0:9b334a45a8ff 805 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 806 {
mbed_official 50:a417edff4437 807 EBI->RDTIMING1 = (EBI->RDTIMING1
mbed_official 50:a417edff4437 808 & ~(_EBI_RDTIMING1_RDSETUP_MASK
mbed_official 50:a417edff4437 809 | _EBI_RDTIMING1_RDSTRB_MASK
mbed_official 50:a417edff4437 810 | _EBI_RDTIMING1_RDHOLD_MASK))
mbed_official 50:a417edff4437 811 | readTiming;
bogdanm 0:9b334a45a8ff 812 }
bogdanm 0:9b334a45a8ff 813 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 814 {
mbed_official 50:a417edff4437 815 EBI->RDTIMING2 = (EBI->RDTIMING2
mbed_official 50:a417edff4437 816 & ~(_EBI_RDTIMING2_RDSETUP_MASK
mbed_official 50:a417edff4437 817 | _EBI_RDTIMING2_RDSTRB_MASK
mbed_official 50:a417edff4437 818 | _EBI_RDTIMING2_RDHOLD_MASK))
mbed_official 50:a417edff4437 819 | readTiming;
bogdanm 0:9b334a45a8ff 820 }
bogdanm 0:9b334a45a8ff 821 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 822 {
mbed_official 50:a417edff4437 823 EBI->RDTIMING3 = (EBI->RDTIMING3
mbed_official 50:a417edff4437 824 & ~(_EBI_RDTIMING3_RDSETUP_MASK
mbed_official 50:a417edff4437 825 | _EBI_RDTIMING3_RDSTRB_MASK
mbed_official 50:a417edff4437 826 | _EBI_RDTIMING3_RDHOLD_MASK))
mbed_official 50:a417edff4437 827 | readTiming;
bogdanm 0:9b334a45a8ff 828 }
bogdanm 0:9b334a45a8ff 829 }
bogdanm 0:9b334a45a8ff 830
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 833 * @brief
bogdanm 0:9b334a45a8ff 834 * Configure write operation parameters for selected bank
bogdanm 0:9b334a45a8ff 835 *
bogdanm 0:9b334a45a8ff 836 * @param[in] banks
bogdanm 0:9b334a45a8ff 837 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 838 *
bogdanm 0:9b334a45a8ff 839 * @param[in] writeBufDisable
bogdanm 0:9b334a45a8ff 840 * If true, disable the write buffer
bogdanm 0:9b334a45a8ff 841 *
bogdanm 0:9b334a45a8ff 842 * @param[in] halfWE
bogdanm 0:9b334a45a8ff 843 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 844 ******************************************************************************/
bogdanm 0:9b334a45a8ff 845 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 848 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /* Configure write operation parameters */
bogdanm 0:9b334a45a8ff 851 if( banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 852 {
mbed_official 50:a417edff4437 853 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
mbed_official 50:a417edff4437 854 BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 855 }
bogdanm 0:9b334a45a8ff 856 if( banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 857 {
mbed_official 50:a417edff4437 858 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
mbed_official 50:a417edff4437 859 BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861 if( banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 862 {
mbed_official 50:a417edff4437 863 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
mbed_official 50:a417edff4437 864 BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 865 }
bogdanm 0:9b334a45a8ff 866 if( banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 867 {
mbed_official 50:a417edff4437 868 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
mbed_official 50:a417edff4437 869 BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 870 }
bogdanm 0:9b334a45a8ff 871 }
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 875 * @brief
bogdanm 0:9b334a45a8ff 876 * Configure timing values of write bus accesses
bogdanm 0:9b334a45a8ff 877 *
bogdanm 0:9b334a45a8ff 878 * @param[in] banks
bogdanm 0:9b334a45a8ff 879 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 880 *
bogdanm 0:9b334a45a8ff 881 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 882 * Number of clock cycles for address setup before WEn is asserted
bogdanm 0:9b334a45a8ff 883 *
bogdanm 0:9b334a45a8ff 884 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 885 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 886 *
bogdanm 0:9b334a45a8ff 887 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 888 * Number of cycles CSn is held active after the WEn is deasserted
bogdanm 0:9b334a45a8ff 889 ******************************************************************************/
bogdanm 0:9b334a45a8ff 890 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 891 {
bogdanm 0:9b334a45a8ff 892 uint32_t writeTiming;
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 895 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 898 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 899 EFM_ASSERT(strobeCycles < 64);
bogdanm 0:9b334a45a8ff 900 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 901
bogdanm 0:9b334a45a8ff 902 /* Configure timing values */
mbed_official 50:a417edff4437 903 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
mbed_official 50:a417edff4437 904 | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
mbed_official 50:a417edff4437 905 | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 906
bogdanm 0:9b334a45a8ff 907 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 908 {
mbed_official 50:a417edff4437 909 EBI->WRTIMING = (EBI->WRTIMING
mbed_official 50:a417edff4437 910 & ~(_EBI_WRTIMING_WRSETUP_MASK
mbed_official 50:a417edff4437 911 | _EBI_WRTIMING_WRSTRB_MASK
mbed_official 50:a417edff4437 912 | _EBI_WRTIMING_WRHOLD_MASK))
mbed_official 50:a417edff4437 913 | writeTiming;
bogdanm 0:9b334a45a8ff 914 }
bogdanm 0:9b334a45a8ff 915 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 916 {
mbed_official 50:a417edff4437 917 EBI->WRTIMING1 = (EBI->WRTIMING1
mbed_official 50:a417edff4437 918 & ~(_EBI_WRTIMING1_WRSETUP_MASK
mbed_official 50:a417edff4437 919 | _EBI_WRTIMING1_WRSTRB_MASK
mbed_official 50:a417edff4437 920 | _EBI_WRTIMING1_WRHOLD_MASK))
mbed_official 50:a417edff4437 921 | writeTiming;
bogdanm 0:9b334a45a8ff 922 }
bogdanm 0:9b334a45a8ff 923 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 924 {
mbed_official 50:a417edff4437 925 EBI->WRTIMING2 = (EBI->WRTIMING2
mbed_official 50:a417edff4437 926 & ~(_EBI_WRTIMING2_WRSETUP_MASK
mbed_official 50:a417edff4437 927 | _EBI_WRTIMING2_WRSTRB_MASK
mbed_official 50:a417edff4437 928 | _EBI_WRTIMING2_WRHOLD_MASK))
mbed_official 50:a417edff4437 929 | writeTiming;
bogdanm 0:9b334a45a8ff 930 }
bogdanm 0:9b334a45a8ff 931 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 932 {
mbed_official 50:a417edff4437 933 EBI->WRTIMING3 = (EBI->WRTIMING3
mbed_official 50:a417edff4437 934 & ~(_EBI_WRTIMING3_WRSETUP_MASK
mbed_official 50:a417edff4437 935 | _EBI_WRTIMING3_WRSTRB_MASK
mbed_official 50:a417edff4437 936 | _EBI_WRTIMING3_WRHOLD_MASK))
mbed_official 50:a417edff4437 937 | writeTiming;
bogdanm 0:9b334a45a8ff 938 }
bogdanm 0:9b334a45a8ff 939 }
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 943 * @brief
bogdanm 0:9b334a45a8ff 944 * Configure address operation parameters for selected bank
bogdanm 0:9b334a45a8ff 945 *
bogdanm 0:9b334a45a8ff 946 * @param[in] banks
bogdanm 0:9b334a45a8ff 947 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 948 *
bogdanm 0:9b334a45a8ff 949 * @param[in] halfALE
bogdanm 0:9b334a45a8ff 950 * Enables or disables half cycle ALE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 951 ******************************************************************************/
bogdanm 0:9b334a45a8ff 952 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
bogdanm 0:9b334a45a8ff 953 {
bogdanm 0:9b334a45a8ff 954 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 955 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 956
bogdanm 0:9b334a45a8ff 957 if( banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 958 {
mbed_official 50:a417edff4437 959 BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 960 }
bogdanm 0:9b334a45a8ff 961 if( banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 962 {
mbed_official 50:a417edff4437 963 BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 964 }
bogdanm 0:9b334a45a8ff 965 if( banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 966 {
mbed_official 50:a417edff4437 967 BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 968 }
bogdanm 0:9b334a45a8ff 969 if( banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 970 {
mbed_official 50:a417edff4437 971 BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 972 }
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 977 * @brief
bogdanm 0:9b334a45a8ff 978 * Configure timing values of address latch bus accesses
bogdanm 0:9b334a45a8ff 979 *
bogdanm 0:9b334a45a8ff 980 * @param[in] banks
bogdanm 0:9b334a45a8ff 981 * Mask of memory bank(s) to configure address timing for
bogdanm 0:9b334a45a8ff 982 *
bogdanm 0:9b334a45a8ff 983 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 984 * Sets the number of cycles the address is held after ALE is asserted
bogdanm 0:9b334a45a8ff 985 *
bogdanm 0:9b334a45a8ff 986 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 987 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
bogdanm 0:9b334a45a8ff 988 * ALE is asserted. If set 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 989 ******************************************************************************/
bogdanm 0:9b334a45a8ff 990 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 991 {
bogdanm 0:9b334a45a8ff 992 uint32_t addressLatchTiming;
bogdanm 0:9b334a45a8ff 993
bogdanm 0:9b334a45a8ff 994 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 995 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 996
bogdanm 0:9b334a45a8ff 997 /* Check that timing values are within limits */
bogdanm 0:9b334a45a8ff 998 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 999 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 1000
bogdanm 0:9b334a45a8ff 1001 /* Configure address latch timing values */
mbed_official 50:a417edff4437 1002 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
mbed_official 50:a417edff4437 1003 | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 1004
bogdanm 0:9b334a45a8ff 1005 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 1006 {
mbed_official 50:a417edff4437 1007 EBI->ADDRTIMING = (EBI->ADDRTIMING
mbed_official 50:a417edff4437 1008 & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
mbed_official 50:a417edff4437 1009 | _EBI_ADDRTIMING_ADDRHOLD_MASK))
mbed_official 50:a417edff4437 1010 | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1011 }
bogdanm 0:9b334a45a8ff 1012 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 1013 {
mbed_official 50:a417edff4437 1014 EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
mbed_official 50:a417edff4437 1015 & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
mbed_official 50:a417edff4437 1016 | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
mbed_official 50:a417edff4437 1017 | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1018 }
bogdanm 0:9b334a45a8ff 1019 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 1020 {
mbed_official 50:a417edff4437 1021 EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
mbed_official 50:a417edff4437 1022 & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
mbed_official 50:a417edff4437 1023 | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
mbed_official 50:a417edff4437 1024 | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1025 }
bogdanm 0:9b334a45a8ff 1026 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 1027 {
mbed_official 50:a417edff4437 1028 EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
mbed_official 50:a417edff4437 1029 & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
mbed_official 50:a417edff4437 1030 | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
mbed_official 50:a417edff4437 1031 | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1032 }
bogdanm 0:9b334a45a8ff 1033 }
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035
bogdanm 0:9b334a45a8ff 1036 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 1037 * @brief
bogdanm 0:9b334a45a8ff 1038 * Configure EBI pin polarity for selected bank(s) for devices with individual
bogdanm 0:9b334a45a8ff 1039 * timing support
bogdanm 0:9b334a45a8ff 1040 *
bogdanm 0:9b334a45a8ff 1041 * @param[in] banks
bogdanm 0:9b334a45a8ff 1042 * Mask of memory bank(s) to configure polarity for
bogdanm 0:9b334a45a8ff 1043 *
bogdanm 0:9b334a45a8ff 1044 * @param[in] line
bogdanm 0:9b334a45a8ff 1045 * Which pin/line to configure
bogdanm 0:9b334a45a8ff 1046 *
bogdanm 0:9b334a45a8ff 1047 * @param[in] polarity
bogdanm 0:9b334a45a8ff 1048 * Active high, or active low
bogdanm 0:9b334a45a8ff 1049 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1050 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
bogdanm 0:9b334a45a8ff 1051 {
bogdanm 0:9b334a45a8ff 1052 uint32_t bankSet = 0;
bogdanm 0:9b334a45a8ff 1053 volatile uint32_t *polRegister = 0;
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 1056 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 1057
bogdanm 0:9b334a45a8ff 1058 while (banks)
bogdanm 0:9b334a45a8ff 1059 {
bogdanm 0:9b334a45a8ff 1060 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 1061 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 polRegister = &EBI->POLARITY;
bogdanm 0:9b334a45a8ff 1064 bankSet = EBI_BANK0;
bogdanm 0:9b334a45a8ff 1065 }
bogdanm 0:9b334a45a8ff 1066 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 1067 {
bogdanm 0:9b334a45a8ff 1068 polRegister = &EBI->POLARITY1;
bogdanm 0:9b334a45a8ff 1069 bankSet = EBI_BANK1;
bogdanm 0:9b334a45a8ff 1070 }
bogdanm 0:9b334a45a8ff 1071 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 1072 {
bogdanm 0:9b334a45a8ff 1073 polRegister = &EBI->POLARITY2;
bogdanm 0:9b334a45a8ff 1074 bankSet = EBI_BANK2;
bogdanm 0:9b334a45a8ff 1075 }
bogdanm 0:9b334a45a8ff 1076 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 1077 {
bogdanm 0:9b334a45a8ff 1078 polRegister = &EBI->POLARITY3;
bogdanm 0:9b334a45a8ff 1079 bankSet = EBI_BANK3;
bogdanm 0:9b334a45a8ff 1080 }
bogdanm 0:9b334a45a8ff 1081 #else
bogdanm 0:9b334a45a8ff 1082 polRegister = &EBI->POLARITY;
bogdanm 0:9b334a45a8ff 1083 banks = 0;
bogdanm 0:9b334a45a8ff 1084 #endif
bogdanm 0:9b334a45a8ff 1085
bogdanm 0:9b334a45a8ff 1086 /* What line to configure */
bogdanm 0:9b334a45a8ff 1087 switch (line)
bogdanm 0:9b334a45a8ff 1088 {
mbed_official 50:a417edff4437 1089 case ebiLineARDY:
mbed_official 50:a417edff4437 1090 BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1091 break;
mbed_official 50:a417edff4437 1092 case ebiLineALE:
mbed_official 50:a417edff4437 1093 BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1094 break;
mbed_official 50:a417edff4437 1095 case ebiLineWE:
mbed_official 50:a417edff4437 1096 BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1097 break;
mbed_official 50:a417edff4437 1098 case ebiLineRE:
mbed_official 50:a417edff4437 1099 BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1100 break;
mbed_official 50:a417edff4437 1101 case ebiLineCS:
mbed_official 50:a417edff4437 1102 BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1103 break;
bogdanm 0:9b334a45a8ff 1104 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
mbed_official 50:a417edff4437 1105 case ebiLineBL:
mbed_official 50:a417edff4437 1106 BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1107 break;
mbed_official 50:a417edff4437 1108 case ebiLineTFTVSync:
mbed_official 50:a417edff4437 1109 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1110 break;
mbed_official 50:a417edff4437 1111 case ebiLineTFTHSync:
mbed_official 50:a417edff4437 1112 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1113 break;
mbed_official 50:a417edff4437 1114 case ebiLineTFTDataEn:
mbed_official 50:a417edff4437 1115 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1116 break;
mbed_official 50:a417edff4437 1117 case ebiLineTFTDClk:
mbed_official 50:a417edff4437 1118 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1119 break;
mbed_official 50:a417edff4437 1120 case ebiLineTFTCS:
mbed_official 50:a417edff4437 1121 BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
mbed_official 50:a417edff4437 1122 break;
bogdanm 0:9b334a45a8ff 1123 #endif
mbed_official 50:a417edff4437 1124 default:
mbed_official 50:a417edff4437 1125 EFM_ASSERT(0);
mbed_official 50:a417edff4437 1126 break;
bogdanm 0:9b334a45a8ff 1127 }
mbed_official 50:a417edff4437 1128 banks = banks & ~bankSet;
bogdanm 0:9b334a45a8ff 1129 }
bogdanm 0:9b334a45a8ff 1130 }
bogdanm 0:9b334a45a8ff 1131
bogdanm 0:9b334a45a8ff 1132
bogdanm 0:9b334a45a8ff 1133 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 1134 * @brief
bogdanm 0:9b334a45a8ff 1135 * Configure Byte Lane Enable for select banks
bogdanm 0:9b334a45a8ff 1136 * timing support
bogdanm 0:9b334a45a8ff 1137 *
bogdanm 0:9b334a45a8ff 1138 * @param[in] banks
bogdanm 0:9b334a45a8ff 1139 * Mask of memory bank(s) to configure polarity for
bogdanm 0:9b334a45a8ff 1140 *
bogdanm 0:9b334a45a8ff 1141 * @param[in] enable
bogdanm 0:9b334a45a8ff 1142 * Flag
bogdanm 0:9b334a45a8ff 1143 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1144 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
bogdanm 0:9b334a45a8ff 1145 {
bogdanm 0:9b334a45a8ff 1146 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 1147 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 1148
bogdanm 0:9b334a45a8ff 1149 /* Configure byte lane support for each selected bank */
bogdanm 0:9b334a45a8ff 1150 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 1151 {
mbed_official 50:a417edff4437 1152 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1153 }
bogdanm 0:9b334a45a8ff 1154 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 1155 {
mbed_official 50:a417edff4437 1156 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1157 }
bogdanm 0:9b334a45a8ff 1158 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 1159 {
mbed_official 50:a417edff4437 1160 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1161 }
bogdanm 0:9b334a45a8ff 1162 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 1163 {
mbed_official 50:a417edff4437 1164 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1165 }
bogdanm 0:9b334a45a8ff 1166 }
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 1170 * @brief
bogdanm 0:9b334a45a8ff 1171 * Configure Alternate Address Map support
bogdanm 0:9b334a45a8ff 1172 * Enables or disables 256MB address range for all banks
bogdanm 0:9b334a45a8ff 1173 *
bogdanm 0:9b334a45a8ff 1174 * @param[in] enable
bogdanm 0:9b334a45a8ff 1175 * Set or clear address map extension
bogdanm 0:9b334a45a8ff 1176 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1177 void EBI_AltMapEnable(bool enable)
bogdanm 0:9b334a45a8ff 1178 {
mbed_official 50:a417edff4437 1179 BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1180 }
bogdanm 0:9b334a45a8ff 1181
bogdanm 0:9b334a45a8ff 1182 #endif
bogdanm 0:9b334a45a8ff 1183
bogdanm 0:9b334a45a8ff 1184 /** @} (end addtogroup EBI) */
bogdanm 0:9b334a45a8ff 1185 /** @} (end addtogroup EM_Library) */
bogdanm 0:9b334a45a8ff 1186
bogdanm 0:9b334a45a8ff 1187 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */