Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_ftm.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_ftm.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Prototypes
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /*!
<> 144:ef7eb2e8f9f7 37 * @brief Gets the instance from the base address
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 * @return The FTM instance
<> 144:ef7eb2e8f9f7 42 */
<> 144:ef7eb2e8f9f7 43 static uint32_t FTM_GetInstance(FTM_Type *base);
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /*!
<> 144:ef7eb2e8f9f7 46 * @brief Sets the FTM register PWM synchronization method
<> 144:ef7eb2e8f9f7 47 *
<> 144:ef7eb2e8f9f7 48 * This function will set the necessary bits for the PWM synchronization mode that
<> 144:ef7eb2e8f9f7 49 * user wishes to use.
<> 144:ef7eb2e8f9f7 50 *
<> 144:ef7eb2e8f9f7 51 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 52 * @param syncMethod Syncronization methods to use to update buffered registers. This is a logical
<> 144:ef7eb2e8f9f7 53 * OR of members of the enumeration ::ftm_pwm_sync_method_t
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod);
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*!
<> 144:ef7eb2e8f9f7 58 * @brief Sets the reload points used as loading points for register update
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * This function will set the necessary bits based on what the user wishes to use as loading
<> 144:ef7eb2e8f9f7 61 * points for FTM register update. When using this it is not required to use PWM synchnronization.
<> 144:ef7eb2e8f9f7 62 *
<> 144:ef7eb2e8f9f7 63 * @param base FTM peripheral base address
<> 144:ef7eb2e8f9f7 64 * @param reloadPoints FTM reload points. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 65 * enumeration ::ftm_reload_point_t
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints);
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /*******************************************************************************
<> 144:ef7eb2e8f9f7 70 * Variables
<> 144:ef7eb2e8f9f7 71 ******************************************************************************/
<> 144:ef7eb2e8f9f7 72 /*! @brief Pointers to FTM bases for each instance. */
<> 144:ef7eb2e8f9f7 73 static FTM_Type *const s_ftmBases[] = FTM_BASE_PTRS;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /*! @brief Pointers to FTM clocks for each instance. */
<> 144:ef7eb2e8f9f7 76 static const clock_ip_name_t s_ftmClocks[] = FTM_CLOCKS;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /*******************************************************************************
<> 144:ef7eb2e8f9f7 79 * Code
<> 144:ef7eb2e8f9f7 80 ******************************************************************************/
<> 144:ef7eb2e8f9f7 81 static uint32_t FTM_GetInstance(FTM_Type *base)
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 uint32_t instance;
<> 144:ef7eb2e8f9f7 84 uint32_t ftmArrayCount = (sizeof(s_ftmBases) / sizeof(s_ftmBases[0]));
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Find the instance index from base address mappings. */
<> 144:ef7eb2e8f9f7 87 for (instance = 0; instance < ftmArrayCount; instance++)
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 if (s_ftmBases[instance] == base)
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 break;
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 assert(instance < ftmArrayCount);
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 return instance;
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod)
<> 144:ef7eb2e8f9f7 101 {
<> 144:ef7eb2e8f9f7 102 uint8_t chnlNumber = 0;
<> 144:ef7eb2e8f9f7 103 uint32_t reg = 0, syncReg = 0;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 syncReg = base->SYNC;
<> 144:ef7eb2e8f9f7 106 /* Enable PWM synchronization of output mask register */
<> 144:ef7eb2e8f9f7 107 syncReg |= FTM_SYNC_SYNCHOM_MASK;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 reg = base->COMBINE;
<> 144:ef7eb2e8f9f7 110 for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++)
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 /* Enable PWM synchronization of registers C(n)V and C(n+1)V */
<> 144:ef7eb2e8f9f7 113 reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber)));
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115 base->COMBINE = reg;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 reg = base->SYNCONF;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Use enhanced PWM synchronization method. Use PWM sync to update register values */
<> 144:ef7eb2e8f9f7 120 reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_SWOC_MASK);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 if (syncMethod & FTM_SYNC_SWSYNC_MASK)
<> 144:ef7eb2e8f9f7 123 {
<> 144:ef7eb2e8f9f7 124 /* Enable needed bits for software trigger to update registers with its buffer value */
<> 144:ef7eb2e8f9f7 125 reg |= (FTM_SYNCONF_SWRSTCNT_MASK | FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK |
<> 144:ef7eb2e8f9f7 126 FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_SWOM_MASK);
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 if (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK))
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 /* Enable needed bits for hardware trigger to update registers with its buffer value */
<> 144:ef7eb2e8f9f7 132 reg |= (FTM_SYNCONF_HWRSTCNT_MASK | FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK |
<> 144:ef7eb2e8f9f7 133 FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_HWOM_MASK);
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Enable the appropriate hardware trigger that is used for PWM sync */
<> 144:ef7eb2e8f9f7 136 if (syncMethod & FTM_SYNC_TRIG0_MASK)
<> 144:ef7eb2e8f9f7 137 {
<> 144:ef7eb2e8f9f7 138 syncReg |= FTM_SYNC_TRIG0_MASK;
<> 144:ef7eb2e8f9f7 139 }
<> 144:ef7eb2e8f9f7 140 if (syncMethod & FTM_SYNC_TRIG1_MASK)
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 syncReg |= FTM_SYNC_TRIG1_MASK;
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144 if (syncMethod & FTM_SYNC_TRIG2_MASK)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 syncReg |= FTM_SYNC_TRIG2_MASK;
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Write back values to the SYNC register */
<> 144:ef7eb2e8f9f7 151 base->SYNC = syncReg;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Write the PWM synch values to the SYNCONF register */
<> 144:ef7eb2e8f9f7 154 base->SYNCONF = reg;
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 uint32_t chnlNumber = 0;
<> 144:ef7eb2e8f9f7 160 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Need CNTINC bit to be 1 for CNTIN register to update with its buffer value on reload */
<> 144:ef7eb2e8f9f7 163 base->SYNCONF |= FTM_SYNCONF_CNTINC_MASK;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 reg = base->COMBINE;
<> 144:ef7eb2e8f9f7 166 for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 /* Need SYNCEN bit to be 1 for CnV reg to update with its buffer value on reload */
<> 144:ef7eb2e8f9f7 169 reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber)));
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171 base->COMBINE = reg;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Set the reload points */
<> 144:ef7eb2e8f9f7 174 reg = base->PWMLOAD;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Enable the selected channel match reload points */
<> 144:ef7eb2e8f9f7 177 reg &= ~((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1);
<> 144:ef7eb2e8f9f7 178 reg |= (reloadPoints & ((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1));
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #if defined(FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) && (FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD)
<> 144:ef7eb2e8f9f7 181 /* Enable half cycle match as a reload point */
<> 144:ef7eb2e8f9f7 182 if (reloadPoints & kFTM_HalfCycMatch)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 reg |= FTM_PWMLOAD_HCSEL_MASK;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 else
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 reg &= ~FTM_PWMLOAD_HCSEL_MASK;
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 #endif /* FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 base->PWMLOAD = reg;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* These reload points are used when counter is in up-down counting mode */
<> 144:ef7eb2e8f9f7 195 reg = base->SYNC;
<> 144:ef7eb2e8f9f7 196 if (reloadPoints & kFTM_CntMax)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 /* Reload when counter turns from up to down */
<> 144:ef7eb2e8f9f7 199 reg |= FTM_SYNC_CNTMAX_MASK;
<> 144:ef7eb2e8f9f7 200 }
<> 144:ef7eb2e8f9f7 201 else
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 reg &= ~FTM_SYNC_CNTMAX_MASK;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 if (reloadPoints & kFTM_CntMin)
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 /* Reload when counter turns from down to up */
<> 144:ef7eb2e8f9f7 209 reg |= FTM_SYNC_CNTMIN_MASK;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211 else
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 reg &= ~FTM_SYNC_CNTMIN_MASK;
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215 base->SYNC = reg;
<> 144:ef7eb2e8f9f7 216 }
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 assert(config);
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 uint32_t reg;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 if (!(config->pwmSyncMode &
<> 144:ef7eb2e8f9f7 225 (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_SWSYNC_MASK)))
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 /* Invalid PWM sync mode */
<> 144:ef7eb2e8f9f7 228 return kStatus_Fail;
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Ungate the FTM clock*/
<> 144:ef7eb2e8f9f7 232 CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Configure the fault mode, enable FTM mode and disable write protection */
<> 144:ef7eb2e8f9f7 235 base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* Configure the update mechanism for buffered registers */
<> 144:ef7eb2e8f9f7 238 FTM_SetPwmSync(base, config->pwmSyncMode);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Setup intermediate register reload points */
<> 144:ef7eb2e8f9f7 241 FTM_SetReloadPoints(base, config->reloadPoints);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Set the clock prescale factor */
<> 144:ef7eb2e8f9f7 244 base->SC = FTM_SC_PS(config->prescale);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Setup the counter operation */
<> 144:ef7eb2e8f9f7 247 base->CONF = (FTM_CONF_BDMMODE(config->bdmMode) | FTM_CONF_GTBEEN(config->useGlobalTimeBase));
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Initial state of channel output */
<> 144:ef7eb2e8f9f7 250 base->OUTINIT = config->chnlInitState;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Channel polarity */
<> 144:ef7eb2e8f9f7 253 base->POL = config->chnlPolarity;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Set the external trigger sources */
<> 144:ef7eb2e8f9f7 256 base->EXTTRIG = config->extTriggers;
<> 144:ef7eb2e8f9f7 257 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER)
<> 144:ef7eb2e8f9f7 258 if (config->extTriggers & kFTM_ReloadInitTrigger)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 base->CONF |= FTM_CONF_ITRIGR_MASK;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262 else
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 base->CONF &= ~FTM_CONF_ITRIGR_MASK;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266 #endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* FTM deadtime insertion control */
<> 144:ef7eb2e8f9f7 269 base->DEADTIME = (FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue));
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* FTM fault filter value */
<> 144:ef7eb2e8f9f7 272 reg = base->FLTCTRL;
<> 144:ef7eb2e8f9f7 273 reg &= ~FTM_FLTCTRL_FFVAL_MASK;
<> 144:ef7eb2e8f9f7 274 reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue);
<> 144:ef7eb2e8f9f7 275 base->FLTCTRL = reg;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 return kStatus_Success;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 void FTM_Deinit(FTM_Type *base)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Set clock source to none to disable counter */
<> 144:ef7eb2e8f9f7 283 base->SC &= ~(FTM_SC_CLKS_MASK);
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Gate the FTM clock */
<> 144:ef7eb2e8f9f7 286 CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 void FTM_GetDefaultConfig(ftm_config_t *config)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 assert(config);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Divide FTM clock by 1 */
<> 144:ef7eb2e8f9f7 294 config->prescale = kFTM_Prescale_Divide_1;
<> 144:ef7eb2e8f9f7 295 /* FTM behavior in BDM mode */
<> 144:ef7eb2e8f9f7 296 config->bdmMode = kFTM_BdmMode_0;
<> 144:ef7eb2e8f9f7 297 /* Software trigger will be used to update registers */
<> 144:ef7eb2e8f9f7 298 config->pwmSyncMode = kFTM_SoftwareTrigger;
<> 144:ef7eb2e8f9f7 299 /* No intermediate register load */
<> 144:ef7eb2e8f9f7 300 config->reloadPoints = 0;
<> 144:ef7eb2e8f9f7 301 /* Fault control disabled for all channels */
<> 144:ef7eb2e8f9f7 302 config->faultMode = kFTM_Fault_Disable;
<> 144:ef7eb2e8f9f7 303 /* Disable the fault filter */
<> 144:ef7eb2e8f9f7 304 config->faultFilterValue = 0;
<> 144:ef7eb2e8f9f7 305 /* Divide the system clock by 1 */
<> 144:ef7eb2e8f9f7 306 config->deadTimePrescale = kFTM_Deadtime_Prescale_1;
<> 144:ef7eb2e8f9f7 307 /* No counts are inserted */
<> 144:ef7eb2e8f9f7 308 config->deadTimeValue = 0;
<> 144:ef7eb2e8f9f7 309 /* No external trigger */
<> 144:ef7eb2e8f9f7 310 config->extTriggers = 0;
<> 144:ef7eb2e8f9f7 311 /* Initialization value is 0 for all channels */
<> 144:ef7eb2e8f9f7 312 config->chnlInitState = 0;
<> 144:ef7eb2e8f9f7 313 /* Active high polarity for all channels */
<> 144:ef7eb2e8f9f7 314 config->chnlPolarity = 0;
<> 144:ef7eb2e8f9f7 315 /* Use internal FTM counter as timebase */
<> 144:ef7eb2e8f9f7 316 config->useGlobalTimeBase = false;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 status_t FTM_SetupPwm(FTM_Type *base,
<> 144:ef7eb2e8f9f7 320 const ftm_chnl_pwm_signal_param_t *chnlParams,
<> 144:ef7eb2e8f9f7 321 uint8_t numOfChnls,
<> 144:ef7eb2e8f9f7 322 ftm_pwm_mode_t mode,
<> 144:ef7eb2e8f9f7 323 uint32_t pwmFreq_Hz,
<> 144:ef7eb2e8f9f7 324 uint32_t srcClock_Hz)
<> 144:ef7eb2e8f9f7 325 {
<> 144:ef7eb2e8f9f7 326 assert(chnlParams);
<> 144:ef7eb2e8f9f7 327 assert(srcClock_Hz);
<> 144:ef7eb2e8f9f7 328 assert(pwmFreq_Hz);
<> 144:ef7eb2e8f9f7 329 assert(numOfChnls);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 uint32_t mod, reg;
<> 144:ef7eb2e8f9f7 332 uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK)));
<> 144:ef7eb2e8f9f7 333 uint16_t cnv, cnvFirstEdge;
<> 144:ef7eb2e8f9f7 334 uint8_t i;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 switch (mode)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 case kFTM_EdgeAlignedPwm:
<> 144:ef7eb2e8f9f7 339 case kFTM_CombinedPwm:
<> 144:ef7eb2e8f9f7 340 base->SC &= ~FTM_SC_CPWMS_MASK;
<> 144:ef7eb2e8f9f7 341 mod = (ftmClock / pwmFreq_Hz) - 1;
<> 144:ef7eb2e8f9f7 342 break;
<> 144:ef7eb2e8f9f7 343 case kFTM_CenterAlignedPwm:
<> 144:ef7eb2e8f9f7 344 base->SC |= FTM_SC_CPWMS_MASK;
<> 144:ef7eb2e8f9f7 345 mod = ftmClock / (pwmFreq_Hz * 2);
<> 144:ef7eb2e8f9f7 346 break;
<> 144:ef7eb2e8f9f7 347 default:
<> 144:ef7eb2e8f9f7 348 return kStatus_Fail;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Return an error in case we overflow the registers, probably would require changing
<> 144:ef7eb2e8f9f7 352 * clock source to get the desired frequency */
<> 144:ef7eb2e8f9f7 353 if (mod > 65535U)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 return kStatus_Fail;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 /* Set the PWM period */
<> 144:ef7eb2e8f9f7 358 base->MOD = mod;
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Setup each FTM channel */
<> 144:ef7eb2e8f9f7 361 for (i = 0; i < numOfChnls; i++)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 /* Return error if requested dutycycle is greater than the max allowed */
<> 144:ef7eb2e8f9f7 364 if (chnlParams->dutyCyclePercent > 100)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 return kStatus_Fail;
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 if ((mode == kFTM_EdgeAlignedPwm) || (mode == kFTM_CenterAlignedPwm))
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Clear the current mode and edge level bits */
<> 144:ef7eb2e8f9f7 372 reg = base->CONTROLS[chnlParams->chnlNumber].CnSC;
<> 144:ef7eb2e8f9f7 373 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Setup the active level */
<> 144:ef7eb2e8f9f7 376 reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */
<> 144:ef7eb2e8f9f7 379 reg |= FTM_CnSC_MSB(1U);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Update the mode and edge level */
<> 144:ef7eb2e8f9f7 382 base->CONTROLS[chnlParams->chnlNumber].CnSC = reg;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 if (chnlParams->dutyCyclePercent == 0)
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 /* Signal stays low */
<> 144:ef7eb2e8f9f7 387 cnv = 0;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 else
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 cnv = (mod * chnlParams->dutyCyclePercent) / 100;
<> 144:ef7eb2e8f9f7 392 /* For 100% duty cycle */
<> 144:ef7eb2e8f9f7 393 if (cnv >= mod)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 cnv = mod + 1;
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 base->CONTROLS[chnlParams->chnlNumber].CnV = cnv;
<> 144:ef7eb2e8f9f7 400 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
<> 144:ef7eb2e8f9f7 401 /* Set to output mode */
<> 144:ef7eb2e8f9f7 402 FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);
<> 144:ef7eb2e8f9f7 403 #endif
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 else
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 /* This check is added for combined mode as the channel number should be the pair number */
<> 144:ef7eb2e8f9f7 408 if (chnlParams->chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2))
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 return kStatus_Fail;
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Return error if requested value is greater than the max allowed */
<> 144:ef7eb2e8f9f7 414 if (chnlParams->firstEdgeDelayPercent > 100)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 return kStatus_Fail;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Configure delay of the first edge */
<> 144:ef7eb2e8f9f7 420 if (chnlParams->firstEdgeDelayPercent == 0)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* No delay for the first edge */
<> 144:ef7eb2e8f9f7 423 cnvFirstEdge = 0;
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425 else
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Configure dutycycle */
<> 144:ef7eb2e8f9f7 431 if (chnlParams->dutyCyclePercent == 0)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* Signal stays low */
<> 144:ef7eb2e8f9f7 434 cnv = 0;
<> 144:ef7eb2e8f9f7 435 cnvFirstEdge = 0;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 else
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 cnv = (mod * chnlParams->dutyCyclePercent) / 100;
<> 144:ef7eb2e8f9f7 440 /* For 100% duty cycle */
<> 144:ef7eb2e8f9f7 441 if (cnv >= mod)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 cnv = mod + 1;
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Clear the current mode and edge level bits for channel n */
<> 144:ef7eb2e8f9f7 448 reg = base->CONTROLS[chnlParams->chnlNumber * 2].CnSC;
<> 144:ef7eb2e8f9f7 449 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Setup the active level for channel n */
<> 144:ef7eb2e8f9f7 452 reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Update the mode and edge level for channel n */
<> 144:ef7eb2e8f9f7 455 base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Clear the current mode and edge level bits for channel n + 1 */
<> 144:ef7eb2e8f9f7 458 reg = base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC;
<> 144:ef7eb2e8f9f7 459 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Setup the active level for channel n + 1 */
<> 144:ef7eb2e8f9f7 462 reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Update the mode and edge level for channel n + 1*/
<> 144:ef7eb2e8f9f7 465 base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg;
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Set the combine bit for the channel pair */
<> 144:ef7eb2e8f9f7 468 base->COMBINE |=
<> 144:ef7eb2e8f9f7 469 (1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber)));
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Set the channel pair values */
<> 144:ef7eb2e8f9f7 472 base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge;
<> 144:ef7eb2e8f9f7 473 base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
<> 144:ef7eb2e8f9f7 476 /* Set to output mode */
<> 144:ef7eb2e8f9f7 477 FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2), true);
<> 144:ef7eb2e8f9f7 478 FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2 + 1), true);
<> 144:ef7eb2e8f9f7 479 #endif
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481 chnlParams++;
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 return kStatus_Success;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 void FTM_UpdatePwmDutycycle(FTM_Type *base,
<> 144:ef7eb2e8f9f7 488 ftm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 489 ftm_pwm_mode_t currentPwmMode,
<> 144:ef7eb2e8f9f7 490 uint8_t dutyCyclePercent)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 uint16_t cnv, cnvFirstEdge = 0, mod;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 mod = base->MOD;
<> 144:ef7eb2e8f9f7 495 if ((currentPwmMode == kFTM_EdgeAlignedPwm) || (currentPwmMode == kFTM_CenterAlignedPwm))
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 cnv = (mod * dutyCyclePercent) / 100;
<> 144:ef7eb2e8f9f7 498 /* For 100% duty cycle */
<> 144:ef7eb2e8f9f7 499 if (cnv >= mod)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 cnv = mod + 1;
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503 base->CONTROLS[chnlNumber].CnV = cnv;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 else
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 /* This check is added for combined mode as the channel number should be the pair number */
<> 144:ef7eb2e8f9f7 508 if (chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2))
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 return;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 cnv = (mod * dutyCyclePercent) / 100;
<> 144:ef7eb2e8f9f7 514 cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV;
<> 144:ef7eb2e8f9f7 515 /* For 100% duty cycle */
<> 144:ef7eb2e8f9f7 516 if (cnv >= mod)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 cnv = mod + 1;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520 base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 uint32_t reg = base->CONTROLS[chnlNumber].CnSC;
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Clear the field and write the new level value */
<> 144:ef7eb2e8f9f7 529 reg &= ~(FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 530 reg |= ((uint32_t)level << FTM_CnSC_ELSA_SHIFT) & (FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 base->CONTROLS[chnlNumber].CnSC = reg;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 void FTM_SetupInputCapture(FTM_Type *base,
<> 144:ef7eb2e8f9f7 536 ftm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 537 ftm_input_capture_edge_t captureMode,
<> 144:ef7eb2e8f9f7 538 uint32_t filterValue)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 uint32_t reg;
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Clear the combine bit for the channel pair */
<> 144:ef7eb2e8f9f7 543 base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
<> 144:ef7eb2e8f9f7 544 /* Clear the dual edge capture mode because it's it's higher priority */
<> 144:ef7eb2e8f9f7 545 base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
<> 144:ef7eb2e8f9f7 546 /* Clear the quadrature decoder mode beacause it's higher priority */
<> 144:ef7eb2e8f9f7 547 base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 reg = base->CONTROLS[chnlNumber].CnSC;
<> 144:ef7eb2e8f9f7 550 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 551 reg |= captureMode;
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Set the requested input capture mode */
<> 144:ef7eb2e8f9f7 554 base->CONTROLS[chnlNumber].CnSC = reg;
<> 144:ef7eb2e8f9f7 555 /* Input filter available only for channels 0, 1, 2, 3 */
<> 144:ef7eb2e8f9f7 556 if (chnlNumber < kFTM_Chnl_4)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 reg = base->FILTER;
<> 144:ef7eb2e8f9f7 559 reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber));
<> 144:ef7eb2e8f9f7 560 reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber));
<> 144:ef7eb2e8f9f7 561 base->FILTER = reg;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
<> 144:ef7eb2e8f9f7 564 /* Set to input mode */
<> 144:ef7eb2e8f9f7 565 FTM_SetPwmOutputEnable(base, chnlNumber, false);
<> 144:ef7eb2e8f9f7 566 #endif
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 void FTM_SetupOutputCompare(FTM_Type *base,
<> 144:ef7eb2e8f9f7 570 ftm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 571 ftm_output_compare_mode_t compareMode,
<> 144:ef7eb2e8f9f7 572 uint32_t compareValue)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 uint32_t reg;
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /* Clear the combine bit for the channel pair */
<> 144:ef7eb2e8f9f7 577 base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
<> 144:ef7eb2e8f9f7 578 /* Clear the dual edge capture mode because it's it's higher priority */
<> 144:ef7eb2e8f9f7 579 base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
<> 144:ef7eb2e8f9f7 580 /* Clear the quadrature decoder mode beacause it's higher priority */
<> 144:ef7eb2e8f9f7 581 base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 reg = base->CONTROLS[chnlNumber].CnSC;
<> 144:ef7eb2e8f9f7 584 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 585 reg |= compareMode;
<> 144:ef7eb2e8f9f7 586 /* Setup the channel output behaviour when a match occurs with the compare value */
<> 144:ef7eb2e8f9f7 587 base->CONTROLS[chnlNumber].CnSC = reg;
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Set output on match to the requested level */
<> 144:ef7eb2e8f9f7 590 base->CONTROLS[chnlNumber].CnV = compareValue;
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
<> 144:ef7eb2e8f9f7 593 /* Set to output mode */
<> 144:ef7eb2e8f9f7 594 FTM_SetPwmOutputEnable(base, chnlNumber, true);
<> 144:ef7eb2e8f9f7 595 #endif
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 void FTM_SetupDualEdgeCapture(FTM_Type *base,
<> 144:ef7eb2e8f9f7 599 ftm_chnl_t chnlPairNumber,
<> 144:ef7eb2e8f9f7 600 const ftm_dual_edge_capture_param_t *edgeParam,
<> 144:ef7eb2e8f9f7 601 uint32_t filterValue)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 assert(edgeParam);
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 uint32_t reg;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 reg = base->COMBINE;
<> 144:ef7eb2e8f9f7 608 /* Clear the combine bit for the channel pair */
<> 144:ef7eb2e8f9f7 609 reg &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 610 /* Enable the DECAPEN bit */
<> 144:ef7eb2e8f9f7 611 reg |= (1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 612 reg |= (1U << (FTM_COMBINE_DECAP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber)));
<> 144:ef7eb2e8f9f7 613 base->COMBINE = reg;
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Setup the edge detection from channel n and n + 1 */
<> 144:ef7eb2e8f9f7 616 reg = base->CONTROLS[chnlPairNumber * 2].CnSC;
<> 144:ef7eb2e8f9f7 617 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 618 reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->currChanEdgeMode);
<> 144:ef7eb2e8f9f7 619 base->CONTROLS[chnlPairNumber * 2].CnSC = reg;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 reg = base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC;
<> 144:ef7eb2e8f9f7 622 reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
<> 144:ef7eb2e8f9f7 623 reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->nextChanEdgeMode);
<> 144:ef7eb2e8f9f7 624 base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC = reg;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Input filter available only for channels 0, 1, 2, 3 */
<> 144:ef7eb2e8f9f7 627 if (chnlPairNumber < kFTM_Chnl_4)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 reg = base->FILTER;
<> 144:ef7eb2e8f9f7 630 reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber));
<> 144:ef7eb2e8f9f7 631 reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber));
<> 144:ef7eb2e8f9f7 632 base->FILTER = reg;
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
<> 144:ef7eb2e8f9f7 636 /* Set to input mode */
<> 144:ef7eb2e8f9f7 637 FTM_SetPwmOutputEnable(base, chnlPairNumber, false);
<> 144:ef7eb2e8f9f7 638 #endif
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 void FTM_SetupQuadDecode(FTM_Type *base,
<> 144:ef7eb2e8f9f7 642 const ftm_phase_params_t *phaseAParams,
<> 144:ef7eb2e8f9f7 643 const ftm_phase_params_t *phaseBParams,
<> 144:ef7eb2e8f9f7 644 ftm_quad_decode_mode_t quadMode)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 assert(phaseAParams);
<> 144:ef7eb2e8f9f7 647 assert(phaseBParams);
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 uint32_t reg;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Set Phase A filter value if phase filter is enabled */
<> 144:ef7eb2e8f9f7 652 if (phaseAParams->enablePhaseFilter)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 reg = base->FILTER;
<> 144:ef7eb2e8f9f7 655 reg &= ~(FTM_FILTER_CH0FVAL_MASK);
<> 144:ef7eb2e8f9f7 656 reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal);
<> 144:ef7eb2e8f9f7 657 base->FILTER = reg;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Set Phase B filter value if phase filter is enabled */
<> 144:ef7eb2e8f9f7 661 if (phaseBParams->enablePhaseFilter)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 reg = base->FILTER;
<> 144:ef7eb2e8f9f7 664 reg &= ~(FTM_FILTER_CH1FVAL_MASK);
<> 144:ef7eb2e8f9f7 665 reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal);
<> 144:ef7eb2e8f9f7 666 base->FILTER = reg;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Set Quadrature decode properties */
<> 144:ef7eb2e8f9f7 670 reg = base->QDCTRL;
<> 144:ef7eb2e8f9f7 671 reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK |
<> 144:ef7eb2e8f9f7 672 FTM_QDCTRL_PHBPOL_MASK);
<> 144:ef7eb2e8f9f7 673 reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) |
<> 144:ef7eb2e8f9f7 674 FTM_QDCTRL_PHBFLTREN(phaseBParams->enablePhaseFilter) | FTM_QDCTRL_PHAPOL(phaseAParams->phasePolarity) |
<> 144:ef7eb2e8f9f7 675 FTM_QDCTRL_PHBPOL(phaseBParams->phasePolarity));
<> 144:ef7eb2e8f9f7 676 base->QDCTRL = reg;
<> 144:ef7eb2e8f9f7 677 /* Enable Quad decode */
<> 144:ef7eb2e8f9f7 678 base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK;
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 assert(faultParams);
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 uint32_t reg;
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 reg = base->FLTCTRL;
<> 144:ef7eb2e8f9f7 688 if (faultParams->enableFaultInput)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 /* Enable the fault input */
<> 144:ef7eb2e8f9f7 691 reg |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber);
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 else
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Disable the fault input */
<> 144:ef7eb2e8f9f7 696 reg &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber);
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 if (faultParams->useFaultFilter)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 /* Enable the fault filter */
<> 144:ef7eb2e8f9f7 702 reg |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber));
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704 else
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 /* Disable the fault filter */
<> 144:ef7eb2e8f9f7 707 reg &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber));
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 base->FLTCTRL = reg;
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 if (faultParams->faultLevel)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Active low polarity for the fault input pin */
<> 144:ef7eb2e8f9f7 714 base->FLTPOL |= (1U << faultNumber);
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716 else
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 /* Active high polarity for the fault input pin */
<> 144:ef7eb2e8f9f7 719 base->FLTPOL &= ~(1U << faultNumber);
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 uint32_t chnlInts = (mask & 0xFFU);
<> 144:ef7eb2e8f9f7 726 uint8_t chnlNumber = 0;
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /* Enable the timer overflow interrupt */
<> 144:ef7eb2e8f9f7 729 if (mask & kFTM_TimeOverflowInterruptEnable)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 base->SC |= FTM_SC_TOIE_MASK;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Enable the fault interrupt */
<> 144:ef7eb2e8f9f7 735 if (mask & kFTM_FaultInterruptEnable)
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 base->MODE |= FTM_MODE_FAULTIE_MASK;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT)
<> 144:ef7eb2e8f9f7 741 /* Enable the reload interrupt available only on certain SoC's */
<> 144:ef7eb2e8f9f7 742 if (mask & kFTM_ReloadInterruptEnable)
<> 144:ef7eb2e8f9f7 743 {
<> 144:ef7eb2e8f9f7 744 base->SC |= FTM_SC_RIE_MASK;
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746 #endif
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Enable the channel interrupts */
<> 144:ef7eb2e8f9f7 749 while (chnlInts)
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 if (chnlInts & 0x1)
<> 144:ef7eb2e8f9f7 752 {
<> 144:ef7eb2e8f9f7 753 base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_CHIE_MASK;
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 chnlNumber++;
<> 144:ef7eb2e8f9f7 756 chnlInts = chnlInts >> 1U;
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 761 {
<> 144:ef7eb2e8f9f7 762 uint32_t chnlInts = (mask & 0xFF);
<> 144:ef7eb2e8f9f7 763 uint8_t chnlNumber = 0;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Disable the timer overflow interrupt */
<> 144:ef7eb2e8f9f7 766 if (mask & kFTM_TimeOverflowInterruptEnable)
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 base->SC &= ~FTM_SC_TOIE_MASK;
<> 144:ef7eb2e8f9f7 769 }
<> 144:ef7eb2e8f9f7 770 /* Disable the fault interrupt */
<> 144:ef7eb2e8f9f7 771 if (mask & kFTM_FaultInterruptEnable)
<> 144:ef7eb2e8f9f7 772 {
<> 144:ef7eb2e8f9f7 773 base->MODE &= ~FTM_MODE_FAULTIE_MASK;
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT)
<> 144:ef7eb2e8f9f7 777 /* Disable the reload interrupt available only on certain SoC's */
<> 144:ef7eb2e8f9f7 778 if (mask & kFTM_ReloadInterruptEnable)
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 base->SC &= ~FTM_SC_RIE_MASK;
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782 #endif
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Disable the channel interrupts */
<> 144:ef7eb2e8f9f7 785 while (chnlInts)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 if (chnlInts & 0x1)
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_CHIE_MASK;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 chnlNumber++;
<> 144:ef7eb2e8f9f7 792 chnlInts = chnlInts >> 1U;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 uint32_t FTM_GetEnabledInterrupts(FTM_Type *base)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 uint32_t enabledInterrupts = 0;
<> 144:ef7eb2e8f9f7 799 int8_t chnlCount = FSL_FEATURE_FTM_CHANNEL_COUNTn(base);
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* The CHANNEL_COUNT macro returns -1 if it cannot match the FTM instance */
<> 144:ef7eb2e8f9f7 802 assert(chnlCount != -1);
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Check if timer overflow interrupt is enabled */
<> 144:ef7eb2e8f9f7 805 if (base->SC & FTM_SC_TOIE_MASK)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 enabledInterrupts |= kFTM_TimeOverflowInterruptEnable;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809 /* Check if fault interrupt is enabled */
<> 144:ef7eb2e8f9f7 810 if (base->MODE & FTM_MODE_FAULTIE_MASK)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 enabledInterrupts |= kFTM_FaultInterruptEnable;
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT)
<> 144:ef7eb2e8f9f7 816 /* Check if the reload interrupt is enabled */
<> 144:ef7eb2e8f9f7 817 if (base->SC & FTM_SC_RIE_MASK)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 enabledInterrupts |= kFTM_ReloadInterruptEnable;
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821 #endif
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Check if the channel interrupts are enabled */
<> 144:ef7eb2e8f9f7 824 while (chnlCount > 0)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 chnlCount--;
<> 144:ef7eb2e8f9f7 827 if (base->CONTROLS[chnlCount].CnSC & FTM_CnSC_CHIE_MASK)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 enabledInterrupts |= (1U << chnlCount);
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 return enabledInterrupts;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 uint32_t FTM_GetStatusFlags(FTM_Type *base)
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 uint32_t statusFlags = 0;
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Check the timer flag */
<> 144:ef7eb2e8f9f7 841 if (base->SC & FTM_SC_TOF_MASK)
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 statusFlags |= kFTM_TimeOverflowFlag;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845 /* Check fault flag */
<> 144:ef7eb2e8f9f7 846 if (base->FMS & FTM_FMS_FAULTF_MASK)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 statusFlags |= kFTM_FaultFlag;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 /* Check channel trigger flag */
<> 144:ef7eb2e8f9f7 851 if (base->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK)
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 statusFlags |= kFTM_ChnlTriggerFlag;
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT)
<> 144:ef7eb2e8f9f7 856 /* Check reload flag */
<> 144:ef7eb2e8f9f7 857 if (base->SC & FTM_SC_RF_MASK)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 statusFlags |= kFTM_ReloadFlag;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861 #endif
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* Lower 8 bits contain the channel status flags */
<> 144:ef7eb2e8f9f7 864 statusFlags |= (base->STATUS & 0xFFU);
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 return statusFlags;
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 870 {
<> 144:ef7eb2e8f9f7 871 /* Clear the timer overflow flag by writing a 0 to the bit while it is set */
<> 144:ef7eb2e8f9f7 872 if (mask & kFTM_TimeOverflowFlag)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 base->SC &= ~FTM_SC_TOF_MASK;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876 /* Clear fault flag by writing a 0 to the bit while it is set */
<> 144:ef7eb2e8f9f7 877 if (mask & kFTM_FaultFlag)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 base->FMS &= ~FTM_FMS_FAULTF_MASK;
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881 /* Clear channel trigger flag */
<> 144:ef7eb2e8f9f7 882 if (mask & kFTM_ChnlTriggerFlag)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 base->EXTTRIG &= ~FTM_EXTTRIG_TRIGF_MASK;
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 #if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT)
<> 144:ef7eb2e8f9f7 888 /* Check reload flag by writing a 0 to the bit while it is set */
<> 144:ef7eb2e8f9f7 889 if (mask & kFTM_ReloadFlag)
<> 144:ef7eb2e8f9f7 890 {
<> 144:ef7eb2e8f9f7 891 base->SC &= ~FTM_SC_RF_MASK;
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893 #endif
<> 144:ef7eb2e8f9f7 894 /* Clear the channel status flags by writing a 0 to the bit */
<> 144:ef7eb2e8f9f7 895 base->STATUS &= ~(mask & 0xFFU);
<> 144:ef7eb2e8f9f7 896 }