Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MKL46Z256VLH4
<> 144:ef7eb2e8f9f7 4 ** MKL46Z128VLH4
<> 144:ef7eb2e8f9f7 5 ** MKL46Z256VLL4
<> 144:ef7eb2e8f9f7 6 ** MKL46Z128VLL4
<> 144:ef7eb2e8f9f7 7 ** MKL46Z256VMC4
<> 144:ef7eb2e8f9f7 8 ** MKL46Z128VMC4
<> 144:ef7eb2e8f9f7 9 **
<> 144:ef7eb2e8f9f7 10 ** Compilers: ARM Compiler
<> 144:ef7eb2e8f9f7 11 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 12 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 13 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 14 **
<> 144:ef7eb2e8f9f7 15 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
<> 144:ef7eb2e8f9f7 16 ** Version: rev. 2.0, 2012-12-12
<> 144:ef7eb2e8f9f7 17 **
<> 144:ef7eb2e8f9f7 18 ** Abstract:
<> 144:ef7eb2e8f9f7 19 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 20 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 21 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 22 **
<> 144:ef7eb2e8f9f7 23 ** Copyright: 2012 Freescale, Inc. All Rights Reserved.
<> 144:ef7eb2e8f9f7 24 **
<> 144:ef7eb2e8f9f7 25 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 26 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 27 **
<> 144:ef7eb2e8f9f7 28 ** Revisions:
<> 144:ef7eb2e8f9f7 29 ** - rev. 1.0 (2012-10-16)
<> 144:ef7eb2e8f9f7 30 ** Initial version.
<> 144:ef7eb2e8f9f7 31 ** - rev. 2.0 (2012-12-12)
<> 144:ef7eb2e8f9f7 32 ** Update to reference manual rev. 1.
<> 144:ef7eb2e8f9f7 33 **
<> 144:ef7eb2e8f9f7 34 ** ###################################################################
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /**
<> 144:ef7eb2e8f9f7 38 * @file MKL46Z4
<> 144:ef7eb2e8f9f7 39 * @version 2.0
<> 144:ef7eb2e8f9f7 40 * @date 2012-12-12
<> 144:ef7eb2e8f9f7 41 * @brief Device specific configuration file for MKL46Z4 (implementation file)
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 44 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 45 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #include <stdint.h>
<> 144:ef7eb2e8f9f7 49 #include "MKL46Z4.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #define DISABLE_WDOG 1
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #define CLOCK_SETUP 1
<> 144:ef7eb2e8f9f7 54 /* Predefined clock setups
<> 144:ef7eb2e8f9f7 55 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
<> 144:ef7eb2e8f9f7 56 Reference clock source for MCG module is the slow internal clock source 32.768kHz
<> 144:ef7eb2e8f9f7 57 Core clock = 41.94MHz, BusClock = 13.98MHz
<> 144:ef7eb2e8f9f7 58 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
<> 144:ef7eb2e8f9f7 59 Reference clock source for MCG module is an external crystal 8MHz
<> 144:ef7eb2e8f9f7 60 Core clock = 48MHz, BusClock = 24MHz
<> 144:ef7eb2e8f9f7 61 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
<> 144:ef7eb2e8f9f7 62 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
<> 144:ef7eb2e8f9f7 63 Core clock = 8MHz, BusClock = 8MHz
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 67 Define clock source values
<> 144:ef7eb2e8f9f7 68 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 69 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 71 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 72 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 73 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
<> 144:ef7eb2e8f9f7 74 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 75 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 76 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 77 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 78 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 79 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 80 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 81 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 82 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 83 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 84 #endif /* (CLOCK_SETUP == 2) */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 88 -- Core clock
<> 144:ef7eb2e8f9f7 89 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 94 -- SystemInit()
<> 144:ef7eb2e8f9f7 95 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 98 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 99 /* Disable the WDOG module */
<> 144:ef7eb2e8f9f7 100 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
<> 144:ef7eb2e8f9f7 101 SIM->COPC = (uint32_t)0x00u;
<> 144:ef7eb2e8f9f7 102 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 103 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 104 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 105 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
<> 144:ef7eb2e8f9f7 106 /* Switch to FEI Mode */
<> 144:ef7eb2e8f9f7 107 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 108 MCG->C1 = (uint8_t)0x06U;
<> 144:ef7eb2e8f9f7 109 /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 110 MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
<> 144:ef7eb2e8f9f7 111 /* MCG->C4: DMX32=0,DRST_DRS=1 */
<> 144:ef7eb2e8f9f7 112 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
<> 144:ef7eb2e8f9f7 113 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 114 OSC0->CR = (uint8_t)0x80U;
<> 144:ef7eb2e8f9f7 115 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 116 MCG->C5 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 117 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 118 MCG->C6 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 119 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 124 /* SIM->SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 125 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
<> 144:ef7eb2e8f9f7 126 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 127 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
<> 144:ef7eb2e8f9f7 128 /* PORTA->PCR18: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 129 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 130 /* PORTA->PCR19: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 131 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 132 /* Switch to FBE Mode */
<> 144:ef7eb2e8f9f7 133 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 134 MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
<> 144:ef7eb2e8f9f7 135 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 136 OSC0->CR = (uint8_t)0x80U;
<> 144:ef7eb2e8f9f7 137 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 138 MCG->C1 = (uint8_t)0x9AU;
<> 144:ef7eb2e8f9f7 139 /* MCG->C4: DMX32=0,DRST_DRS=0 */
<> 144:ef7eb2e8f9f7 140 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
<> 144:ef7eb2e8f9f7 141 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
<> 144:ef7eb2e8f9f7 142 MCG->C5 = (uint8_t)0x01U;
<> 144:ef7eb2e8f9f7 143 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 144 MCG->C6 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 145 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149 /* Switch to PBE Mode */
<> 144:ef7eb2e8f9f7 150 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 151 MCG->C6 = (uint8_t)0x40U;
<> 144:ef7eb2e8f9f7 152 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156 /* Switch to PEE Mode */
<> 144:ef7eb2e8f9f7 157 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 158 MCG->C1 = (uint8_t)0x1AU;
<> 144:ef7eb2e8f9f7 159 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 162 /* SIM->SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 163 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
<> 144:ef7eb2e8f9f7 164 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 165 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
<> 144:ef7eb2e8f9f7 166 /* PORTA->PCR18: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 167 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 168 /* PORTA->PCR19: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 169 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 170 /* Switch to FBE Mode */
<> 144:ef7eb2e8f9f7 171 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 172 MCG->C2 = (uint8_t)0x24U;
<> 144:ef7eb2e8f9f7 173 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 174 OSC0->CR = (uint8_t)0x80U;
<> 144:ef7eb2e8f9f7 175 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 176 MCG->C1 = (uint8_t)0x9AU;
<> 144:ef7eb2e8f9f7 177 /* MCG->C4: DMX32=0,DRST_DRS=0 */
<> 144:ef7eb2e8f9f7 178 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
<> 144:ef7eb2e8f9f7 179 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 180 MCG->C5 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 181 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 182 MCG->C6 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 183 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 /* Switch to BLPE Mode */
<> 144:ef7eb2e8f9f7 188 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
<> 144:ef7eb2e8f9f7 189 MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
<> 144:ef7eb2e8f9f7 190 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192 #endif /* (CLOCK_SETUP == 2) */
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 196 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 197 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 200 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 201 uint8_t Divider;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 204 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 205 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 206 /* FLL is selected */
<> 144:ef7eb2e8f9f7 207 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 208 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 209 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 210 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 211 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 212 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
<> 144:ef7eb2e8f9f7 213 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
<> 144:ef7eb2e8f9f7 214 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
<> 144:ef7eb2e8f9f7 215 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 216 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 217 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 218 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 219 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 220 case 0x0u:
<> 144:ef7eb2e8f9f7 221 MCGOUTClock *= 640u;
<> 144:ef7eb2e8f9f7 222 break;
<> 144:ef7eb2e8f9f7 223 case 0x20u:
<> 144:ef7eb2e8f9f7 224 MCGOUTClock *= 1280u;
<> 144:ef7eb2e8f9f7 225 break;
<> 144:ef7eb2e8f9f7 226 case 0x40u:
<> 144:ef7eb2e8f9f7 227 MCGOUTClock *= 1920u;
<> 144:ef7eb2e8f9f7 228 break;
<> 144:ef7eb2e8f9f7 229 case 0x60u:
<> 144:ef7eb2e8f9f7 230 MCGOUTClock *= 2560u;
<> 144:ef7eb2e8f9f7 231 break;
<> 144:ef7eb2e8f9f7 232 case 0x80u:
<> 144:ef7eb2e8f9f7 233 MCGOUTClock *= 732u;
<> 144:ef7eb2e8f9f7 234 break;
<> 144:ef7eb2e8f9f7 235 case 0xA0u:
<> 144:ef7eb2e8f9f7 236 MCGOUTClock *= 1464u;
<> 144:ef7eb2e8f9f7 237 break;
<> 144:ef7eb2e8f9f7 238 case 0xC0u:
<> 144:ef7eb2e8f9f7 239 MCGOUTClock *= 2197u;
<> 144:ef7eb2e8f9f7 240 break;
<> 144:ef7eb2e8f9f7 241 case 0xE0u:
<> 144:ef7eb2e8f9f7 242 MCGOUTClock *= 2929u;
<> 144:ef7eb2e8f9f7 243 break;
<> 144:ef7eb2e8f9f7 244 default:
<> 144:ef7eb2e8f9f7 245 break;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 248 /* PLL is selected */
<> 144:ef7eb2e8f9f7 249 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
<> 144:ef7eb2e8f9f7 250 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 251 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
<> 144:ef7eb2e8f9f7 252 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 253 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 254 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
<> 144:ef7eb2e8f9f7 255 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 256 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 257 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 258 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 259 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 260 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 261 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
<> 144:ef7eb2e8f9f7 262 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 263 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 264 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 265 /* Reserved value */
<> 144:ef7eb2e8f9f7 266 return;
<> 144:ef7eb2e8f9f7 267 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 268 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 269 }