Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processors: MKL46Z256VLH4
bogdanm 0:9b334a45a8ff 4 ** MKL46Z128VLH4
bogdanm 0:9b334a45a8ff 5 ** MKL46Z256VLL4
bogdanm 0:9b334a45a8ff 6 ** MKL46Z128VLL4
bogdanm 0:9b334a45a8ff 7 ** MKL46Z256VMC4
bogdanm 0:9b334a45a8ff 8 ** MKL46Z128VMC4
bogdanm 0:9b334a45a8ff 9 **
bogdanm 0:9b334a45a8ff 10 ** Compilers: ARM Compiler
bogdanm 0:9b334a45a8ff 11 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 12 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 13 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 14 **
bogdanm 0:9b334a45a8ff 15 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
bogdanm 0:9b334a45a8ff 16 ** Version: rev. 2.0, 2012-12-12
bogdanm 0:9b334a45a8ff 17 **
bogdanm 0:9b334a45a8ff 18 ** Abstract:
bogdanm 0:9b334a45a8ff 19 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 20 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 21 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 22 **
bogdanm 0:9b334a45a8ff 23 ** Copyright: 2012 Freescale, Inc. All Rights Reserved.
bogdanm 0:9b334a45a8ff 24 **
bogdanm 0:9b334a45a8ff 25 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 26 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 27 **
bogdanm 0:9b334a45a8ff 28 ** Revisions:
bogdanm 0:9b334a45a8ff 29 ** - rev. 1.0 (2012-10-16)
bogdanm 0:9b334a45a8ff 30 ** Initial version.
bogdanm 0:9b334a45a8ff 31 ** - rev. 2.0 (2012-12-12)
bogdanm 0:9b334a45a8ff 32 ** Update to reference manual rev. 1.
bogdanm 0:9b334a45a8ff 33 **
bogdanm 0:9b334a45a8ff 34 ** ###################################################################
bogdanm 0:9b334a45a8ff 35 */
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 /**
bogdanm 0:9b334a45a8ff 38 * @file MKL46Z4
bogdanm 0:9b334a45a8ff 39 * @version 2.0
bogdanm 0:9b334a45a8ff 40 * @date 2012-12-12
bogdanm 0:9b334a45a8ff 41 * @brief Device specific configuration file for MKL46Z4 (implementation file)
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 44 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 45 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 46 */
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 #include <stdint.h>
bogdanm 0:9b334a45a8ff 49 #include "MKL46Z4.h"
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 #define DISABLE_WDOG 1
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 #define CLOCK_SETUP 1
bogdanm 0:9b334a45a8ff 54 /* Predefined clock setups
bogdanm 0:9b334a45a8ff 55 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
bogdanm 0:9b334a45a8ff 56 Reference clock source for MCG module is the slow internal clock source 32.768kHz
bogdanm 0:9b334a45a8ff 57 Core clock = 41.94MHz, BusClock = 13.98MHz
bogdanm 0:9b334a45a8ff 58 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
bogdanm 0:9b334a45a8ff 59 Reference clock source for MCG module is an external crystal 8MHz
bogdanm 0:9b334a45a8ff 60 Core clock = 48MHz, BusClock = 24MHz
bogdanm 0:9b334a45a8ff 61 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
bogdanm 0:9b334a45a8ff 62 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
bogdanm 0:9b334a45a8ff 63 Core clock = 8MHz, BusClock = 8MHz
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 67 Define clock source values
bogdanm 0:9b334a45a8ff 68 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 69 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 71 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 72 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 73 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
bogdanm 0:9b334a45a8ff 74 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 75 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 76 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 77 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 78 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 79 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 80 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 81 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 82 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 83 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 84 #endif /* (CLOCK_SETUP == 2) */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 88 -- Core clock
bogdanm 0:9b334a45a8ff 89 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 94 -- SystemInit()
bogdanm 0:9b334a45a8ff 95 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 98 #if (DISABLE_WDOG)
bogdanm 0:9b334a45a8ff 99 /* Disable the WDOG module */
bogdanm 0:9b334a45a8ff 100 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
bogdanm 0:9b334a45a8ff 101 SIM->COPC = (uint32_t)0x00u;
bogdanm 0:9b334a45a8ff 102 #endif /* (DISABLE_WDOG) */
bogdanm 0:9b334a45a8ff 103 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 104 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 0:9b334a45a8ff 105 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
bogdanm 0:9b334a45a8ff 106 /* Switch to FEI Mode */
bogdanm 0:9b334a45a8ff 107 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 108 MCG->C1 = (uint8_t)0x06U;
bogdanm 0:9b334a45a8ff 109 /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 110 MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
bogdanm 0:9b334a45a8ff 111 /* MCG->C4: DMX32=0,DRST_DRS=1 */
bogdanm 0:9b334a45a8ff 112 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
bogdanm 0:9b334a45a8ff 113 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 114 OSC0->CR = (uint8_t)0x80U;
bogdanm 0:9b334a45a8ff 115 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 116 MCG->C5 = (uint8_t)0x00U;
bogdanm 0:9b334a45a8ff 117 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 118 MCG->C6 = (uint8_t)0x00U;
bogdanm 0:9b334a45a8ff 119 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
bogdanm 0:9b334a45a8ff 120 }
bogdanm 0:9b334a45a8ff 121 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
bogdanm 0:9b334a45a8ff 122 }
bogdanm 0:9b334a45a8ff 123 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 124 /* SIM->SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 125 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
bogdanm 0:9b334a45a8ff 126 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 0:9b334a45a8ff 127 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
bogdanm 0:9b334a45a8ff 128 /* PORTA->PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 129 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
bogdanm 0:9b334a45a8ff 130 /* PORTA->PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 131 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
bogdanm 0:9b334a45a8ff 132 /* Switch to FBE Mode */
bogdanm 0:9b334a45a8ff 133 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 134 MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
bogdanm 0:9b334a45a8ff 135 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 136 OSC0->CR = (uint8_t)0x80U;
bogdanm 0:9b334a45a8ff 137 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 138 MCG->C1 = (uint8_t)0x9AU;
bogdanm 0:9b334a45a8ff 139 /* MCG->C4: DMX32=0,DRST_DRS=0 */
bogdanm 0:9b334a45a8ff 140 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
bogdanm 0:9b334a45a8ff 141 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
bogdanm 0:9b334a45a8ff 142 MCG->C5 = (uint8_t)0x01U;
bogdanm 0:9b334a45a8ff 143 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 144 MCG->C6 = (uint8_t)0x00U;
bogdanm 0:9b334a45a8ff 145 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
bogdanm 0:9b334a45a8ff 146 }
bogdanm 0:9b334a45a8ff 147 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 148 }
bogdanm 0:9b334a45a8ff 149 /* Switch to PBE Mode */
bogdanm 0:9b334a45a8ff 150 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 151 MCG->C6 = (uint8_t)0x40U;
bogdanm 0:9b334a45a8ff 152 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 153 }
bogdanm 0:9b334a45a8ff 154 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
bogdanm 0:9b334a45a8ff 155 }
bogdanm 0:9b334a45a8ff 156 /* Switch to PEE Mode */
bogdanm 0:9b334a45a8ff 157 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 158 MCG->C1 = (uint8_t)0x1AU;
bogdanm 0:9b334a45a8ff 159 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
bogdanm 0:9b334a45a8ff 160 }
bogdanm 0:9b334a45a8ff 161 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 162 /* SIM->SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 163 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
bogdanm 0:9b334a45a8ff 164 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
bogdanm 0:9b334a45a8ff 165 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
bogdanm 0:9b334a45a8ff 166 /* PORTA->PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 167 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
bogdanm 0:9b334a45a8ff 168 /* PORTA->PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 169 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
bogdanm 0:9b334a45a8ff 170 /* Switch to FBE Mode */
bogdanm 0:9b334a45a8ff 171 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 172 MCG->C2 = (uint8_t)0x24U;
bogdanm 0:9b334a45a8ff 173 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 174 OSC0->CR = (uint8_t)0x80U;
bogdanm 0:9b334a45a8ff 175 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 176 MCG->C1 = (uint8_t)0x9AU;
bogdanm 0:9b334a45a8ff 177 /* MCG->C4: DMX32=0,DRST_DRS=0 */
bogdanm 0:9b334a45a8ff 178 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
bogdanm 0:9b334a45a8ff 179 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 180 MCG->C5 = (uint8_t)0x00U;
bogdanm 0:9b334a45a8ff 181 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 182 MCG->C6 = (uint8_t)0x00U;
bogdanm 0:9b334a45a8ff 183 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
bogdanm 0:9b334a45a8ff 184 }
bogdanm 0:9b334a45a8ff 185 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 186 }
bogdanm 0:9b334a45a8ff 187 /* Switch to BLPE Mode */
bogdanm 0:9b334a45a8ff 188 /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
bogdanm 0:9b334a45a8ff 189 MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
bogdanm 0:9b334a45a8ff 190 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 191 }
bogdanm 0:9b334a45a8ff 192 #endif /* (CLOCK_SETUP == 2) */
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 196 -- SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 197 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 void SystemCoreClockUpdate (void) {
bogdanm 0:9b334a45a8ff 200 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
bogdanm 0:9b334a45a8ff 201 uint8_t Divider;
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 204 /* Output of FLL or PLL is selected */
bogdanm 0:9b334a45a8ff 205 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 206 /* FLL is selected */
bogdanm 0:9b334a45a8ff 207 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 208 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 209 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 210 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 211 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 0:9b334a45a8ff 212 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
bogdanm 0:9b334a45a8ff 213 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
bogdanm 0:9b334a45a8ff 214 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
bogdanm 0:9b334a45a8ff 215 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 216 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 0:9b334a45a8ff 217 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 218 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 219 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 220 case 0x0u:
bogdanm 0:9b334a45a8ff 221 MCGOUTClock *= 640u;
bogdanm 0:9b334a45a8ff 222 break;
bogdanm 0:9b334a45a8ff 223 case 0x20u:
bogdanm 0:9b334a45a8ff 224 MCGOUTClock *= 1280u;
bogdanm 0:9b334a45a8ff 225 break;
bogdanm 0:9b334a45a8ff 226 case 0x40u:
bogdanm 0:9b334a45a8ff 227 MCGOUTClock *= 1920u;
bogdanm 0:9b334a45a8ff 228 break;
bogdanm 0:9b334a45a8ff 229 case 0x60u:
bogdanm 0:9b334a45a8ff 230 MCGOUTClock *= 2560u;
bogdanm 0:9b334a45a8ff 231 break;
bogdanm 0:9b334a45a8ff 232 case 0x80u:
bogdanm 0:9b334a45a8ff 233 MCGOUTClock *= 732u;
bogdanm 0:9b334a45a8ff 234 break;
bogdanm 0:9b334a45a8ff 235 case 0xA0u:
bogdanm 0:9b334a45a8ff 236 MCGOUTClock *= 1464u;
bogdanm 0:9b334a45a8ff 237 break;
bogdanm 0:9b334a45a8ff 238 case 0xC0u:
bogdanm 0:9b334a45a8ff 239 MCGOUTClock *= 2197u;
bogdanm 0:9b334a45a8ff 240 break;
bogdanm 0:9b334a45a8ff 241 case 0xE0u:
bogdanm 0:9b334a45a8ff 242 MCGOUTClock *= 2929u;
bogdanm 0:9b334a45a8ff 243 break;
bogdanm 0:9b334a45a8ff 244 default:
bogdanm 0:9b334a45a8ff 245 break;
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 248 /* PLL is selected */
bogdanm 0:9b334a45a8ff 249 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
bogdanm 0:9b334a45a8ff 250 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
bogdanm 0:9b334a45a8ff 251 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
bogdanm 0:9b334a45a8ff 252 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 253 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 254 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
bogdanm 0:9b334a45a8ff 255 /* Internal reference clock is selected */
bogdanm 0:9b334a45a8ff 256 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
bogdanm 0:9b334a45a8ff 257 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 0:9b334a45a8ff 258 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 259 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
bogdanm 0:9b334a45a8ff 260 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
bogdanm 0:9b334a45a8ff 261 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
bogdanm 0:9b334a45a8ff 262 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 263 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 264 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
bogdanm 0:9b334a45a8ff 265 /* Reserved value */
bogdanm 0:9b334a45a8ff 266 return;
bogdanm 0:9b334a45a8ff 267 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
bogdanm 0:9b334a45a8ff 268 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 269 }