Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
121:7f86b4238bec
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 4 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 5 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 6 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 0:9b334a45a8ff 7 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 8 **
bogdanm 0:9b334a45a8ff 9 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
bogdanm 0:9b334a45a8ff 10 ** Version: rev. 2.5, 2014-05-06
bogdanm 0:9b334a45a8ff 11 ** Build: b140611
bogdanm 0:9b334a45a8ff 12 **
bogdanm 0:9b334a45a8ff 13 ** Abstract:
bogdanm 0:9b334a45a8ff 14 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 15 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 16 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 17 **
bogdanm 0:9b334a45a8ff 18 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 19 ** All rights reserved.
bogdanm 0:9b334a45a8ff 20 **
bogdanm 0:9b334a45a8ff 21 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 22 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 23 **
bogdanm 0:9b334a45a8ff 24 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 25 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 26 **
bogdanm 0:9b334a45a8ff 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 28 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 29 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 30 **
bogdanm 0:9b334a45a8ff 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 32 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 33 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 34 **
bogdanm 0:9b334a45a8ff 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 45 **
bogdanm 0:9b334a45a8ff 46 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 47 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 48 **
bogdanm 0:9b334a45a8ff 49 ** Revisions:
bogdanm 0:9b334a45a8ff 50 ** - rev. 1.0 (2013-07-23)
bogdanm 0:9b334a45a8ff 51 ** Initial version.
bogdanm 0:9b334a45a8ff 52 ** - rev. 1.1 (2013-09-17)
bogdanm 0:9b334a45a8ff 53 ** RM rev. 0.4 update.
bogdanm 0:9b334a45a8ff 54 ** - rev. 2.0 (2013-10-29)
bogdanm 0:9b334a45a8ff 55 ** Register accessor macros added to the memory map.
bogdanm 0:9b334a45a8ff 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
bogdanm 0:9b334a45a8ff 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
bogdanm 0:9b334a45a8ff 58 ** System initialization updated.
bogdanm 0:9b334a45a8ff 59 ** - rev. 2.1 (2013-10-30)
bogdanm 0:9b334a45a8ff 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
bogdanm 0:9b334a45a8ff 61 ** - rev. 2.2 (2013-12-20)
bogdanm 0:9b334a45a8ff 62 ** Update according to reference manual rev. 0.6,
bogdanm 0:9b334a45a8ff 63 ** - rev. 2.3 (2014-01-13)
bogdanm 0:9b334a45a8ff 64 ** Update according to reference manual rev. 0.61,
bogdanm 0:9b334a45a8ff 65 ** - rev. 2.4 (2014-02-10)
bogdanm 0:9b334a45a8ff 66 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
bogdanm 0:9b334a45a8ff 67 ** - rev. 2.5 (2014-05-06)
bogdanm 0:9b334a45a8ff 68 ** Update according to reference manual rev. 1.0,
bogdanm 0:9b334a45a8ff 69 ** Update of system and startup files.
bogdanm 0:9b334a45a8ff 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
bogdanm 0:9b334a45a8ff 71 **
bogdanm 0:9b334a45a8ff 72 ** ###################################################################
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 /*!
bogdanm 0:9b334a45a8ff 76 * @file MK22F51212
bogdanm 0:9b334a45a8ff 77 * @version 2.5
bogdanm 0:9b334a45a8ff 78 * @date 2014-05-06
bogdanm 0:9b334a45a8ff 79 * @brief Device specific configuration file for MK22F51212 (implementation file)
bogdanm 0:9b334a45a8ff 80 *
bogdanm 0:9b334a45a8ff 81 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 82 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 83 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #include <stdint.h>
bogdanm 0:9b334a45a8ff 87 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 92 -- Core clock
bogdanm 0:9b334a45a8ff 93 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 98 -- SystemInit()
bogdanm 0:9b334a45a8ff 99 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 102 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
bogdanm 0:9b334a45a8ff 103 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
bogdanm 0:9b334a45a8ff 104 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 #if (DISABLE_WDOG)
bogdanm 0:9b334a45a8ff 107 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
bogdanm 0:9b334a45a8ff 108 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
bogdanm 0:9b334a45a8ff 109 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
bogdanm 0:9b334a45a8ff 110 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
bogdanm 0:9b334a45a8ff 111 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
bogdanm 0:9b334a45a8ff 112 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
bogdanm 0:9b334a45a8ff 113 WDOG_STCTRLH_WAITEN_MASK |
bogdanm 0:9b334a45a8ff 114 WDOG_STCTRLH_STOPEN_MASK |
bogdanm 0:9b334a45a8ff 115 WDOG_STCTRLH_ALLOWUPDATE_MASK |
bogdanm 0:9b334a45a8ff 116 WDOG_STCTRLH_CLKSRC_MASK |
bogdanm 0:9b334a45a8ff 117 0x0100U;
bogdanm 0:9b334a45a8ff 118 #endif /* (DISABLE_WDOG) */
bogdanm 0:9b334a45a8ff 119 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
bogdanm 0:9b334a45a8ff 120 {
bogdanm 0:9b334a45a8ff 121 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
bogdanm 0:9b334a45a8ff 122 {
bogdanm 0:9b334a45a8ff 123 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
bogdanm 0:9b334a45a8ff 124 }
bogdanm 0:9b334a45a8ff 125 } else {
bogdanm 0:9b334a45a8ff 126 #ifdef SYSTEM_RTC_CR_VALUE
bogdanm 0:9b334a45a8ff 127 SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
bogdanm 0:9b334a45a8ff 128 if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
bogdanm 0:9b334a45a8ff 129 RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
bogdanm 0:9b334a45a8ff 130 RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
bogdanm 0:9b334a45a8ff 131 RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
bogdanm 0:9b334a45a8ff 132 }
bogdanm 0:9b334a45a8ff 133 #endif
bogdanm 0:9b334a45a8ff 134 }
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /* Power mode protection initialization */
bogdanm 0:9b334a45a8ff 137 #ifdef SYSTEM_SMC_PMPROT_VALUE
bogdanm 0:9b334a45a8ff 138 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
bogdanm 0:9b334a45a8ff 139 #endif
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* High speed run mode enable */
bogdanm 0:9b334a45a8ff 142 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
bogdanm 0:9b334a45a8ff 143 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
bogdanm 0:9b334a45a8ff 144 while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146 #endif
bogdanm 0:9b334a45a8ff 147 /* System clock initialization */
bogdanm 0:9b334a45a8ff 148 /* Internal reference clock trim initialization */
bogdanm 0:9b334a45a8ff 149 #if defined(SLOW_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 150 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
bogdanm 0:9b334a45a8ff 151 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
bogdanm 0:9b334a45a8ff 152 #endif /* defined(SLOW_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 153 #if defined(SLOW_FINE_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 154 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
bogdanm 0:9b334a45a8ff 155 #endif
bogdanm 0:9b334a45a8ff 156 #if defined(FAST_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 157 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
bogdanm 0:9b334a45a8ff 158 #endif
bogdanm 0:9b334a45a8ff 159 #if defined(FAST_FINE_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 160 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
bogdanm 0:9b334a45a8ff 161 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 162 #if defined(SLOW_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 163 }
bogdanm 0:9b334a45a8ff 164 #endif /* defined(SLOW_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /* Set system prescalers and clock sources */
bogdanm 0:9b334a45a8ff 167 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
bogdanm 0:9b334a45a8ff 168 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
bogdanm 0:9b334a45a8ff 169 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
bogdanm 0:9b334a45a8ff 170 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
bogdanm 0:9b334a45a8ff 171 /* Set MCG and OSC */
bogdanm 0:9b334a45a8ff 172 #if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
bogdanm 0:9b334a45a8ff 173 /* SIM_SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 174 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 0:9b334a45a8ff 175 /* PORTA_PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 176 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 177 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 178 /* PORTA_PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 179 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 180 }
bogdanm 0:9b334a45a8ff 181 #endif
bogdanm 0:9b334a45a8ff 182 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
bogdanm 0:9b334a45a8ff 183 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
bogdanm 0:9b334a45a8ff 184 /* Check that the source of the FLL reference clock is the requested one. */
bogdanm 0:9b334a45a8ff 185 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 186 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 187 }
bogdanm 0:9b334a45a8ff 188 } else {
bogdanm 0:9b334a45a8ff 189 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191 }
bogdanm 0:9b334a45a8ff 192 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
bogdanm 0:9b334a45a8ff 193 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
bogdanm 0:9b334a45a8ff 194 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
bogdanm 0:9b334a45a8ff 195 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
bogdanm 0:9b334a45a8ff 196 #if (MCG_MODE == MCG_MODE_BLPI)
bogdanm 0:9b334a45a8ff 197 /* BLPI specific */
bogdanm 0:9b334a45a8ff 198 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
bogdanm 0:9b334a45a8ff 199 #endif
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 #else /* MCG_MODE */
bogdanm 0:9b334a45a8ff 202 /* Set MCG and OSC */
bogdanm 0:9b334a45a8ff 203 #if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
bogdanm 0:9b334a45a8ff 204 /* SIM_SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 205 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 0:9b334a45a8ff 206 /* PORTA_PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 207 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 208 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 209 /* PORTA_PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 210 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 211 }
bogdanm 0:9b334a45a8ff 212 #endif
bogdanm 0:9b334a45a8ff 213 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
bogdanm 0:9b334a45a8ff 214 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
bogdanm 0:9b334a45a8ff 215 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
bogdanm 0:9b334a45a8ff 216 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
bogdanm 0:9b334a45a8ff 217 #if (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 218 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
bogdanm 0:9b334a45a8ff 219 #else
bogdanm 0:9b334a45a8ff 220 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
bogdanm 0:9b334a45a8ff 221 #endif
bogdanm 0:9b334a45a8ff 222 if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
bogdanm 0:9b334a45a8ff 223 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225 }
bogdanm 0:9b334a45a8ff 226 /* Check that the source of the FLL reference clock is the requested one. */
bogdanm 0:9b334a45a8ff 227 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 228 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230 } else {
bogdanm 0:9b334a45a8ff 231 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
bogdanm 0:9b334a45a8ff 235 #endif /* MCG_MODE */
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /* Common for all MCG modes */
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
bogdanm 0:9b334a45a8ff 240 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
bogdanm 0:9b334a45a8ff 241 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
bogdanm 0:9b334a45a8ff 242 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
bogdanm 0:9b334a45a8ff 243 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245 /* BLPE, PEE and PBE MCG mode specific */
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 #if (MCG_MODE == MCG_MODE_BLPE)
bogdanm 0:9b334a45a8ff 248 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
bogdanm 0:9b334a45a8ff 249 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
bogdanm 0:9b334a45a8ff 250 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
bogdanm 0:9b334a45a8ff 251 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
bogdanm 0:9b334a45a8ff 252 }
bogdanm 0:9b334a45a8ff 253 #if (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 254 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
bogdanm 0:9b334a45a8ff 255 #endif
bogdanm 0:9b334a45a8ff 256 #endif
bogdanm 0:9b334a45a8ff 257 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
bogdanm 0:9b334a45a8ff 258 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
bogdanm 0:9b334a45a8ff 261 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
bogdanm 0:9b334a45a8ff 264 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266 #elif (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 267 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269 #endif
bogdanm 0:9b334a45a8ff 270 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
bogdanm 0:9b334a45a8ff 271 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
bogdanm 0:9b334a45a8ff 272 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
bogdanm 0:9b334a45a8ff 273 }
bogdanm 0:9b334a45a8ff 274 #endif
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
bogdanm 0:9b334a45a8ff 277 SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
bogdanm 0:9b334a45a8ff 278 #endif
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /* PLL loss of lock interrupt request initialization */
bogdanm 0:9b334a45a8ff 281 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
bogdanm 0:9b334a45a8ff 282 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284 }
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 287 -- SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 288 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 void SystemCoreClockUpdate (void) {
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
bogdanm 0:9b334a45a8ff 293 uint16_t Divider;
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 296 /* Output of FLL or PLL is selected */
bogdanm 0:9b334a45a8ff 297 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 298 /* FLL is selected */
bogdanm 0:9b334a45a8ff 299 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 300 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 301 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
bogdanm 0:9b334a45a8ff 302 case 0x00U:
bogdanm 0:9b334a45a8ff 303 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 304 break;
bogdanm 0:9b334a45a8ff 305 case 0x01U:
bogdanm 0:9b334a45a8ff 306 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 307 break;
bogdanm 0:9b334a45a8ff 308 case 0x02U:
bogdanm 0:9b334a45a8ff 309 default:
bogdanm 0:9b334a45a8ff 310 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 311 break;
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
bogdanm 0:9b334a45a8ff 314 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
bogdanm 0:9b334a45a8ff 315 case 0x38U:
bogdanm 0:9b334a45a8ff 316 Divider = 1536U;
bogdanm 0:9b334a45a8ff 317 break;
bogdanm 0:9b334a45a8ff 318 case 0x30U:
bogdanm 0:9b334a45a8ff 319 Divider = 1280U;
bogdanm 0:9b334a45a8ff 320 break;
bogdanm 0:9b334a45a8ff 321 default:
bogdanm 0:9b334a45a8ff 322 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 323 break;
bogdanm 0:9b334a45a8ff 324 }
bogdanm 0:9b334a45a8ff 325 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
bogdanm 0:9b334a45a8ff 326 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 327 }
bogdanm 0:9b334a45a8ff 328 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 0:9b334a45a8ff 329 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 330 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 0:9b334a45a8ff 331 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 332 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 333 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 334 case 0x00U:
bogdanm 0:9b334a45a8ff 335 MCGOUTClock *= 640U;
bogdanm 0:9b334a45a8ff 336 break;
bogdanm 0:9b334a45a8ff 337 case 0x20U:
bogdanm 0:9b334a45a8ff 338 MCGOUTClock *= 1280U;
bogdanm 0:9b334a45a8ff 339 break;
bogdanm 0:9b334a45a8ff 340 case 0x40U:
bogdanm 0:9b334a45a8ff 341 MCGOUTClock *= 1920U;
bogdanm 0:9b334a45a8ff 342 break;
bogdanm 0:9b334a45a8ff 343 case 0x60U:
bogdanm 0:9b334a45a8ff 344 MCGOUTClock *= 2560U;
bogdanm 0:9b334a45a8ff 345 break;
bogdanm 0:9b334a45a8ff 346 case 0x80U:
bogdanm 0:9b334a45a8ff 347 MCGOUTClock *= 732U;
bogdanm 0:9b334a45a8ff 348 break;
bogdanm 0:9b334a45a8ff 349 case 0xA0U:
bogdanm 0:9b334a45a8ff 350 MCGOUTClock *= 1464U;
bogdanm 0:9b334a45a8ff 351 break;
bogdanm 0:9b334a45a8ff 352 case 0xC0U:
bogdanm 0:9b334a45a8ff 353 MCGOUTClock *= 2197U;
bogdanm 0:9b334a45a8ff 354 break;
bogdanm 0:9b334a45a8ff 355 case 0xE0U:
bogdanm 0:9b334a45a8ff 356 MCGOUTClock *= 2929U;
bogdanm 0:9b334a45a8ff 357 break;
bogdanm 0:9b334a45a8ff 358 default:
bogdanm 0:9b334a45a8ff 359 break;
bogdanm 0:9b334a45a8ff 360 }
bogdanm 0:9b334a45a8ff 361 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 362 /* PLL is selected */
bogdanm 0:9b334a45a8ff 363 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
bogdanm 0:9b334a45a8ff 364 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
bogdanm 0:9b334a45a8ff 365 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
bogdanm 0:9b334a45a8ff 366 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 367 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 368 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
bogdanm 0:9b334a45a8ff 369 /* Internal reference clock is selected */
bogdanm 0:9b334a45a8ff 370 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 371 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 0:9b334a45a8ff 372 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 373 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 374 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
bogdanm 0:9b334a45a8ff 375 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 376 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
bogdanm 0:9b334a45a8ff 377 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 378 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
bogdanm 0:9b334a45a8ff 379 case 0x00U:
bogdanm 0:9b334a45a8ff 380 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 381 break;
bogdanm 0:9b334a45a8ff 382 case 0x01U:
bogdanm 0:9b334a45a8ff 383 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 384 break;
bogdanm 0:9b334a45a8ff 385 case 0x02U:
bogdanm 0:9b334a45a8ff 386 default:
bogdanm 0:9b334a45a8ff 387 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 388 break;
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 391 /* Reserved value */
bogdanm 0:9b334a45a8ff 392 return;
bogdanm 0:9b334a45a8ff 393 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 394 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 395 }