Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c@121:7f86b4238bec, 2016-05-03 (annotated)

Committer:
mbed_official
Date:
Tue May 03 00:15:16 2016 +0100
Revision:
121:7f86b4238bec
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 9cef243de23875778f461bbe9a8c1bc47e65212b



Full URL: https://github.com/mbedmicro/mbed/commit/9cef243de23875778f461bbe9a8c1bc47e65212b/



Switch to KSDK 2.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
mbed_official 121:7f86b4238bec 3 ** Processors: MK22FN512CAP12
mbed_official 121:7f86b4238bec 4 ** MK22FN512VDC12
mbed_official 121:7f86b4238bec 5 ** MK22FN512VLH12
mbed_official 121:7f86b4238bec 6 ** MK22FN512VLL12
mbed_official 121:7f86b4238bec 7 ** MK22FN512VMP12
mbed_official 121:7f86b4238bec 8 **
bogdanm 0:9b334a45a8ff 9 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 10 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 11 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 12 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 13 **
bogdanm 0:9b334a45a8ff 14 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 121:7f86b4238bec 15 ** Version: rev. 2.8, 2015-02-19
mbed_official 121:7f86b4238bec 16 ** Build: b151217
bogdanm 0:9b334a45a8ff 17 **
bogdanm 0:9b334a45a8ff 18 ** Abstract:
bogdanm 0:9b334a45a8ff 19 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 20 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 21 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 22 **
mbed_official 121:7f86b4238bec 23 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 24 ** All rights reserved.
bogdanm 0:9b334a45a8ff 25 **
bogdanm 0:9b334a45a8ff 26 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 27 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 28 **
bogdanm 0:9b334a45a8ff 29 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 30 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 31 **
bogdanm 0:9b334a45a8ff 32 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 33 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 34 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 35 **
bogdanm 0:9b334a45a8ff 36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 37 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 38 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 39 **
bogdanm 0:9b334a45a8ff 40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 50 **
bogdanm 0:9b334a45a8ff 51 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 52 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 53 **
bogdanm 0:9b334a45a8ff 54 ** Revisions:
bogdanm 0:9b334a45a8ff 55 ** - rev. 1.0 (2013-07-23)
bogdanm 0:9b334a45a8ff 56 ** Initial version.
bogdanm 0:9b334a45a8ff 57 ** - rev. 1.1 (2013-09-17)
bogdanm 0:9b334a45a8ff 58 ** RM rev. 0.4 update.
bogdanm 0:9b334a45a8ff 59 ** - rev. 2.0 (2013-10-29)
bogdanm 0:9b334a45a8ff 60 ** Register accessor macros added to the memory map.
bogdanm 0:9b334a45a8ff 61 ** Symbols for Processor Expert memory map compatibility added to the memory map.
bogdanm 0:9b334a45a8ff 62 ** Startup file for gcc has been updated according to CMSIS 3.2.
bogdanm 0:9b334a45a8ff 63 ** System initialization updated.
bogdanm 0:9b334a45a8ff 64 ** - rev. 2.1 (2013-10-30)
bogdanm 0:9b334a45a8ff 65 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
bogdanm 0:9b334a45a8ff 66 ** - rev. 2.2 (2013-12-20)
bogdanm 0:9b334a45a8ff 67 ** Update according to reference manual rev. 0.6,
bogdanm 0:9b334a45a8ff 68 ** - rev. 2.3 (2014-01-13)
bogdanm 0:9b334a45a8ff 69 ** Update according to reference manual rev. 0.61,
bogdanm 0:9b334a45a8ff 70 ** - rev. 2.4 (2014-02-10)
bogdanm 0:9b334a45a8ff 71 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
bogdanm 0:9b334a45a8ff 72 ** - rev. 2.5 (2014-05-06)
bogdanm 0:9b334a45a8ff 73 ** Update according to reference manual rev. 1.0,
bogdanm 0:9b334a45a8ff 74 ** Update of system and startup files.
bogdanm 0:9b334a45a8ff 75 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 121:7f86b4238bec 76 ** - rev. 2.6 (2014-08-28)
mbed_official 121:7f86b4238bec 77 ** Update of system files - default clock configuration changed.
mbed_official 121:7f86b4238bec 78 ** Update of startup files - possibility to override DefaultISR added.
mbed_official 121:7f86b4238bec 79 ** - rev. 2.7 (2014-10-14)
mbed_official 121:7f86b4238bec 80 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
mbed_official 121:7f86b4238bec 81 ** - rev. 2.8 (2015-02-19)
mbed_official 121:7f86b4238bec 82 ** Renamed interrupt vector LLW to LLWU.
bogdanm 0:9b334a45a8ff 83 **
bogdanm 0:9b334a45a8ff 84 ** ###################################################################
bogdanm 0:9b334a45a8ff 85 */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /*!
bogdanm 0:9b334a45a8ff 88 * @file MK22F51212
mbed_official 121:7f86b4238bec 89 * @version 2.8
mbed_official 121:7f86b4238bec 90 * @date 2015-02-19
bogdanm 0:9b334a45a8ff 91 * @brief Device specific configuration file for MK22F51212 (implementation file)
bogdanm 0:9b334a45a8ff 92 *
bogdanm 0:9b334a45a8ff 93 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 94 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 95 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 #include <stdint.h>
mbed_official 121:7f86b4238bec 99 #include "fsl_device_registers.h"
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 104 -- Core clock
bogdanm 0:9b334a45a8ff 105 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 110 -- SystemInit()
bogdanm 0:9b334a45a8ff 111 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 114 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
bogdanm 0:9b334a45a8ff 115 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
bogdanm 0:9b334a45a8ff 116 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 #if (DISABLE_WDOG)
bogdanm 0:9b334a45a8ff 119 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
bogdanm 0:9b334a45a8ff 120 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
bogdanm 0:9b334a45a8ff 121 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
bogdanm 0:9b334a45a8ff 122 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
bogdanm 0:9b334a45a8ff 123 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
bogdanm 0:9b334a45a8ff 124 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
bogdanm 0:9b334a45a8ff 125 WDOG_STCTRLH_WAITEN_MASK |
bogdanm 0:9b334a45a8ff 126 WDOG_STCTRLH_STOPEN_MASK |
bogdanm 0:9b334a45a8ff 127 WDOG_STCTRLH_ALLOWUPDATE_MASK |
bogdanm 0:9b334a45a8ff 128 WDOG_STCTRLH_CLKSRC_MASK |
bogdanm 0:9b334a45a8ff 129 0x0100U;
bogdanm 0:9b334a45a8ff 130 #endif /* (DISABLE_WDOG) */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 }
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 135 -- SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 136 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 void SystemCoreClockUpdate (void) {
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
bogdanm 0:9b334a45a8ff 141 uint16_t Divider;
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 144 /* Output of FLL or PLL is selected */
bogdanm 0:9b334a45a8ff 145 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 146 /* FLL is selected */
bogdanm 0:9b334a45a8ff 147 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 148 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 149 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
bogdanm 0:9b334a45a8ff 150 case 0x00U:
bogdanm 0:9b334a45a8ff 151 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 152 break;
bogdanm 0:9b334a45a8ff 153 case 0x01U:
bogdanm 0:9b334a45a8ff 154 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 155 break;
bogdanm 0:9b334a45a8ff 156 case 0x02U:
bogdanm 0:9b334a45a8ff 157 default:
bogdanm 0:9b334a45a8ff 158 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 159 break;
bogdanm 0:9b334a45a8ff 160 }
bogdanm 0:9b334a45a8ff 161 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
bogdanm 0:9b334a45a8ff 162 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
bogdanm 0:9b334a45a8ff 163 case 0x38U:
bogdanm 0:9b334a45a8ff 164 Divider = 1536U;
bogdanm 0:9b334a45a8ff 165 break;
bogdanm 0:9b334a45a8ff 166 case 0x30U:
bogdanm 0:9b334a45a8ff 167 Divider = 1280U;
bogdanm 0:9b334a45a8ff 168 break;
bogdanm 0:9b334a45a8ff 169 default:
bogdanm 0:9b334a45a8ff 170 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 171 break;
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
bogdanm 0:9b334a45a8ff 174 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 175 }
bogdanm 0:9b334a45a8ff 176 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 0:9b334a45a8ff 177 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 178 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 0:9b334a45a8ff 179 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 180 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 181 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 182 case 0x00U:
bogdanm 0:9b334a45a8ff 183 MCGOUTClock *= 640U;
bogdanm 0:9b334a45a8ff 184 break;
bogdanm 0:9b334a45a8ff 185 case 0x20U:
bogdanm 0:9b334a45a8ff 186 MCGOUTClock *= 1280U;
bogdanm 0:9b334a45a8ff 187 break;
bogdanm 0:9b334a45a8ff 188 case 0x40U:
bogdanm 0:9b334a45a8ff 189 MCGOUTClock *= 1920U;
bogdanm 0:9b334a45a8ff 190 break;
bogdanm 0:9b334a45a8ff 191 case 0x60U:
bogdanm 0:9b334a45a8ff 192 MCGOUTClock *= 2560U;
bogdanm 0:9b334a45a8ff 193 break;
bogdanm 0:9b334a45a8ff 194 case 0x80U:
bogdanm 0:9b334a45a8ff 195 MCGOUTClock *= 732U;
bogdanm 0:9b334a45a8ff 196 break;
bogdanm 0:9b334a45a8ff 197 case 0xA0U:
bogdanm 0:9b334a45a8ff 198 MCGOUTClock *= 1464U;
bogdanm 0:9b334a45a8ff 199 break;
bogdanm 0:9b334a45a8ff 200 case 0xC0U:
bogdanm 0:9b334a45a8ff 201 MCGOUTClock *= 2197U;
bogdanm 0:9b334a45a8ff 202 break;
bogdanm 0:9b334a45a8ff 203 case 0xE0U:
bogdanm 0:9b334a45a8ff 204 MCGOUTClock *= 2929U;
bogdanm 0:9b334a45a8ff 205 break;
bogdanm 0:9b334a45a8ff 206 default:
bogdanm 0:9b334a45a8ff 207 break;
bogdanm 0:9b334a45a8ff 208 }
bogdanm 0:9b334a45a8ff 209 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 210 /* PLL is selected */
bogdanm 0:9b334a45a8ff 211 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
bogdanm 0:9b334a45a8ff 212 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
bogdanm 0:9b334a45a8ff 213 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
bogdanm 0:9b334a45a8ff 214 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 215 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 216 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
bogdanm 0:9b334a45a8ff 217 /* Internal reference clock is selected */
bogdanm 0:9b334a45a8ff 218 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 219 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 0:9b334a45a8ff 220 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 221 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 222 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
bogdanm 0:9b334a45a8ff 223 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 224 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
bogdanm 0:9b334a45a8ff 225 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 226 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
bogdanm 0:9b334a45a8ff 227 case 0x00U:
bogdanm 0:9b334a45a8ff 228 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 229 break;
bogdanm 0:9b334a45a8ff 230 case 0x01U:
bogdanm 0:9b334a45a8ff 231 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 232 break;
bogdanm 0:9b334a45a8ff 233 case 0x02U:
bogdanm 0:9b334a45a8ff 234 default:
bogdanm 0:9b334a45a8ff 235 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 236 break;
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 239 /* Reserved value */
bogdanm 0:9b334a45a8ff 240 return;
bogdanm 0:9b334a45a8ff 241 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 242 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 243 }