Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_uart_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_uart_dma.h"
<> 144:ef7eb2e8f9f7 32 #include "fsl_dmamux.h"
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /*******************************************************************************
<> 144:ef7eb2e8f9f7 35 * Definitions
<> 144:ef7eb2e8f9f7 36 ******************************************************************************/
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Array of UART handle. */
<> 144:ef7eb2e8f9f7 39 #if (defined(UART5))
<> 144:ef7eb2e8f9f7 40 #define UART_HANDLE_ARRAY_SIZE 6
<> 144:ef7eb2e8f9f7 41 #else /* UART5 */
<> 144:ef7eb2e8f9f7 42 #if (defined(UART4))
<> 144:ef7eb2e8f9f7 43 #define UART_HANDLE_ARRAY_SIZE 5
<> 144:ef7eb2e8f9f7 44 #else /* UART4 */
<> 144:ef7eb2e8f9f7 45 #if (defined(UART3))
<> 144:ef7eb2e8f9f7 46 #define UART_HANDLE_ARRAY_SIZE 4
<> 144:ef7eb2e8f9f7 47 #else /* UART3 */
<> 144:ef7eb2e8f9f7 48 #if (defined(UART2))
<> 144:ef7eb2e8f9f7 49 #define UART_HANDLE_ARRAY_SIZE 3
<> 144:ef7eb2e8f9f7 50 #else /* UART2 */
<> 144:ef7eb2e8f9f7 51 #if (defined(UART1))
<> 144:ef7eb2e8f9f7 52 #define UART_HANDLE_ARRAY_SIZE 2
<> 144:ef7eb2e8f9f7 53 #else /* UART1 */
<> 144:ef7eb2e8f9f7 54 #if (defined(UART0))
<> 144:ef7eb2e8f9f7 55 #define UART_HANDLE_ARRAY_SIZE 1
<> 144:ef7eb2e8f9f7 56 #else /* UART0 */
<> 144:ef7eb2e8f9f7 57 #error No UART instance.
<> 144:ef7eb2e8f9f7 58 #endif /* UART 0 */
<> 144:ef7eb2e8f9f7 59 #endif /* UART 1 */
<> 144:ef7eb2e8f9f7 60 #endif /* UART 2 */
<> 144:ef7eb2e8f9f7 61 #endif /* UART 3 */
<> 144:ef7eb2e8f9f7 62 #endif /* UART 4 */
<> 144:ef7eb2e8f9f7 63 #endif /* UART 5 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /*<! Structure definition for uart_dma_handle_t. The structure is private. */
<> 144:ef7eb2e8f9f7 66 typedef struct _uart_dma_private_handle
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 UART_Type *base;
<> 144:ef7eb2e8f9f7 69 uart_dma_handle_t *handle;
<> 144:ef7eb2e8f9f7 70 } uart_dma_private_handle_t;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* UART DMA transfer handle. */
<> 144:ef7eb2e8f9f7 73 enum _uart_dma_tansfer_states
<> 144:ef7eb2e8f9f7 74 {
<> 144:ef7eb2e8f9f7 75 kUART_TxIdle, /* TX idle. */
<> 144:ef7eb2e8f9f7 76 kUART_TxBusy, /* TX busy. */
<> 144:ef7eb2e8f9f7 77 kUART_RxIdle, /* RX idle. */
<> 144:ef7eb2e8f9f7 78 kUART_RxBusy /* RX busy. */
<> 144:ef7eb2e8f9f7 79 };
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /*******************************************************************************
<> 144:ef7eb2e8f9f7 82 * Variables
<> 144:ef7eb2e8f9f7 83 ******************************************************************************/
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*<! Private handle only used for internally. */
<> 144:ef7eb2e8f9f7 86 static uart_dma_private_handle_t s_dmaPrivateHandle[UART_HANDLE_ARRAY_SIZE];
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /*******************************************************************************
<> 144:ef7eb2e8f9f7 89 * Prototypes
<> 144:ef7eb2e8f9f7 90 ******************************************************************************/
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*!
<> 144:ef7eb2e8f9f7 93 * @brief UART DMA send finished callback function.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * This function is called when UART DMA send finished. It disables the UART
<> 144:ef7eb2e8f9f7 96 * TX DMA request and sends @ref kStatus_UART_TxIdle to UART callback.
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * @param handle The DMA handle.
<> 144:ef7eb2e8f9f7 99 * @param param Callback function parameter.
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 static void UART_TransferSendDMACallback(dma_handle_t *handle, void *param);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /*!
<> 144:ef7eb2e8f9f7 104 * @brief UART DMA receive finished callback function.
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * This function is called when UART DMA receive finished. It disables the UART
<> 144:ef7eb2e8f9f7 107 * RX DMA request and sends @ref kStatus_UART_RxIdle to UART callback.
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 * @param handle The DMA handle.
<> 144:ef7eb2e8f9f7 110 * @param param Callback function parameter.
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112 static void UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param);
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /*!
<> 144:ef7eb2e8f9f7 115 * @brief Get the UART instance from peripheral base address.
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 118 * @return UART instance.
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 extern uint32_t UART_GetInstance(UART_Type *base);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /*******************************************************************************
<> 144:ef7eb2e8f9f7 123 * Code
<> 144:ef7eb2e8f9f7 124 ******************************************************************************/
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 static void UART_TransferSendDMACallback(dma_handle_t *handle, void *param)
<> 144:ef7eb2e8f9f7 127 {
<> 144:ef7eb2e8f9f7 128 uart_dma_private_handle_t *uartPrivateHandle = (uart_dma_private_handle_t *)param;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Disable UART TX DMA. */
<> 144:ef7eb2e8f9f7 131 UART_EnableTxDMA(uartPrivateHandle->base, false);
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Disable interrupt. */
<> 144:ef7eb2e8f9f7 134 DMA_DisableInterrupts(handle->base, handle->channel);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 uartPrivateHandle->handle->txState = kUART_TxIdle;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 if (uartPrivateHandle->handle->callback)
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle,
<> 144:ef7eb2e8f9f7 141 uartPrivateHandle->handle->userData);
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 static void UART_TransferReceiveDMACallback(dma_handle_t *handle, void *param)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 uart_dma_private_handle_t *uartPrivateHandle = (uart_dma_private_handle_t *)param;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Disable UART RX DMA. */
<> 144:ef7eb2e8f9f7 150 UART_EnableRxDMA(uartPrivateHandle->base, false);
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /* Disable interrupt. */
<> 144:ef7eb2e8f9f7 153 DMA_DisableInterrupts(handle->base, handle->channel);
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uartPrivateHandle->handle->rxState = kUART_RxIdle;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 if (uartPrivateHandle->handle->callback)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle,
<> 144:ef7eb2e8f9f7 160 uartPrivateHandle->handle->userData);
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 void UART_TransferCreateHandleDMA(UART_Type *base,
<> 144:ef7eb2e8f9f7 165 uart_dma_handle_t *handle,
<> 144:ef7eb2e8f9f7 166 uart_dma_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 167 void *userData,
<> 144:ef7eb2e8f9f7 168 dma_handle_t *txDmaHandle,
<> 144:ef7eb2e8f9f7 169 dma_handle_t *rxDmaHandle)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 assert(handle);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 uint32_t instance = UART_GetInstance(base);
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 memset(handle, 0, sizeof(*handle));
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 s_dmaPrivateHandle[instance].base = base;
<> 144:ef7eb2e8f9f7 178 s_dmaPrivateHandle[instance].handle = handle;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 handle->rxState = kUART_RxIdle;
<> 144:ef7eb2e8f9f7 181 handle->txState = kUART_TxIdle;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 handle->callback = callback;
<> 144:ef7eb2e8f9f7 184 handle->userData = userData;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
<> 144:ef7eb2e8f9f7 187 /* Note:
<> 144:ef7eb2e8f9f7 188 Take care of the RX FIFO, DMA request only assert when received bytes
<> 144:ef7eb2e8f9f7 189 equal or more than RX water mark, there is potential issue if RX water
<> 144:ef7eb2e8f9f7 190 mark larger than 1.
<> 144:ef7eb2e8f9f7 191 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
<> 144:ef7eb2e8f9f7 192 5 bytes are received. the last byte will be saved in FIFO but not trigger
<> 144:ef7eb2e8f9f7 193 DMA transfer because the water mark is 2.
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 if (rxDmaHandle)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 base->RWFIFO = 1U;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199 #endif
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 handle->rxDmaHandle = rxDmaHandle;
<> 144:ef7eb2e8f9f7 202 handle->txDmaHandle = txDmaHandle;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Configure TX. */
<> 144:ef7eb2e8f9f7 205 if (txDmaHandle)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 DMA_SetCallback(txDmaHandle, UART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Configure RX. */
<> 144:ef7eb2e8f9f7 211 if (rxDmaHandle)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 DMA_SetCallback(rxDmaHandle, UART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 status_t UART_TransferSendDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 dma_transfer_config_t xferConfig;
<> 144:ef7eb2e8f9f7 222 status_t status;
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Return error if xfer invalid. */
<> 144:ef7eb2e8f9f7 225 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* If previous TX not finished. */
<> 144:ef7eb2e8f9f7 231 if (kUART_TxBusy == handle->txState)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 status = kStatus_UART_TxBusy;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 else
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 handle->txState = kUART_TxBusy;
<> 144:ef7eb2e8f9f7 238 handle->txDataSizeAll = xfer->dataSize;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Prepare transfer. */
<> 144:ef7eb2e8f9f7 241 DMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base),
<> 144:ef7eb2e8f9f7 242 sizeof(uint8_t), xfer->dataSize, kDMA_MemoryToPeripheral);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Submit transfer. */
<> 144:ef7eb2e8f9f7 245 DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig, kDMA_EnableInterrupt);
<> 144:ef7eb2e8f9f7 246 DMA_StartTransfer(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Enable UART TX DMA. */
<> 144:ef7eb2e8f9f7 249 UART_EnableTxDMA(base, true);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 status = kStatus_Success;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 return status;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 status_t UART_TransferReceiveDMA(UART_Type *base, uart_dma_handle_t *handle, uart_transfer_t *xfer)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 dma_transfer_config_t xferConfig;
<> 144:ef7eb2e8f9f7 262 status_t status;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Return error if xfer invalid. */
<> 144:ef7eb2e8f9f7 265 if ((0U == xfer->dataSize) || (NULL == xfer->data))
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* If previous RX not finished. */
<> 144:ef7eb2e8f9f7 271 if (kUART_RxBusy == handle->rxState)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 status = kStatus_UART_RxBusy;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275 else
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 handle->rxState = kUART_RxBusy;
<> 144:ef7eb2e8f9f7 278 handle->rxDataSizeAll = xfer->dataSize;
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Prepare transfer. */
<> 144:ef7eb2e8f9f7 281 DMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
<> 144:ef7eb2e8f9f7 282 sizeof(uint8_t), xfer->dataSize, kDMA_PeripheralToMemory);
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Submit transfer. */
<> 144:ef7eb2e8f9f7 285 DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig, kDMA_EnableInterrupt);
<> 144:ef7eb2e8f9f7 286 DMA_StartTransfer(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Enable UART RX DMA. */
<> 144:ef7eb2e8f9f7 289 UART_EnableRxDMA(base, true);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 status = kStatus_Success;
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 return status;
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 void UART_TransferAbortSendDMA(UART_Type *base, uart_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Disable UART TX DMA. */
<> 144:ef7eb2e8f9f7 302 UART_EnableTxDMA(base, false);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Stop transfer. */
<> 144:ef7eb2e8f9f7 305 DMA_AbortTransfer(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 144:ef7eb2e8f9f7 308 DMA_ClearChannelStatusFlags(handle->txDmaHandle->base, handle->txDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 handle->txState = kUART_TxIdle;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 void UART_TransferAbortReceiveDMA(UART_Type *base, uart_dma_handle_t *handle)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Disable UART RX DMA. */
<> 144:ef7eb2e8f9f7 318 UART_EnableRxDMA(base, false);
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Stop transfer. */
<> 144:ef7eb2e8f9f7 321 DMA_AbortTransfer(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Write DMA->DSR[DONE] to abort transfer and clear status. */
<> 144:ef7eb2e8f9f7 324 DMA_ClearChannelStatusFlags(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, kDMA_TransactionsDoneFlag);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 handle->rxState = kUART_RxIdle;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 status_t UART_TransferGetSendCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 assert(handle->txDmaHandle);
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 if (kUART_TxIdle == handle->txState)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 return kStatus_NoTransferInProgress;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 if (!count)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 return kStatus_Success;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 status_t UART_TransferGetReceiveCountDMA(UART_Type *base, uart_dma_handle_t *handle, uint32_t *count)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 assert(handle->rxDmaHandle);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 if (kUART_RxIdle == handle->rxState)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 return kStatus_NoTransferInProgress;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 if (!count)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 return kStatus_InvalidArgument;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 return kStatus_Success;
<> 144:ef7eb2e8f9f7 365 }