Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MKL26Z128CAL4
<> 144:ef7eb2e8f9f7 4 ** MKL26Z128VFM4
<> 144:ef7eb2e8f9f7 5 ** MKL26Z64VFM4
<> 144:ef7eb2e8f9f7 6 ** MKL26Z32VM4
<> 144:ef7eb2e8f9f7 7 ** MKL26Z128VFT4
<> 144:ef7eb2e8f9f7 8 ** MKL26Z64VFT4
<> 144:ef7eb2e8f9f7 9 ** MKL26Z32VFT4
<> 144:ef7eb2e8f9f7 10 ** MKL26Z128VLH4
<> 144:ef7eb2e8f9f7 11 ** MKL26Z64VLH4
<> 144:ef7eb2e8f9f7 12 ** MKL26Z32VLH4
<> 144:ef7eb2e8f9f7 13 ** MKL26Z256VLH4
<> 144:ef7eb2e8f9f7 14 ** MKL26Z256VLL4
<> 144:ef7eb2e8f9f7 15 ** MKL26Z128VLL4
<> 144:ef7eb2e8f9f7 16 ** MKL26Z256VMC4
<> 144:ef7eb2e8f9f7 17 ** MKL26Z128VMC4
<> 144:ef7eb2e8f9f7 18 ** MKL26Z256VMP4
<> 144:ef7eb2e8f9f7 19 **
<> 144:ef7eb2e8f9f7 20 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 21 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 22 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 23 ** GNU C Compiler - CodeSourcery Sourcery G++
<> 144:ef7eb2e8f9f7 24 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
<> 144:ef7eb2e8f9f7 27 ** KL26P121M48SF4RM, Rev.2, Dec 2012
<> 144:ef7eb2e8f9f7 28 **
<> 144:ef7eb2e8f9f7 29 ** Version: rev. 1.7, 2015-01-13
<> 144:ef7eb2e8f9f7 30 ** Build: b150129
<> 144:ef7eb2e8f9f7 31 **
<> 144:ef7eb2e8f9f7 32 ** Abstract:
<> 144:ef7eb2e8f9f7 33 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 34 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 35 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 36 **
<> 144:ef7eb2e8f9f7 37 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 38 ** All rights reserved.
<> 144:ef7eb2e8f9f7 39 **
<> 144:ef7eb2e8f9f7 40 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 41 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 42 **
<> 144:ef7eb2e8f9f7 43 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 44 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 45 **
<> 144:ef7eb2e8f9f7 46 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 47 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 48 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 49 **
<> 144:ef7eb2e8f9f7 50 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 51 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 52 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 53 **
<> 144:ef7eb2e8f9f7 54 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 55 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 56 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 57 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 58 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 59 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 60 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 61 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 62 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 63 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 64 **
<> 144:ef7eb2e8f9f7 65 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 66 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 67 **
<> 144:ef7eb2e8f9f7 68 ** Revisions:
<> 144:ef7eb2e8f9f7 69 ** - rev. 1.0 (2012-12-12)
<> 144:ef7eb2e8f9f7 70 ** Initial version.
<> 144:ef7eb2e8f9f7 71 ** - rev. 1.1 (2013-04-05)
<> 144:ef7eb2e8f9f7 72 ** Changed start of doxygen comment.
<> 144:ef7eb2e8f9f7 73 ** - rev. 1.2 (2013-04-12)
<> 144:ef7eb2e8f9f7 74 ** SystemInit function fixed for clock configuration 1.
<> 144:ef7eb2e8f9f7 75 ** Name of the interrupt num. 31 updated to reflect proper function.
<> 144:ef7eb2e8f9f7 76 ** - rev. 1.3 (2014-05-27)
<> 144:ef7eb2e8f9f7 77 ** Updated to Kinetis SDK support standard.
<> 144:ef7eb2e8f9f7 78 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
<> 144:ef7eb2e8f9f7 79 ** - rev. 1.4 (2014-07-25)
<> 144:ef7eb2e8f9f7 80 ** System initialization updated:
<> 144:ef7eb2e8f9f7 81 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
<> 144:ef7eb2e8f9f7 82 ** - VLLSx wake-up recovery added.
<> 144:ef7eb2e8f9f7 83 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
<> 144:ef7eb2e8f9f7 84 ** - rev. 1.5 (2014-08-28)
<> 144:ef7eb2e8f9f7 85 ** Update of system files - default clock configuration changed, fix of OSC initialization.
<> 144:ef7eb2e8f9f7 86 ** Update of startup files - possibility to override DefaultISR added.
<> 144:ef7eb2e8f9f7 87 ** - rev. 1.6 (2014-10-14)
<> 144:ef7eb2e8f9f7 88 ** Renamed interrupt vector LPTimer to LPTMR0
<> 144:ef7eb2e8f9f7 89 ** - rev. 1.7 (2015-01-13)
<> 144:ef7eb2e8f9f7 90 ** Update of the copyright.
<> 144:ef7eb2e8f9f7 91 **
<> 144:ef7eb2e8f9f7 92 ** ###################################################################
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /*!
<> 144:ef7eb2e8f9f7 96 * @file MKL26Z4
<> 144:ef7eb2e8f9f7 97 * @version 1.7
<> 144:ef7eb2e8f9f7 98 * @date 2015-01-13
<> 144:ef7eb2e8f9f7 99 * @brief Device specific configuration file for MKL26Z4 (implementation file)
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 102 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 103 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #include <stdint.h>
<> 144:ef7eb2e8f9f7 107 #include "MKL26Z4.h"
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 112 -- Core clock
<> 144:ef7eb2e8f9f7 113 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 118 -- SystemInit()
<> 144:ef7eb2e8f9f7 119 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #if (ACK_ISOLATION)
<> 144:ef7eb2e8f9f7 124 if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
<> 144:ef7eb2e8f9f7 125 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127 #endif
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Watchdog disable */
<> 144:ef7eb2e8f9f7 130 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 131 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
<> 144:ef7eb2e8f9f7 132 SIM->COPC = (uint32_t)0x00u;
<> 144:ef7eb2e8f9f7 133 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #ifdef CLOCK_SETUP
<> 144:ef7eb2e8f9f7 136 /* RTC_CLKIN route */
<> 144:ef7eb2e8f9f7 137 #if (RTC_CLKIN_USED)
<> 144:ef7eb2e8f9f7 138 /* SIM_SCGC5: PORTC=1 */
<> 144:ef7eb2e8f9f7 139 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
<> 144:ef7eb2e8f9f7 140 /* PORTC_PCR1: ISF=0,MUX=1 */
<> 144:ef7eb2e8f9f7 141 PORTC->PCR[1] = (uint32_t)((PORTC->PCR[1] & (uint32_t)~(uint32_t)(
<> 144:ef7eb2e8f9f7 142 PORT_PCR_ISF_MASK |
<> 144:ef7eb2e8f9f7 143 PORT_PCR_MUX(0x06)
<> 144:ef7eb2e8f9f7 144 )) | (uint32_t)(
<> 144:ef7eb2e8f9f7 145 PORT_PCR_MUX(0x01)
<> 144:ef7eb2e8f9f7 146 ));
<> 144:ef7eb2e8f9f7 147 #endif /* (RTC_CLKIN_USED) */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Wake-up from VLLSx? */
<> 144:ef7eb2e8f9f7 150 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 /* VLLSx recovery */
<> 144:ef7eb2e8f9f7 153 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Power mode protection initialization */
<> 144:ef7eb2e8f9f7 160 #ifdef SYSTEM_SMC_PMPROT_VALUE
<> 144:ef7eb2e8f9f7 161 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
<> 144:ef7eb2e8f9f7 162 #endif
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* System clock initialization */
<> 144:ef7eb2e8f9f7 165 /* Internal reference clock trim initialization */
<> 144:ef7eb2e8f9f7 166 #if defined(SLOW_TRIM_ADDRESS)
<> 144:ef7eb2e8f9f7 167 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
<> 144:ef7eb2e8f9f7 168 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
<> 144:ef7eb2e8f9f7 169 #endif /* defined(SLOW_TRIM_ADDRESS) */
<> 144:ef7eb2e8f9f7 170 #if defined(SLOW_FINE_TRIM_ADDRESS)
<> 144:ef7eb2e8f9f7 171 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
<> 144:ef7eb2e8f9f7 172 #endif
<> 144:ef7eb2e8f9f7 173 #if defined(FAST_TRIM_ADDRESS)
<> 144:ef7eb2e8f9f7 174 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
<> 144:ef7eb2e8f9f7 175 #endif
<> 144:ef7eb2e8f9f7 176 #if defined(FAST_FINE_TRIM_ADDRESS)
<> 144:ef7eb2e8f9f7 177 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
<> 144:ef7eb2e8f9f7 178 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
<> 144:ef7eb2e8f9f7 179 #if defined(SLOW_TRIM_ADDRESS)
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181 #endif /* defined(SLOW_TRIM_ADDRESS) */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Set system prescalers and clock sources */
<> 144:ef7eb2e8f9f7 184 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
<> 144:ef7eb2e8f9f7 185 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
<> 144:ef7eb2e8f9f7 186 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(
<> 144:ef7eb2e8f9f7 187 SIM_SOPT2_TPMSRC_MASK |
<> 144:ef7eb2e8f9f7 188 SIM_SOPT2_UART0SRC_MASK |
<> 144:ef7eb2e8f9f7 189 SIM_SOPT2_PLLFLLSEL_MASK |
<> 144:ef7eb2e8f9f7 190 SIM_SOPT2_USBSRC_MASK
<> 144:ef7eb2e8f9f7 191 ))) | ((SYSTEM_SIM_SOPT2_VALUE) & (
<> 144:ef7eb2e8f9f7 192 SIM_SOPT2_TPMSRC_MASK |
<> 144:ef7eb2e8f9f7 193 SIM_SOPT2_UART0SRC_MASK |
<> 144:ef7eb2e8f9f7 194 SIM_SOPT2_PLLFLLSEL_MASK |
<> 144:ef7eb2e8f9f7 195 SIM_SOPT2_USBSRC_MASK
<> 144:ef7eb2e8f9f7 196 )); /* Select TPM, LPUARTs, USB clock sources. */
<> 144:ef7eb2e8f9f7 197 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
<> 144:ef7eb2e8f9f7 198 /* Set MCG and OSC */
<> 144:ef7eb2e8f9f7 199 #if ((((SYSTEM_OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U))
<> 144:ef7eb2e8f9f7 200 /* SIM_SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 201 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
<> 144:ef7eb2e8f9f7 202 /* PORTA_PCR18: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 203 PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 204 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 205 /* PORTA_PCR19: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 206 PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 #endif
<> 144:ef7eb2e8f9f7 209 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
<> 144:ef7eb2e8f9f7 210 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
<> 144:ef7eb2e8f9f7 211 /* Check that the source of the FLL reference clock is the requested one. */
<> 144:ef7eb2e8f9f7 212 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 213 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215 } else {
<> 144:ef7eb2e8f9f7 216 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
<> 144:ef7eb2e8f9f7 220 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
<> 144:ef7eb2e8f9f7 221 OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #else /* MCG_MODE */
<> 144:ef7eb2e8f9f7 224 /* Set MCG and OSC */
<> 144:ef7eb2e8f9f7 225 /* SIM_SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 226 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
<> 144:ef7eb2e8f9f7 227 /* PORTA_PCR18: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 228 PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 229 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 230 /* PORTA_PCR19: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 231 PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
<> 144:ef7eb2e8f9f7 234 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
<> 144:ef7eb2e8f9f7 235 OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
<> 144:ef7eb2e8f9f7 236 #if (MCG_MODE == MCG_MODE_PEE)
<> 144:ef7eb2e8f9f7 237 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
<> 144:ef7eb2e8f9f7 238 #else
<> 144:ef7eb2e8f9f7 239 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
<> 144:ef7eb2e8f9f7 240 #endif
<> 144:ef7eb2e8f9f7 241 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 242 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245 /* Check that the source of the FLL reference clock is the requested one. */
<> 144:ef7eb2e8f9f7 246 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 247 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 } else {
<> 144:ef7eb2e8f9f7 250 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
<> 144:ef7eb2e8f9f7 254 #endif /* MCG_MODE */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Common for all MCG modes */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
<> 144:ef7eb2e8f9f7 259 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
<> 144:ef7eb2e8f9f7 260 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
<> 144:ef7eb2e8f9f7 261 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
<> 144:ef7eb2e8f9f7 262 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* BLPI and BLPE MCG mode specific */
<> 144:ef7eb2e8f9f7 266 #if ((MCG_MODE == MCG_MODE_BLPI) || (MCG_MODE == MCG_MODE_BLPE))
<> 144:ef7eb2e8f9f7 267 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
<> 144:ef7eb2e8f9f7 268 /* PEE and PBE MCG mode specific */
<> 144:ef7eb2e8f9f7 269 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
<> 144:ef7eb2e8f9f7 270 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
<> 144:ef7eb2e8f9f7 271 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273 #if (MCG_MODE == MCG_MODE_PEE)
<> 144:ef7eb2e8f9f7 274 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
<> 144:ef7eb2e8f9f7 275 #endif
<> 144:ef7eb2e8f9f7 276 #endif
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Clock mode status check */
<> 144:ef7eb2e8f9f7 279 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
<> 144:ef7eb2e8f9f7 280 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282 /* Use LPTMR to wait for 1ms for FLL clock stabilization */
<> 144:ef7eb2e8f9f7 283 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Allow software control of LPMTR */
<> 144:ef7eb2e8f9f7 284 LPTMR0->CMR = LPTMR_CMR_COMPARE(0); /* Default 1 LPO tick */
<> 144:ef7eb2e8f9f7 285 LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
<> 144:ef7eb2e8f9f7 286 LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
<> 144:ef7eb2e8f9f7 287 LPTMR0->CSR = LPTMR_CSR_TEN_MASK; /* LPMTR enable */
<> 144:ef7eb2e8f9f7 288 while((LPTMR0->CSR & LPTMR_CSR_TCF_MASK) == 0u) {
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290 LPTMR0->CSR = 0x00; /* Disable LPTMR */
<> 144:ef7eb2e8f9f7 291 SIM->SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
<> 144:ef7eb2e8f9f7 292 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
<> 144:ef7eb2e8f9f7 293 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
<> 144:ef7eb2e8f9f7 296 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 #elif (MCG_MODE == MCG_MODE_PEE)
<> 144:ef7eb2e8f9f7 299 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 #endif
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Very-low-power run mode enable */
<> 144:ef7eb2e8f9f7 304 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
<> 144:ef7eb2e8f9f7 305 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
<> 144:ef7eb2e8f9f7 306 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
<> 144:ef7eb2e8f9f7 307 }
<> 144:ef7eb2e8f9f7 308 #endif
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* PLL loss of lock interrupt request initialization */
<> 144:ef7eb2e8f9f7 311 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
<> 144:ef7eb2e8f9f7 312 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 #endif //#ifdef CLOCK_SETUP
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 319 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 320 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 325 uint16_t Divider;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 328 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 329 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 330 /* FLL is selected */
<> 144:ef7eb2e8f9f7 331 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 332 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 333 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 334 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) {
<> 144:ef7eb2e8f9f7 335 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
<> 144:ef7eb2e8f9f7 336 case 0x38U:
<> 144:ef7eb2e8f9f7 337 Divider = 1536U;
<> 144:ef7eb2e8f9f7 338 break;
<> 144:ef7eb2e8f9f7 339 case 0x30U:
<> 144:ef7eb2e8f9f7 340 Divider = 1280U;
<> 144:ef7eb2e8f9f7 341 break;
<> 144:ef7eb2e8f9f7 342 default:
<> 144:ef7eb2e8f9f7 343 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 344 break;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
<> 144:ef7eb2e8f9f7 347 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 350 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 351 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 352 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 353 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 354 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 355 case 0x00U:
<> 144:ef7eb2e8f9f7 356 MCGOUTClock *= 640U;
<> 144:ef7eb2e8f9f7 357 break;
<> 144:ef7eb2e8f9f7 358 case 0x20U:
<> 144:ef7eb2e8f9f7 359 MCGOUTClock *= 1280U;
<> 144:ef7eb2e8f9f7 360 break;
<> 144:ef7eb2e8f9f7 361 case 0x40U:
<> 144:ef7eb2e8f9f7 362 MCGOUTClock *= 1920U;
<> 144:ef7eb2e8f9f7 363 break;
<> 144:ef7eb2e8f9f7 364 case 0x60U:
<> 144:ef7eb2e8f9f7 365 MCGOUTClock *= 2560U;
<> 144:ef7eb2e8f9f7 366 break;
<> 144:ef7eb2e8f9f7 367 case 0x80U:
<> 144:ef7eb2e8f9f7 368 MCGOUTClock *= 732U;
<> 144:ef7eb2e8f9f7 369 break;
<> 144:ef7eb2e8f9f7 370 case 0xA0U:
<> 144:ef7eb2e8f9f7 371 MCGOUTClock *= 1464U;
<> 144:ef7eb2e8f9f7 372 break;
<> 144:ef7eb2e8f9f7 373 case 0xC0U:
<> 144:ef7eb2e8f9f7 374 MCGOUTClock *= 2197U;
<> 144:ef7eb2e8f9f7 375 break;
<> 144:ef7eb2e8f9f7 376 case 0xE0U:
<> 144:ef7eb2e8f9f7 377 MCGOUTClock *= 2929U;
<> 144:ef7eb2e8f9f7 378 break;
<> 144:ef7eb2e8f9f7 379 default:
<> 144:ef7eb2e8f9f7 380 break;
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 383 /* PLL is selected */
<> 144:ef7eb2e8f9f7 384 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
<> 144:ef7eb2e8f9f7 385 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 386 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
<> 144:ef7eb2e8f9f7 387 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 388 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 389 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
<> 144:ef7eb2e8f9f7 390 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 391 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 392 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 393 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 394 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 395 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 396 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 397 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
<> 144:ef7eb2e8f9f7 398 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 399 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 400 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 401 /* Reserved value */
<> 144:ef7eb2e8f9f7 402 return;
<> 144:ef7eb2e8f9f7 403 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 404 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 }