Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processors: MKL26Z128CAL4
bogdanm 0:9b334a45a8ff 4 ** MKL26Z128VFM4
bogdanm 0:9b334a45a8ff 5 ** MKL26Z64VFM4
bogdanm 0:9b334a45a8ff 6 ** MKL26Z32VM4
bogdanm 0:9b334a45a8ff 7 ** MKL26Z128VFT4
bogdanm 0:9b334a45a8ff 8 ** MKL26Z64VFT4
bogdanm 0:9b334a45a8ff 9 ** MKL26Z32VFT4
bogdanm 0:9b334a45a8ff 10 ** MKL26Z128VLH4
bogdanm 0:9b334a45a8ff 11 ** MKL26Z64VLH4
bogdanm 0:9b334a45a8ff 12 ** MKL26Z32VLH4
bogdanm 0:9b334a45a8ff 13 ** MKL26Z256VLH4
bogdanm 0:9b334a45a8ff 14 ** MKL26Z256VLL4
bogdanm 0:9b334a45a8ff 15 ** MKL26Z128VLL4
bogdanm 0:9b334a45a8ff 16 ** MKL26Z256VMC4
bogdanm 0:9b334a45a8ff 17 ** MKL26Z128VMC4
bogdanm 0:9b334a45a8ff 18 ** MKL26Z256VMP4
bogdanm 0:9b334a45a8ff 19 **
bogdanm 0:9b334a45a8ff 20 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 21 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 22 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 23 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 0:9b334a45a8ff 24 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 25 **
bogdanm 0:9b334a45a8ff 26 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
bogdanm 0:9b334a45a8ff 27 ** KL26P121M48SF4RM, Rev.2, Dec 2012
bogdanm 0:9b334a45a8ff 28 **
bogdanm 0:9b334a45a8ff 29 ** Version: rev. 1.7, 2015-01-13
bogdanm 0:9b334a45a8ff 30 ** Build: b150129
bogdanm 0:9b334a45a8ff 31 **
bogdanm 0:9b334a45a8ff 32 ** Abstract:
bogdanm 0:9b334a45a8ff 33 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 34 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 35 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 36 **
bogdanm 0:9b334a45a8ff 37 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 38 ** All rights reserved.
bogdanm 0:9b334a45a8ff 39 **
bogdanm 0:9b334a45a8ff 40 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 41 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 42 **
bogdanm 0:9b334a45a8ff 43 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 44 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 45 **
bogdanm 0:9b334a45a8ff 46 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 47 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 48 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 49 **
bogdanm 0:9b334a45a8ff 50 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 51 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 52 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 53 **
bogdanm 0:9b334a45a8ff 54 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 55 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 56 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 57 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 58 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 59 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 60 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 61 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 62 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 63 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 64 **
bogdanm 0:9b334a45a8ff 65 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 66 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 67 **
bogdanm 0:9b334a45a8ff 68 ** Revisions:
bogdanm 0:9b334a45a8ff 69 ** - rev. 1.0 (2012-12-12)
bogdanm 0:9b334a45a8ff 70 ** Initial version.
bogdanm 0:9b334a45a8ff 71 ** - rev. 1.1 (2013-04-05)
bogdanm 0:9b334a45a8ff 72 ** Changed start of doxygen comment.
bogdanm 0:9b334a45a8ff 73 ** - rev. 1.2 (2013-04-12)
bogdanm 0:9b334a45a8ff 74 ** SystemInit function fixed for clock configuration 1.
bogdanm 0:9b334a45a8ff 75 ** Name of the interrupt num. 31 updated to reflect proper function.
bogdanm 0:9b334a45a8ff 76 ** - rev. 1.3 (2014-05-27)
bogdanm 0:9b334a45a8ff 77 ** Updated to Kinetis SDK support standard.
bogdanm 0:9b334a45a8ff 78 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
bogdanm 0:9b334a45a8ff 79 ** - rev. 1.4 (2014-07-25)
bogdanm 0:9b334a45a8ff 80 ** System initialization updated:
bogdanm 0:9b334a45a8ff 81 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
bogdanm 0:9b334a45a8ff 82 ** - VLLSx wake-up recovery added.
bogdanm 0:9b334a45a8ff 83 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
bogdanm 0:9b334a45a8ff 84 ** - rev. 1.5 (2014-08-28)
bogdanm 0:9b334a45a8ff 85 ** Update of system files - default clock configuration changed, fix of OSC initialization.
bogdanm 0:9b334a45a8ff 86 ** Update of startup files - possibility to override DefaultISR added.
bogdanm 0:9b334a45a8ff 87 ** - rev. 1.6 (2014-10-14)
bogdanm 0:9b334a45a8ff 88 ** Renamed interrupt vector LPTimer to LPTMR0
bogdanm 0:9b334a45a8ff 89 ** - rev. 1.7 (2015-01-13)
bogdanm 0:9b334a45a8ff 90 ** Update of the copyright.
bogdanm 0:9b334a45a8ff 91 **
bogdanm 0:9b334a45a8ff 92 ** ###################################################################
bogdanm 0:9b334a45a8ff 93 */
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /*!
bogdanm 0:9b334a45a8ff 96 * @file MKL26Z4
bogdanm 0:9b334a45a8ff 97 * @version 1.7
bogdanm 0:9b334a45a8ff 98 * @date 2015-01-13
bogdanm 0:9b334a45a8ff 99 * @brief Device specific configuration file for MKL26Z4 (implementation file)
bogdanm 0:9b334a45a8ff 100 *
bogdanm 0:9b334a45a8ff 101 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 102 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 103 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 #include <stdint.h>
bogdanm 0:9b334a45a8ff 107 #include "MKL26Z4.h"
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 112 -- Core clock
bogdanm 0:9b334a45a8ff 113 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 118 -- SystemInit()
bogdanm 0:9b334a45a8ff 119 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 void SystemInit (void) {
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 #if (ACK_ISOLATION)
bogdanm 0:9b334a45a8ff 124 if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
bogdanm 0:9b334a45a8ff 125 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
bogdanm 0:9b334a45a8ff 126 }
bogdanm 0:9b334a45a8ff 127 #endif
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /* Watchdog disable */
bogdanm 0:9b334a45a8ff 130 #if (DISABLE_WDOG)
bogdanm 0:9b334a45a8ff 131 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
bogdanm 0:9b334a45a8ff 132 SIM->COPC = (uint32_t)0x00u;
bogdanm 0:9b334a45a8ff 133 #endif /* (DISABLE_WDOG) */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 #ifdef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 136 /* RTC_CLKIN route */
bogdanm 0:9b334a45a8ff 137 #if (RTC_CLKIN_USED)
bogdanm 0:9b334a45a8ff 138 /* SIM_SCGC5: PORTC=1 */
bogdanm 0:9b334a45a8ff 139 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
bogdanm 0:9b334a45a8ff 140 /* PORTC_PCR1: ISF=0,MUX=1 */
bogdanm 0:9b334a45a8ff 141 PORTC->PCR[1] = (uint32_t)((PORTC->PCR[1] & (uint32_t)~(uint32_t)(
bogdanm 0:9b334a45a8ff 142 PORT_PCR_ISF_MASK |
bogdanm 0:9b334a45a8ff 143 PORT_PCR_MUX(0x06)
bogdanm 0:9b334a45a8ff 144 )) | (uint32_t)(
bogdanm 0:9b334a45a8ff 145 PORT_PCR_MUX(0x01)
bogdanm 0:9b334a45a8ff 146 ));
bogdanm 0:9b334a45a8ff 147 #endif /* (RTC_CLKIN_USED) */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /* Wake-up from VLLSx? */
bogdanm 0:9b334a45a8ff 150 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
bogdanm 0:9b334a45a8ff 151 {
bogdanm 0:9b334a45a8ff 152 /* VLLSx recovery */
bogdanm 0:9b334a45a8ff 153 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
bogdanm 0:9b334a45a8ff 154 {
bogdanm 0:9b334a45a8ff 155 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
bogdanm 0:9b334a45a8ff 156 }
bogdanm 0:9b334a45a8ff 157 }
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Power mode protection initialization */
bogdanm 0:9b334a45a8ff 160 #ifdef SYSTEM_SMC_PMPROT_VALUE
bogdanm 0:9b334a45a8ff 161 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
bogdanm 0:9b334a45a8ff 162 #endif
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /* System clock initialization */
bogdanm 0:9b334a45a8ff 165 /* Internal reference clock trim initialization */
bogdanm 0:9b334a45a8ff 166 #if defined(SLOW_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 167 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
bogdanm 0:9b334a45a8ff 168 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
bogdanm 0:9b334a45a8ff 169 #endif /* defined(SLOW_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 170 #if defined(SLOW_FINE_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 171 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
bogdanm 0:9b334a45a8ff 172 #endif
bogdanm 0:9b334a45a8ff 173 #if defined(FAST_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 174 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
bogdanm 0:9b334a45a8ff 175 #endif
bogdanm 0:9b334a45a8ff 176 #if defined(FAST_FINE_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 177 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
bogdanm 0:9b334a45a8ff 178 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 179 #if defined(SLOW_TRIM_ADDRESS)
bogdanm 0:9b334a45a8ff 180 }
bogdanm 0:9b334a45a8ff 181 #endif /* defined(SLOW_TRIM_ADDRESS) */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Set system prescalers and clock sources */
bogdanm 0:9b334a45a8ff 184 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
bogdanm 0:9b334a45a8ff 185 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
bogdanm 0:9b334a45a8ff 186 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(
bogdanm 0:9b334a45a8ff 187 SIM_SOPT2_TPMSRC_MASK |
bogdanm 0:9b334a45a8ff 188 SIM_SOPT2_UART0SRC_MASK |
bogdanm 0:9b334a45a8ff 189 SIM_SOPT2_PLLFLLSEL_MASK |
bogdanm 0:9b334a45a8ff 190 SIM_SOPT2_USBSRC_MASK
bogdanm 0:9b334a45a8ff 191 ))) | ((SYSTEM_SIM_SOPT2_VALUE) & (
bogdanm 0:9b334a45a8ff 192 SIM_SOPT2_TPMSRC_MASK |
bogdanm 0:9b334a45a8ff 193 SIM_SOPT2_UART0SRC_MASK |
bogdanm 0:9b334a45a8ff 194 SIM_SOPT2_PLLFLLSEL_MASK |
bogdanm 0:9b334a45a8ff 195 SIM_SOPT2_USBSRC_MASK
bogdanm 0:9b334a45a8ff 196 )); /* Select TPM, LPUARTs, USB clock sources. */
bogdanm 0:9b334a45a8ff 197 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
bogdanm 0:9b334a45a8ff 198 /* Set MCG and OSC */
bogdanm 0:9b334a45a8ff 199 #if ((((SYSTEM_OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U))
bogdanm 0:9b334a45a8ff 200 /* SIM_SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 201 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 0:9b334a45a8ff 202 /* PORTA_PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 203 PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 204 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 205 /* PORTA_PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 206 PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 207 }
bogdanm 0:9b334a45a8ff 208 #endif
bogdanm 0:9b334a45a8ff 209 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
bogdanm 0:9b334a45a8ff 210 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
bogdanm 0:9b334a45a8ff 211 /* Check that the source of the FLL reference clock is the requested one. */
bogdanm 0:9b334a45a8ff 212 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 213 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 214 }
bogdanm 0:9b334a45a8ff 215 } else {
bogdanm 0:9b334a45a8ff 216 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 217 }
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
bogdanm 0:9b334a45a8ff 220 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
bogdanm 0:9b334a45a8ff 221 OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 #else /* MCG_MODE */
bogdanm 0:9b334a45a8ff 224 /* Set MCG and OSC */
bogdanm 0:9b334a45a8ff 225 /* SIM_SCGC5: PORTA=1 */
bogdanm 0:9b334a45a8ff 226 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
bogdanm 0:9b334a45a8ff 227 /* PORTA_PCR18: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 228 PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 229 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 230 /* PORTA_PCR19: ISF=0,MUX=0 */
bogdanm 0:9b334a45a8ff 231 PORTA->PCR[19] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
bogdanm 0:9b334a45a8ff 234 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
bogdanm 0:9b334a45a8ff 235 OSC0->CR = SYSTEM_OSC0_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
bogdanm 0:9b334a45a8ff 236 #if (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 237 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
bogdanm 0:9b334a45a8ff 238 #else
bogdanm 0:9b334a45a8ff 239 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
bogdanm 0:9b334a45a8ff 240 #endif
bogdanm 0:9b334a45a8ff 241 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 242 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
bogdanm 0:9b334a45a8ff 243 }
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245 /* Check that the source of the FLL reference clock is the requested one. */
bogdanm 0:9b334a45a8ff 246 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 247 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 248 }
bogdanm 0:9b334a45a8ff 249 } else {
bogdanm 0:9b334a45a8ff 250 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252 }
bogdanm 0:9b334a45a8ff 253 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
bogdanm 0:9b334a45a8ff 254 #endif /* MCG_MODE */
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /* Common for all MCG modes */
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
bogdanm 0:9b334a45a8ff 259 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
bogdanm 0:9b334a45a8ff 260 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
bogdanm 0:9b334a45a8ff 261 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
bogdanm 0:9b334a45a8ff 262 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /* BLPI and BLPE MCG mode specific */
bogdanm 0:9b334a45a8ff 266 #if ((MCG_MODE == MCG_MODE_BLPI) || (MCG_MODE == MCG_MODE_BLPE))
bogdanm 0:9b334a45a8ff 267 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
bogdanm 0:9b334a45a8ff 268 /* PEE and PBE MCG mode specific */
bogdanm 0:9b334a45a8ff 269 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
bogdanm 0:9b334a45a8ff 270 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
bogdanm 0:9b334a45a8ff 271 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
bogdanm 0:9b334a45a8ff 272 }
bogdanm 0:9b334a45a8ff 273 #if (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 274 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
bogdanm 0:9b334a45a8ff 275 #endif
bogdanm 0:9b334a45a8ff 276 #endif
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Clock mode status check */
bogdanm 0:9b334a45a8ff 279 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
bogdanm 0:9b334a45a8ff 280 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282 /* Use LPTMR to wait for 1ms for FLL clock stabilization */
bogdanm 0:9b334a45a8ff 283 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* Allow software control of LPMTR */
bogdanm 0:9b334a45a8ff 284 LPTMR0->CMR = LPTMR_CMR_COMPARE(0); /* Default 1 LPO tick */
bogdanm 0:9b334a45a8ff 285 LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
bogdanm 0:9b334a45a8ff 286 LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
bogdanm 0:9b334a45a8ff 287 LPTMR0->CSR = LPTMR_CSR_TEN_MASK; /* LPMTR enable */
bogdanm 0:9b334a45a8ff 288 while((LPTMR0->CSR & LPTMR_CSR_TCF_MASK) == 0u) {
bogdanm 0:9b334a45a8ff 289 }
bogdanm 0:9b334a45a8ff 290 LPTMR0->CSR = 0x00; /* Disable LPTMR */
bogdanm 0:9b334a45a8ff 291 SIM->SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
bogdanm 0:9b334a45a8ff 292 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
bogdanm 0:9b334a45a8ff 293 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
bogdanm 0:9b334a45a8ff 296 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298 #elif (MCG_MODE == MCG_MODE_PEE)
bogdanm 0:9b334a45a8ff 299 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301 #endif
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /* Very-low-power run mode enable */
bogdanm 0:9b334a45a8ff 304 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
bogdanm 0:9b334a45a8ff 305 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
bogdanm 0:9b334a45a8ff 306 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
bogdanm 0:9b334a45a8ff 307 }
bogdanm 0:9b334a45a8ff 308 #endif
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /* PLL loss of lock interrupt request initialization */
bogdanm 0:9b334a45a8ff 311 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
bogdanm 0:9b334a45a8ff 312 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314 #endif //#ifdef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 }
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 319 -- SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 320 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 void SystemCoreClockUpdate (void) {
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
bogdanm 0:9b334a45a8ff 325 uint16_t Divider;
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 328 /* Output of FLL or PLL is selected */
bogdanm 0:9b334a45a8ff 329 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 330 /* FLL is selected */
bogdanm 0:9b334a45a8ff 331 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 332 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 333 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 334 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) {
bogdanm 0:9b334a45a8ff 335 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
bogdanm 0:9b334a45a8ff 336 case 0x38U:
bogdanm 0:9b334a45a8ff 337 Divider = 1536U;
bogdanm 0:9b334a45a8ff 338 break;
bogdanm 0:9b334a45a8ff 339 case 0x30U:
bogdanm 0:9b334a45a8ff 340 Divider = 1280U;
bogdanm 0:9b334a45a8ff 341 break;
bogdanm 0:9b334a45a8ff 342 default:
bogdanm 0:9b334a45a8ff 343 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 344 break;
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
bogdanm 0:9b334a45a8ff 347 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 348 }
bogdanm 0:9b334a45a8ff 349 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
bogdanm 0:9b334a45a8ff 350 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 351 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
bogdanm 0:9b334a45a8ff 352 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 353 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 354 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 355 case 0x00U:
bogdanm 0:9b334a45a8ff 356 MCGOUTClock *= 640U;
bogdanm 0:9b334a45a8ff 357 break;
bogdanm 0:9b334a45a8ff 358 case 0x20U:
bogdanm 0:9b334a45a8ff 359 MCGOUTClock *= 1280U;
bogdanm 0:9b334a45a8ff 360 break;
bogdanm 0:9b334a45a8ff 361 case 0x40U:
bogdanm 0:9b334a45a8ff 362 MCGOUTClock *= 1920U;
bogdanm 0:9b334a45a8ff 363 break;
bogdanm 0:9b334a45a8ff 364 case 0x60U:
bogdanm 0:9b334a45a8ff 365 MCGOUTClock *= 2560U;
bogdanm 0:9b334a45a8ff 366 break;
bogdanm 0:9b334a45a8ff 367 case 0x80U:
bogdanm 0:9b334a45a8ff 368 MCGOUTClock *= 732U;
bogdanm 0:9b334a45a8ff 369 break;
bogdanm 0:9b334a45a8ff 370 case 0xA0U:
bogdanm 0:9b334a45a8ff 371 MCGOUTClock *= 1464U;
bogdanm 0:9b334a45a8ff 372 break;
bogdanm 0:9b334a45a8ff 373 case 0xC0U:
bogdanm 0:9b334a45a8ff 374 MCGOUTClock *= 2197U;
bogdanm 0:9b334a45a8ff 375 break;
bogdanm 0:9b334a45a8ff 376 case 0xE0U:
bogdanm 0:9b334a45a8ff 377 MCGOUTClock *= 2929U;
bogdanm 0:9b334a45a8ff 378 break;
bogdanm 0:9b334a45a8ff 379 default:
bogdanm 0:9b334a45a8ff 380 break;
bogdanm 0:9b334a45a8ff 381 }
bogdanm 0:9b334a45a8ff 382 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 383 /* PLL is selected */
bogdanm 0:9b334a45a8ff 384 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
bogdanm 0:9b334a45a8ff 385 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
bogdanm 0:9b334a45a8ff 386 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
bogdanm 0:9b334a45a8ff 387 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 388 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 389 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
bogdanm 0:9b334a45a8ff 390 /* Internal reference clock is selected */
bogdanm 0:9b334a45a8ff 391 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
bogdanm 0:9b334a45a8ff 392 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
bogdanm 0:9b334a45a8ff 393 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 394 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 395 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
bogdanm 0:9b334a45a8ff 396 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
bogdanm 0:9b334a45a8ff 397 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
bogdanm 0:9b334a45a8ff 398 /* External reference clock is selected */
bogdanm 0:9b334a45a8ff 399 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
bogdanm 0:9b334a45a8ff 400 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 401 /* Reserved value */
bogdanm 0:9b334a45a8ff 402 return;
bogdanm 0:9b334a45a8ff 403 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
bogdanm 0:9b334a45a8ff 404 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 }