Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
121:7f86b4238bec 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MK22FN512CAP12
<> 144:ef7eb2e8f9f7 4 ** MK22FN512VDC12
<> 144:ef7eb2e8f9f7 5 ** MK22FN512VLH12
<> 144:ef7eb2e8f9f7 6 ** MK22FN512VLL12
<> 144:ef7eb2e8f9f7 7 ** MK22FN512VMP12
<> 144:ef7eb2e8f9f7 8 **
<> 144:ef7eb2e8f9f7 9 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 10 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 11 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 12 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 13 **
<> 144:ef7eb2e8f9f7 14 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
<> 144:ef7eb2e8f9f7 15 ** Version: rev. 2.8, 2015-02-19
<> 144:ef7eb2e8f9f7 16 ** Build: b151217
<> 144:ef7eb2e8f9f7 17 **
<> 144:ef7eb2e8f9f7 18 ** Abstract:
<> 144:ef7eb2e8f9f7 19 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 20 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 21 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 22 **
<> 144:ef7eb2e8f9f7 23 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 24 ** All rights reserved.
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 27 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 28 **
<> 144:ef7eb2e8f9f7 29 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 30 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 31 **
<> 144:ef7eb2e8f9f7 32 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 33 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 34 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 35 **
<> 144:ef7eb2e8f9f7 36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 37 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 38 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 39 **
<> 144:ef7eb2e8f9f7 40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 50 **
<> 144:ef7eb2e8f9f7 51 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 52 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 53 **
<> 144:ef7eb2e8f9f7 54 ** Revisions:
<> 144:ef7eb2e8f9f7 55 ** - rev. 1.0 (2013-07-23)
<> 144:ef7eb2e8f9f7 56 ** Initial version.
<> 144:ef7eb2e8f9f7 57 ** - rev. 1.1 (2013-09-17)
<> 144:ef7eb2e8f9f7 58 ** RM rev. 0.4 update.
<> 144:ef7eb2e8f9f7 59 ** - rev. 2.0 (2013-10-29)
<> 144:ef7eb2e8f9f7 60 ** Register accessor macros added to the memory map.
<> 144:ef7eb2e8f9f7 61 ** Symbols for Processor Expert memory map compatibility added to the memory map.
<> 144:ef7eb2e8f9f7 62 ** Startup file for gcc has been updated according to CMSIS 3.2.
<> 144:ef7eb2e8f9f7 63 ** System initialization updated.
<> 144:ef7eb2e8f9f7 64 ** - rev. 2.1 (2013-10-30)
<> 144:ef7eb2e8f9f7 65 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
<> 144:ef7eb2e8f9f7 66 ** - rev. 2.2 (2013-12-20)
<> 144:ef7eb2e8f9f7 67 ** Update according to reference manual rev. 0.6,
<> 144:ef7eb2e8f9f7 68 ** - rev. 2.3 (2014-01-13)
<> 144:ef7eb2e8f9f7 69 ** Update according to reference manual rev. 0.61,
<> 144:ef7eb2e8f9f7 70 ** - rev. 2.4 (2014-02-10)
<> 144:ef7eb2e8f9f7 71 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
<> 144:ef7eb2e8f9f7 72 ** - rev. 2.5 (2014-05-06)
<> 144:ef7eb2e8f9f7 73 ** Update according to reference manual rev. 1.0,
<> 144:ef7eb2e8f9f7 74 ** Update of system and startup files.
<> 144:ef7eb2e8f9f7 75 ** Module access macro module_BASES replaced by module_BASE_PTRS.
<> 144:ef7eb2e8f9f7 76 ** - rev. 2.6 (2014-08-28)
<> 144:ef7eb2e8f9f7 77 ** Update of system files - default clock configuration changed.
<> 144:ef7eb2e8f9f7 78 ** Update of startup files - possibility to override DefaultISR added.
<> 144:ef7eb2e8f9f7 79 ** - rev. 2.7 (2014-10-14)
<> 144:ef7eb2e8f9f7 80 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
<> 144:ef7eb2e8f9f7 81 ** - rev. 2.8 (2015-02-19)
<> 144:ef7eb2e8f9f7 82 ** Renamed interrupt vector LLW to LLWU.
<> 144:ef7eb2e8f9f7 83 **
<> 144:ef7eb2e8f9f7 84 ** ###################################################################
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*!
<> 144:ef7eb2e8f9f7 88 * @file MK22F51212
<> 144:ef7eb2e8f9f7 89 * @version 2.8
<> 144:ef7eb2e8f9f7 90 * @date 2015-02-19
<> 144:ef7eb2e8f9f7 91 * @brief Device specific configuration file for MK22F51212 (implementation file)
<> 144:ef7eb2e8f9f7 92 *
<> 144:ef7eb2e8f9f7 93 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 94 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 95 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #include <stdint.h>
<> 144:ef7eb2e8f9f7 99 #include "fsl_device_registers.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 104 -- Core clock
<> 144:ef7eb2e8f9f7 105 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 110 -- SystemInit()
<> 144:ef7eb2e8f9f7 111 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 114 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
<> 144:ef7eb2e8f9f7 115 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
<> 144:ef7eb2e8f9f7 116 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 119 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
<> 144:ef7eb2e8f9f7 120 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
<> 144:ef7eb2e8f9f7 121 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
<> 144:ef7eb2e8f9f7 122 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
<> 144:ef7eb2e8f9f7 123 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
<> 144:ef7eb2e8f9f7 124 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
<> 144:ef7eb2e8f9f7 125 WDOG_STCTRLH_WAITEN_MASK |
<> 144:ef7eb2e8f9f7 126 WDOG_STCTRLH_STOPEN_MASK |
<> 144:ef7eb2e8f9f7 127 WDOG_STCTRLH_ALLOWUPDATE_MASK |
<> 144:ef7eb2e8f9f7 128 WDOG_STCTRLH_CLKSRC_MASK |
<> 144:ef7eb2e8f9f7 129 0x0100U;
<> 144:ef7eb2e8f9f7 130 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 135 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 136 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 141 uint16_t Divider;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 144 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 145 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 146 /* FLL is selected */
<> 144:ef7eb2e8f9f7 147 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 148 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 149 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
<> 144:ef7eb2e8f9f7 150 case 0x00U:
<> 144:ef7eb2e8f9f7 151 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 152 break;
<> 144:ef7eb2e8f9f7 153 case 0x01U:
<> 144:ef7eb2e8f9f7 154 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 155 break;
<> 144:ef7eb2e8f9f7 156 case 0x02U:
<> 144:ef7eb2e8f9f7 157 default:
<> 144:ef7eb2e8f9f7 158 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 159 break;
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
<> 144:ef7eb2e8f9f7 162 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
<> 144:ef7eb2e8f9f7 163 case 0x38U:
<> 144:ef7eb2e8f9f7 164 Divider = 1536U;
<> 144:ef7eb2e8f9f7 165 break;
<> 144:ef7eb2e8f9f7 166 case 0x30U:
<> 144:ef7eb2e8f9f7 167 Divider = 1280U;
<> 144:ef7eb2e8f9f7 168 break;
<> 144:ef7eb2e8f9f7 169 default:
<> 144:ef7eb2e8f9f7 170 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 171 break;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
<> 144:ef7eb2e8f9f7 174 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 177 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 178 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 179 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 180 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 181 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 182 case 0x00U:
<> 144:ef7eb2e8f9f7 183 MCGOUTClock *= 640U;
<> 144:ef7eb2e8f9f7 184 break;
<> 144:ef7eb2e8f9f7 185 case 0x20U:
<> 144:ef7eb2e8f9f7 186 MCGOUTClock *= 1280U;
<> 144:ef7eb2e8f9f7 187 break;
<> 144:ef7eb2e8f9f7 188 case 0x40U:
<> 144:ef7eb2e8f9f7 189 MCGOUTClock *= 1920U;
<> 144:ef7eb2e8f9f7 190 break;
<> 144:ef7eb2e8f9f7 191 case 0x60U:
<> 144:ef7eb2e8f9f7 192 MCGOUTClock *= 2560U;
<> 144:ef7eb2e8f9f7 193 break;
<> 144:ef7eb2e8f9f7 194 case 0x80U:
<> 144:ef7eb2e8f9f7 195 MCGOUTClock *= 732U;
<> 144:ef7eb2e8f9f7 196 break;
<> 144:ef7eb2e8f9f7 197 case 0xA0U:
<> 144:ef7eb2e8f9f7 198 MCGOUTClock *= 1464U;
<> 144:ef7eb2e8f9f7 199 break;
<> 144:ef7eb2e8f9f7 200 case 0xC0U:
<> 144:ef7eb2e8f9f7 201 MCGOUTClock *= 2197U;
<> 144:ef7eb2e8f9f7 202 break;
<> 144:ef7eb2e8f9f7 203 case 0xE0U:
<> 144:ef7eb2e8f9f7 204 MCGOUTClock *= 2929U;
<> 144:ef7eb2e8f9f7 205 break;
<> 144:ef7eb2e8f9f7 206 default:
<> 144:ef7eb2e8f9f7 207 break;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 210 /* PLL is selected */
<> 144:ef7eb2e8f9f7 211 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
<> 144:ef7eb2e8f9f7 212 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 213 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
<> 144:ef7eb2e8f9f7 214 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 215 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 216 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
<> 144:ef7eb2e8f9f7 217 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 218 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 219 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 220 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 221 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 222 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 223 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 224 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
<> 144:ef7eb2e8f9f7 225 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 226 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
<> 144:ef7eb2e8f9f7 227 case 0x00U:
<> 144:ef7eb2e8f9f7 228 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 229 break;
<> 144:ef7eb2e8f9f7 230 case 0x01U:
<> 144:ef7eb2e8f9f7 231 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 232 break;
<> 144:ef7eb2e8f9f7 233 case 0x02U:
<> 144:ef7eb2e8f9f7 234 default:
<> 144:ef7eb2e8f9f7 235 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 236 break;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 239 /* Reserved value */
<> 144:ef7eb2e8f9f7 240 return;
<> 144:ef7eb2e8f9f7 241 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 242 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 243 }