Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M4/CMSDK_CM4.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
80:bdf1132a57cf 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* MPS2 CMSIS Library
<> 144:ef7eb2e8f9f7 2 *
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2006-2016 ARM Limited
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 13 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 14 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * 3. Neither the name of the copyright holder nor the names of its contributors
<> 144:ef7eb2e8f9f7 17 * may be used to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 18 * specific prior written permission.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 30 * POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 * @file CMSDK_CM4.h
<> 144:ef7eb2e8f9f7 33 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 34 * Device CMSDK_CM4
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 *******************************************************************************/
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifndef CMSDK_CM4_H
<> 144:ef7eb2e8f9f7 40 #define CMSDK_CM4_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 typedef enum IRQn
<> 144:ef7eb2e8f9f7 50 {
<> 144:ef7eb2e8f9f7 51 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
<> 144:ef7eb2e8f9f7 52 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 53 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
<> 144:ef7eb2e8f9f7 54 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 55 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 56 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 57 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 58 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 59 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 60 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /****** CMSDK Specific Interrupt Numbers *********************************************************/
<> 144:ef7eb2e8f9f7 63 UARTRX0_IRQn = 0, /*!< UART 0 RX Interrupt */
<> 144:ef7eb2e8f9f7 64 UARTTX0_IRQn = 1, /*!< UART 0 TX Interrupt */
<> 144:ef7eb2e8f9f7 65 UARTRX1_IRQn = 2, /*!< UART 1 RX Interrupt */
<> 144:ef7eb2e8f9f7 66 UARTTX1_IRQn = 3, /*!< UART 1 TX Interrupt */
<> 144:ef7eb2e8f9f7 67 UARTRX2_IRQn = 4, /*!< UART 2 RX Interrupt */
<> 144:ef7eb2e8f9f7 68 UARTTX2_IRQn = 5, /*!< UART 2 TX Interrupt */
<> 144:ef7eb2e8f9f7 69 PORT0_ALL_IRQn = 6, /*!< Port 0 combined Interrupt */
<> 144:ef7eb2e8f9f7 70 PORT1_ALL_IRQn = 7, /*!< Port 1 combined Interrupt */
<> 144:ef7eb2e8f9f7 71 TIMER0_IRQn = 8, /*!< TIMER 0 Interrupt */
<> 144:ef7eb2e8f9f7 72 TIMER1_IRQn = 9, /*!< TIMER 1 Interrupt */
<> 144:ef7eb2e8f9f7 73 DUALTIMER_IRQn = 10, /*!< Dual Timer Interrupt */
<> 144:ef7eb2e8f9f7 74 SPI_IRQn = 11, /*!< SPI Interrupt */
<> 144:ef7eb2e8f9f7 75 UARTOVF_IRQn = 12, /*!< UART 0,1,2 Overflow Interrupt */
<> 144:ef7eb2e8f9f7 76 ETHERNET_IRQn = 13, /*!< Ethernet Interrupt */
<> 144:ef7eb2e8f9f7 77 I2S_IRQn = 14, /*!< I2S Interrupt */
<> 144:ef7eb2e8f9f7 78 TSC_IRQn = 15, /*!< Touch Screen Interrupt */
<> 144:ef7eb2e8f9f7 79 PORT2_ALL_IRQn = 16, /*!< Port 2 combined Interrupt */
<> 144:ef7eb2e8f9f7 80 PORT3_ALL_IRQn = 17, /*!< Port 3 combined Interrupt */
<> 144:ef7eb2e8f9f7 81 UARTRX3_IRQn = 18, /*!< UART 3 RX Interrupt */
<> 144:ef7eb2e8f9f7 82 UARTTX3_IRQn = 19, /*!< UART 3 TX Interrupt */
<> 144:ef7eb2e8f9f7 83 UARTRX4_IRQn = 20, /*!< UART 4 RX Interrupt */
<> 144:ef7eb2e8f9f7 84 UARTTX4_IRQn = 21, /*!< UART 4 TX Interrupt */
<> 144:ef7eb2e8f9f7 85 ADCSPI_IRQn = 22, /*!< SHIELD ADC SPI Interrupt */
<> 144:ef7eb2e8f9f7 86 SHIELDSPI_IRQn = 23, /*!< SHIELD SPI Combined Interrupt */
<> 144:ef7eb2e8f9f7 87 PORT0_0_IRQn = 24, /*!< GPIO Port 0 pin 0 Interrupt */
<> 144:ef7eb2e8f9f7 88 PORT0_1_IRQn = 25, /*!< GPIO Port 0 pin 1 Interrupt */
<> 144:ef7eb2e8f9f7 89 PORT0_2_IRQn = 26, /*!< GPIO Port 0 pin 2 Interrupt */
<> 144:ef7eb2e8f9f7 90 PORT0_3_IRQn = 27, /*!< GPIO Port 0 pin 3 Interrupt */
<> 144:ef7eb2e8f9f7 91 PORT0_4_IRQn = 28, /*!< GPIO Port 0 pin 4 Interrupt */
<> 144:ef7eb2e8f9f7 92 PORT0_5_IRQn = 29, /*!< GPIO Port 0 pin 5 Interrupt */
<> 144:ef7eb2e8f9f7 93 PORT0_6_IRQn = 30, /*!< GPIO Port 0 pin 6 Interrupt */
<> 144:ef7eb2e8f9f7 94 PORT0_7_IRQn = 31, /*!< GPIO Port 0 pin 7 Interrupt */
<> 144:ef7eb2e8f9f7 95 } IRQn_Type;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*
<> 144:ef7eb2e8f9f7 99 * ==========================================================================
<> 144:ef7eb2e8f9f7 100 * ----------- Processor and Core Peripheral Section ------------------------
<> 144:ef7eb2e8f9f7 101 * ==========================================================================
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /* Configuration of the Cortex-M4 Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 105 #define __CM4_REV 0x0001 /*!< Core Revision r0p1 */
<> 144:ef7eb2e8f9f7 106 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 107 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 108 #define __MPU_PRESENT 1 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 109 #define __FPU_PRESENT 1 /*!< FPU present or not */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /*@}*/ /* end of group CMSDK_CM4_CMSIS */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 144:ef7eb2e8f9f7 115 #include "system_CMSDK_CM4.h" /* CMSDK_CM4 System include file */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /******************************************************************************/
<> 144:ef7eb2e8f9f7 119 /* Device Specific Peripheral registers structures */
<> 144:ef7eb2e8f9f7 120 /******************************************************************************/
<> 144:ef7eb2e8f9f7 121 /** @addtogroup CMSDK_CM4_Peripherals CMSDK_CM4 Peripherals
<> 144:ef7eb2e8f9f7 122 CMSDK_CM4 Device Specific Peripheral registers structures
<> 144:ef7eb2e8f9f7 123 @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 127 #pragma anon_unions
<> 144:ef7eb2e8f9f7 128 #endif
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
<> 144:ef7eb2e8f9f7 131 /** @addtogroup CMSDK_UART CMSDK Universal Asynchronous Receiver/Transmitter
<> 144:ef7eb2e8f9f7 132 memory mapped structure for CMSDK_UART
<> 144:ef7eb2e8f9f7 133 @{
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135 typedef struct
<> 144:ef7eb2e8f9f7 136 {
<> 144:ef7eb2e8f9f7 137 __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
<> 144:ef7eb2e8f9f7 138 __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
<> 144:ef7eb2e8f9f7 139 __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
<> 144:ef7eb2e8f9f7 140 union {
<> 144:ef7eb2e8f9f7 141 __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 142 __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
<> 144:ef7eb2e8f9f7 143 };
<> 144:ef7eb2e8f9f7 144 __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 } CMSDK_UART_TypeDef;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* CMSDK_UART DATA Register Definitions */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define CMSDK_UART_DATA_Pos 0 /*!< CMSDK_UART_DATA_Pos: DATA Position */
<> 144:ef7eb2e8f9f7 151 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /*!< CMSDK_UART DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 #define CMSDK_UART_STATE_RXOR_Pos 3 /*!< CMSDK_UART STATE: RXOR Position */
<> 144:ef7eb2e8f9f7 154 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /*!< CMSDK_UART STATE: RXOR Mask */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #define CMSDK_UART_STATE_TXOR_Pos 2 /*!< CMSDK_UART STATE: TXOR Position */
<> 144:ef7eb2e8f9f7 157 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /*!< CMSDK_UART STATE: TXOR Mask */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #define CMSDK_UART_STATE_RXBF_Pos 1 /*!< CMSDK_UART STATE: RXBF Position */
<> 144:ef7eb2e8f9f7 160 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /*!< CMSDK_UART STATE: RXBF Mask */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define CMSDK_UART_STATE_TXBF_Pos 0 /*!< CMSDK_UART STATE: TXBF Position */
<> 144:ef7eb2e8f9f7 163 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /*!< CMSDK_UART STATE: TXBF Mask */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #define CMSDK_UART_CTRL_HSTM_Pos 6 /*!< CMSDK_UART CTRL: HSTM Position */
<> 144:ef7eb2e8f9f7 166 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /*!< CMSDK_UART CTRL: HSTM Mask */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /*!< CMSDK_UART CTRL: RXORIRQEN Position */
<> 144:ef7eb2e8f9f7 169 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /*!< CMSDK_UART CTRL: RXORIRQEN Mask */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /*!< CMSDK_UART CTRL: TXORIRQEN Position */
<> 144:ef7eb2e8f9f7 172 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /*!< CMSDK_UART CTRL: TXORIRQEN Mask */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /*!< CMSDK_UART CTRL: RXIRQEN Position */
<> 144:ef7eb2e8f9f7 175 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /*!< CMSDK_UART CTRL: RXIRQEN Mask */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /*!< CMSDK_UART CTRL: TXIRQEN Position */
<> 144:ef7eb2e8f9f7 178 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /*!< CMSDK_UART CTRL: TXIRQEN Mask */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define CMSDK_UART_CTRL_RXEN_Pos 1 /*!< CMSDK_UART CTRL: RXEN Position */
<> 144:ef7eb2e8f9f7 181 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /*!< CMSDK_UART CTRL: RXEN Mask */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define CMSDK_UART_CTRL_TXEN_Pos 0 /*!< CMSDK_UART CTRL: TXEN Position */
<> 144:ef7eb2e8f9f7 184 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /*!< CMSDK_UART CTRL: TXEN Mask */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /*!< CMSDK_UART CTRL: RXORIRQ Position */
<> 144:ef7eb2e8f9f7 187 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /*!< CMSDK_UART CTRL: RXORIRQ Mask */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /*!< CMSDK_UART CTRL: TXORIRQ Position */
<> 144:ef7eb2e8f9f7 190 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /*!< CMSDK_UART CTRL: TXORIRQ Mask */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /*!< CMSDK_UART CTRL: RXIRQ Position */
<> 144:ef7eb2e8f9f7 193 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /*!< CMSDK_UART CTRL: RXIRQ Mask */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /*!< CMSDK_UART CTRL: TXIRQ Position */
<> 144:ef7eb2e8f9f7 196 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /*!< CMSDK_UART CTRL: TXIRQ Mask */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 #define CMSDK_UART_BAUDDIV_Pos 0 /*!< CMSDK_UART BAUDDIV: BAUDDIV Position */
<> 144:ef7eb2e8f9f7 199 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /*!< CMSDK_UART BAUDDIV: BAUDDIV Mask */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /*@}*/ /* end of group CMSDK_UART */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /*----------------------------- Timer (TIMER) -------------------------------*/
<> 144:ef7eb2e8f9f7 205 /** @addtogroup CMSDK_TIMER CMSDK Timer
<> 144:ef7eb2e8f9f7 206 @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208 typedef struct
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
<> 144:ef7eb2e8f9f7 213 union {
<> 144:ef7eb2e8f9f7 214 __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
<> 144:ef7eb2e8f9f7 215 __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
<> 144:ef7eb2e8f9f7 216 };
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 } CMSDK_TIMER_TypeDef;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* CMSDK_TIMER CTRL Register Definitions */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /*!< CMSDK_TIMER CTRL: IRQEN Position */
<> 144:ef7eb2e8f9f7 223 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /*!< CMSDK_TIMER CTRL: IRQEN Mask */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /*!< CMSDK_TIMER CTRL: SELEXTCLK Position */
<> 144:ef7eb2e8f9f7 226 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /*!< CMSDK_TIMER CTRL: SELEXTCLK Mask */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /*!< CMSDK_TIMER CTRL: SELEXTEN Position */
<> 144:ef7eb2e8f9f7 229 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /*!< CMSDK_TIMER CTRL: SELEXTEN Mask */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 #define CMSDK_TIMER_CTRL_EN_Pos 0 /*!< CMSDK_TIMER CTRL: EN Position */
<> 144:ef7eb2e8f9f7 232 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /*!< CMSDK_TIMER CTRL: EN Mask */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /*!< CMSDK_TIMER VALUE: CURRENT Position */
<> 144:ef7eb2e8f9f7 235 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /*!< CMSDK_TIMER VALUE: CURRENT Mask */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /*!< CMSDK_TIMER RELOAD: RELOAD Position */
<> 144:ef7eb2e8f9f7 238 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /*!< CMSDK_TIMER RELOAD: RELOAD Mask */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 #define CMSDK_TIMER_INTSTATUS_Pos 0 /*!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
<> 144:ef7eb2e8f9f7 241 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /*!< CMSDK_TIMER INTSTATUS: INTSTATUSMask */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 #define CMSDK_TIMER_INTCLEAR_Pos 0 /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Position */
<> 144:ef7eb2e8f9f7 244 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /*@}*/ /* end of group CMSDK_TIMER */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /*------------- Timer (TIM) --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 250 // <g> Timer (TIM)
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @addtogroup CMSDK_DualTIMER CMSDK Dual Timer
<> 144:ef7eb2e8f9f7 253 @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 typedef struct
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
<> 144:ef7eb2e8f9f7 259 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
<> 144:ef7eb2e8f9f7 260 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
<> 144:ef7eb2e8f9f7 261 /* <o.7> TimerEn: Timer Enable */
<> 144:ef7eb2e8f9f7 262 /* <o.6> TimerMode: Timer Mode */
<> 144:ef7eb2e8f9f7 263 /* <0=> Freerunning-mode */
<> 144:ef7eb2e8f9f7 264 /* <1=> Periodic mode */
<> 144:ef7eb2e8f9f7 265 /* <o.5> IntEnable: Interrupt Enable */
<> 144:ef7eb2e8f9f7 266 /* <o.2..3> TimerPre: Timer Prescale */
<> 144:ef7eb2e8f9f7 267 /* <0=> / 1 */
<> 144:ef7eb2e8f9f7 268 /* <1=> / 16 */
<> 144:ef7eb2e8f9f7 269 /* <2=> / 256 */
<> 144:ef7eb2e8f9f7 270 /* <3=> Undefined! */
<> 144:ef7eb2e8f9f7 271 /* <o.1> TimerSize: Timer Size */
<> 144:ef7eb2e8f9f7 272 /* <0=> 16-bit counter */
<> 144:ef7eb2e8f9f7 273 /* <1=> 32-bit counter */
<> 144:ef7eb2e8f9f7 274 /* <o.0> OneShot: One-shoot mode */
<> 144:ef7eb2e8f9f7 275 /* <0=> Wrapping mode */
<> 144:ef7eb2e8f9f7 276 /* <1=> One-shot mode */
<> 144:ef7eb2e8f9f7 277 /* </h> */
<> 144:ef7eb2e8f9f7 278 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
<> 144:ef7eb2e8f9f7 279 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 280 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 282 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 283 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
<> 144:ef7eb2e8f9f7 284 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
<> 144:ef7eb2e8f9f7 285 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
<> 144:ef7eb2e8f9f7 286 /* <o.7> TimerEn: Timer Enable */
<> 144:ef7eb2e8f9f7 287 /* <o.6> TimerMode: Timer Mode */
<> 144:ef7eb2e8f9f7 288 /* <0=> Freerunning-mode */
<> 144:ef7eb2e8f9f7 289 /* <1=> Periodic mode */
<> 144:ef7eb2e8f9f7 290 /* <o.5> IntEnable: Interrupt Enable */
<> 144:ef7eb2e8f9f7 291 /* <o.2..3> TimerPre: Timer Prescale */
<> 144:ef7eb2e8f9f7 292 /* <0=> / 1 */
<> 144:ef7eb2e8f9f7 293 /* <1=> / 16 */
<> 144:ef7eb2e8f9f7 294 /* <2=> / 256 */
<> 144:ef7eb2e8f9f7 295 /* <3=> Undefined! */
<> 144:ef7eb2e8f9f7 296 /* <o.1> TimerSize: Timer Size */
<> 144:ef7eb2e8f9f7 297 /* <0=> 16-bit counter */
<> 144:ef7eb2e8f9f7 298 /* <1=> 32-bit counter */
<> 144:ef7eb2e8f9f7 299 /* <o.0> OneShot: One-shoot mode */
<> 144:ef7eb2e8f9f7 300 /* <0=> Wrapping mode */
<> 144:ef7eb2e8f9f7 301 /* <1=> One-shot mode */
<> 144:ef7eb2e8f9f7 302 /* </h> */
<> 144:ef7eb2e8f9f7 303 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
<> 144:ef7eb2e8f9f7 304 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 305 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 306 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 307 uint32_t RESERVED1[945];
<> 144:ef7eb2e8f9f7 308 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
<> 144:ef7eb2e8f9f7 309 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
<> 144:ef7eb2e8f9f7 310 } CMSDK_DUALTIMER_BOTH_TypeDef;
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /*!< CMSDK_DUALTIMER1 LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 313 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /*!< CMSDK_DUALTIMER1 LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /*!< CMSDK_DUALTIMER1 VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 316 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /*!< CMSDK_DUALTIMER1 VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 319 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 322 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 325 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 328 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 331 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 334 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 337 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /*!< CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 340 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 343 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 346 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /*!< CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /*!< CMSDK_DUALTIMER2 LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 349 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /*!< CMSDK_DUALTIMER2 LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /*!< CMSDK_DUALTIMER2 VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 352 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /*!< CMSDK_DUALTIMER2 VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 355 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 358 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 361 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 364 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 367 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 370 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 373 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /*!< CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 376 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 379 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 382 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /*!< CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 typedef struct
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
<> 144:ef7eb2e8f9f7 387 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
<> 144:ef7eb2e8f9f7 389 /* <o.7> TimerEn: Timer Enable */
<> 144:ef7eb2e8f9f7 390 /* <o.6> TimerMode: Timer Mode */
<> 144:ef7eb2e8f9f7 391 /* <0=> Freerunning-mode */
<> 144:ef7eb2e8f9f7 392 /* <1=> Periodic mode */
<> 144:ef7eb2e8f9f7 393 /* <o.5> IntEnable: Interrupt Enable */
<> 144:ef7eb2e8f9f7 394 /* <o.2..3> TimerPre: Timer Prescale */
<> 144:ef7eb2e8f9f7 395 /* <0=> / 1 */
<> 144:ef7eb2e8f9f7 396 /* <1=> / 16 */
<> 144:ef7eb2e8f9f7 397 /* <2=> / 256 */
<> 144:ef7eb2e8f9f7 398 /* <3=> Undefined! */
<> 144:ef7eb2e8f9f7 399 /* <o.1> TimerSize: Timer Size */
<> 144:ef7eb2e8f9f7 400 /* <0=> 16-bit counter */
<> 144:ef7eb2e8f9f7 401 /* <1=> 32-bit counter */
<> 144:ef7eb2e8f9f7 402 /* <o.0> OneShot: One-shoot mode */
<> 144:ef7eb2e8f9f7 403 /* <0=> Wrapping mode */
<> 144:ef7eb2e8f9f7 404 /* <1=> One-shot mode */
<> 144:ef7eb2e8f9f7 405 /* </h> */
<> 144:ef7eb2e8f9f7 406 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
<> 144:ef7eb2e8f9f7 407 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
<> 144:ef7eb2e8f9f7 408 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
<> 144:ef7eb2e8f9f7 409 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
<> 144:ef7eb2e8f9f7 410 } CMSDK_DUALTIMER_SINGLE_TypeDef;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 #define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 413 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /*!< CMSDK_DUALTIMER LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 #define CMSDK_DUALTIMER_VALUE_Pos 0 /*!< CMSDK_DUALTIMER VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 416 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /*!< CMSDK_DUALTIMER VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
<> 144:ef7eb2e8f9f7 419 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
<> 144:ef7eb2e8f9f7 422 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
<> 144:ef7eb2e8f9f7 425 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
<> 144:ef7eb2e8f9f7 428 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
<> 144:ef7eb2e8f9f7 431 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
<> 144:ef7eb2e8f9f7 434 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /*!< CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER INTCLR: INT Clear Position */
<> 144:ef7eb2e8f9f7 437 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /*!< CMSDK_DUALTIMER INTCLR: INT Clear Mask */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 440 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 443 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER BGLOAD: Background Load Position */
<> 144:ef7eb2e8f9f7 446 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /*!< CMSDK_DUALTIMER BGLOAD: Background Load Mask */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /*@}*/ /* end of group CMSDK_DualTIMER */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
<> 144:ef7eb2e8f9f7 452 /** @addtogroup CMSDK_GPIO CMSDK GPIO
<> 144:ef7eb2e8f9f7 453 @{
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 typedef struct
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
<> 144:ef7eb2e8f9f7 458 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
<> 144:ef7eb2e8f9f7 459 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 460 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
<> 144:ef7eb2e8f9f7 462 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
<> 144:ef7eb2e8f9f7 463 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
<> 144:ef7eb2e8f9f7 464 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
<> 144:ef7eb2e8f9f7 465 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
<> 144:ef7eb2e8f9f7 466 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
<> 144:ef7eb2e8f9f7 467 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
<> 144:ef7eb2e8f9f7 468 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
<> 144:ef7eb2e8f9f7 469 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
<> 144:ef7eb2e8f9f7 470 union {
<> 144:ef7eb2e8f9f7 471 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
<> 144:ef7eb2e8f9f7 472 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 473 };
<> 144:ef7eb2e8f9f7 474 uint32_t RESERVED1[241];
<> 144:ef7eb2e8f9f7 475 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
<> 144:ef7eb2e8f9f7 476 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
<> 144:ef7eb2e8f9f7 477 } CMSDK_GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 #define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATA: DATA Position */
<> 144:ef7eb2e8f9f7 480 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 #define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */
<> 144:ef7eb2e8f9f7 483 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #define CMSDK_GPIO_OUTENSET_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
<> 144:ef7eb2e8f9f7 486 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 #define CMSDK_GPIO_OUTENCLR_Pos 0 /*!< CMSDK_GPIO OUTEN: OUTEN Position */
<> 144:ef7eb2e8f9f7 489 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /*!< CMSDK_GPIO OUTEN: OUTEN Mask */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
<> 144:ef7eb2e8f9f7 492 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Position */
<> 144:ef7eb2e8f9f7 495 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /*!< CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 #define CMSDK_GPIO_INTENSET_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 498 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #define CMSDK_GPIO_INTENCLR_Pos 0 /*!< CMSDK_GPIO INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 501 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /*!< CMSDK_GPIO INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 #define CMSDK_GPIO_INTTYPESET_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
<> 144:ef7eb2e8f9f7 504 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /*!< CMSDK_GPIO INTTYPE: INTTYPE Position */
<> 144:ef7eb2e8f9f7 507 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /*!< CMSDK_GPIO INTTYPE: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 #define CMSDK_GPIO_INTPOLSET_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
<> 144:ef7eb2e8f9f7 510 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /*!< CMSDK_GPIO INTPOL: INTPOL Position */
<> 144:ef7eb2e8f9f7 513 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /*!< CMSDK_GPIO INTPOL: INTPOL Mask */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #define CMSDK_GPIO_INTSTATUS_Pos 0 /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Position */
<> 144:ef7eb2e8f9f7 516 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /*!< CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 #define CMSDK_GPIO_INTCLEAR_Pos 0 /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Position */
<> 144:ef7eb2e8f9f7 519 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /*!< CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
<> 144:ef7eb2e8f9f7 522 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /*!< CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
<> 144:ef7eb2e8f9f7 525 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /*!< CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /*@}*/ /* end of group CMSDK_GPIO */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /*------------- System Control (SYSCON) --------------------------------------*/
<> 144:ef7eb2e8f9f7 531 /** @addtogroup CMSDK_SYSCON CMSDK System Control
<> 144:ef7eb2e8f9f7 532 @{
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534 typedef struct
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
<> 144:ef7eb2e8f9f7 537 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
<> 144:ef7eb2e8f9f7 538 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
<> 144:ef7eb2e8f9f7 539 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
<> 144:ef7eb2e8f9f7 540 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
<> 144:ef7eb2e8f9f7 541 } CMSDK_SYSCON_TypeDef;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 #define CMSDK_SYSCON_REMAP_Pos 0
<> 144:ef7eb2e8f9f7 544 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /*!< CMSDK_SYSCON MEME_CTRL: REMAP Mask */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
<> 144:ef7eb2e8f9f7 547 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /*!< CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
<> 144:ef7eb2e8f9f7 550 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /*!< CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
<> 144:ef7eb2e8f9f7 553 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /*!< CMSDK_SYSCON EMICTRL: SIZE Mask */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
<> 144:ef7eb2e8f9f7 556 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /*!< CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
<> 144:ef7eb2e8f9f7 559 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
<> 144:ef7eb2e8f9f7 562 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /*!< CMSDK_SYSCON EMICTRL: READCYCLE Mask */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
<> 144:ef7eb2e8f9f7 565 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
<> 144:ef7eb2e8f9f7 568 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /*!< CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
<> 144:ef7eb2e8f9f7 571 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /*!< CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /*@}*/ /* end of group CMSDK_SYSCON */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /*------------- PL230 uDMA (PL230) --------------------------------------*/
<> 144:ef7eb2e8f9f7 576 /** @addtogroup CMSDK_PL230 CMSDK uDMA controller
<> 144:ef7eb2e8f9f7 577 @{
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 typedef struct
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
<> 144:ef7eb2e8f9f7 582 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
<> 144:ef7eb2e8f9f7 583 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
<> 144:ef7eb2e8f9f7 584 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
<> 144:ef7eb2e8f9f7 585 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
<> 144:ef7eb2e8f9f7 586 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
<> 144:ef7eb2e8f9f7 587 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
<> 144:ef7eb2e8f9f7 588 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
<> 144:ef7eb2e8f9f7 589 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
<> 144:ef7eb2e8f9f7 590 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
<> 144:ef7eb2e8f9f7 591 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
<> 144:ef7eb2e8f9f7 592 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
<> 144:ef7eb2e8f9f7 593 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
<> 144:ef7eb2e8f9f7 594 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
<> 144:ef7eb2e8f9f7 595 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
<> 144:ef7eb2e8f9f7 596 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
<> 144:ef7eb2e8f9f7 597 uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 598 __IO uint32_t ERR_CLR; /* Offset: 0x04C (R/W) Bus Error Clear Register */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 } CMSDK_PL230_TypeDef;
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #define PL230_DMA_CHNL_BITS 0
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA STATUS: MSTREN Position */
<> 144:ef7eb2e8f9f7 605 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /*!< CMSDK_PL230 DMA STATUS: MSTREN Mask */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /*!< CMSDK_PL230 DMA STATUS: STATE Position */
<> 144:ef7eb2e8f9f7 608 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /*!< CMSDK_PL230 DMA STATUS: STATE Mask */
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
<> 144:ef7eb2e8f9f7 611 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
<> 144:ef7eb2e8f9f7 614 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /*!< CMSDK_PL230 DMA CFG: MSTREN Position */
<> 144:ef7eb2e8f9f7 617 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /*!< CMSDK_PL230 DMA CFG: MSTREN Mask */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< CMSDK_PL230 DMA CFG: CPCCACHE Position */
<> 144:ef7eb2e8f9f7 620 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /*!< CMSDK_PL230 DMA CFG: CPCCACHE Mask */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< CMSDK_PL230 DMA CFG: CPCBUF Position */
<> 144:ef7eb2e8f9f7 623 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /*!< CMSDK_PL230 DMA CFG: CPCBUF Mask */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< CMSDK_PL230 DMA CFG: CPCPRIV Position */
<> 144:ef7eb2e8f9f7 626 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /*!< CMSDK_PL230 DMA CFG: CPCPRIV Mask */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< CMSDK_PL230 STATUS: BASE_PTR Position */
<> 144:ef7eb2e8f9f7 629 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: BASE_PTR Mask */
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< CMSDK_PL230 STATUS: MSTREN Position */
<> 144:ef7eb2e8f9f7 632 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< CMSDK_PL230 STATUS: MSTREN Mask */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
<> 144:ef7eb2e8f9f7 635 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
<> 144:ef7eb2e8f9f7 638 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /*!< CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: SET Position */
<> 144:ef7eb2e8f9f7 641 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: SET Mask */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_USEBURST: CLR Position */
<> 144:ef7eb2e8f9f7 644 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /*!< CMSDK_PL230 CHNL_USEBURST: CLR Mask */
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Position */
<> 144:ef7eb2e8f9f7 647 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
<> 144:ef7eb2e8f9f7 650 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: SET Position */
<> 144:ef7eb2e8f9f7 653 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: SET Mask */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_ENABLE: CLR Position */
<> 144:ef7eb2e8f9f7 656 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /*!< CMSDK_PL230 CHNL_ENABLE: CLR Mask */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Position */
<> 144:ef7eb2e8f9f7 659 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
<> 144:ef7eb2e8f9f7 662 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: SET Position */
<> 144:ef7eb2e8f9f7 665 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: SET Mask */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Position */
<> 144:ef7eb2e8f9f7 668 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /*!< CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 #define CMSDK_PL230_ERR_CLR_Pos 0 /*!< CMSDK_PL230 ERR: CLR Position */
<> 144:ef7eb2e8f9f7 671 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /*!< CMSDK_PL230 ERR: CLR Mask */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /*@}*/ /* end of group CMSDK_PL230 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /*------------- PrimeCell UART (PL110) --------------------------------------*/
<> 144:ef7eb2e8f9f7 678 /** @addtogroup CMSDK_PL110 CMSDK PrimeCell UART
<> 144:ef7eb2e8f9f7 679 @{
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 typedef struct
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 __IO uint32_t UARTDR; // <h> Data
<> 144:ef7eb2e8f9f7 685 // <o.11> OE: Overrun error <r>
<> 144:ef7eb2e8f9f7 686 // <o.10> BE: Break error <r>
<> 144:ef7eb2e8f9f7 687 // <o.9> PE: Parity error <r>
<> 144:ef7eb2e8f9f7 688 // <o.8> FE: Framing error <r>
<> 144:ef7eb2e8f9f7 689 // <o.0..7> DATA: Received or Transmitting data (0..255)
<> 144:ef7eb2e8f9f7 690 // </h>
<> 144:ef7eb2e8f9f7 691 union {
<> 144:ef7eb2e8f9f7 692 __I uint32_t UARTRSR; // <h> Receive Status <r>
<> 144:ef7eb2e8f9f7 693 // <o.3> OE: Overrun error <r>
<> 144:ef7eb2e8f9f7 694 // <o.2> BE: Break error <r>
<> 144:ef7eb2e8f9f7 695 // <o.1> PE: Parity error <r>
<> 144:ef7eb2e8f9f7 696 // <o.0> FE: Framing error <r>
<> 144:ef7eb2e8f9f7 697 // </h>
<> 144:ef7eb2e8f9f7 698 __O uint32_t UARTECR; // <h> Error Clear <w>
<> 144:ef7eb2e8f9f7 699 // <o.3> OE: Overrun error <w>
<> 144:ef7eb2e8f9f7 700 // <o.2> BE: Break error <w>
<> 144:ef7eb2e8f9f7 701 // <o.1> PE: Parity error <w>
<> 144:ef7eb2e8f9f7 702 // <o.0> FE: Framing error <w>
<> 144:ef7eb2e8f9f7 703 // </h>
<> 144:ef7eb2e8f9f7 704 };
<> 144:ef7eb2e8f9f7 705 uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 706 __IO uint32_t UARTFR; // <h> Flags <r>
<> 144:ef7eb2e8f9f7 707 // <o.8> RI: Ring indicator <r>
<> 144:ef7eb2e8f9f7 708 // <o.7> TXFE: Transmit FIFO empty <r>
<> 144:ef7eb2e8f9f7 709 // <o.6> RXFF: Receive FIFO full <r>
<> 144:ef7eb2e8f9f7 710 // <o.5> TXFF: Transmit FIFO full <r>
<> 144:ef7eb2e8f9f7 711 // <o.4> RXFE: Receive FIFO empty <r>
<> 144:ef7eb2e8f9f7 712 // <o.3> BUSY: UART busy <r>
<> 144:ef7eb2e8f9f7 713 // <o.2> DCD: Data carrier detect <r>
<> 144:ef7eb2e8f9f7 714 // <o.1> DSR: Data set ready <r>
<> 144:ef7eb2e8f9f7 715 // <o.0> CTS: Clear to send <r>
<> 144:ef7eb2e8f9f7 716 // </h>
<> 144:ef7eb2e8f9f7 717 uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 718 __IO uint32_t UARTILPR; // <h> IrDA Low-power Counter
<> 144:ef7eb2e8f9f7 719 // <o.0..7> ILPDVSR: 8-bit low-power divisor value (0..255)
<> 144:ef7eb2e8f9f7 720 // </h>
<> 144:ef7eb2e8f9f7 721 __IO uint32_t UARTIBRD; // <h> Integer Baud Rate
<> 144:ef7eb2e8f9f7 722 // <o.0..15> BAUD DIVINT: Integer baud rate divisor (0..65535)
<> 144:ef7eb2e8f9f7 723 // </h>
<> 144:ef7eb2e8f9f7 724 __IO uint32_t UARTFBRD; // <h> Fractional Baud Rate
<> 144:ef7eb2e8f9f7 725 // <o.0..5> BAUD DIVFRAC: Fractional baud rate divisor (0..63)
<> 144:ef7eb2e8f9f7 726 // </h>
<> 144:ef7eb2e8f9f7 727 __IO uint32_t UARTLCR_H; // <h> Line Control
<> 144:ef7eb2e8f9f7 728 // <o.8> SPS: Stick parity select
<> 144:ef7eb2e8f9f7 729 // <o.5..6> WLEN: Word length
<> 144:ef7eb2e8f9f7 730 // <0=> 5 bits
<> 144:ef7eb2e8f9f7 731 // <1=> 6 bits
<> 144:ef7eb2e8f9f7 732 // <2=> 7 bits
<> 144:ef7eb2e8f9f7 733 // <3=> 8 bits
<> 144:ef7eb2e8f9f7 734 // <o.4> FEN: Enable FIFOs
<> 144:ef7eb2e8f9f7 735 // <o.3> STP2: Two stop bits select
<> 144:ef7eb2e8f9f7 736 // <o.2> EPS: Even parity select
<> 144:ef7eb2e8f9f7 737 // <o.1> PEN: Parity enable
<> 144:ef7eb2e8f9f7 738 // <o.0> BRK: Send break
<> 144:ef7eb2e8f9f7 739 // </h>
<> 144:ef7eb2e8f9f7 740 __IO uint32_t UARTCR; // <h> Control
<> 144:ef7eb2e8f9f7 741 // <o.15> CTSEn: CTS hardware flow control enable
<> 144:ef7eb2e8f9f7 742 // <o.14> RTSEn: RTS hardware flow control enable
<> 144:ef7eb2e8f9f7 743 // <o.13> Out2: Complement of Out2 modem status output
<> 144:ef7eb2e8f9f7 744 // <o.12> Out1: Complement of Out1 modem status output
<> 144:ef7eb2e8f9f7 745 // <o.11> RTS: Request to send
<> 144:ef7eb2e8f9f7 746 // <o.10> DTR: Data transmit ready
<> 144:ef7eb2e8f9f7 747 // <o.9> RXE: Receive enable
<> 144:ef7eb2e8f9f7 748 // <o.8> TXE: Transmit enable
<> 144:ef7eb2e8f9f7 749 // <o.7> LBE: Loop-back enable
<> 144:ef7eb2e8f9f7 750 // <o.2> SIRLP: IrDA SIR low power mode
<> 144:ef7eb2e8f9f7 751 // <o.1> SIREN: SIR enable
<> 144:ef7eb2e8f9f7 752 // <o.0> UARTEN: UART enable
<> 144:ef7eb2e8f9f7 753 // </h>
<> 144:ef7eb2e8f9f7 754 __IO uint32_t UARTIFLS; // <h> Interrupt FIFO Level Select
<> 144:ef7eb2e8f9f7 755 // <o.3..5> RXIFLSEL: Receive interrupt FIFO level select
<> 144:ef7eb2e8f9f7 756 // <0=> >= 1/8 full
<> 144:ef7eb2e8f9f7 757 // <1=> >= 1/4 full
<> 144:ef7eb2e8f9f7 758 // <2=> >= 1/2 full
<> 144:ef7eb2e8f9f7 759 // <3=> >= 3/4 full
<> 144:ef7eb2e8f9f7 760 // <4=> >= 7/8 full
<> 144:ef7eb2e8f9f7 761 // <5=> reserved
<> 144:ef7eb2e8f9f7 762 // <6=> reserved
<> 144:ef7eb2e8f9f7 763 // <7=> reserved
<> 144:ef7eb2e8f9f7 764 // <o.0..2> TXIFLSEL: Transmit interrupt FIFO level select
<> 144:ef7eb2e8f9f7 765 // <0=> <= 1/8 full
<> 144:ef7eb2e8f9f7 766 // <1=> <= 1/4 full
<> 144:ef7eb2e8f9f7 767 // <2=> <= 1/2 full
<> 144:ef7eb2e8f9f7 768 // <3=> <= 3/4 full
<> 144:ef7eb2e8f9f7 769 // <4=> <= 7/8 full
<> 144:ef7eb2e8f9f7 770 // <5=> reserved
<> 144:ef7eb2e8f9f7 771 // <6=> reserved
<> 144:ef7eb2e8f9f7 772 // <7=> reserved
<> 144:ef7eb2e8f9f7 773 // </h>
<> 144:ef7eb2e8f9f7 774 __IO uint32_t UARTIMSC; // <h> Interrupt Mask Set / Clear
<> 144:ef7eb2e8f9f7 775 // <o.10> OEIM: Overrun error interrupt mask
<> 144:ef7eb2e8f9f7 776 // <o.9> BEIM: Break error interrupt mask
<> 144:ef7eb2e8f9f7 777 // <o.8> PEIM: Parity error interrupt mask
<> 144:ef7eb2e8f9f7 778 // <o.7> FEIM: Framing error interrupt mask
<> 144:ef7eb2e8f9f7 779 // <o.6> RTIM: Receive interrupt mask
<> 144:ef7eb2e8f9f7 780 // <o.5> TXIM: Transmit interrupt mask
<> 144:ef7eb2e8f9f7 781 // <o.4> RXIM: Receive interrupt mask
<> 144:ef7eb2e8f9f7 782 // <o.3> DSRMIM: nUARTDSR modem interrupt mask
<> 144:ef7eb2e8f9f7 783 // <o.2> DCDMIM: nUARTDCD modem interrupt mask
<> 144:ef7eb2e8f9f7 784 // <o.1> CTSMIM: nUARTCTS modem interrupt mask
<> 144:ef7eb2e8f9f7 785 // <o.0> RIMIM: nUARTRI modem interrupt mask
<> 144:ef7eb2e8f9f7 786 // </h>
<> 144:ef7eb2e8f9f7 787 __IO uint32_t UARTRIS; // <h> Raw Interrupt Status <r>
<> 144:ef7eb2e8f9f7 788 // <o.10> OERIS: Overrun error interrupt status <r>
<> 144:ef7eb2e8f9f7 789 // <o.9> BERIS: Break error interrupt status <r>
<> 144:ef7eb2e8f9f7 790 // <o.8> PERIS: Parity error interrupt status <r>
<> 144:ef7eb2e8f9f7 791 // <o.7> FERIS: Framing error interrupt status <r>
<> 144:ef7eb2e8f9f7 792 // <o.6> RTRIS: Receive timeout interrupt status <r>
<> 144:ef7eb2e8f9f7 793 // <o.5> TXRIS: Transmit interrupt status <r>
<> 144:ef7eb2e8f9f7 794 // <o.4> RXRIS: Receive interrupt status <r>
<> 144:ef7eb2e8f9f7 795 // <o.3> DSRRMIS: nUARTDSR modem interrupt status <r>
<> 144:ef7eb2e8f9f7 796 // <o.2> DCDRMIS: nUARTDCD modem interrupt status <r>
<> 144:ef7eb2e8f9f7 797 // <o.1> CTSRMIS: nUARTCTS modem interrupt status <r>
<> 144:ef7eb2e8f9f7 798 // <o.0> RIRMIS: nUARTRI modem interrupt status <r>
<> 144:ef7eb2e8f9f7 799 // </h>
<> 144:ef7eb2e8f9f7 800 __IO uint32_t UARTMIS; // <h> Masked Interrupt Status <r>
<> 144:ef7eb2e8f9f7 801 // <o.10> OEMIS: Overrun error masked interrupt status <r>
<> 144:ef7eb2e8f9f7 802 // <o.9> BEMIS: Break error masked interrupt status <r>
<> 144:ef7eb2e8f9f7 803 // <o.8> PEMIS: Parity error masked interrupt status <r>
<> 144:ef7eb2e8f9f7 804 // <o.7> FEMIS: Framing error masked interrupt status <r>
<> 144:ef7eb2e8f9f7 805 // <o.6> RTMIS: Receive timeout masked interrupt status <r>
<> 144:ef7eb2e8f9f7 806 // <o.5> TXMIS: Transmit masked interrupt status <r>
<> 144:ef7eb2e8f9f7 807 // <o.4> RXMIS: Receive masked interrupt status <r>
<> 144:ef7eb2e8f9f7 808 // <o.3> DSRMMIS: nUARTDSR modem masked interrupt status <r>
<> 144:ef7eb2e8f9f7 809 // <o.2> DCDMMIS: nUARTDCD modem masked interrupt status <r>
<> 144:ef7eb2e8f9f7 810 // <o.1> CTSMMIS: nUARTCTS modem masked interrupt status <r>
<> 144:ef7eb2e8f9f7 811 // <o.0> RIMMIS: nUARTRI modem masked interrupt status <r>
<> 144:ef7eb2e8f9f7 812 // </h>
<> 144:ef7eb2e8f9f7 813 __O uint32_t UARTICR; // <h> Interrupt Clear <w>
<> 144:ef7eb2e8f9f7 814 // <o.10> OEIC: Overrun error interrupt clear <w>
<> 144:ef7eb2e8f9f7 815 // <o.9> BEIC: Break error interrupt clear <w>
<> 144:ef7eb2e8f9f7 816 // <o.8> PEIC: Parity error interrupt clear <w>
<> 144:ef7eb2e8f9f7 817 // <o.7> FEIC: Framing error interrupt clear <w>
<> 144:ef7eb2e8f9f7 818 // <o.6> RTIC: Receive timeout interrupt clear <w>
<> 144:ef7eb2e8f9f7 819 // <o.5> TXIC: Transmit interrupt clear <w>
<> 144:ef7eb2e8f9f7 820 // <o.4> RXIC: Receive interrupt clear <w>
<> 144:ef7eb2e8f9f7 821 // <o.3> DSRMIC: nUARTDSR modem interrupt clear <w>
<> 144:ef7eb2e8f9f7 822 // <o.2> DCDMIC: nUARTDCD modem interrupt clear <w>
<> 144:ef7eb2e8f9f7 823 // <o.1> CTSMIC: nUARTCTS modem interrupt clear <w>
<> 144:ef7eb2e8f9f7 824 // <o.0> RIMIC: nUARTRI modem interrupt clear <w>
<> 144:ef7eb2e8f9f7 825 // </h>
<> 144:ef7eb2e8f9f7 826 __IO uint32_t UARTDMACR; // <h> DMA Control
<> 144:ef7eb2e8f9f7 827 // <o.2> DMAONERR: DMA on error
<> 144:ef7eb2e8f9f7 828 // <o.1> TXDMAE: Transmit DMA enable
<> 144:ef7eb2e8f9f7 829 // <o.0> RXDMAE: Receive DMA enable
<> 144:ef7eb2e8f9f7 830 // </h>
<> 144:ef7eb2e8f9f7 831 } PL110_UART_TypeDef;
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 #define CMSDK_PL110_DATAOVRRUN_Pos 11 /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Position */
<> 144:ef7eb2e8f9f7 834 #define CMSDK_PL110_DATAOVRRUN_Msk (0x1ul << CMSDK_PL110_DATAOVRRUN_Pos) /*!< CMSDK_PL110 DATAOVRRUN: Data Overrun Mask */
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 #define CMSDK_PL110_DATABREAKERR_Pos 10 /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Position */
<> 144:ef7eb2e8f9f7 837 #define CMSDK_PL110_DATABREAKERR_Msk (0x1ul << CMSDK_PL110_DATABREAKERR_Pos) /*!< CMSDK_PL110 DATABREAKERR: Data Break Error Mask */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 #define CMSDK_PL110_DATAPARITYERR_Pos 9 /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Position */
<> 144:ef7eb2e8f9f7 840 #define CMSDK_PL110_DATAPARITYERR_Msk (0x1ul << CMSDK_PL110_DATAPARITYERR_Pos) /*!< CMSDK_PL110 DATAPARITYERR: Data Parity Error Mask */
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 #define CMSDK_PL110_DATAFRAMEERR_Pos 8 /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Position */
<> 144:ef7eb2e8f9f7 843 #define CMSDK_PL110_DATAFRAMEERR_Msk (0x1ul << CMSDK_PL110_DATAFRAMEERR_Pos) /*!< CMSDK_PL110 DATAFRAMEERR: Data Frame Error Mask */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 #define CMSDK_PL110_RECOVRRUN_Pos 3 /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Position */
<> 144:ef7eb2e8f9f7 846 #define CMSDK_PL110_RECOVRRUN_Msk (0x1ul << CMSDK_PL110_RECOVRRUN_Pos) /*!< CMSDK_PL110 RECOVRRUN: Receive Overrun Mask */
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 #define CMSDK_PL110_RECBREAKERR_Pos 2 /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Position */
<> 144:ef7eb2e8f9f7 849 #define CMSDK_PL110_RECBREAKERR_Msk (0x1ul << CMSDK_PL110_RECBREAKERR_Pos) /*!< CMSDK_PL110 RECBREAKERR: Receive Break Error Mask */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 #define CMSDK_PL110_RECPARITYERR_Pos 1 /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Position */
<> 144:ef7eb2e8f9f7 852 #define CMSDK_PL110_RECPARITYERR_Msk (0x1ul << CMSDK_PL110_RECPARITYERR_Pos) /*!< CMSDK_PL110 RECPARITYERR: Receive Parity Error Mask */
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 #define CMSDK_PL110_RECFRAMEERR_Pos 0 /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Position */
<> 144:ef7eb2e8f9f7 855 #define CMSDK_PL110_RECFRAMEERR_Msk (0x1ul << CMSDK_PL110_RECFRAMEERR_Pos) /*!< CMSDK_PL110 RECFRAMEERR: Receive Frame Error Mask */
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 #define CMSDK_PL110_ERRCLROVRRUN_Pos 3 /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Position */
<> 144:ef7eb2e8f9f7 858 #define CMSDK_PL110_ERRCLROVRRUN_Msk (0x1ul << CMSDK_PL110_ERRCLROVRRUN_Pos) /*!< CMSDK_PL110 ERRCLROVRRUN: Clear Overrun Mask */
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 #define CMSDK_PL110_ERRCLRBREAKERR_Pos 2 /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Position */
<> 144:ef7eb2e8f9f7 861 #define CMSDK_PL110_ERRCLRBREAKERR_Msk (0x1ul << CMSDK_PL110_ERRCLRBREAKERR_Pos) /*!< CMSDK_PL110 ERRCLRBREAKERR: Clear Break Error Mask */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 #define CMSDK_PL110_ERRCLRPARITYERR_Pos 1 /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Position */
<> 144:ef7eb2e8f9f7 864 #define CMSDK_PL110_ERRCLRPARITYERR_Msk (0x1ul << CMSDK_PL110_ERRCLRPARITYERR_Pos) /*!< CMSDK_PL110 ERRCLRPARITYERR: Clear Parity Error Mask */
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 #define CMSDK_PL110_ERRCLRFRAMEERR_Pos 0 /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Position */
<> 144:ef7eb2e8f9f7 867 #define CMSDK_PL110_ERRCLRFRAMEERR_Msk (0x1ul << CMSDK_PL110_ERRCLRFRAMEERR_Pos) /*!< CMSDK_PL110 ERRCLRFRAMEERR: Clear Frame Error Mask */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 #define CMSDK_PL110_FLAG_RINGIND_Pos 8 /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Position */
<> 144:ef7eb2e8f9f7 870 #define CMSDK_PL110_FLAG_RINGIND_Msk (0x1ul << CMSDK_PL110_FLAG_RINGIND_Pos) /*!< CMSDK_PL110 FLAG_RINGIND: Ring Indicator Mask */
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 #define CMSDK_PL110_FLAG_TXFEMPTY_Pos 7 /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Position */
<> 144:ef7eb2e8f9f7 873 #define CMSDK_PL110_FLAG_TXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_TXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_TXFEMPTY: Transmit FIFO Empty Mask */
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 #define CMSDK_PL110_FLAG_RXFFULL_Pos 6 /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Position */
<> 144:ef7eb2e8f9f7 876 #define CMSDK_PL110_FLAG_RXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_RXFFULL_Pos) /*!< CMSDK_PL110 FLAG_RXFFULL: Receive FIFO Full Mask */
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 #define CMSDK_PL110_FLAG_TXFFULL_Pos 5 /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Position */
<> 144:ef7eb2e8f9f7 879 #define CMSDK_PL110_FLAG_TXFFULL_Msk (0x1ul << CMSDK_PL110_FLAG_TXFFULL_Pos) /*!< CMSDK_PL110 FLAG_TXFFULL: Transmit FIFO Full Mask */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 #define CMSDK_PL110_FLAG_RXFEMPTY_Pos 4 /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Position */
<> 144:ef7eb2e8f9f7 882 #define CMSDK_PL110_FLAG_RXFEMPTY_Msk (0x1ul << CMSDK_PL110_FLAG_RXFEMPTY_Pos) /*!< CMSDK_PL110 FLAG_RXFEMPTY: Receive FIFO Empty Mask */
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 #define CMSDK_PL110_FLAG_UARTBUSY_Pos 3 /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Position */
<> 144:ef7eb2e8f9f7 885 #define CMSDK_PL110_FLAG_UARTBUSY_Msk (0x1ul << CMSDK_PL110_FLAG_UARTBUSY_Pos) /*!< CMSDK_PL110 FLAG_UARTBUSY: UART Busy Mask */
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 #define CMSDK_PL110_FLAG_CARRIERDETECT_Pos 2 /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Position */
<> 144:ef7eb2e8f9f7 888 #define CMSDK_PL110_FLAG_CARRIERDETECT_Msk (0x1ul << CMSDK_PL110_FLAG_CARRIERDETECT_Pos) /*!< CMSDK_PL110 FLAG_CARRIERDETECT: Carrier Detect Mask */
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 #define CMSDK_PL110_FLAG_DATASETREADY_Pos 1 /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Position */
<> 144:ef7eb2e8f9f7 891 #define CMSDK_PL110_FLAG_DATASETREADY_Msk (0x1ul << CMSDK_PL110_FLAG_DATASETREADY_Pos) /*!< CMSDK_PL110 FLAG_DATASETREADY: Data Set Ready Mask */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 #define CMSDK_PL110_FLAG_CLR2SEND_Pos 0 /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Position */
<> 144:ef7eb2e8f9f7 894 #define CMSDK_PL110_FLAG_CLR2SEND_Msk (0x1ul << CMSDK_PL110_FLAG_CLR2SEND_Pos) /*!< CMSDK_PL110 FLAG_CLR2SEND: Clear To Send Mask */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 #define CMSDK_PL110_IRDALOWPOWERCOUNT_Pos 0 /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Position */
<> 144:ef7eb2e8f9f7 897 #define CMSDK_PL110_IRDALOWPOWERCOUNT_Msk (0xFFul << CMSDK_PL110_IRDALOWPOWERCOUNT_Pos) /*!< CMSDK_PL110 IRDALOWPOWERCOUNT: IrDA 8-bit low-power divisor value Mask */
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 #define CMSDK_PL110_INTDIVIDER_Pos 0 /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Position */
<> 144:ef7eb2e8f9f7 900 #define CMSDK_PL110_INTDIVIDER_Msk (0xFFFFul << CMSDK_PL110_INTDIVIDER_Pos) /*!< CMSDK_PL110 INTDIVIDER: Integer Divider Mask */
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 #define CMSDK_PL110_FRACTDIVIDER_Pos 0 /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Position */
<> 144:ef7eb2e8f9f7 903 #define CMSDK_PL110_FRACTDIVIDER_Msk (0x3Ful << CMSDK_PL110_FRACTDIVIDER_Pos) /*!< CMSDK_PL110 FRACTDIVIDER: Fractional Divider Mask */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #define CMSDK_PL110_STICKPARITYSEL_Pos 8 /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Position */
<> 144:ef7eb2e8f9f7 906 #define CMSDK_PL110_STICKPARITYSEL_Msk (0x1ul << CMSDK_PL110_STICKPARITYSEL_Pos) /*!< CMSDK_PL110 STICKPARITYSEL: Stick parity select Mask */
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 #define CMSDK_PL110_WORDLEN_Pos 5 /*!< CMSDK_PL110 WORDLEN: Word Length Select Position */
<> 144:ef7eb2e8f9f7 909 #define CMSDK_PL110_WORDLEN_Msk (0x3ul << CMSDK_PL110_WORDLEN_Pos) /*!< CMSDK_PL110 WORDLEN: Word Length Select Mask */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 #define CMSDK_PL110_ENFIFOS_Pos 4 /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Position */
<> 144:ef7eb2e8f9f7 912 #define CMSDK_PL110_ENFIFOS_Msk (0x1ul << CMSDK_PL110_ENFIFOS_Pos) /*!< CMSDK_PL110 ENFIFOS: Enable FIFOs Mask */
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 #define CMSDK_PL110_2STOPBITS_Pos 3 /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Position */
<> 144:ef7eb2e8f9f7 915 #define CMSDK_PL110_2STOPBITS_Msk (0x1ul << CMSDK_PL110_2STOPBITS_Pos) /*!< CMSDK_PL110 2STOPBITS: Two Stop Bits Select Mask */
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 #define CMSDK_PL110_EVENPARITY_Pos 2 /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Position */
<> 144:ef7eb2e8f9f7 918 #define CMSDK_PL110_EVENPARITY_Msk (0x1ul << CMSDK_PL110_EVENPARITY_Pos) /*!< CMSDK_PL110 EVENPARITY: Even Parity Select Mask */
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 #define CMSDK_PL110_PARITYEN_Pos 1 /*!< CMSDK_PL110 PARITYEN: Parity Enable Position */
<> 144:ef7eb2e8f9f7 921 #define CMSDK_PL110_PARITYEN_Msk (0x1ul << CMSDK_PL110_PARITYEN_Pos) /*!< CMSDK_PL110 PARITYEN: Parity Enable Mask */
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 #define CMSDK_PL110_SENDBREAK_Pos 0 /*!< CMSDK_PL110 SENDBREAK: Send Break Position */
<> 144:ef7eb2e8f9f7 924 #define CMSDK_PL110_SENDBREAK_Msk (0x1ul << CMSDK_PL110_SENDBREAK_Pos) /*!< CMSDK_PL110 SENDBREAK: Send Break Mask */
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 #define CMSDK_PL110_CTS_FLOWCTRL_Pos 15 /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Position */
<> 144:ef7eb2e8f9f7 927 #define CMSDK_PL110_CTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_CTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 CTS_FLOWCTRL: Enable CTS Flow Control Mask */
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 #define CMSDK_PL110_RTS_FLOWCTRL_Pos 14 /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Position */
<> 144:ef7eb2e8f9f7 930 #define CMSDK_PL110_RTS_FLOWCTRL_Msk (0x1ul << CMSDK_PL110_RTS_FLOWCTRL_Pos) /*!< CMSDK_PL110 RTS_FLOWCTRL: Enable RTS Flow Control Mask */
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 #define CMSDK_PL110_OUT2_Pos 13 /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Position */
<> 144:ef7eb2e8f9f7 933 #define CMSDK_PL110_OUT2_Msk (0x1ul << CMSDK_PL110_OUT2_Pos) /*!< CMSDK_PL110 OUT2: Complement of Out2 modem status output Mask */
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 #define CMSDK_PL110_OUT1_Pos 12 /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Position */
<> 144:ef7eb2e8f9f7 936 #define CMSDK_PL110_OUT1_Msk (0x1ul << CMSDK_PL110_OUT1_Pos) /*!< CMSDK_PL110 OUT1: Complement of Out1 modem status output Mask */
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 #define CMSDK_PL110_REQ2SEND_Pos 11 /*!< CMSDK_PL110 REQ2SEND: Request To Send Position */
<> 144:ef7eb2e8f9f7 939 #define CMSDK_PL110_REQ2SEND_Msk (0x1ul << CMSDK_PL110_REQ2SEND_Pos) /*!< CMSDK_PL110 REQ2SEND: Request To Send Mask */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #define CMSDK_PL110_DATATRANSREADY_Pos 10 /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Position */
<> 144:ef7eb2e8f9f7 942 #define CMSDK_PL110_DATATRANSREADY_Msk (0x1ul << CMSDK_PL110_DATATRANSREADY_Pos) /*!< CMSDK_PL110 DATATRANSREADY: Transmit Ready Mask */
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 #define CMSDK_PL110_RXEN_Pos 9 /*!< CMSDK_PL110 RXEN: Receive Enable Position */
<> 144:ef7eb2e8f9f7 945 #define CMSDK_PL110_RXEN_Msk (0x1ul << CMSDK_PL110_RXEN_Pos) /*!< CMSDK_PL110 RXEN: Receive Enable Mask */
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 #define CMSDK_PL110_TXEN_Pos 8 /*!< CMSDK_PL110 TXEN: Transmit Enable Position */
<> 144:ef7eb2e8f9f7 948 #define CMSDK_PL110_TXEN_Msk (0x1ul << CMSDK_PL110_TXEN_Pos) /*!< CMSDK_PL110 TXEN: Transmit Enable Mask */
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 #define CMSDK_PL110_LOOPBACKEN_Pos 7 /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Position */
<> 144:ef7eb2e8f9f7 951 #define CMSDK_PL110_LOOPBACKEN_Msk (0x1ul << CMSDK_PL110_LOOPBACKEN_Pos) /*!< CMSDK_PL110 LOOPBACKEN: Loopback Enable Mask */
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 #define CMSDK_PL110_IRDASIRLPM_Pos 2 /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Position */
<> 144:ef7eb2e8f9f7 954 #define CMSDK_PL110_IRDASIRLPM_Msk (0x1ul << CMSDK_PL110_IRDASIRLPM_Pos) /*!< CMSDK_PL110 IRDASIRLPM: IRDA SIR Low Power Mask */
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 #define CMSDK_PL110_SIREN_Pos 1 /*!< CMSDK_PL110 SIREN: SIR Enable Position */
<> 144:ef7eb2e8f9f7 957 #define CMSDK_PL110_SIREN_Msk (0x1ul << CMSDK_PL110_SIREN_Pos) /*!< CMSDK_PL110 SIREN: SIR Enable Mask */
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 #define CMSDK_PL110_UARTEN_Pos 0 /*!< CMSDK_PL110 UARTEN: UART Enable Position */
<> 144:ef7eb2e8f9f7 960 #define CMSDK_PL110_UARTEN_Msk (0x1ul << CMSDK_PL110_UARTEN_Pos) /*!< CMSDK_PL110 UARTEN: UART Enable Mask */
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 #define CMSDK_PL110_RECINTFIFOLEVEL_Pos 3 /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Position */
<> 144:ef7eb2e8f9f7 963 #define CMSDK_PL110_RECINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_RECINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 RECINTFIFOLEVEL: Set Receive Int FIFO Level Mask */
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 #define CMSDK_PL110_TRANSINTFIFOLEVEL_Pos 0 /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Position */
<> 144:ef7eb2e8f9f7 966 #define CMSDK_PL110_TRANSINTFIFOLEVEL_Msk (0x7ul << CMSDK_PL110_TRANSINTFIFOLEVEL_Pos) /*!< CMSDK_PL110 TRANSINTFIFOLEVEL: Set Transmit Int FIFO Level Mask */
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 #define CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Position */
<> 144:ef7eb2e8f9f7 969 #define CMSDK_PL110_SETMASK_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 SETMASK_OVRRUNERRINT: Set Overrun Error Int Mask Mask */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 #define CMSDK_PL110_SETMASK_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Position */
<> 144:ef7eb2e8f9f7 972 #define CMSDK_PL110_SETMASK_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_BREAKERRINT_Pos) /*!< CMSDK_PL110 SETMASK_BREAKERRINT: Set Break Error Int Mask Mask */
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 #define CMSDK_PL110_SETMASK_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Position */
<> 144:ef7eb2e8f9f7 975 #define CMSDK_PL110_SETMASK_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_PARITYERRINT_Pos) /*!< CMSDK_PL110 SETMASK_PARITYERRINT: Set Parity Error Int Mask Mask */
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 #define CMSDK_PL110_SETMASK_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Position */
<> 144:ef7eb2e8f9f7 978 #define CMSDK_PL110_SETMASK_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_SETMASK_FRAMEERRINT_Pos) /*!< CMSDK_PL110 SETMASK_FRAMEERRINT: Set Frame Error Int Mask Mask */
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 #define CMSDK_PL110_SETMASK_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Position */
<> 144:ef7eb2e8f9f7 981 #define CMSDK_PL110_SETMASK_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECTRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_RECTRANSINT: Set Transmit Receive Comb Int Mask Mask */
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 #define CMSDK_PL110_SETMASK_TRANSINT_Pos 5 /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Position */
<> 144:ef7eb2e8f9f7 984 #define CMSDK_PL110_SETMASK_TRANSINT_Msk (0x1ul << CMSDK_PL110_SETMASK_TRANSINT_Pos) /*!< CMSDK_PL110 SETMASK_TRANSINT: Set Transmit Int Mask Mask */
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 #define CMSDK_PL110_SETMASK_RECINT_Pos 4 /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Position */
<> 144:ef7eb2e8f9f7 987 #define CMSDK_PL110_SETMASK_RECINT_Msk (0x1ul << CMSDK_PL110_SETMASK_RECINT_Pos) /*!< CMSDK_PL110 SETMASK_RECINT: Set Receive Int Mask Mask */
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 #define CMSDK_PL110_SETMASK_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Position */
<> 144:ef7eb2e8f9f7 990 #define CMSDK_PL110_SETMASK_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DSRMODINT: Set Data Set Ready Modem Int Mask Mask */
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 #define CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Position */
<> 144:ef7eb2e8f9f7 993 #define CMSDK_PL110_SETMASK_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_DCDMODINT: Set Data Carrier Detect Modem Int Mask Mask */
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 #define CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Position */
<> 144:ef7eb2e8f9f7 996 #define CMSDK_PL110_SETMASK_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_CTSMODINT: Set Clear To Send Modem Int Mask Mask */
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 #define CMSDK_PL110_SETMASK_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Position */
<> 144:ef7eb2e8f9f7 999 #define CMSDK_PL110_SETMASK_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_SETMASK_UART_RIMODINT_Pos) /*!< CMSDK_PL110 SETMASK_UART_RIMODINT: Set nUARTRI Modem Int Mask Mask */
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 #define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask Position */
<> 144:ef7eb2e8f9f7 1002 #define CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_OVRRUNERRINT: Raw Overrun Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 #define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask Position */
<> 144:ef7eb2e8f9f7 1005 #define CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_BREAKERRINT: Raw Break Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 #define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask Position */
<> 144:ef7eb2e8f9f7 1008 #define CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_PARITYERRINT: Raw Parity Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 #define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask Position */
<> 144:ef7eb2e8f9f7 1011 #define CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_FRAMEERRINT: Raw Frame Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 #define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Position */
<> 144:ef7eb2e8f9f7 1014 #define CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECTRANSINT: Raw Transmit Receive Comb Int Status Mask */
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 #define CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Position */
<> 144:ef7eb2e8f9f7 1017 #define CMSDK_PL110_RAWINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_TRANSINT: Raw Transmit Int Status Mask */
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 #define CMSDK_PL110_RAWINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Position */
<> 144:ef7eb2e8f9f7 1020 #define CMSDK_PL110_RAWINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_RECINT: Raw Receive Int Status Mask */
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 #define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 RAWINTSTAT_UART_DSRMODINT: Raw Data Set Ready Int Status Position */
<> 144:ef7eb2e8f9f7 1023 #define CMSDK_PL110_RAWINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UARTD_SRMODINT: Raw Data Set Ready Int Status Mask */
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 #define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Position */
<> 144:ef7eb2e8f9f7 1026 #define CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_DCDMODINT: Raw Data Carrier Detect Int Status Mask */
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 #define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Position */
<> 144:ef7eb2e8f9f7 1029 #define CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_CTSMODINT: Raw Clear To Send Int Status Mask */
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 #define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Position */
<> 144:ef7eb2e8f9f7 1032 #define CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_RAWINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 RAWINTSTAT_UART_RIMODINT: Raw nUARTRI Modem Int Status Mask */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 #define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Position */
<> 144:ef7eb2e8f9f7 1035 #define CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_OVRRUNERRINT: Masked Overrun Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 #define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Position */
<> 144:ef7eb2e8f9f7 1038 #define CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_BREAKERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_BREAKERRINT: Masked Break Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 #define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Position */
<> 144:ef7eb2e8f9f7 1041 #define CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_PARITYERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_PARITYERRINT: Masked Parity Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 #define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Position */
<> 144:ef7eb2e8f9f7 1044 #define CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_FRAMEERRINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_FRAMEERRINT: Masked Frame Error Int Status Mask */
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 #define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Position */
<> 144:ef7eb2e8f9f7 1047 #define CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECTRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECTRANSINT: Masked Transmit Receive Comb Int Status Mask */
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 #define CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos 5 /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Position */
<> 144:ef7eb2e8f9f7 1050 #define CMSDK_PL110_MSKINTSTAT_TRANSINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_TRANSINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_TRANSINT: Masked Transmit Int Status Mask */
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 #define CMSDK_PL110_MSKINTSTAT_RECINT_Pos 4 /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Position */
<> 144:ef7eb2e8f9f7 1053 #define CMSDK_PL110_MSKINTSTAT_RECINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_RECINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_RECINT: Masked Receive Int Status Mask */
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 #define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Position */
<> 144:ef7eb2e8f9f7 1056 #define CMSDK_PL110_MSKINTSTAT_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DSRMODINT: Masked Data Set Ready Int Status Mask */
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 #define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Position */
<> 144:ef7eb2e8f9f7 1059 #define CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_DCDMODINT: Masked Data Carrier Detect Int Status Mask */
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 #define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Position */
<> 144:ef7eb2e8f9f7 1062 #define CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_CTSMODINT: Masked Clear To Send Int Status Mask */
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 #define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Position */
<> 144:ef7eb2e8f9f7 1065 #define CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_MSKINTSTAT_UART_RIMODINT_Pos) /*!< CMSDK_PL110 MSKINTSTAT_UART_RIMODINT: Masked nUARTRI Modem Int Status Mask */
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 #define CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos 10 /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Position */
<> 144:ef7eb2e8f9f7 1068 #define CMSDK_PL110_INTCLR_OVRRUNERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_OVRRUNERRINT_Pos) /*!< CMSDK_PL110 INTCLR_OVRRUNERRINT: Clear Overrun Error Int Mask */
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 #define CMSDK_PL110_INTCLR_BREAKERRINT_Pos 9 /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Position */
<> 144:ef7eb2e8f9f7 1071 #define CMSDK_PL110_INTCLR_BREAKERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_BREAKERRINT_Pos) /*!< CMSDK_PL110 INTCLR_BREAKERRINT: Clear Break Error Int Mask */
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 #define CMSDK_PL110_INTCLR_PARITYERRINT_Pos 8 /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Position */
<> 144:ef7eb2e8f9f7 1074 #define CMSDK_PL110_INTCLR_PARITYERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_PARITYERRINT_Pos) /*!< CMSDK_PL110 INTCLR_PARITYERRINT: Clear Parity Error Int Mask */
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 #define CMSDK_PL110_INTCLR_FRAMEERRINT_Pos 7 /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Position */
<> 144:ef7eb2e8f9f7 1077 #define CMSDK_PL110_INTCLR_FRAMEERRINT_Msk (0x1ul << CMSDK_PL110_INTCLR_FRAMEERRINT_Pos) /*!< CMSDK_PL110 INTCLR_FRAMEERRINT: Clear Frame Error Int Mask */
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 #define CMSDK_PL110_INTCLR_RECTRANSINT_Pos 6 /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Position */
<> 144:ef7eb2e8f9f7 1080 #define CMSDK_PL110_INTCLR_RECTRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECTRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_RECTRANSINT: Clear Receive Transmit Comb Int Mask */
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 #define CMSDK_PL110_INTCLR_TRANSINT_Pos 5 /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Position */
<> 144:ef7eb2e8f9f7 1083 #define CMSDK_PL110_INTCLR_TRANSINT_Msk (0x1ul << CMSDK_PL110_INTCLR_TRANSINT_Pos) /*!< CMSDK_PL110 INTCLR_TRANSINT: Clear Transmit Int Mask */
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 #define CMSDK_PL110_INTCLR_RECINT_Pos 4 /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Position */
<> 144:ef7eb2e8f9f7 1086 #define CMSDK_PL110_INTCLR_RECINT_Msk (0x1ul << CMSDK_PL110_INTCLR_RECINT_Pos) /*!< CMSDK_PL110 INTCLR_RECINT: Clear Receive Int Mask */
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 #define CMSDK_PL110_INTCLR_UART_DSRMODINT_Pos 3 /*!< CMSDK_PL110 INTCLR_UART_DSRMODINT: Clear Data Carrier Detect Int Position */
<> 144:ef7eb2e8f9f7 1089 #define CMSDK_PL110_INTCLR_UART_DSRMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UARTD_SRMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UARTD_SRMODINT: Clear Data Carrier Detect Int Mask */
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 #define CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos 2 /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Position */
<> 144:ef7eb2e8f9f7 1092 #define CMSDK_PL110_INTCLR_UART_DCDMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_DCDMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_DCDMODINT: Clear Data Set Ready Int Mask */
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 #define CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos 1 /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Position */
<> 144:ef7eb2e8f9f7 1095 #define CMSDK_PL110_INTCLR_UART_CTSMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_CTSMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_CTSMODINT: Clear Clear To Sent Int Mask */
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 #define CMSDK_PL110_INTCLR_UART_RIMODINT_Pos 0 /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Position */
<> 144:ef7eb2e8f9f7 1098 #define CMSDK_PL110_INTCLR_UART_RIMODINT_Msk (0x1ul << CMSDK_PL110_INTCLR_UART_RIMODINT_Pos) /*!< CMSDK_PL110 INTCLR_UART_RIMODINT: Clear nUARTRI Modem Int Mask */
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 #define CMSDK_PL110_DMA_ERR_Pos 2 /*!< CMSDK_PL110 DMA_ERR: DMA Error Position */
<> 144:ef7eb2e8f9f7 1101 #define CMSDK_PL110_DMA_ERR_Msk (0x1ul << CMSDK_PL110_DMA_ERR_Pos) /*!< CMSDK_PL110 DMA_ERR: DMA Error Mask */
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 #define CMSDK_PL110_DMA_TRANS_EN_Pos 1 /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Position */
<> 144:ef7eb2e8f9f7 1104 #define CMSDK_PL110_DMA_TRANS_EN_Msk (0x1ul << CMSDK_PL110_DMA_TRANS_EN_Pos) /*!< CMSDK_PL110 DMA_TRANS_EN: DMA Transmit Error Mask */
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 #define CMSDK_PL110_DMA_REC_EN_Pos 0 /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Position */
<> 144:ef7eb2e8f9f7 1107 #define CMSDK_PL110_DMA_REC_EN_Msk (0x1ul << CMSDK_PL110_DMA_REC_EN_Pos) /*!< CMSDK_PL110 DMA_REC_EN: DMA Receive Error Mask */
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /*@}*/ /* end of group CMSDK_PL110 */
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /*------------------- Watchdog ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1113 /** @addtogroup CMSDK_Watchdog CMSDK Watchdog
<> 144:ef7eb2e8f9f7 1114 @{
<> 144:ef7eb2e8f9f7 1115 */
<> 144:ef7eb2e8f9f7 1116 typedef struct
<> 144:ef7eb2e8f9f7 1117 {
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
<> 144:ef7eb2e8f9f7 1120 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
<> 144:ef7eb2e8f9f7 1121 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
<> 144:ef7eb2e8f9f7 1122 /* <o.1> RESEN: Reset enable */
<> 144:ef7eb2e8f9f7 1123 /* <o.0> INTEN: Interrupt enable */
<> 144:ef7eb2e8f9f7 1124 /* </h> */
<> 144:ef7eb2e8f9f7 1125 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
<> 144:ef7eb2e8f9f7 1126 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
<> 144:ef7eb2e8f9f7 1127 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
<> 144:ef7eb2e8f9f7 1128 uint32_t RESERVED0[762];
<> 144:ef7eb2e8f9f7 1129 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
<> 144:ef7eb2e8f9f7 1130 uint32_t RESERVED1[191];
<> 144:ef7eb2e8f9f7 1131 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
<> 144:ef7eb2e8f9f7 1132 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
<> 144:ef7eb2e8f9f7 1133 }CMSDK_WATCHDOG_TypeDef;
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 #define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */
<> 144:ef7eb2e8f9f7 1136 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 #define CMSDK_Watchdog_VALUE_Pos 0 /*!< CMSDK_Watchdog VALUE: VALUE Position */
<> 144:ef7eb2e8f9f7 1139 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /*!< CMSDK_Watchdog VALUE: VALUE Mask */
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
<> 144:ef7eb2e8f9f7 1142 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
<> 144:ef7eb2e8f9f7 1145 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 #define CMSDK_Watchdog_INTCLR_Pos 0 /*!< CMSDK_Watchdog INTCLR: Int Clear Position */
<> 144:ef7eb2e8f9f7 1148 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /*!< CMSDK_Watchdog INTCLR: Int Clear Mask */
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 1151 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 1154 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 #define CMSDK_Watchdog_LOCK_Pos 0 /*!< CMSDK_Watchdog LOCK: LOCK Position */
<> 144:ef7eb2e8f9f7 1157 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /*!< CMSDK_Watchdog LOCK: LOCK Mask */
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
<> 144:ef7eb2e8f9f7 1160 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
<> 144:ef7eb2e8f9f7 1163 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /*@}*/ /* end of group CMSDK_Watchdog */
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /*------------------- PrimeCell APB GPIO --------------------------------------*/
<> 144:ef7eb2e8f9f7 1168 /** @addtogroup CMSDK_PL061 CMSDK APB GPIO
<> 144:ef7eb2e8f9f7 1169 @{
<> 144:ef7eb2e8f9f7 1170 */
<> 144:ef7eb2e8f9f7 1171 typedef struct
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 __IO uint32_t DATA[256];
<> 144:ef7eb2e8f9f7 1175 __IO uint32_t DIR;
<> 144:ef7eb2e8f9f7 1176 __IO uint32_t INTSENSE;
<> 144:ef7eb2e8f9f7 1177 __IO uint32_t INTBOTHEDGE;
<> 144:ef7eb2e8f9f7 1178 __IO uint32_t INTEVENT;
<> 144:ef7eb2e8f9f7 1179 __IO uint32_t INTMASK;
<> 144:ef7eb2e8f9f7 1180 __O uint32_t RAWINTSTAT;
<> 144:ef7eb2e8f9f7 1181 __O uint32_t MASKINTSTAT;
<> 144:ef7eb2e8f9f7 1182 __I uint32_t INTCLR;
<> 144:ef7eb2e8f9f7 1183 __IO uint32_t MODECTRL;
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 }APBGPIO_TypeDef;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 #define CMSDK_PL061_DATA_Pos 0 /*!< CMSDK_PL061 DATA: DATA Position */
<> 144:ef7eb2e8f9f7 1188 #define CMSDK_PL061_DATA_Msk (0xFFFFFFFFul << CMSDK_PL061_LOAD_Pos) /*!< CMSDK_PL061 DATA: DATA Mask */
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 #define CMSDK_PL061_DIR_Pos 0 /*!< CMSDK_PL061 DIR: Data Direction Position */
<> 144:ef7eb2e8f9f7 1191 #define CMSDK_PL061_DIR_Msk (0x1ul << CMSDK_PL061_DIR_Pos) /*!< CMSDK_PL061 DIR: Data Direction Mask */
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 #define CMSDK_PL061_INTSENSE_Pos 0 /*!< CMSDK_PL061 INTSENSE: INT SENSE Position */
<> 144:ef7eb2e8f9f7 1194 #define CMSDK_PL061_INTSENSE_Msk (0x1ul << CMSDK_PL061_INTSENSE_Pos) /*!< CMSDK_PL061 INTSENSE: INT SENSE Mask */
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 #define CMSDK_PL061_INTBOTHEDGE_Pos 0 /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Position */
<> 144:ef7eb2e8f9f7 1197 #define CMSDK_PL061_INTBOTHEDGE_Msk (0x1ul << CMSDK_PL061_INTBOTHEDGE_Pos) /*!< CMSDK_PL061 INTBOTHEDGE: INT BOTH EDGE Mask */
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 #define CMSDK_PL061_INTEVENT_Pos 0 /*!< CMSDK_PL061 INTEVENT: INT EVENT Position */
<> 144:ef7eb2e8f9f7 1200 #define CMSDK_PL061_INTEVENT_Msk (0x1ul << CMSDK_PL061_INTEVENT_Pos) /*!< CMSDK_PL061 INTEVENT: INT EVENT Mask */
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 #define CMSDK_PL061_INTMASK_Pos 0 /*!< CMSDK_PL061 INTMASK: INT MASK Position */
<> 144:ef7eb2e8f9f7 1203 #define CMSDK_PL061_INTMASK_Msk (0x1ul << CMSDK_PL061_INTMASK_Pos) /*!< CMSDK_PL061 INTMASK: INT MASK Mask */
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 #define CMSDK_PL061_RAWINTSTAT_Pos 0 /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Position */
<> 144:ef7eb2e8f9f7 1206 #define CMSDK_PL061_RAWINTSTAT_Msk (0x1ul << CMSDK_PL061_RAWINTSTAT_Pos) /*!< CMSDK_PL061 RAWINTSTAT: Raw Int Status Mask */
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 #define CMSDK_PL061_MASKINTSTAT_Pos 0 /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Position */
<> 144:ef7eb2e8f9f7 1209 #define CMSDK_PL061_MASKINTSTAT_Msk (0x1ul << CMSDK_PL061_MASKINTSTAT_Pos) /*!< CMSDK_PL061 MASKINTSTAT: Mask Int Status Mask */
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 #define CMSDK_PL061_INTCLR_Pos 0 /*!< CMSDK_PL061 INTCLR: Int Clear Position */
<> 144:ef7eb2e8f9f7 1212 #define CMSDK_PL061_INTCLR_Msk (0x1ul << CMSDK_PL061_INTCLR_Pos) /*!< CMSDK_PL061 INTCLR: Int Clear Mask */
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 #define CMSDK_PL061_MODECTRL_HWEN_Pos 0 /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Position */
<> 144:ef7eb2e8f9f7 1215 #define CMSDK_PL061_MODECTRL_HWEN_Msk (0x1ul << CMSDK_PL061_MODECTRL_HWEN_Pos) /*!< CMSDK_PL061 MODECTRL_HWEN: Mode Control Hardware Enable Mask */
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /*@}*/ /* end of group CMSDK_PL061 */
<> 144:ef7eb2e8f9f7 1219
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 1222 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 1223 #endif
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /*@}*/ /* end of group CMSDK_CM4_Peripherals */
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1229 /* Peripheral memory map */
<> 144:ef7eb2e8f9f7 1230 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1231 /** @addtogroup CMSDK_CM4_MemoryMap CMSDK_CM4 Memory Mapping
<> 144:ef7eb2e8f9f7 1232 @{
<> 144:ef7eb2e8f9f7 1233 */
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /* Peripheral and SRAM base address */
<> 144:ef7eb2e8f9f7 1236 #define CMSDK_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
<> 144:ef7eb2e8f9f7 1237 #define CMSDK_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
<> 144:ef7eb2e8f9f7 1238 #define CMSDK_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* Base addresses */
<> 144:ef7eb2e8f9f7 1241 #define CMSDK_RAM_BASE (0x20000000UL)
<> 144:ef7eb2e8f9f7 1242 #define CMSDK_APB_BASE (0x40000000UL)
<> 144:ef7eb2e8f9f7 1243 #define CMSDK_AHB_BASE (0x40010000UL)
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /* APB peripherals */
<> 144:ef7eb2e8f9f7 1246 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 1247 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
<> 144:ef7eb2e8f9f7 1248 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
<> 144:ef7eb2e8f9f7 1249 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
<> 144:ef7eb2e8f9f7 1250 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
<> 144:ef7eb2e8f9f7 1251 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
<> 144:ef7eb2e8f9f7 1252 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
<> 144:ef7eb2e8f9f7 1253 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
<> 144:ef7eb2e8f9f7 1254 #define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
<> 144:ef7eb2e8f9f7 1255 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
<> 144:ef7eb2e8f9f7 1256 #define CMSDK_UART4_BASE (CMSDK_APB_BASE + 0x9000UL)
<> 144:ef7eb2e8f9f7 1257 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* AHB peripherals */
<> 144:ef7eb2e8f9f7 1260 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
<> 144:ef7eb2e8f9f7 1261 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
<> 144:ef7eb2e8f9f7 1262 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
<> 144:ef7eb2e8f9f7 1263 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
<> 144:ef7eb2e8f9f7 1264 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
<> 144:ef7eb2e8f9f7 1265 /*@}*/ /* end of group CMSDK_CM4_MemoryMap */
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1269 /* Peripheral declaration */
<> 144:ef7eb2e8f9f7 1270 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1271 /** @addtogroup CMSDK_CM4_PeripheralDecl CMSDK_CM4 Peripheral Declaration
<> 144:ef7eb2e8f9f7 1272 @{
<> 144:ef7eb2e8f9f7 1273 */
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
<> 144:ef7eb2e8f9f7 1276 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
<> 144:ef7eb2e8f9f7 1277 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
<> 144:ef7eb2e8f9f7 1278 #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
<> 144:ef7eb2e8f9f7 1279 #define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
<> 144:ef7eb2e8f9f7 1280 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
<> 144:ef7eb2e8f9f7 1281 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
<> 144:ef7eb2e8f9f7 1282 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
<> 144:ef7eb2e8f9f7 1283 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
<> 144:ef7eb2e8f9f7 1284 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
<> 144:ef7eb2e8f9f7 1285 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
<> 144:ef7eb2e8f9f7 1286 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
<> 144:ef7eb2e8f9f7 1287 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
<> 144:ef7eb2e8f9f7 1288 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
<> 144:ef7eb2e8f9f7 1289 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
<> 144:ef7eb2e8f9f7 1290 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
<> 144:ef7eb2e8f9f7 1291 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
<> 144:ef7eb2e8f9f7 1292 /*@}*/ /* end of group CMSDK_CM4_PeripheralDecl */
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 /*@}*/ /* end of group CMSDK_CM4_Definitions */
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298 #endif
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 #endif /* CMSDK_CM4_H */