added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_clock.c@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 32 | #include "fsl_clock.h" |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 35 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 36 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | #if (defined(OSC) && !(defined(OSC0))) |
<> | 144:ef7eb2e8f9f7 | 39 | #define OSC0 OSC |
<> | 144:ef7eb2e8f9f7 | 40 | #endif |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #define MCG_HIRC_FREQ (48000000U) |
<> | 144:ef7eb2e8f9f7 | 43 | #define MCG_LIRC_FREQ1 (2000000U) |
<> | 144:ef7eb2e8f9f7 | 44 | #define MCG_LIRC_FREQ2 (8000000U) |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | #define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 47 | #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 48 | #define MCG_MC_LIRC_DIV2_VAL ((MCG->MC & MCG_MC_LIRC_DIV2_MASK) >> MCG_MC_LIRC_DIV2_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 49 | #define MCG_C2_IRCS_VAL ((MCG->C2 & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | #define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 52 | #define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 53 | #define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 56 | * Variables |
<> | 144:ef7eb2e8f9f7 | 57 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | /* External XTAL0 (OSC0) clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 60 | uint32_t g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | /* External XTAL32K clock frequency. */ |
<> | 144:ef7eb2e8f9f7 | 63 | uint32_t g_xtal32Freq; |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 66 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 67 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | /*! |
<> | 144:ef7eb2e8f9f7 | 70 | * @brief Get the current MCG_Lite LIRC_CLK frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 71 | * |
<> | 144:ef7eb2e8f9f7 | 72 | * This function will return the LIRC_CLK value in frequency(Hz) based |
<> | 144:ef7eb2e8f9f7 | 73 | * on current MCG_Lite configurations and settings. It is an internal function. |
<> | 144:ef7eb2e8f9f7 | 74 | * |
<> | 144:ef7eb2e8f9f7 | 75 | * @return MCG_Lite LIRC_CLK frequency. |
<> | 144:ef7eb2e8f9f7 | 76 | */ |
<> | 144:ef7eb2e8f9f7 | 77 | static uint32_t CLOCK_GetLircClkFreq(void); |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | /*! |
<> | 144:ef7eb2e8f9f7 | 80 | * @brief Get RANGE value based on OSC frequency. |
<> | 144:ef7eb2e8f9f7 | 81 | * |
<> | 144:ef7eb2e8f9f7 | 82 | * To setup external crystal oscillator, must set the register bits RANGE base |
<> | 144:ef7eb2e8f9f7 | 83 | * on the crystal frequency. This function returns the RANGE base on the input |
<> | 144:ef7eb2e8f9f7 | 84 | * frequency. This is an internal function. |
<> | 144:ef7eb2e8f9f7 | 85 | * |
<> | 144:ef7eb2e8f9f7 | 86 | * @return RANGE value. |
<> | 144:ef7eb2e8f9f7 | 87 | */ |
<> | 144:ef7eb2e8f9f7 | 88 | static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 91 | * Code |
<> | 144:ef7eb2e8f9f7 | 92 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | static uint32_t CLOCK_GetLircClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 95 | { |
<> | 144:ef7eb2e8f9f7 | 96 | static const uint32_t lircFreqs[] = {MCG_LIRC_FREQ1, MCG_LIRC_FREQ2}; |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | /* Check whether the LIRC is enabled. */ |
<> | 144:ef7eb2e8f9f7 | 99 | if ((MCG->C1 & MCG_C1_IRCLKEN_MASK) || (kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL)) |
<> | 144:ef7eb2e8f9f7 | 100 | { |
<> | 144:ef7eb2e8f9f7 | 101 | return lircFreqs[MCG_C2_IRCS_VAL]; |
<> | 144:ef7eb2e8f9f7 | 102 | } |
<> | 144:ef7eb2e8f9f7 | 103 | else |
<> | 144:ef7eb2e8f9f7 | 104 | { |
<> | 144:ef7eb2e8f9f7 | 105 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 106 | } |
<> | 144:ef7eb2e8f9f7 | 107 | } |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 110 | { |
<> | 144:ef7eb2e8f9f7 | 111 | uint8_t range; |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | if (freq <= 39063U) |
<> | 144:ef7eb2e8f9f7 | 114 | { |
<> | 144:ef7eb2e8f9f7 | 115 | range = 0U; |
<> | 144:ef7eb2e8f9f7 | 116 | } |
<> | 144:ef7eb2e8f9f7 | 117 | else if (freq <= 8000000U) |
<> | 144:ef7eb2e8f9f7 | 118 | { |
<> | 144:ef7eb2e8f9f7 | 119 | range = 1U; |
<> | 144:ef7eb2e8f9f7 | 120 | } |
<> | 144:ef7eb2e8f9f7 | 121 | else |
<> | 144:ef7eb2e8f9f7 | 122 | { |
<> | 144:ef7eb2e8f9f7 | 123 | range = 2U; |
<> | 144:ef7eb2e8f9f7 | 124 | } |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | return range; |
<> | 144:ef7eb2e8f9f7 | 127 | } |
<> | 144:ef7eb2e8f9f7 | 128 | |
<> | 144:ef7eb2e8f9f7 | 129 | uint32_t CLOCK_GetOsc0ErClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 130 | { |
<> | 144:ef7eb2e8f9f7 | 131 | if (OSC0->CR & OSC_CR_ERCLKEN_MASK) |
<> | 144:ef7eb2e8f9f7 | 132 | { |
<> | 144:ef7eb2e8f9f7 | 133 | /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ |
<> | 144:ef7eb2e8f9f7 | 134 | assert(g_xtal0Freq); |
<> | 144:ef7eb2e8f9f7 | 135 | return g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 136 | } |
<> | 144:ef7eb2e8f9f7 | 137 | else |
<> | 144:ef7eb2e8f9f7 | 138 | { |
<> | 144:ef7eb2e8f9f7 | 139 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 140 | } |
<> | 144:ef7eb2e8f9f7 | 141 | } |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | uint32_t CLOCK_GetEr32kClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 144 | { |
<> | 144:ef7eb2e8f9f7 | 145 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | switch (SIM_SOPT1_OSC32KSEL_VAL) |
<> | 144:ef7eb2e8f9f7 | 148 | { |
<> | 144:ef7eb2e8f9f7 | 149 | case 0U: /* OSC 32k clock */ |
<> | 144:ef7eb2e8f9f7 | 150 | freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; |
<> | 144:ef7eb2e8f9f7 | 151 | break; |
<> | 144:ef7eb2e8f9f7 | 152 | case 2U: /* RTC 32k clock */ |
<> | 144:ef7eb2e8f9f7 | 153 | /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ |
<> | 144:ef7eb2e8f9f7 | 154 | assert(g_xtal32Freq); |
<> | 144:ef7eb2e8f9f7 | 155 | freq = g_xtal32Freq; |
<> | 144:ef7eb2e8f9f7 | 156 | break; |
<> | 144:ef7eb2e8f9f7 | 157 | case 3U: /* LPO clock */ |
<> | 144:ef7eb2e8f9f7 | 158 | freq = LPO_CLK_FREQ; |
<> | 144:ef7eb2e8f9f7 | 159 | break; |
<> | 144:ef7eb2e8f9f7 | 160 | default: |
<> | 144:ef7eb2e8f9f7 | 161 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 162 | break; |
<> | 144:ef7eb2e8f9f7 | 163 | } |
<> | 144:ef7eb2e8f9f7 | 164 | return freq; |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | uint32_t CLOCK_GetPlatClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 168 | { |
<> | 144:ef7eb2e8f9f7 | 169 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | uint32_t CLOCK_GetFlashClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 173 | { |
<> | 144:ef7eb2e8f9f7 | 174 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 177 | freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | return freq; |
<> | 144:ef7eb2e8f9f7 | 180 | } |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | uint32_t CLOCK_GetBusClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 183 | { |
<> | 144:ef7eb2e8f9f7 | 184 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 187 | freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | return freq; |
<> | 144:ef7eb2e8f9f7 | 190 | } |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | uint32_t CLOCK_GetCoreSysClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 193 | { |
<> | 144:ef7eb2e8f9f7 | 194 | return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 195 | } |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | uint32_t CLOCK_GetFreq(clock_name_t clockName) |
<> | 144:ef7eb2e8f9f7 | 198 | { |
<> | 144:ef7eb2e8f9f7 | 199 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 200 | |
<> | 144:ef7eb2e8f9f7 | 201 | switch (clockName) |
<> | 144:ef7eb2e8f9f7 | 202 | { |
<> | 144:ef7eb2e8f9f7 | 203 | case kCLOCK_CoreSysClk: |
<> | 144:ef7eb2e8f9f7 | 204 | case kCLOCK_PlatClk: |
<> | 144:ef7eb2e8f9f7 | 205 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 206 | break; |
<> | 144:ef7eb2e8f9f7 | 207 | case kCLOCK_BusClk: |
<> | 144:ef7eb2e8f9f7 | 208 | case kCLOCK_FlashClk: |
<> | 144:ef7eb2e8f9f7 | 209 | freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 210 | freq /= (SIM_CLKDIV1_OUTDIV4_VAL + 1); |
<> | 144:ef7eb2e8f9f7 | 211 | break; |
<> | 144:ef7eb2e8f9f7 | 212 | case kCLOCK_Er32kClk: |
<> | 144:ef7eb2e8f9f7 | 213 | freq = CLOCK_GetEr32kClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 214 | break; |
<> | 144:ef7eb2e8f9f7 | 215 | case kCLOCK_Osc0ErClk: |
<> | 144:ef7eb2e8f9f7 | 216 | freq = CLOCK_GetOsc0ErClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 217 | break; |
<> | 144:ef7eb2e8f9f7 | 218 | case kCLOCK_McgInternalRefClk: |
<> | 144:ef7eb2e8f9f7 | 219 | freq = CLOCK_GetInternalRefClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 220 | break; |
<> | 144:ef7eb2e8f9f7 | 221 | case kCLOCK_McgPeriphClk: |
<> | 144:ef7eb2e8f9f7 | 222 | case kCLOCK_McgIrc48MClk: |
<> | 144:ef7eb2e8f9f7 | 223 | freq = CLOCK_GetPeriphClkFreq(); |
<> | 144:ef7eb2e8f9f7 | 224 | break; |
<> | 144:ef7eb2e8f9f7 | 225 | case kCLOCK_LpoClk: |
<> | 144:ef7eb2e8f9f7 | 226 | freq = LPO_CLK_FREQ; |
<> | 144:ef7eb2e8f9f7 | 227 | break; |
<> | 144:ef7eb2e8f9f7 | 228 | default: |
<> | 144:ef7eb2e8f9f7 | 229 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 230 | break; |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | return freq; |
<> | 144:ef7eb2e8f9f7 | 234 | } |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | void CLOCK_SetSimConfig(sim_clock_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 237 | { |
<> | 144:ef7eb2e8f9f7 | 238 | SIM->CLKDIV1 = config->clkdiv1; |
<> | 144:ef7eb2e8f9f7 | 239 | CLOCK_SetEr32kClock(config->er32kSrc); |
<> | 144:ef7eb2e8f9f7 | 240 | } |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) |
<> | 144:ef7eb2e8f9f7 | 243 | { |
<> | 144:ef7eb2e8f9f7 | 244 | bool ret = true; |
<> | 144:ef7eb2e8f9f7 | 245 | |
<> | 144:ef7eb2e8f9f7 | 246 | CLOCK_DisableClock(kCLOCK_Usbfs0); |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | if (kCLOCK_UsbSrcExt == src) |
<> | 144:ef7eb2e8f9f7 | 249 | { |
<> | 144:ef7eb2e8f9f7 | 250 | SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; |
<> | 144:ef7eb2e8f9f7 | 251 | } |
<> | 144:ef7eb2e8f9f7 | 252 | else |
<> | 144:ef7eb2e8f9f7 | 253 | { |
<> | 144:ef7eb2e8f9f7 | 254 | SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK; |
<> | 144:ef7eb2e8f9f7 | 255 | } |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | CLOCK_EnableClock(kCLOCK_Usbfs0); |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | if (kCLOCK_UsbSrcIrc48M == src) |
<> | 144:ef7eb2e8f9f7 | 260 | { |
<> | 144:ef7eb2e8f9f7 | 261 | USB0->CLK_RECOVER_IRC_EN = 0x03U; |
<> | 144:ef7eb2e8f9f7 | 262 | USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; |
<> | 144:ef7eb2e8f9f7 | 263 | } |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | return ret; |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | uint32_t CLOCK_GetInternalRefClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 269 | { |
<> | 144:ef7eb2e8f9f7 | 270 | uint8_t divider1 = MCG_SC_FCRDIV_VAL; |
<> | 144:ef7eb2e8f9f7 | 271 | uint8_t divider2 = MCG_MC_LIRC_DIV2_VAL; |
<> | 144:ef7eb2e8f9f7 | 272 | /* LIRC internal reference clock is selected*/ |
<> | 144:ef7eb2e8f9f7 | 273 | return CLOCK_GetLircClkFreq() >> (divider1 + divider2); |
<> | 144:ef7eb2e8f9f7 | 274 | } |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | uint32_t CLOCK_GetPeriphClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 277 | { |
<> | 144:ef7eb2e8f9f7 | 278 | /* Check whether the HIRC is enabled. */ |
<> | 144:ef7eb2e8f9f7 | 279 | if ((MCG->MC & MCG_MC_HIRCEN_MASK) || (kMCGLITE_ClkSrcHirc == MCG_S_CLKST_VAL)) |
<> | 144:ef7eb2e8f9f7 | 280 | { |
<> | 144:ef7eb2e8f9f7 | 281 | return MCG_HIRC_FREQ; |
<> | 144:ef7eb2e8f9f7 | 282 | } |
<> | 144:ef7eb2e8f9f7 | 283 | else |
<> | 144:ef7eb2e8f9f7 | 284 | { |
<> | 144:ef7eb2e8f9f7 | 285 | return 0U; |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 144:ef7eb2e8f9f7 | 287 | } |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | uint32_t CLOCK_GetOutClkFreq(void) |
<> | 144:ef7eb2e8f9f7 | 290 | { |
<> | 144:ef7eb2e8f9f7 | 291 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | switch (MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 294 | { |
<> | 144:ef7eb2e8f9f7 | 295 | case kMCGLITE_ClkSrcHirc: |
<> | 144:ef7eb2e8f9f7 | 296 | freq = MCG_HIRC_FREQ; |
<> | 144:ef7eb2e8f9f7 | 297 | break; |
<> | 144:ef7eb2e8f9f7 | 298 | case kMCGLITE_ClkSrcLirc: |
<> | 144:ef7eb2e8f9f7 | 299 | freq = CLOCK_GetLircClkFreq() >> MCG_SC_FCRDIV_VAL; |
<> | 144:ef7eb2e8f9f7 | 300 | break; |
<> | 144:ef7eb2e8f9f7 | 301 | case kMCGLITE_ClkSrcExt: |
<> | 144:ef7eb2e8f9f7 | 302 | /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ |
<> | 144:ef7eb2e8f9f7 | 303 | assert(g_xtal0Freq); |
<> | 144:ef7eb2e8f9f7 | 304 | freq = g_xtal0Freq; |
<> | 144:ef7eb2e8f9f7 | 305 | break; |
<> | 144:ef7eb2e8f9f7 | 306 | default: |
<> | 144:ef7eb2e8f9f7 | 307 | freq = 0U; |
<> | 144:ef7eb2e8f9f7 | 308 | break; |
<> | 144:ef7eb2e8f9f7 | 309 | } |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | return freq; |
<> | 144:ef7eb2e8f9f7 | 312 | } |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | mcglite_mode_t CLOCK_GetMode(void) |
<> | 144:ef7eb2e8f9f7 | 315 | { |
<> | 144:ef7eb2e8f9f7 | 316 | mcglite_mode_t mode; |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | switch (MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 319 | { |
<> | 144:ef7eb2e8f9f7 | 320 | case kMCGLITE_ClkSrcHirc: /* HIRC */ |
<> | 144:ef7eb2e8f9f7 | 321 | mode = kMCGLITE_ModeHirc48M; |
<> | 144:ef7eb2e8f9f7 | 322 | break; |
<> | 144:ef7eb2e8f9f7 | 323 | case kMCGLITE_ClkSrcLirc: /* LIRC */ |
<> | 144:ef7eb2e8f9f7 | 324 | if (kMCGLITE_Lirc2M == MCG_C2_IRCS_VAL) |
<> | 144:ef7eb2e8f9f7 | 325 | { |
<> | 144:ef7eb2e8f9f7 | 326 | mode = kMCGLITE_ModeLirc2M; |
<> | 144:ef7eb2e8f9f7 | 327 | } |
<> | 144:ef7eb2e8f9f7 | 328 | else |
<> | 144:ef7eb2e8f9f7 | 329 | { |
<> | 144:ef7eb2e8f9f7 | 330 | mode = kMCGLITE_ModeLirc8M; |
<> | 144:ef7eb2e8f9f7 | 331 | } |
<> | 144:ef7eb2e8f9f7 | 332 | break; |
<> | 144:ef7eb2e8f9f7 | 333 | case kMCGLITE_ClkSrcExt: /* EXT */ |
<> | 144:ef7eb2e8f9f7 | 334 | mode = kMCGLITE_ModeExt; |
<> | 144:ef7eb2e8f9f7 | 335 | break; |
<> | 144:ef7eb2e8f9f7 | 336 | default: |
<> | 144:ef7eb2e8f9f7 | 337 | mode = kMCGLITE_ModeError; |
<> | 144:ef7eb2e8f9f7 | 338 | break; |
<> | 144:ef7eb2e8f9f7 | 339 | } |
<> | 144:ef7eb2e8f9f7 | 340 | |
<> | 144:ef7eb2e8f9f7 | 341 | return mode; |
<> | 144:ef7eb2e8f9f7 | 342 | } |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig) |
<> | 144:ef7eb2e8f9f7 | 345 | { |
<> | 144:ef7eb2e8f9f7 | 346 | assert(targetConfig); |
<> | 144:ef7eb2e8f9f7 | 347 | |
<> | 144:ef7eb2e8f9f7 | 348 | /* |
<> | 144:ef7eb2e8f9f7 | 349 | * If switch between LIRC8M and LIRC2M, need to switch to HIRC mode first, |
<> | 144:ef7eb2e8f9f7 | 350 | * because could not switch directly. |
<> | 144:ef7eb2e8f9f7 | 351 | */ |
<> | 144:ef7eb2e8f9f7 | 352 | if ((kMCGLITE_ClkSrcLirc == MCG_S_CLKST_VAL) && (kMCGLITE_ClkSrcLirc == targetConfig->outSrc) && |
<> | 144:ef7eb2e8f9f7 | 353 | (MCG_C2_IRCS_VAL != targetConfig->ircs)) |
<> | 144:ef7eb2e8f9f7 | 354 | { |
<> | 144:ef7eb2e8f9f7 | 355 | MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCGLITE_ClkSrcHirc); |
<> | 144:ef7eb2e8f9f7 | 356 | while (kMCGLITE_ClkSrcHirc != MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 357 | { |
<> | 144:ef7eb2e8f9f7 | 358 | } |
<> | 144:ef7eb2e8f9f7 | 359 | } |
<> | 144:ef7eb2e8f9f7 | 360 | |
<> | 144:ef7eb2e8f9f7 | 361 | /* Set configuration now. */ |
<> | 144:ef7eb2e8f9f7 | 362 | MCG->SC = MCG_SC_FCRDIV(targetConfig->fcrdiv); |
<> | 144:ef7eb2e8f9f7 | 363 | MCG->MC = MCG_MC_HIRCEN(targetConfig->hircEnableInNotHircMode) | MCG_MC_LIRC_DIV2(targetConfig->lircDiv2); |
<> | 144:ef7eb2e8f9f7 | 364 | MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | MCG_C2_IRCS(targetConfig->ircs); |
<> | 144:ef7eb2e8f9f7 | 365 | MCG->C1 = MCG_C1_CLKS(targetConfig->outSrc) | targetConfig->irclkEnableMode; |
<> | 144:ef7eb2e8f9f7 | 366 | |
<> | 144:ef7eb2e8f9f7 | 367 | /* |
<> | 144:ef7eb2e8f9f7 | 368 | * If external oscillator used and MCG_Lite is set to EXT mode, need to |
<> | 144:ef7eb2e8f9f7 | 369 | * wait for the OSC stable. |
<> | 144:ef7eb2e8f9f7 | 370 | */ |
<> | 144:ef7eb2e8f9f7 | 371 | if ((MCG->C2 & MCG_C2_EREFS0_MASK) && (kMCGLITE_ClkSrcExt == targetConfig->outSrc)) |
<> | 144:ef7eb2e8f9f7 | 372 | { |
<> | 144:ef7eb2e8f9f7 | 373 | while (!(MCG->S & MCG_S_OSCINIT0_MASK)) |
<> | 144:ef7eb2e8f9f7 | 374 | { |
<> | 144:ef7eb2e8f9f7 | 375 | } |
<> | 144:ef7eb2e8f9f7 | 376 | } |
<> | 144:ef7eb2e8f9f7 | 377 | |
<> | 144:ef7eb2e8f9f7 | 378 | /* Wait for clock source change completed. */ |
<> | 144:ef7eb2e8f9f7 | 379 | while (targetConfig->outSrc != MCG_S_CLKST_VAL) |
<> | 144:ef7eb2e8f9f7 | 380 | { |
<> | 144:ef7eb2e8f9f7 | 381 | } |
<> | 144:ef7eb2e8f9f7 | 382 | |
<> | 144:ef7eb2e8f9f7 | 383 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 384 | } |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | void CLOCK_InitOsc0(osc_config_t const *config) |
<> | 144:ef7eb2e8f9f7 | 387 | { |
<> | 144:ef7eb2e8f9f7 | 388 | uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | OSC_SetCapLoad(OSC0, config->capLoad); |
<> | 144:ef7eb2e8f9f7 | 391 | OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | MCG->C2 = ((MCG->C2 & MCG_C2_IRCS_MASK) | MCG_C2_RANGE0(range) | (uint8_t)config->workMode); |
<> | 144:ef7eb2e8f9f7 | 394 | |
<> | 144:ef7eb2e8f9f7 | 395 | if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) |
<> | 144:ef7eb2e8f9f7 | 396 | { |
<> | 144:ef7eb2e8f9f7 | 397 | /* Wait for stable. */ |
<> | 144:ef7eb2e8f9f7 | 398 | while (!(MCG->S & MCG_S_OSCINIT0_MASK)) |
<> | 144:ef7eb2e8f9f7 | 399 | { |
<> | 144:ef7eb2e8f9f7 | 400 | } |
<> | 144:ef7eb2e8f9f7 | 401 | } |
<> | 144:ef7eb2e8f9f7 | 402 | } |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | void CLOCK_DeinitOsc0(void) |
<> | 144:ef7eb2e8f9f7 | 405 | { |
<> | 144:ef7eb2e8f9f7 | 406 | OSC0->CR = 0U; |
<> | 144:ef7eb2e8f9f7 | 407 | MCG->C2 &= MCG_C2_IRCS_MASK; |
<> | 144:ef7eb2e8f9f7 | 408 | } |