Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_ebi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file em_ebi.c
bogdanm 0:9b334a45a8ff 3 * @brief External Bus Interface (EBI) Peripheral API
bogdanm 0:9b334a45a8ff 4 * @version 3.20.12
bogdanm 0:9b334a45a8ff 5 *******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
bogdanm 0:9b334a45a8ff 7 * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 *******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 21 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 22 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 23 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 24 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 25 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 28 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 29 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 ******************************************************************************/
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #include "em_ebi.h"
bogdanm 0:9b334a45a8ff 35 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
bogdanm 0:9b334a45a8ff 36 #include "em_assert.h"
bogdanm 0:9b334a45a8ff 37 #include "em_bitband.h"
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 40 * @addtogroup EM_Library
bogdanm 0:9b334a45a8ff 41 * @{
bogdanm 0:9b334a45a8ff 42 ******************************************************************************/
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 45 * @addtogroup EBI
bogdanm 0:9b334a45a8ff 46 * @brief EBI External Bus Interface (EBI) Peripheral API
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 ******************************************************************************/
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 51 * @brief
bogdanm 0:9b334a45a8ff 52 * Configure and enable External Bus Interface
bogdanm 0:9b334a45a8ff 53 *
bogdanm 0:9b334a45a8ff 54 * @param[in] ebiInit
bogdanm 0:9b334a45a8ff 55 * EBI configuration structure
bogdanm 0:9b334a45a8ff 56 *
bogdanm 0:9b334a45a8ff 57 * @note
bogdanm 0:9b334a45a8ff 58 * GPIO lines must be configured as PUSH_PULL for correct operation
bogdanm 0:9b334a45a8ff 59 * GPIO and EBI clocks must be enabled in the CMU
bogdanm 0:9b334a45a8ff 60 ******************************************************************************/
bogdanm 0:9b334a45a8ff 61 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
bogdanm 0:9b334a45a8ff 62 {
bogdanm 0:9b334a45a8ff 63 uint32_t ctrl = EBI->CTRL;
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 66 /* Enable Independent Timing for devices that supports it */
bogdanm 0:9b334a45a8ff 67 ctrl |= EBI_CTRL_ITS;
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 /* Set polarity of address ready */
bogdanm 0:9b334a45a8ff 70 EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
bogdanm 0:9b334a45a8ff 71 /* Set polarity of address latch enable */
bogdanm 0:9b334a45a8ff 72 EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
bogdanm 0:9b334a45a8ff 73 /* Set polarity of write enable */
bogdanm 0:9b334a45a8ff 74 EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
bogdanm 0:9b334a45a8ff 75 /* Set polarity of read enable */
bogdanm 0:9b334a45a8ff 76 EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
bogdanm 0:9b334a45a8ff 77 /* Set polarity of chip select lines */
bogdanm 0:9b334a45a8ff 78 EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
bogdanm 0:9b334a45a8ff 79 /* Set polarity of byte lane line */
bogdanm 0:9b334a45a8ff 80 EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
bogdanm 0:9b334a45a8ff 81 #else
bogdanm 0:9b334a45a8ff 82 /* Set polarity of address ready */
bogdanm 0:9b334a45a8ff 83 EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
bogdanm 0:9b334a45a8ff 84 /* Set polarity of address latch enable */
bogdanm 0:9b334a45a8ff 85 EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
bogdanm 0:9b334a45a8ff 86 /* Set polarity of write enable */
bogdanm 0:9b334a45a8ff 87 EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
bogdanm 0:9b334a45a8ff 88 /* Set polarity of read enable */
bogdanm 0:9b334a45a8ff 89 EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
bogdanm 0:9b334a45a8ff 90 /* Set polarity of chip select lines */
bogdanm 0:9b334a45a8ff 91 EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
bogdanm 0:9b334a45a8ff 92 #endif
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /* Configure EBI mode and control settings */
bogdanm 0:9b334a45a8ff 95 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 96 if (ebiInit->banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 ctrl &= ~(_EBI_CTRL_MODE_MASK|
bogdanm 0:9b334a45a8ff 99 _EBI_CTRL_ARDYEN_MASK|
bogdanm 0:9b334a45a8ff 100 _EBI_CTRL_ARDYTODIS_MASK|
bogdanm 0:9b334a45a8ff 101 _EBI_CTRL_BL_MASK|
bogdanm 0:9b334a45a8ff 102 _EBI_CTRL_NOIDLE_MASK|
bogdanm 0:9b334a45a8ff 103 _EBI_CTRL_BANK0EN_MASK);
bogdanm 0:9b334a45a8ff 104 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
bogdanm 0:9b334a45a8ff 105 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
bogdanm 0:9b334a45a8ff 106 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
bogdanm 0:9b334a45a8ff 107 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
bogdanm 0:9b334a45a8ff 108 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
bogdanm 0:9b334a45a8ff 109 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 110 {
bogdanm 0:9b334a45a8ff 111 ctrl |= EBI_CTRL_BANK0EN;
bogdanm 0:9b334a45a8ff 112 }
bogdanm 0:9b334a45a8ff 113 }
bogdanm 0:9b334a45a8ff 114 if (ebiInit->banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 115 {
bogdanm 0:9b334a45a8ff 116 ctrl &= ~(_EBI_CTRL_BL1_MASK|
bogdanm 0:9b334a45a8ff 117 _EBI_CTRL_MODE1_MASK|
bogdanm 0:9b334a45a8ff 118 _EBI_CTRL_ARDY1EN_MASK|
bogdanm 0:9b334a45a8ff 119 _EBI_CTRL_ARDYTO1DIS_MASK|
bogdanm 0:9b334a45a8ff 120 _EBI_CTRL_NOIDLE1_MASK|
bogdanm 0:9b334a45a8ff 121 _EBI_CTRL_BANK1EN_MASK);
bogdanm 0:9b334a45a8ff 122 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
bogdanm 0:9b334a45a8ff 123 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
bogdanm 0:9b334a45a8ff 124 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
bogdanm 0:9b334a45a8ff 125 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
bogdanm 0:9b334a45a8ff 126 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
bogdanm 0:9b334a45a8ff 127 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 128 {
bogdanm 0:9b334a45a8ff 129 ctrl |= EBI_CTRL_BANK1EN;
bogdanm 0:9b334a45a8ff 130 }
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132 if (ebiInit->banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 133 {
bogdanm 0:9b334a45a8ff 134 ctrl &= ~(_EBI_CTRL_BL2_MASK|
bogdanm 0:9b334a45a8ff 135 _EBI_CTRL_MODE2_MASK|
bogdanm 0:9b334a45a8ff 136 _EBI_CTRL_ARDY2EN_MASK|
bogdanm 0:9b334a45a8ff 137 _EBI_CTRL_ARDYTO2DIS_MASK|
bogdanm 0:9b334a45a8ff 138 _EBI_CTRL_NOIDLE2_MASK|
bogdanm 0:9b334a45a8ff 139 _EBI_CTRL_BANK2EN_MASK);
bogdanm 0:9b334a45a8ff 140 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
bogdanm 0:9b334a45a8ff 141 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
bogdanm 0:9b334a45a8ff 142 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
bogdanm 0:9b334a45a8ff 143 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
bogdanm 0:9b334a45a8ff 144 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
bogdanm 0:9b334a45a8ff 145 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 146 {
bogdanm 0:9b334a45a8ff 147 ctrl |= EBI_CTRL_BANK2EN;
bogdanm 0:9b334a45a8ff 148 }
bogdanm 0:9b334a45a8ff 149 }
bogdanm 0:9b334a45a8ff 150 if (ebiInit->banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 151 {
bogdanm 0:9b334a45a8ff 152 ctrl &= ~(_EBI_CTRL_BL3_MASK|
bogdanm 0:9b334a45a8ff 153 _EBI_CTRL_MODE3_MASK|
bogdanm 0:9b334a45a8ff 154 _EBI_CTRL_ARDY3EN_MASK|
bogdanm 0:9b334a45a8ff 155 _EBI_CTRL_ARDYTO3DIS_MASK|
bogdanm 0:9b334a45a8ff 156 _EBI_CTRL_NOIDLE3_MASK|
bogdanm 0:9b334a45a8ff 157 _EBI_CTRL_BANK3EN_MASK);
bogdanm 0:9b334a45a8ff 158 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
bogdanm 0:9b334a45a8ff 159 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
bogdanm 0:9b334a45a8ff 160 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
bogdanm 0:9b334a45a8ff 161 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
bogdanm 0:9b334a45a8ff 162 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
bogdanm 0:9b334a45a8ff 163 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 164 {
bogdanm 0:9b334a45a8ff 165 ctrl |= EBI_CTRL_BANK3EN;
bogdanm 0:9b334a45a8ff 166 }
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168 #else
bogdanm 0:9b334a45a8ff 169 ctrl &= ~(_EBI_CTRL_MODE_MASK|
bogdanm 0:9b334a45a8ff 170 _EBI_CTRL_ARDYEN_MASK|
bogdanm 0:9b334a45a8ff 171 _EBI_CTRL_ARDYTODIS_MASK|
bogdanm 0:9b334a45a8ff 172 _EBI_CTRL_BANK0EN_MASK|
bogdanm 0:9b334a45a8ff 173 _EBI_CTRL_BANK1EN_MASK|
bogdanm 0:9b334a45a8ff 174 _EBI_CTRL_BANK2EN_MASK|
bogdanm 0:9b334a45a8ff 175 _EBI_CTRL_BANK3EN_MASK);
bogdanm 0:9b334a45a8ff 176 if ( ebiInit->enable)
bogdanm 0:9b334a45a8ff 177 {
bogdanm 0:9b334a45a8ff 178 if ( ebiInit->banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 179 {
bogdanm 0:9b334a45a8ff 180 ctrl |= EBI_CTRL_BANK0EN;
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182 if ( ebiInit->banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 183 {
bogdanm 0:9b334a45a8ff 184 ctrl |= EBI_CTRL_BANK1EN;
bogdanm 0:9b334a45a8ff 185 }
bogdanm 0:9b334a45a8ff 186 if ( ebiInit->banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 187 {
bogdanm 0:9b334a45a8ff 188 ctrl |= EBI_CTRL_BANK2EN;
bogdanm 0:9b334a45a8ff 189 }
bogdanm 0:9b334a45a8ff 190 if ( ebiInit->banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 ctrl |= EBI_CTRL_BANK3EN;
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195 ctrl |= ebiInit->mode;
bogdanm 0:9b334a45a8ff 196 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
bogdanm 0:9b334a45a8ff 197 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
bogdanm 0:9b334a45a8ff 198 #endif
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Configure timing */
bogdanm 0:9b334a45a8ff 201 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 202 EBI_BankReadTimingSet(ebiInit->banks,
bogdanm 0:9b334a45a8ff 203 ebiInit->readSetupCycles,
bogdanm 0:9b334a45a8ff 204 ebiInit->readStrobeCycles,
bogdanm 0:9b334a45a8ff 205 ebiInit->readHoldCycles);
bogdanm 0:9b334a45a8ff 206 EBI_BankReadTimingConfig(ebiInit->banks,
bogdanm 0:9b334a45a8ff 207 ebiInit->readPageMode,
bogdanm 0:9b334a45a8ff 208 ebiInit->readPrefetch,
bogdanm 0:9b334a45a8ff 209 ebiInit->readHalfRE);
bogdanm 0:9b334a45a8ff 210 EBI_BankWriteTimingSet(ebiInit->banks,
bogdanm 0:9b334a45a8ff 211 ebiInit->writeSetupCycles,
bogdanm 0:9b334a45a8ff 212 ebiInit->writeStrobeCycles,
bogdanm 0:9b334a45a8ff 213 ebiInit->writeHoldCycles);
bogdanm 0:9b334a45a8ff 214 EBI_BankWriteTimingConfig(ebiInit->banks,
bogdanm 0:9b334a45a8ff 215 ebiInit->writeBufferDisable,
bogdanm 0:9b334a45a8ff 216 ebiInit->writeHalfWE);
bogdanm 0:9b334a45a8ff 217 EBI_BankAddressTimingSet(ebiInit->banks,
bogdanm 0:9b334a45a8ff 218 ebiInit->addrSetupCycles,
bogdanm 0:9b334a45a8ff 219 ebiInit->addrHoldCycles);
bogdanm 0:9b334a45a8ff 220 EBI_BankAddressTimingConfig(ebiInit->banks,
bogdanm 0:9b334a45a8ff 221 ebiInit->addrHalfALE);
bogdanm 0:9b334a45a8ff 222 #else
bogdanm 0:9b334a45a8ff 223 EBI_ReadTimingSet(ebiInit->readSetupCycles,
bogdanm 0:9b334a45a8ff 224 ebiInit->readStrobeCycles,
bogdanm 0:9b334a45a8ff 225 ebiInit->readHoldCycles);
bogdanm 0:9b334a45a8ff 226 EBI_WriteTimingSet(ebiInit->writeSetupCycles,
bogdanm 0:9b334a45a8ff 227 ebiInit->writeStrobeCycles,
bogdanm 0:9b334a45a8ff 228 ebiInit->writeHoldCycles);
bogdanm 0:9b334a45a8ff 229 EBI_AddressTimingSet(ebiInit->addrSetupCycles,
bogdanm 0:9b334a45a8ff 230 ebiInit->addrHoldCycles);
bogdanm 0:9b334a45a8ff 231 #endif
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Activate new configuration */
bogdanm 0:9b334a45a8ff 234 EBI->CTRL = ctrl;
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* Configure Adress Latch Enable */
bogdanm 0:9b334a45a8ff 237 switch (ebiInit->mode)
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 case ebiModeD16A16ALE:
bogdanm 0:9b334a45a8ff 240 case ebiModeD8A24ALE:
bogdanm 0:9b334a45a8ff 241 /* Address Latch Enable */
bogdanm 0:9b334a45a8ff 242 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
bogdanm 0:9b334a45a8ff 243 break;
bogdanm 0:9b334a45a8ff 244 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 245 case ebiModeD16:
bogdanm 0:9b334a45a8ff 246 #endif
bogdanm 0:9b334a45a8ff 247 case ebiModeD8A8:
bogdanm 0:9b334a45a8ff 248 /* Make sure Address Latch is disabled */
bogdanm 0:9b334a45a8ff 249 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
bogdanm 0:9b334a45a8ff 250 break;
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 253 /* Limit pin enable */
bogdanm 0:9b334a45a8ff 254 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
bogdanm 0:9b334a45a8ff 255 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
bogdanm 0:9b334a45a8ff 256 /* Location */
bogdanm 0:9b334a45a8ff 257 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /* Enable EBI BL pin if necessary */
bogdanm 0:9b334a45a8ff 260 if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
bogdanm 0:9b334a45a8ff 261 {
bogdanm 0:9b334a45a8ff 262 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264 #endif
bogdanm 0:9b334a45a8ff 265 /* Enable EBI pins EBI_WEn and EBI_REn */
bogdanm 0:9b334a45a8ff 266 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /* Enable chip select lines */
bogdanm 0:9b334a45a8ff 269 EBI_ChipSelectEnable(ebiInit->csLines, true);
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 274 * @brief
bogdanm 0:9b334a45a8ff 275 * Disable External Bus Interface
bogdanm 0:9b334a45a8ff 276 ******************************************************************************/
bogdanm 0:9b334a45a8ff 277 void EBI_Disable(void)
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 /* Disable pins */
bogdanm 0:9b334a45a8ff 280 EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
bogdanm 0:9b334a45a8ff 281 /* Disable banks */
bogdanm 0:9b334a45a8ff 282 EBI->CTRL = _EBI_CTRL_RESETVALUE;
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 287 * @brief
bogdanm 0:9b334a45a8ff 288 * Enable or disable EBI Bank
bogdanm 0:9b334a45a8ff 289 *
bogdanm 0:9b334a45a8ff 290 * @param[in] banks
bogdanm 0:9b334a45a8ff 291 * Banks to reconfigure, mask of EBI_BANK<n> flags
bogdanm 0:9b334a45a8ff 292 *
bogdanm 0:9b334a45a8ff 293 * @param[in] enable
bogdanm 0:9b334a45a8ff 294 * True to enable, false to disable
bogdanm 0:9b334a45a8ff 295 ******************************************************************************/
bogdanm 0:9b334a45a8ff 296 void EBI_BankEnable(uint32_t banks, bool enable)
bogdanm 0:9b334a45a8ff 297 {
bogdanm 0:9b334a45a8ff 298 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 299 {
bogdanm 0:9b334a45a8ff 300 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 307 {
bogdanm 0:9b334a45a8ff 308 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 309 }
bogdanm 0:9b334a45a8ff 310 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 313 }
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 318 * @brief
bogdanm 0:9b334a45a8ff 319 * Return base address of EBI bank
bogdanm 0:9b334a45a8ff 320 *
bogdanm 0:9b334a45a8ff 321 * @param[in] bank
bogdanm 0:9b334a45a8ff 322 * Bank to return start address for
bogdanm 0:9b334a45a8ff 323 *
bogdanm 0:9b334a45a8ff 324 * @return
bogdanm 0:9b334a45a8ff 325 * Absolute address of bank
bogdanm 0:9b334a45a8ff 326 ******************************************************************************/
bogdanm 0:9b334a45a8ff 327 uint32_t EBI_BankAddress(uint32_t bank)
bogdanm 0:9b334a45a8ff 328 {
bogdanm 0:9b334a45a8ff 329 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 330 if(EBI->CTRL & EBI_CTRL_ALTMAP)
bogdanm 0:9b334a45a8ff 331 {
bogdanm 0:9b334a45a8ff 332 switch (bank)
bogdanm 0:9b334a45a8ff 333 {
bogdanm 0:9b334a45a8ff 334 case EBI_BANK0:
bogdanm 0:9b334a45a8ff 335 return(EBI_MEM_BASE);
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 case EBI_BANK1:
bogdanm 0:9b334a45a8ff 338 return(EBI_MEM_BASE + 0x10000000UL);
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 case EBI_BANK2:
bogdanm 0:9b334a45a8ff 341 return(EBI_MEM_BASE + 0x20000000UL);
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 case EBI_BANK3:
bogdanm 0:9b334a45a8ff 344 return(EBI_MEM_BASE + 0x30000000UL);
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 default:
bogdanm 0:9b334a45a8ff 347 EFM_ASSERT(0);
bogdanm 0:9b334a45a8ff 348 break;
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 }
bogdanm 0:9b334a45a8ff 351 #endif
bogdanm 0:9b334a45a8ff 352 switch (bank)
bogdanm 0:9b334a45a8ff 353 {
bogdanm 0:9b334a45a8ff 354 case EBI_BANK0:
bogdanm 0:9b334a45a8ff 355 return(EBI_MEM_BASE);
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 case EBI_BANK1:
bogdanm 0:9b334a45a8ff 358 return(EBI_MEM_BASE + 0x04000000UL);
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 case EBI_BANK2:
bogdanm 0:9b334a45a8ff 361 return(EBI_MEM_BASE + 0x08000000UL);
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 case EBI_BANK3:
bogdanm 0:9b334a45a8ff 364 return(EBI_MEM_BASE + 0x0C000000UL);
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 default:
bogdanm 0:9b334a45a8ff 367 EFM_ASSERT(0);
bogdanm 0:9b334a45a8ff 368 break;
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370 return 0;
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 375 * @brief
bogdanm 0:9b334a45a8ff 376 * Enable or disable EBI Chip Select
bogdanm 0:9b334a45a8ff 377 *
bogdanm 0:9b334a45a8ff 378 * @param[in] cs
bogdanm 0:9b334a45a8ff 379 * ChipSelect lines to reconfigure, mask of EBI_CS<n> flags
bogdanm 0:9b334a45a8ff 380 *
bogdanm 0:9b334a45a8ff 381 * @param[in] enable
bogdanm 0:9b334a45a8ff 382 * True to enable, false to disable
bogdanm 0:9b334a45a8ff 383 ******************************************************************************/
bogdanm 0:9b334a45a8ff 384 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
bogdanm 0:9b334a45a8ff 385 {
bogdanm 0:9b334a45a8ff 386 if (cs & EBI_CS0)
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390 if (cs & EBI_CS1)
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394 if (cs & EBI_CS2)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398 if (cs & EBI_CS3)
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
bogdanm 0:9b334a45a8ff 401 }
bogdanm 0:9b334a45a8ff 402 }
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 406 * @brief
bogdanm 0:9b334a45a8ff 407 * Configure EBI pin polarity
bogdanm 0:9b334a45a8ff 408 *
bogdanm 0:9b334a45a8ff 409 * @param[in] line
bogdanm 0:9b334a45a8ff 410 * Which pin/line to configure
bogdanm 0:9b334a45a8ff 411 *
bogdanm 0:9b334a45a8ff 412 * @param[in] polarity
bogdanm 0:9b334a45a8ff 413 * Active high, or active low
bogdanm 0:9b334a45a8ff 414 ******************************************************************************/
bogdanm 0:9b334a45a8ff 415 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
bogdanm 0:9b334a45a8ff 416 {
bogdanm 0:9b334a45a8ff 417 switch (line)
bogdanm 0:9b334a45a8ff 418 {
bogdanm 0:9b334a45a8ff 419 case ebiLineARDY:
bogdanm 0:9b334a45a8ff 420 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 421 break;
bogdanm 0:9b334a45a8ff 422 case ebiLineALE:
bogdanm 0:9b334a45a8ff 423 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 424 break;
bogdanm 0:9b334a45a8ff 425 case ebiLineWE:
bogdanm 0:9b334a45a8ff 426 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 427 break;
bogdanm 0:9b334a45a8ff 428 case ebiLineRE:
bogdanm 0:9b334a45a8ff 429 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 430 break;
bogdanm 0:9b334a45a8ff 431 case ebiLineCS:
bogdanm 0:9b334a45a8ff 432 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 433 break;
bogdanm 0:9b334a45a8ff 434 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 435 case ebiLineBL:
bogdanm 0:9b334a45a8ff 436 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 437 break;
bogdanm 0:9b334a45a8ff 438 case ebiLineTFTVSync:
bogdanm 0:9b334a45a8ff 439 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 440 break;
bogdanm 0:9b334a45a8ff 441 case ebiLineTFTHSync:
bogdanm 0:9b334a45a8ff 442 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 443 break;
bogdanm 0:9b334a45a8ff 444 case ebiLineTFTDataEn:
bogdanm 0:9b334a45a8ff 445 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 446 break;
bogdanm 0:9b334a45a8ff 447 case ebiLineTFTDClk:
bogdanm 0:9b334a45a8ff 448 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 449 break;
bogdanm 0:9b334a45a8ff 450 case ebiLineTFTCS:
bogdanm 0:9b334a45a8ff 451 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 452 break;
bogdanm 0:9b334a45a8ff 453 #endif
bogdanm 0:9b334a45a8ff 454 default:
bogdanm 0:9b334a45a8ff 455 EFM_ASSERT(0);
bogdanm 0:9b334a45a8ff 456 break;
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458 }
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 462 * @brief
bogdanm 0:9b334a45a8ff 463 * Configure timing values of read bus accesses
bogdanm 0:9b334a45a8ff 464 *
bogdanm 0:9b334a45a8ff 465 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 466 * Number of clock cycles for address setup before REn is asserted
bogdanm 0:9b334a45a8ff 467 *
bogdanm 0:9b334a45a8ff 468 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 469 * The number of cycles the REn is held active. After the specified number of
bogdanm 0:9b334a45a8ff 470 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 471 *
bogdanm 0:9b334a45a8ff 472 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 473 * The number of cycles CSn is held active after the REn is dessarted
bogdanm 0:9b334a45a8ff 474 ******************************************************************************/
bogdanm 0:9b334a45a8ff 475 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 476 {
bogdanm 0:9b334a45a8ff 477 uint32_t readTiming;
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 480 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 481 EFM_ASSERT(strobeCycles < 16);
bogdanm 0:9b334a45a8ff 482 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Configure timing values */
bogdanm 0:9b334a45a8ff 485 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 486 (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
bogdanm 0:9b334a45a8ff 487 (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 EBI->RDTIMING = (EBI->RDTIMING &
bogdanm 0:9b334a45a8ff 491 ~(_EBI_RDTIMING_RDSETUP_MASK |
bogdanm 0:9b334a45a8ff 492 _EBI_RDTIMING_RDSTRB_MASK |
bogdanm 0:9b334a45a8ff 493 _EBI_RDTIMING_RDHOLD_MASK)) | readTiming;
bogdanm 0:9b334a45a8ff 494 }
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 498 * @brief
bogdanm 0:9b334a45a8ff 499 * Configure timing values of write bus accesses
bogdanm 0:9b334a45a8ff 500 *
bogdanm 0:9b334a45a8ff 501 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 502 * Number of clock cycles for address setup before WEn is asserted
bogdanm 0:9b334a45a8ff 503 *
bogdanm 0:9b334a45a8ff 504 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 505 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 506 *
bogdanm 0:9b334a45a8ff 507 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 508 * Number of cycles CSn is held active after the WEn is deasserted
bogdanm 0:9b334a45a8ff 509 ******************************************************************************/
bogdanm 0:9b334a45a8ff 510 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 511 {
bogdanm 0:9b334a45a8ff 512 uint32_t writeTiming;
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 515 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 516 EFM_ASSERT(strobeCycles < 16);
bogdanm 0:9b334a45a8ff 517 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /* Configure timing values */
bogdanm 0:9b334a45a8ff 520 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 521 (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
bogdanm 0:9b334a45a8ff 522 (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 EBI->WRTIMING = (EBI->WRTIMING &
bogdanm 0:9b334a45a8ff 525 ~(_EBI_WRTIMING_WRSETUP_MASK |
bogdanm 0:9b334a45a8ff 526 _EBI_WRTIMING_WRSTRB_MASK |
bogdanm 0:9b334a45a8ff 527 _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming;
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 532 * @brief
bogdanm 0:9b334a45a8ff 533 * Configure timing values of address latch bus accesses
bogdanm 0:9b334a45a8ff 534 *
bogdanm 0:9b334a45a8ff 535 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 536 * Sets the number of cycles the address is held after ALE is asserted
bogdanm 0:9b334a45a8ff 537 *
bogdanm 0:9b334a45a8ff 538 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 539 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
bogdanm 0:9b334a45a8ff 540 * ALE is asserted. If set 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 541 ******************************************************************************/
bogdanm 0:9b334a45a8ff 542 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 543 {
bogdanm 0:9b334a45a8ff 544 uint32_t addressLatchTiming;
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 /* Check that timing values are within limits */
bogdanm 0:9b334a45a8ff 547 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 548 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /* Configure address latch timing values */
bogdanm 0:9b334a45a8ff 551 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 552 (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 EBI->ADDRTIMING = (EBI->ADDRTIMING &
bogdanm 0:9b334a45a8ff 555 ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
bogdanm 0:9b334a45a8ff 556 _EBI_ADDRTIMING_ADDRHOLD_MASK)) | addressLatchTiming;
bogdanm 0:9b334a45a8ff 557 }
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 560 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 561 * @brief
bogdanm 0:9b334a45a8ff 562 * Configure and initialize TFT Direct Drive
bogdanm 0:9b334a45a8ff 563 *
bogdanm 0:9b334a45a8ff 564 * @param[in] ebiTFTInit
bogdanm 0:9b334a45a8ff 565 * TFT Initialization structure
bogdanm 0:9b334a45a8ff 566 ******************************************************************************/
bogdanm 0:9b334a45a8ff 567 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
bogdanm 0:9b334a45a8ff 568 {
bogdanm 0:9b334a45a8ff 569 uint32_t ctrl;
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /* Configure base address for frame buffer offset to EBI bank */
bogdanm 0:9b334a45a8ff 572 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 /* Configure display size and porch areas */
bogdanm 0:9b334a45a8ff 575 EBI_TFTSizeSet(ebiTFTInit->hsize,
bogdanm 0:9b334a45a8ff 576 ebiTFTInit->vsize);
bogdanm 0:9b334a45a8ff 577 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
bogdanm 0:9b334a45a8ff 578 ebiTFTInit->hPorchBack,
bogdanm 0:9b334a45a8ff 579 ebiTFTInit->hPulseWidth);
bogdanm 0:9b334a45a8ff 580 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
bogdanm 0:9b334a45a8ff 581 ebiTFTInit->vPorchBack,
bogdanm 0:9b334a45a8ff 582 ebiTFTInit->vPulseWidth);
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 /* Configure timing settings */
bogdanm 0:9b334a45a8ff 585 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
bogdanm 0:9b334a45a8ff 586 ebiTFTInit->startPosition,
bogdanm 0:9b334a45a8ff 587 ebiTFTInit->setupCycles,
bogdanm 0:9b334a45a8ff 588 ebiTFTInit->holdCycles);
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /* Configure line polarity settings */
bogdanm 0:9b334a45a8ff 591 EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
bogdanm 0:9b334a45a8ff 592 EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
bogdanm 0:9b334a45a8ff 593 EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
bogdanm 0:9b334a45a8ff 594 EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
bogdanm 0:9b334a45a8ff 595 EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 /* Main control, EBI bank select, mask and blending configuration */
bogdanm 0:9b334a45a8ff 598 ctrl =
bogdanm 0:9b334a45a8ff 599 (uint32_t)(ebiTFTInit->bank) |
bogdanm 0:9b334a45a8ff 600 (uint32_t)(ebiTFTInit->width) |
bogdanm 0:9b334a45a8ff 601 (uint32_t)(ebiTFTInit->colSrc) |
bogdanm 0:9b334a45a8ff 602 (uint32_t)(ebiTFTInit->interleave) |
bogdanm 0:9b334a45a8ff 603 (uint32_t)(ebiTFTInit->fbTrigger) |
bogdanm 0:9b334a45a8ff 604 (uint32_t)(ebiTFTInit->shiftDClk == true ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0) |
bogdanm 0:9b334a45a8ff 605 (uint32_t)(ebiTFTInit->maskBlend) |
bogdanm 0:9b334a45a8ff 606 (uint32_t)(ebiTFTInit->driveMode);
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 EBI->TFTCTRL = ctrl;
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 /* Enable TFT pins */
bogdanm 0:9b334a45a8ff 611 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
bogdanm 0:9b334a45a8ff 612 {
bogdanm 0:9b334a45a8ff 613 EBI->ROUTE |= (EBI_ROUTE_TFTPEN);
bogdanm 0:9b334a45a8ff 614 }
bogdanm 0:9b334a45a8ff 615 }
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 619 * @brief
bogdanm 0:9b334a45a8ff 620 * Configure and initialize TFT size settings
bogdanm 0:9b334a45a8ff 621 *
bogdanm 0:9b334a45a8ff 622 * @param[in] horizontal
bogdanm 0:9b334a45a8ff 623 * TFT display horizontal size in pixels
bogdanm 0:9b334a45a8ff 624 * @param[in] vertical
bogdanm 0:9b334a45a8ff 625 * TFT display vertical size in pixels
bogdanm 0:9b334a45a8ff 626 ******************************************************************************/
bogdanm 0:9b334a45a8ff 627 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
bogdanm 0:9b334a45a8ff 628 {
bogdanm 0:9b334a45a8ff 629 EFM_ASSERT((horizontal-1) < 1024);
bogdanm 0:9b334a45a8ff 630 EFM_ASSERT((vertical-1) < 1024);
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT) |
bogdanm 0:9b334a45a8ff 633 ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
bogdanm 0:9b334a45a8ff 634 }
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 637 * @brief
bogdanm 0:9b334a45a8ff 638 * Configure and initialize Horizontal Porch Settings
bogdanm 0:9b334a45a8ff 639 *
bogdanm 0:9b334a45a8ff 640 * @param[in] front
bogdanm 0:9b334a45a8ff 641 * Horizontal front porch size in pixels
bogdanm 0:9b334a45a8ff 642 * @param[in] back
bogdanm 0:9b334a45a8ff 643 * Horizontal back porch size in pixels
bogdanm 0:9b334a45a8ff 644 * @param[in] pulseWidth
bogdanm 0:9b334a45a8ff 645 * Horizontal synchronization pulse width. Set to required -1.
bogdanm 0:9b334a45a8ff 646 ******************************************************************************/
bogdanm 0:9b334a45a8ff 647 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
bogdanm 0:9b334a45a8ff 648 {
bogdanm 0:9b334a45a8ff 649 EFM_ASSERT(front < 256);
bogdanm 0:9b334a45a8ff 650 EFM_ASSERT(back < 256);
bogdanm 0:9b334a45a8ff 651 EFM_ASSERT((pulseWidth-1) < 128);
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT) |
bogdanm 0:9b334a45a8ff 654 (back << _EBI_TFTHPORCH_HBPORCH_SHIFT) |
bogdanm 0:9b334a45a8ff 655 ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
bogdanm 0:9b334a45a8ff 656 }
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 660 * @brief
bogdanm 0:9b334a45a8ff 661 * Configure Vertical Porch Settings
bogdanm 0:9b334a45a8ff 662 *
bogdanm 0:9b334a45a8ff 663 * @param[in] front
bogdanm 0:9b334a45a8ff 664 * Vertical front porch size in pixels
bogdanm 0:9b334a45a8ff 665 * @param[in] back
bogdanm 0:9b334a45a8ff 666 * Vertical back porch size in pixels
bogdanm 0:9b334a45a8ff 667 * @param[in] pulseWidth
bogdanm 0:9b334a45a8ff 668 * Vertical synchronization pulse width. Set to required -1.
bogdanm 0:9b334a45a8ff 669 ******************************************************************************/
bogdanm 0:9b334a45a8ff 670 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
bogdanm 0:9b334a45a8ff 671 {
bogdanm 0:9b334a45a8ff 672 EFM_ASSERT(front < 256);
bogdanm 0:9b334a45a8ff 673 EFM_ASSERT(back < 256);
bogdanm 0:9b334a45a8ff 674 EFM_ASSERT((pulseWidth-1) < 128);
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT) |
bogdanm 0:9b334a45a8ff 677 (back << _EBI_TFTVPORCH_VBPORCH_SHIFT) |
bogdanm 0:9b334a45a8ff 678 ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 683 * @brief
bogdanm 0:9b334a45a8ff 684 * Configure TFT Direct Drive Timing Settings
bogdanm 0:9b334a45a8ff 685 *
bogdanm 0:9b334a45a8ff 686 * @param[in] dclkPeriod
bogdanm 0:9b334a45a8ff 687 * DCLK period in internal cycles
bogdanm 0:9b334a45a8ff 688 *
bogdanm 0:9b334a45a8ff 689 * @param[in] start
bogdanm 0:9b334a45a8ff 690 * Starting position of external direct drive, relative to DCLK inactive edge
bogdanm 0:9b334a45a8ff 691 *
bogdanm 0:9b334a45a8ff 692 * @param[in] setup
bogdanm 0:9b334a45a8ff 693 * Number of cycles RGB data is driven before active edge of DCLK
bogdanm 0:9b334a45a8ff 694 *
bogdanm 0:9b334a45a8ff 695 * @param[in] hold
bogdanm 0:9b334a45a8ff 696 * Number of cycles RGB data is held after active edge of DCLK
bogdanm 0:9b334a45a8ff 697 ******************************************************************************/
bogdanm 0:9b334a45a8ff 698 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
bogdanm 0:9b334a45a8ff 699 {
bogdanm 0:9b334a45a8ff 700 EFM_ASSERT(dclkPeriod < 2048);
bogdanm 0:9b334a45a8ff 701 EFM_ASSERT(start < 2048);
bogdanm 0:9b334a45a8ff 702 EFM_ASSERT(setup < 4);
bogdanm 0:9b334a45a8ff 703 EFM_ASSERT(hold < 4);
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT) |
bogdanm 0:9b334a45a8ff 706 (start << _EBI_TFTTIMING_TFTSTART_SHIFT) |
bogdanm 0:9b334a45a8ff 707 (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 708 (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 709 }
bogdanm 0:9b334a45a8ff 710 #endif
bogdanm 0:9b334a45a8ff 711
bogdanm 0:9b334a45a8ff 712 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 713 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 714 * @brief
bogdanm 0:9b334a45a8ff 715 * Configure read operation parameters for selected bank
bogdanm 0:9b334a45a8ff 716 *
bogdanm 0:9b334a45a8ff 717 * @param[in] banks
bogdanm 0:9b334a45a8ff 718 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 719 *
bogdanm 0:9b334a45a8ff 720 * @param[in] pageMode
bogdanm 0:9b334a45a8ff 721 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 722 *
bogdanm 0:9b334a45a8ff 723 * @param[in] prefetch
bogdanm 0:9b334a45a8ff 724 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 725 *
bogdanm 0:9b334a45a8ff 726 * @param[in] halfRE
bogdanm 0:9b334a45a8ff 727 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 728 ******************************************************************************/
bogdanm 0:9b334a45a8ff 729 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
bogdanm 0:9b334a45a8ff 730 {
bogdanm 0:9b334a45a8ff 731 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 732 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 /* Configure read operation parameters */
bogdanm 0:9b334a45a8ff 735 if( banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 736 {
bogdanm 0:9b334a45a8ff 737 BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
bogdanm 0:9b334a45a8ff 738 BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
bogdanm 0:9b334a45a8ff 739 BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 740 }
bogdanm 0:9b334a45a8ff 741 if( banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 742 {
bogdanm 0:9b334a45a8ff 743 BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
bogdanm 0:9b334a45a8ff 744 BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
bogdanm 0:9b334a45a8ff 745 BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 746 }
bogdanm 0:9b334a45a8ff 747 if( banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 748 {
bogdanm 0:9b334a45a8ff 749 BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
bogdanm 0:9b334a45a8ff 750 BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
bogdanm 0:9b334a45a8ff 751 BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753 if( banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
bogdanm 0:9b334a45a8ff 756 BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
bogdanm 0:9b334a45a8ff 757 BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
bogdanm 0:9b334a45a8ff 758 }
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 762 * @brief
bogdanm 0:9b334a45a8ff 763 * Configure timing values of read bus accesses
bogdanm 0:9b334a45a8ff 764 *
bogdanm 0:9b334a45a8ff 765 * @param[in] banks
bogdanm 0:9b334a45a8ff 766 * Mask of memory bank(s) to configure timing for
bogdanm 0:9b334a45a8ff 767 *
bogdanm 0:9b334a45a8ff 768 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 769 * Number of clock cycles for address setup before REn is asserted
bogdanm 0:9b334a45a8ff 770 *
bogdanm 0:9b334a45a8ff 771 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 772 * The number of cycles the REn is held active. After the specified number of
bogdanm 0:9b334a45a8ff 773 * cycles, data is read. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 774 *
bogdanm 0:9b334a45a8ff 775 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 776 * The number of cycles CSn is held active after the REn is dessarted
bogdanm 0:9b334a45a8ff 777 ******************************************************************************/
bogdanm 0:9b334a45a8ff 778 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 779 {
bogdanm 0:9b334a45a8ff 780 uint32_t readTiming;
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 783 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 786 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 787 EFM_ASSERT(strobeCycles < 64);
bogdanm 0:9b334a45a8ff 788 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* Configure timing values */
bogdanm 0:9b334a45a8ff 791 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 792 (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
bogdanm 0:9b334a45a8ff 793 (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 796 {
bogdanm 0:9b334a45a8ff 797 EBI->RDTIMING = (EBI->RDTIMING &
bogdanm 0:9b334a45a8ff 798 ~(_EBI_RDTIMING_RDSETUP_MASK |
bogdanm 0:9b334a45a8ff 799 _EBI_RDTIMING_RDSTRB_MASK |
bogdanm 0:9b334a45a8ff 800 _EBI_RDTIMING_RDHOLD_MASK)) | readTiming;
bogdanm 0:9b334a45a8ff 801 }
bogdanm 0:9b334a45a8ff 802 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 803 {
bogdanm 0:9b334a45a8ff 804 EBI->RDTIMING1 = (EBI->RDTIMING1 &
bogdanm 0:9b334a45a8ff 805 ~(_EBI_RDTIMING1_RDSETUP_MASK |
bogdanm 0:9b334a45a8ff 806 _EBI_RDTIMING1_RDSTRB_MASK |
bogdanm 0:9b334a45a8ff 807 _EBI_RDTIMING1_RDHOLD_MASK)) | readTiming;
bogdanm 0:9b334a45a8ff 808 }
bogdanm 0:9b334a45a8ff 809 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 810 {
bogdanm 0:9b334a45a8ff 811 EBI->RDTIMING2 = (EBI->RDTIMING2 &
bogdanm 0:9b334a45a8ff 812 ~(_EBI_RDTIMING2_RDSETUP_MASK |
bogdanm 0:9b334a45a8ff 813 _EBI_RDTIMING2_RDSTRB_MASK |
bogdanm 0:9b334a45a8ff 814 _EBI_RDTIMING2_RDHOLD_MASK)) | readTiming;
bogdanm 0:9b334a45a8ff 815 }
bogdanm 0:9b334a45a8ff 816 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 817 {
bogdanm 0:9b334a45a8ff 818 EBI->RDTIMING3 = (EBI->RDTIMING3 &
bogdanm 0:9b334a45a8ff 819 ~(_EBI_RDTIMING3_RDSETUP_MASK |
bogdanm 0:9b334a45a8ff 820 _EBI_RDTIMING3_RDSTRB_MASK |
bogdanm 0:9b334a45a8ff 821 _EBI_RDTIMING3_RDHOLD_MASK)) | readTiming;
bogdanm 0:9b334a45a8ff 822 }
bogdanm 0:9b334a45a8ff 823 }
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 827 * @brief
bogdanm 0:9b334a45a8ff 828 * Configure write operation parameters for selected bank
bogdanm 0:9b334a45a8ff 829 *
bogdanm 0:9b334a45a8ff 830 * @param[in] banks
bogdanm 0:9b334a45a8ff 831 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 832 *
bogdanm 0:9b334a45a8ff 833 * @param[in] writeBufDisable
bogdanm 0:9b334a45a8ff 834 * If true, disable the write buffer
bogdanm 0:9b334a45a8ff 835 *
bogdanm 0:9b334a45a8ff 836 * @param[in] halfWE
bogdanm 0:9b334a45a8ff 837 * Enables or disables half cycle WE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 838 ******************************************************************************/
bogdanm 0:9b334a45a8ff 839 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
bogdanm 0:9b334a45a8ff 840 {
bogdanm 0:9b334a45a8ff 841 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 842 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Configure write operation parameters */
bogdanm 0:9b334a45a8ff 845 if( banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
bogdanm 0:9b334a45a8ff 848 BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 849 }
bogdanm 0:9b334a45a8ff 850 if( banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 851 {
bogdanm 0:9b334a45a8ff 852 BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
bogdanm 0:9b334a45a8ff 853 BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855 if( banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 856 {
bogdanm 0:9b334a45a8ff 857 BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
bogdanm 0:9b334a45a8ff 858 BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 859 }
bogdanm 0:9b334a45a8ff 860 if( banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 861 {
bogdanm 0:9b334a45a8ff 862 BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
bogdanm 0:9b334a45a8ff 863 BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
bogdanm 0:9b334a45a8ff 864 }
bogdanm 0:9b334a45a8ff 865 }
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 869 * @brief
bogdanm 0:9b334a45a8ff 870 * Configure timing values of write bus accesses
bogdanm 0:9b334a45a8ff 871 *
bogdanm 0:9b334a45a8ff 872 * @param[in] banks
bogdanm 0:9b334a45a8ff 873 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 874 *
bogdanm 0:9b334a45a8ff 875 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 876 * Number of clock cycles for address setup before WEn is asserted
bogdanm 0:9b334a45a8ff 877 *
bogdanm 0:9b334a45a8ff 878 * @param[in] strobeCycles
bogdanm 0:9b334a45a8ff 879 * Number of cycles WEn is held active. If set to 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 880 *
bogdanm 0:9b334a45a8ff 881 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 882 * Number of cycles CSn is held active after the WEn is deasserted
bogdanm 0:9b334a45a8ff 883 ******************************************************************************/
bogdanm 0:9b334a45a8ff 884 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 885 {
bogdanm 0:9b334a45a8ff 886 uint32_t writeTiming;
bogdanm 0:9b334a45a8ff 887
bogdanm 0:9b334a45a8ff 888 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 889 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 /* Check that timings are within limits */
bogdanm 0:9b334a45a8ff 892 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 893 EFM_ASSERT(strobeCycles < 64);
bogdanm 0:9b334a45a8ff 894 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 /* Configure timing values */
bogdanm 0:9b334a45a8ff 897 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 898 (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
bogdanm 0:9b334a45a8ff 899 (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 902 {
bogdanm 0:9b334a45a8ff 903 EBI->WRTIMING = (EBI->WRTIMING &
bogdanm 0:9b334a45a8ff 904 ~(_EBI_WRTIMING_WRSETUP_MASK |
bogdanm 0:9b334a45a8ff 905 _EBI_WRTIMING_WRSTRB_MASK |
bogdanm 0:9b334a45a8ff 906 _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming;
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 909 {
bogdanm 0:9b334a45a8ff 910 EBI->WRTIMING1 = (EBI->WRTIMING1 &
bogdanm 0:9b334a45a8ff 911 ~(_EBI_WRTIMING1_WRSETUP_MASK |
bogdanm 0:9b334a45a8ff 912 _EBI_WRTIMING1_WRSTRB_MASK |
bogdanm 0:9b334a45a8ff 913 _EBI_WRTIMING1_WRHOLD_MASK)) | writeTiming;
bogdanm 0:9b334a45a8ff 914 }
bogdanm 0:9b334a45a8ff 915 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 916 {
bogdanm 0:9b334a45a8ff 917 EBI->WRTIMING2 = (EBI->WRTIMING2 &
bogdanm 0:9b334a45a8ff 918 ~(_EBI_WRTIMING2_WRSETUP_MASK |
bogdanm 0:9b334a45a8ff 919 _EBI_WRTIMING2_WRSTRB_MASK |
bogdanm 0:9b334a45a8ff 920 _EBI_WRTIMING2_WRHOLD_MASK)) | writeTiming;
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 923 {
bogdanm 0:9b334a45a8ff 924 EBI->WRTIMING3 = (EBI->WRTIMING3 &
bogdanm 0:9b334a45a8ff 925 ~(_EBI_WRTIMING3_WRSETUP_MASK |
bogdanm 0:9b334a45a8ff 926 _EBI_WRTIMING3_WRSTRB_MASK |
bogdanm 0:9b334a45a8ff 927 _EBI_WRTIMING3_WRHOLD_MASK)) | writeTiming;
bogdanm 0:9b334a45a8ff 928 }
bogdanm 0:9b334a45a8ff 929 }
bogdanm 0:9b334a45a8ff 930
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 933 * @brief
bogdanm 0:9b334a45a8ff 934 * Configure address operation parameters for selected bank
bogdanm 0:9b334a45a8ff 935 *
bogdanm 0:9b334a45a8ff 936 * @param[in] banks
bogdanm 0:9b334a45a8ff 937 * Mask of memory bank(s) to configure write timing for
bogdanm 0:9b334a45a8ff 938 *
bogdanm 0:9b334a45a8ff 939 * @param[in] halfALE
bogdanm 0:9b334a45a8ff 940 * Enables or disables half cycle ALE strobe in last strobe cycle
bogdanm 0:9b334a45a8ff 941 ******************************************************************************/
bogdanm 0:9b334a45a8ff 942 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
bogdanm 0:9b334a45a8ff 943 {
bogdanm 0:9b334a45a8ff 944 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 945 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 946
bogdanm 0:9b334a45a8ff 947 if( banks & EBI_BANK0 )
bogdanm 0:9b334a45a8ff 948 {
bogdanm 0:9b334a45a8ff 949 BITBAND_Peripheral(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 950 }
bogdanm 0:9b334a45a8ff 951 if( banks & EBI_BANK1 )
bogdanm 0:9b334a45a8ff 952 {
bogdanm 0:9b334a45a8ff 953 BITBAND_Peripheral(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 954 }
bogdanm 0:9b334a45a8ff 955 if( banks & EBI_BANK2 )
bogdanm 0:9b334a45a8ff 956 {
bogdanm 0:9b334a45a8ff 957 BITBAND_Peripheral(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 958 }
bogdanm 0:9b334a45a8ff 959 if( banks & EBI_BANK3 )
bogdanm 0:9b334a45a8ff 960 {
bogdanm 0:9b334a45a8ff 961 BITBAND_Peripheral(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
bogdanm 0:9b334a45a8ff 962 }
bogdanm 0:9b334a45a8ff 963 }
bogdanm 0:9b334a45a8ff 964
bogdanm 0:9b334a45a8ff 965
bogdanm 0:9b334a45a8ff 966 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 967 * @brief
bogdanm 0:9b334a45a8ff 968 * Configure timing values of address latch bus accesses
bogdanm 0:9b334a45a8ff 969 *
bogdanm 0:9b334a45a8ff 970 * @param[in] banks
bogdanm 0:9b334a45a8ff 971 * Mask of memory bank(s) to configure address timing for
bogdanm 0:9b334a45a8ff 972 *
bogdanm 0:9b334a45a8ff 973 * @param[in] setupCycles
bogdanm 0:9b334a45a8ff 974 * Sets the number of cycles the address is held after ALE is asserted
bogdanm 0:9b334a45a8ff 975 *
bogdanm 0:9b334a45a8ff 976 * @param[in] holdCycles
bogdanm 0:9b334a45a8ff 977 * Sets the number of cycles the address is driven onto the ADDRDAT bus before
bogdanm 0:9b334a45a8ff 978 * ALE is asserted. If set 0, 1 cycle is inserted by HW
bogdanm 0:9b334a45a8ff 979 ******************************************************************************/
bogdanm 0:9b334a45a8ff 980 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
bogdanm 0:9b334a45a8ff 981 {
bogdanm 0:9b334a45a8ff 982 uint32_t addressLatchTiming;
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 985 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 986
bogdanm 0:9b334a45a8ff 987 /* Check that timing values are within limits */
bogdanm 0:9b334a45a8ff 988 EFM_ASSERT(setupCycles < 4);
bogdanm 0:9b334a45a8ff 989 EFM_ASSERT(holdCycles < 4);
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /* Configure address latch timing values */
bogdanm 0:9b334a45a8ff 992 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
bogdanm 0:9b334a45a8ff 993 (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
bogdanm 0:9b334a45a8ff 994
bogdanm 0:9b334a45a8ff 995 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 996 {
bogdanm 0:9b334a45a8ff 997 EBI->ADDRTIMING = (EBI->ADDRTIMING &
bogdanm 0:9b334a45a8ff 998 ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
bogdanm 0:9b334a45a8ff 999 _EBI_ADDRTIMING_ADDRHOLD_MASK)) | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1000 }
bogdanm 0:9b334a45a8ff 1001 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 1002 {
bogdanm 0:9b334a45a8ff 1003 EBI->ADDRTIMING1 = (EBI->ADDRTIMING1 &
bogdanm 0:9b334a45a8ff 1004 ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK |
bogdanm 0:9b334a45a8ff 1005 _EBI_ADDRTIMING1_ADDRHOLD_MASK)) | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1006 }
bogdanm 0:9b334a45a8ff 1007 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 1008 {
bogdanm 0:9b334a45a8ff 1009 EBI->ADDRTIMING2 = (EBI->ADDRTIMING2 &
bogdanm 0:9b334a45a8ff 1010 ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK |
bogdanm 0:9b334a45a8ff 1011 _EBI_ADDRTIMING2_ADDRHOLD_MASK)) | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1012 }
bogdanm 0:9b334a45a8ff 1013 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 1014 {
bogdanm 0:9b334a45a8ff 1015 EBI->ADDRTIMING3 = (EBI->ADDRTIMING3 &
bogdanm 0:9b334a45a8ff 1016 ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK |
bogdanm 0:9b334a45a8ff 1017 _EBI_ADDRTIMING3_ADDRHOLD_MASK)) | addressLatchTiming;
bogdanm 0:9b334a45a8ff 1018 }
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021
bogdanm 0:9b334a45a8ff 1022 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 1023 * @brief
bogdanm 0:9b334a45a8ff 1024 * Configure EBI pin polarity for selected bank(s) for devices with individual
bogdanm 0:9b334a45a8ff 1025 * timing support
bogdanm 0:9b334a45a8ff 1026 *
bogdanm 0:9b334a45a8ff 1027 * @param[in] banks
bogdanm 0:9b334a45a8ff 1028 * Mask of memory bank(s) to configure polarity for
bogdanm 0:9b334a45a8ff 1029 *
bogdanm 0:9b334a45a8ff 1030 * @param[in] line
bogdanm 0:9b334a45a8ff 1031 * Which pin/line to configure
bogdanm 0:9b334a45a8ff 1032 *
bogdanm 0:9b334a45a8ff 1033 * @param[in] polarity
bogdanm 0:9b334a45a8ff 1034 * Active high, or active low
bogdanm 0:9b334a45a8ff 1035 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1036 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
bogdanm 0:9b334a45a8ff 1037 {
bogdanm 0:9b334a45a8ff 1038 uint32_t bankSet = 0;
bogdanm 0:9b334a45a8ff 1039 volatile uint32_t *polRegister = 0;
bogdanm 0:9b334a45a8ff 1040
bogdanm 0:9b334a45a8ff 1041 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 1042 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 while (banks)
bogdanm 0:9b334a45a8ff 1045 {
bogdanm 0:9b334a45a8ff 1046 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 1047 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 1048 {
bogdanm 0:9b334a45a8ff 1049 polRegister = &EBI->POLARITY;
bogdanm 0:9b334a45a8ff 1050 bankSet = EBI_BANK0;
bogdanm 0:9b334a45a8ff 1051 }
bogdanm 0:9b334a45a8ff 1052 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 1053 {
bogdanm 0:9b334a45a8ff 1054 polRegister = &EBI->POLARITY1;
bogdanm 0:9b334a45a8ff 1055 bankSet = EBI_BANK1;
bogdanm 0:9b334a45a8ff 1056 }
bogdanm 0:9b334a45a8ff 1057 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 1058 {
bogdanm 0:9b334a45a8ff 1059 polRegister = &EBI->POLARITY2;
bogdanm 0:9b334a45a8ff 1060 bankSet = EBI_BANK2;
bogdanm 0:9b334a45a8ff 1061 }
bogdanm 0:9b334a45a8ff 1062 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 1063 {
bogdanm 0:9b334a45a8ff 1064 polRegister = &EBI->POLARITY3;
bogdanm 0:9b334a45a8ff 1065 bankSet = EBI_BANK3;
bogdanm 0:9b334a45a8ff 1066 }
bogdanm 0:9b334a45a8ff 1067 #else
bogdanm 0:9b334a45a8ff 1068 polRegister = &EBI->POLARITY;
bogdanm 0:9b334a45a8ff 1069 banks = 0;
bogdanm 0:9b334a45a8ff 1070 #endif
bogdanm 0:9b334a45a8ff 1071
bogdanm 0:9b334a45a8ff 1072 /* What line to configure */
bogdanm 0:9b334a45a8ff 1073 switch (line)
bogdanm 0:9b334a45a8ff 1074 {
bogdanm 0:9b334a45a8ff 1075 case ebiLineARDY:
bogdanm 0:9b334a45a8ff 1076 BITBAND_Peripheral(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1077 break;
bogdanm 0:9b334a45a8ff 1078 case ebiLineALE:
bogdanm 0:9b334a45a8ff 1079 BITBAND_Peripheral(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1080 break;
bogdanm 0:9b334a45a8ff 1081 case ebiLineWE:
bogdanm 0:9b334a45a8ff 1082 BITBAND_Peripheral(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1083 break;
bogdanm 0:9b334a45a8ff 1084 case ebiLineRE:
bogdanm 0:9b334a45a8ff 1085 BITBAND_Peripheral(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1086 break;
bogdanm 0:9b334a45a8ff 1087 case ebiLineCS:
bogdanm 0:9b334a45a8ff 1088 BITBAND_Peripheral(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1089 break;
bogdanm 0:9b334a45a8ff 1090 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
bogdanm 0:9b334a45a8ff 1091 case ebiLineBL:
bogdanm 0:9b334a45a8ff 1092 BITBAND_Peripheral(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1093 break;
bogdanm 0:9b334a45a8ff 1094 case ebiLineTFTVSync:
bogdanm 0:9b334a45a8ff 1095 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1096 break;
bogdanm 0:9b334a45a8ff 1097 case ebiLineTFTHSync:
bogdanm 0:9b334a45a8ff 1098 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1099 break;
bogdanm 0:9b334a45a8ff 1100 case ebiLineTFTDataEn:
bogdanm 0:9b334a45a8ff 1101 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1102 break;
bogdanm 0:9b334a45a8ff 1103 case ebiLineTFTDClk:
bogdanm 0:9b334a45a8ff 1104 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1105 break;
bogdanm 0:9b334a45a8ff 1106 case ebiLineTFTCS:
bogdanm 0:9b334a45a8ff 1107 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
bogdanm 0:9b334a45a8ff 1108 break;
bogdanm 0:9b334a45a8ff 1109 #endif
bogdanm 0:9b334a45a8ff 1110 default:
bogdanm 0:9b334a45a8ff 1111 EFM_ASSERT(0);
bogdanm 0:9b334a45a8ff 1112 break;
bogdanm 0:9b334a45a8ff 1113 }
bogdanm 0:9b334a45a8ff 1114 banks = banks & (~bankSet);
bogdanm 0:9b334a45a8ff 1115 }
bogdanm 0:9b334a45a8ff 1116 }
bogdanm 0:9b334a45a8ff 1117
bogdanm 0:9b334a45a8ff 1118
bogdanm 0:9b334a45a8ff 1119 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 1120 * @brief
bogdanm 0:9b334a45a8ff 1121 * Configure Byte Lane Enable for select banks
bogdanm 0:9b334a45a8ff 1122 * timing support
bogdanm 0:9b334a45a8ff 1123 *
bogdanm 0:9b334a45a8ff 1124 * @param[in] banks
bogdanm 0:9b334a45a8ff 1125 * Mask of memory bank(s) to configure polarity for
bogdanm 0:9b334a45a8ff 1126 *
bogdanm 0:9b334a45a8ff 1127 * @param[in] enable
bogdanm 0:9b334a45a8ff 1128 * Flag
bogdanm 0:9b334a45a8ff 1129 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1130 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
bogdanm 0:9b334a45a8ff 1131 {
bogdanm 0:9b334a45a8ff 1132 /* Verify only valid banks are used */
bogdanm 0:9b334a45a8ff 1133 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /* Configure byte lane support for each selected bank */
bogdanm 0:9b334a45a8ff 1136 if (banks & EBI_BANK0)
bogdanm 0:9b334a45a8ff 1137 {
bogdanm 0:9b334a45a8ff 1138 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1139 }
bogdanm 0:9b334a45a8ff 1140 if (banks & EBI_BANK1)
bogdanm 0:9b334a45a8ff 1141 {
bogdanm 0:9b334a45a8ff 1142 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1143 }
bogdanm 0:9b334a45a8ff 1144 if (banks & EBI_BANK2)
bogdanm 0:9b334a45a8ff 1145 {
bogdanm 0:9b334a45a8ff 1146 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1147 }
bogdanm 0:9b334a45a8ff 1148 if (banks & EBI_BANK3)
bogdanm 0:9b334a45a8ff 1149 {
bogdanm 0:9b334a45a8ff 1150 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1151 }
bogdanm 0:9b334a45a8ff 1152 }
bogdanm 0:9b334a45a8ff 1153
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 1156 * @brief
bogdanm 0:9b334a45a8ff 1157 * Configure Alternate Address Map support
bogdanm 0:9b334a45a8ff 1158 * Enables or disables 256MB address range for all banks
bogdanm 0:9b334a45a8ff 1159 *
bogdanm 0:9b334a45a8ff 1160 * @param[in] enable
bogdanm 0:9b334a45a8ff 1161 * Set or clear address map extension
bogdanm 0:9b334a45a8ff 1162 ******************************************************************************/
bogdanm 0:9b334a45a8ff 1163 void EBI_AltMapEnable(bool enable)
bogdanm 0:9b334a45a8ff 1164 {
bogdanm 0:9b334a45a8ff 1165 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
bogdanm 0:9b334a45a8ff 1166 }
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168 #endif
bogdanm 0:9b334a45a8ff 1169
bogdanm 0:9b334a45a8ff 1170 /** @} (end addtogroup EBI) */
bogdanm 0:9b334a45a8ff 1171 /** @} (end addtogroup EM_Library) */
bogdanm 0:9b334a45a8ff 1172
bogdanm 0:9b334a45a8ff 1173 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */