Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_i2c.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file em_i2c.c
bogdanm 0:9b334a45a8ff 3 * @brief Inter-integrated Circuit (I2C) Peripheral API
bogdanm 0:9b334a45a8ff 4 * @version 3.20.12
bogdanm 0:9b334a45a8ff 5 *******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
bogdanm 0:9b334a45a8ff 7 * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 *******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 21 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 22 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 23 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 24 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 25 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 28 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 29 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 ******************************************************************************/
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #include "em_i2c.h"
bogdanm 0:9b334a45a8ff 35 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #include "em_cmu.h"
bogdanm 0:9b334a45a8ff 38 #include "em_bitband.h"
bogdanm 0:9b334a45a8ff 39 #include "em_assert.h"
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 42 * @addtogroup EM_Library
bogdanm 0:9b334a45a8ff 43 * @{
bogdanm 0:9b334a45a8ff 44 ******************************************************************************/
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 47 * @addtogroup I2C
bogdanm 0:9b334a45a8ff 48 * @brief Inter-integrated Circuit (I2C) Peripheral API
bogdanm 0:9b334a45a8ff 49 * @{
bogdanm 0:9b334a45a8ff 50 ******************************************************************************/
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /*******************************************************************************
bogdanm 0:9b334a45a8ff 53 ******************************* DEFINES ***********************************
bogdanm 0:9b334a45a8ff 54 ******************************************************************************/
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 #if (I2C_COUNT == 1)
bogdanm 0:9b334a45a8ff 59 /** Validation of I2C register block pointer reference for assert statements. */
bogdanm 0:9b334a45a8ff 60 #define I2C_REF_VALID(ref) ((ref) == I2C0)
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 #elif (I2C_COUNT == 2)
bogdanm 0:9b334a45a8ff 63 /** Validation of I2C register block pointer reference for assert statements. */
bogdanm 0:9b334a45a8ff 64 #define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1))
bogdanm 0:9b334a45a8ff 65 #endif
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 /** Error flags indicating I2C transfer has failed somehow. */
bogdanm 0:9b334a45a8ff 68 /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
bogdanm 0:9b334a45a8ff 69 /* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
bogdanm 0:9b334a45a8ff 70 /* RXUF is only likely to occur with this SW if using a debugger peeking into */
bogdanm 0:9b334a45a8ff 71 /* RXDATA register. Thus, we ignore those types of fault. */
bogdanm 0:9b334a45a8ff 72 #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /** @endcond */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /*******************************************************************************
bogdanm 0:9b334a45a8ff 77 ******************************** ENUMS ************************************
bogdanm 0:9b334a45a8ff 78 ******************************************************************************/
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /** Master mode transfer states. */
bogdanm 0:9b334a45a8ff 83 typedef enum
bogdanm 0:9b334a45a8ff 84 {
bogdanm 0:9b334a45a8ff 85 i2cStateStartAddrSend, /**< Send start + (first part of) address. */
bogdanm 0:9b334a45a8ff 86 i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (first part of) address. */
bogdanm 0:9b334a45a8ff 87 i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on second part of 10 bit address. */
bogdanm 0:9b334a45a8ff 88 i2cStateRStartAddrSend, /**< Send repeated start + (first part of) address. */
bogdanm 0:9b334a45a8ff 89 i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on address sent after repeated start. */
bogdanm 0:9b334a45a8ff 90 i2cStateDataSend, /**< Send data. */
bogdanm 0:9b334a45a8ff 91 i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */
bogdanm 0:9b334a45a8ff 92 i2cStateWFData, /**< Wait for data. */
bogdanm 0:9b334a45a8ff 93 i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */
bogdanm 0:9b334a45a8ff 94 i2cStateDone /**< Transfer completed successfully. */
bogdanm 0:9b334a45a8ff 95 } I2C_TransferState_TypeDef;
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @endcond */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /*******************************************************************************
bogdanm 0:9b334a45a8ff 100 ******************************* STRUCTS ***********************************
bogdanm 0:9b334a45a8ff 101 ******************************************************************************/
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 /** Structure used to store state information on an ongoing master mode transfer. */
bogdanm 0:9b334a45a8ff 106 typedef struct
bogdanm 0:9b334a45a8ff 107 {
bogdanm 0:9b334a45a8ff 108 /** Current state. */
bogdanm 0:9b334a45a8ff 109 I2C_TransferState_TypeDef state;
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /** Result return code. */
bogdanm 0:9b334a45a8ff 112 I2C_TransferReturn_TypeDef result;
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /** Offset in current sequence buffer. */
bogdanm 0:9b334a45a8ff 115 uint16_t offset;
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Index to current sequence buffer in use. */
bogdanm 0:9b334a45a8ff 118 uint8_t bufIndx;
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /** Reference to I2C transfer sequence definition provided by user. */
bogdanm 0:9b334a45a8ff 121 I2C_TransferSeq_TypeDef *seq;
bogdanm 0:9b334a45a8ff 122 } I2C_Transfer_TypeDef;
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /** @endcond */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /*******************************************************************************
bogdanm 0:9b334a45a8ff 127 ***************************** LOCAL DATA *******^**************************
bogdanm 0:9b334a45a8ff 128 ******************************************************************************/
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /**
bogdanm 0:9b334a45a8ff 133 * Lookup table for Nlow + Nhigh setting defined by CLHR. Set undefined
bogdanm 0:9b334a45a8ff 134 * index (0x3) to reflect default setting just in case.
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136 static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 };
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /** Transfer state info for ongoing master mode transfer */
bogdanm 0:9b334a45a8ff 139 static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT];
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /** @endcond */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /*******************************************************************************
bogdanm 0:9b334a45a8ff 144 ************************** GLOBAL FUNCTIONS *******************************
bogdanm 0:9b334a45a8ff 145 ******************************************************************************/
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 148 * @brief
bogdanm 0:9b334a45a8ff 149 * Get current configured I2C bus frequency.
bogdanm 0:9b334a45a8ff 150 *
bogdanm 0:9b334a45a8ff 151 * @details
bogdanm 0:9b334a45a8ff 152 * This frequency is only of relevance when acting as master.
bogdanm 0:9b334a45a8ff 153 *
bogdanm 0:9b334a45a8ff 154 * @param[in] i2c
bogdanm 0:9b334a45a8ff 155 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 156 *
bogdanm 0:9b334a45a8ff 157 * @return
bogdanm 0:9b334a45a8ff 158 * Current I2C frequency in Hz.
bogdanm 0:9b334a45a8ff 159 ******************************************************************************/
bogdanm 0:9b334a45a8ff 160 uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
bogdanm 0:9b334a45a8ff 161 {
bogdanm 0:9b334a45a8ff 162 uint32_t hfperclk;
bogdanm 0:9b334a45a8ff 163 uint32_t n;
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* Max frequency is given by fSCL = fHFPERCLK/((Nlow + Nhigh)(DIV + 1) + 4) */
bogdanm 0:9b334a45a8ff 166 hfperclk = CMU_ClockFreqGet(cmuClock_HFPER);
bogdanm 0:9b334a45a8ff 167 n = (uint32_t)(i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]);
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 return(hfperclk / ((n * (i2c->CLKDIV + 1)) + 4));
bogdanm 0:9b334a45a8ff 170 }
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 174 * @brief
bogdanm 0:9b334a45a8ff 175 * Set I2C bus frequency.
bogdanm 0:9b334a45a8ff 176 *
bogdanm 0:9b334a45a8ff 177 * @details
bogdanm 0:9b334a45a8ff 178 * The bus frequency is only of relevance when acting as a master. The bus
bogdanm 0:9b334a45a8ff 179 * frequency should not be set higher than the max frequency accepted by the
bogdanm 0:9b334a45a8ff 180 * slowest device on the bus.
bogdanm 0:9b334a45a8ff 181 *
bogdanm 0:9b334a45a8ff 182 * Notice that due to asymmetric requirements on low and high I2C clock
bogdanm 0:9b334a45a8ff 183 * cycles by the I2C specification, the actual max frequency allowed in order
bogdanm 0:9b334a45a8ff 184 * to comply with the specification may be somewhat lower than expected.
bogdanm 0:9b334a45a8ff 185 *
bogdanm 0:9b334a45a8ff 186 * Please refer to the reference manual, details on I2C clock generation,
bogdanm 0:9b334a45a8ff 187 * for max allowed theoretical frequencies for different modes.
bogdanm 0:9b334a45a8ff 188 *
bogdanm 0:9b334a45a8ff 189 * @param[in] i2c
bogdanm 0:9b334a45a8ff 190 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 191 *
bogdanm 0:9b334a45a8ff 192 * @param[in] refFreq
bogdanm 0:9b334a45a8ff 193 * I2C reference clock frequency in Hz that will be used. If set to 0,
bogdanm 0:9b334a45a8ff 194 * the currently configured reference clock is assumed. Setting it to a higher
bogdanm 0:9b334a45a8ff 195 * than actual configured value only has the consequence of reducing the real
bogdanm 0:9b334a45a8ff 196 * I2C frequency.
bogdanm 0:9b334a45a8ff 197 *
bogdanm 0:9b334a45a8ff 198 * @param[in] freq
bogdanm 0:9b334a45a8ff 199 * Bus frequency to set (actual bus speed may be lower due to integer
bogdanm 0:9b334a45a8ff 200 * prescaling). Safe (according to I2C specification) max frequencies for
bogdanm 0:9b334a45a8ff 201 * standard, fast and fast+ modes are available using I2C_FREQ_ defines.
bogdanm 0:9b334a45a8ff 202 * (Using I2C_FREQ_ defines requires corresponding setting of @p type.)
bogdanm 0:9b334a45a8ff 203 * Slowest slave device on bus must always be considered.
bogdanm 0:9b334a45a8ff 204 *
bogdanm 0:9b334a45a8ff 205 * @param[in] type
bogdanm 0:9b334a45a8ff 206 * Clock low to high ratio type to use. If not using i2cClockHLRStandard,
bogdanm 0:9b334a45a8ff 207 * make sure all devices on the bus support the specified mode. Using a
bogdanm 0:9b334a45a8ff 208 * non-standard ratio is useful to achieve higher bus clock in fast and
bogdanm 0:9b334a45a8ff 209 * fast+ modes.
bogdanm 0:9b334a45a8ff 210 ******************************************************************************/
bogdanm 0:9b334a45a8ff 211 void I2C_BusFreqSet(I2C_TypeDef *i2c,
bogdanm 0:9b334a45a8ff 212 uint32_t refFreq,
bogdanm 0:9b334a45a8ff 213 uint32_t freq,
bogdanm 0:9b334a45a8ff 214 I2C_ClockHLR_TypeDef type)
bogdanm 0:9b334a45a8ff 215 {
bogdanm 0:9b334a45a8ff 216 uint32_t n;
bogdanm 0:9b334a45a8ff 217 uint32_t div;
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Avoid divide by 0 */
bogdanm 0:9b334a45a8ff 220 EFM_ASSERT(freq);
bogdanm 0:9b334a45a8ff 221 if (!freq)
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 return;
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Set the CLHR (clock low to high ratio). */
bogdanm 0:9b334a45a8ff 227 i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
bogdanm 0:9b334a45a8ff 228 i2c->CTRL |= type <<_I2C_CTRL_CLHR_SHIFT;
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Frequency is given by fSCL = fHFPERCLK/((Nlow + Nhigh)(DIV + 1) + 4), thus */
bogdanm 0:9b334a45a8ff 231 /* DIV = ((fHFPERCLK - 4fSCL)/((Nlow + Nhigh)fSCL)) - 1 */
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 if (!refFreq)
bogdanm 0:9b334a45a8ff 234 {
bogdanm 0:9b334a45a8ff 235 refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
bogdanm 0:9b334a45a8ff 236 }
bogdanm 0:9b334a45a8ff 237 n = (uint32_t)(i2cNSum[type]);
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 div = (refFreq - (4 * freq)) / (n * freq);
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 /* Clock divisor must be at least 1 in slave mode according to reference */
bogdanm 0:9b334a45a8ff 242 /* manual (in which case there is normally no need to set bus frequency). */
bogdanm 0:9b334a45a8ff 243 if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 div = 1;
bogdanm 0:9b334a45a8ff 246 }
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 EFM_ASSERT(div <= _I2C_CLKDIV_DIV_MASK);
bogdanm 0:9b334a45a8ff 249 i2c->CLKDIV = div;
bogdanm 0:9b334a45a8ff 250 }
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 254 * @brief
bogdanm 0:9b334a45a8ff 255 * Enable/disable I2C.
bogdanm 0:9b334a45a8ff 256 *
bogdanm 0:9b334a45a8ff 257 * @note
bogdanm 0:9b334a45a8ff 258 * After enabling the I2C (from being disabled), the I2C is in BUSY state.
bogdanm 0:9b334a45a8ff 259 *
bogdanm 0:9b334a45a8ff 260 * @param[in] i2c
bogdanm 0:9b334a45a8ff 261 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 262 *
bogdanm 0:9b334a45a8ff 263 * @param[in] enable
bogdanm 0:9b334a45a8ff 264 * true to enable counting, false to disable.
bogdanm 0:9b334a45a8ff 265 ******************************************************************************/
bogdanm 0:9b334a45a8ff 266 void I2C_Enable(I2C_TypeDef *i2c, bool enable)
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 EFM_ASSERT(I2C_REF_VALID(i2c));
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 BITBAND_Peripheral(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, (unsigned int)enable);
bogdanm 0:9b334a45a8ff 271 }
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 275 * @brief
bogdanm 0:9b334a45a8ff 276 * Initialize I2C.
bogdanm 0:9b334a45a8ff 277 *
bogdanm 0:9b334a45a8ff 278 * @param[in] i2c
bogdanm 0:9b334a45a8ff 279 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 280 *
bogdanm 0:9b334a45a8ff 281 * @param[in] init
bogdanm 0:9b334a45a8ff 282 * Pointer to I2C initialization structure.
bogdanm 0:9b334a45a8ff 283 ******************************************************************************/
bogdanm 0:9b334a45a8ff 284 void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
bogdanm 0:9b334a45a8ff 285 {
bogdanm 0:9b334a45a8ff 286 EFM_ASSERT(I2C_REF_VALID(i2c));
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 i2c->IEN = 0;
bogdanm 0:9b334a45a8ff 289 i2c->IFC = _I2C_IFC_MASK;
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Set SLAVE select mode */
bogdanm 0:9b334a45a8ff 292 BITBAND_Peripheral(&(i2c->CTRL),
bogdanm 0:9b334a45a8ff 293 _I2C_CTRL_SLAVE_SHIFT,
bogdanm 0:9b334a45a8ff 294 init->master ? 0 : 1);
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr);
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 BITBAND_Peripheral(&(i2c->CTRL),
bogdanm 0:9b334a45a8ff 299 _I2C_CTRL_EN_SHIFT,
bogdanm 0:9b334a45a8ff 300 (unsigned int)(init->enable));
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 305 * @brief
bogdanm 0:9b334a45a8ff 306 * Reset I2C to same state as after a HW reset.
bogdanm 0:9b334a45a8ff 307 *
bogdanm 0:9b334a45a8ff 308 * @note
bogdanm 0:9b334a45a8ff 309 * The ROUTE register is NOT reset by this function, in order to allow for
bogdanm 0:9b334a45a8ff 310 * centralized setup of this feature.
bogdanm 0:9b334a45a8ff 311 *
bogdanm 0:9b334a45a8ff 312 * @param[in] i2c
bogdanm 0:9b334a45a8ff 313 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 314 ******************************************************************************/
bogdanm 0:9b334a45a8ff 315 void I2C_Reset(I2C_TypeDef *i2c)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 i2c->CTRL = _I2C_CTRL_RESETVALUE;
bogdanm 0:9b334a45a8ff 318 i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE;
bogdanm 0:9b334a45a8ff 319 i2c->SADDR = _I2C_SADDR_RESETVALUE;
bogdanm 0:9b334a45a8ff 320 i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE;
bogdanm 0:9b334a45a8ff 321 i2c->IEN = _I2C_IEN_RESETVALUE;
bogdanm 0:9b334a45a8ff 322 i2c->IFC = _I2C_IFC_MASK;
bogdanm 0:9b334a45a8ff 323 /* Do not reset route register, setting should be done independently */
bogdanm 0:9b334a45a8ff 324 }
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 328 * @brief
bogdanm 0:9b334a45a8ff 329 * Continue an initiated I2C transfer (single master mode only).
bogdanm 0:9b334a45a8ff 330 *
bogdanm 0:9b334a45a8ff 331 * @details
bogdanm 0:9b334a45a8ff 332 * This function is used repeatedly after a I2C_TransferInit() in order to
bogdanm 0:9b334a45a8ff 333 * complete a transfer. It may be used in polled mode as the below example
bogdanm 0:9b334a45a8ff 334 * shows:
bogdanm 0:9b334a45a8ff 335 * @verbatim
bogdanm 0:9b334a45a8ff 336 * I2C_TransferReturn_TypeDef ret;
bogdanm 0:9b334a45a8ff 337 *
bogdanm 0:9b334a45a8ff 338 * // Do a polled transfer
bogdanm 0:9b334a45a8ff 339 * ret = I2C_TransferInit(I2C0, seq);
bogdanm 0:9b334a45a8ff 340 * while (ret == i2cTransferInProgress)
bogdanm 0:9b334a45a8ff 341 * {
bogdanm 0:9b334a45a8ff 342 * ret = I2C_Transfer(I2C0);
bogdanm 0:9b334a45a8ff 343 * }
bogdanm 0:9b334a45a8ff 344 * @endverbatim
bogdanm 0:9b334a45a8ff 345 * It may also be used in interrupt driven mode, where this function is invoked
bogdanm 0:9b334a45a8ff 346 * from the interrupt handler. Notice that if used in interrupt mode, NVIC
bogdanm 0:9b334a45a8ff 347 * interrupts must be configured and enabled for the I2C bus used. I2C
bogdanm 0:9b334a45a8ff 348 * peripheral specific interrupts are managed by this SW.
bogdanm 0:9b334a45a8ff 349 *
bogdanm 0:9b334a45a8ff 350 * @note
bogdanm 0:9b334a45a8ff 351 * Only single master mode is supported.
bogdanm 0:9b334a45a8ff 352 *
bogdanm 0:9b334a45a8ff 353 * @param[in] i2c
bogdanm 0:9b334a45a8ff 354 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 355 *
bogdanm 0:9b334a45a8ff 356 * @return
bogdanm 0:9b334a45a8ff 357 * Returns status for ongoing transfer.
bogdanm 0:9b334a45a8ff 358 * @li #i2cTransferInProgress - indicates that transfer not finished.
bogdanm 0:9b334a45a8ff 359 * @li #i2cTransferDone - transfer completed successfully.
bogdanm 0:9b334a45a8ff 360 * @li otherwise some sort of error has occurred.
bogdanm 0:9b334a45a8ff 361 *
bogdanm 0:9b334a45a8ff 362 ******************************************************************************/
bogdanm 0:9b334a45a8ff 363 I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
bogdanm 0:9b334a45a8ff 364 {
bogdanm 0:9b334a45a8ff 365 uint32_t tmp;
bogdanm 0:9b334a45a8ff 366 uint32_t pending;
bogdanm 0:9b334a45a8ff 367 I2C_Transfer_TypeDef *transfer;
bogdanm 0:9b334a45a8ff 368 I2C_TransferSeq_TypeDef *seq;
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 EFM_ASSERT(I2C_REF_VALID(i2c));
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 /* Support up to 2 I2C buses */
bogdanm 0:9b334a45a8ff 373 if (i2c == I2C0)
bogdanm 0:9b334a45a8ff 374 {
bogdanm 0:9b334a45a8ff 375 transfer = i2cTransfer;
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377 #if (I2C_COUNT > 1)
bogdanm 0:9b334a45a8ff 378 else if (i2c == I2C1)
bogdanm 0:9b334a45a8ff 379 {
bogdanm 0:9b334a45a8ff 380 transfer = i2cTransfer + 1;
bogdanm 0:9b334a45a8ff 381 }
bogdanm 0:9b334a45a8ff 382 #endif
bogdanm 0:9b334a45a8ff 383 else
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 return(i2cTransferUsageFault);
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 seq = transfer->seq;
bogdanm 0:9b334a45a8ff 389 for (;; )
bogdanm 0:9b334a45a8ff 390 {
bogdanm 0:9b334a45a8ff 391 pending = i2c->IF;
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /* If some sort of fault, abort transfer. */
bogdanm 0:9b334a45a8ff 394 if (pending & I2C_IF_ERRORS)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 if (pending & I2C_IF_ARBLOST)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 /* If arbitration fault, it indicates either a slave device */
bogdanm 0:9b334a45a8ff 399 /* not responding as expected, or other master which is not */
bogdanm 0:9b334a45a8ff 400 /* supported by this SW. */
bogdanm 0:9b334a45a8ff 401 transfer->result = i2cTransferArbLost;
bogdanm 0:9b334a45a8ff 402 }
bogdanm 0:9b334a45a8ff 403 else if (pending & I2C_IF_BUSERR)
bogdanm 0:9b334a45a8ff 404 {
bogdanm 0:9b334a45a8ff 405 /* A bus error indicates a misplaced start or stop, which should */
bogdanm 0:9b334a45a8ff 406 /* not occur in master mode controlled by this SW. */
bogdanm 0:9b334a45a8ff 407 transfer->result = i2cTransferBusErr;
bogdanm 0:9b334a45a8ff 408 }
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* If error situation occurred, it is difficult to know */
bogdanm 0:9b334a45a8ff 411 /* exact cause and how to resolve. It will be up to a wrapper */
bogdanm 0:9b334a45a8ff 412 /* to determine how to handle a fault/recovery if possible. */
bogdanm 0:9b334a45a8ff 413 transfer->state = i2cStateDone;
bogdanm 0:9b334a45a8ff 414 goto done;
bogdanm 0:9b334a45a8ff 415 }
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 switch (transfer->state)
bogdanm 0:9b334a45a8ff 418 {
bogdanm 0:9b334a45a8ff 419 /***************************************************/
bogdanm 0:9b334a45a8ff 420 /* Send first start+address (first byte if 10 bit) */
bogdanm 0:9b334a45a8ff 421 /***************************************************/
bogdanm 0:9b334a45a8ff 422 case i2cStateStartAddrSend:
bogdanm 0:9b334a45a8ff 423 if (seq->flags & I2C_FLAG_10BIT_ADDR)
bogdanm 0:9b334a45a8ff 424 {
bogdanm 0:9b334a45a8ff 425 tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* In 10 bit address mode, the address following the first */
bogdanm 0:9b334a45a8ff 428 /* start always indicate write. */
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430 else
bogdanm 0:9b334a45a8ff 431 {
bogdanm 0:9b334a45a8ff 432 tmp = (uint32_t)(seq->addr) & 0xfe;
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 if (seq->flags & I2C_FLAG_READ)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 /* Indicate read request */
bogdanm 0:9b334a45a8ff 437 tmp |= 1;
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439 }
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 transfer->state = i2cStateAddrWFAckNack;
bogdanm 0:9b334a45a8ff 442 i2c->TXDATA = tmp; /* Data not transmitted until START sent */
bogdanm 0:9b334a45a8ff 443 i2c->CMD = I2C_CMD_START;
bogdanm 0:9b334a45a8ff 444 goto done;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /*******************************************************/
bogdanm 0:9b334a45a8ff 447 /* Wait for ACK/NACK on address (first byte if 10 bit) */
bogdanm 0:9b334a45a8ff 448 /*******************************************************/
bogdanm 0:9b334a45a8ff 449 case i2cStateAddrWFAckNack:
bogdanm 0:9b334a45a8ff 450 if (pending & I2C_IF_NACK)
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 i2c->IFC = I2C_IFC_NACK;
bogdanm 0:9b334a45a8ff 453 transfer->result = i2cTransferNack;
bogdanm 0:9b334a45a8ff 454 transfer->state = i2cStateWFStopSent;
bogdanm 0:9b334a45a8ff 455 i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457 else if (pending & I2C_IF_ACK)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 i2c->IFC = I2C_IFC_ACK;
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* If 10 bit address, send 2nd byte of address. */
bogdanm 0:9b334a45a8ff 462 if (seq->flags & I2C_FLAG_10BIT_ADDR)
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464 transfer->state = i2cStateAddrWF2ndAckNack;
bogdanm 0:9b334a45a8ff 465 i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
bogdanm 0:9b334a45a8ff 466 }
bogdanm 0:9b334a45a8ff 467 else
bogdanm 0:9b334a45a8ff 468 {
bogdanm 0:9b334a45a8ff 469 /* Determine whether receiving or sending data */
bogdanm 0:9b334a45a8ff 470 if (seq->flags & I2C_FLAG_READ)
bogdanm 0:9b334a45a8ff 471 {
bogdanm 0:9b334a45a8ff 472 transfer->state = i2cStateWFData;
bogdanm 0:9b334a45a8ff 473 if(seq->buf[transfer->bufIndx].len==1)
bogdanm 0:9b334a45a8ff 474 {
bogdanm 0:9b334a45a8ff 475 i2c->CMD = I2C_CMD_NACK;
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477 }
bogdanm 0:9b334a45a8ff 478 else
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 transfer->state = i2cStateDataSend;
bogdanm 0:9b334a45a8ff 481 continue;
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485 goto done;
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /******************************************************/
bogdanm 0:9b334a45a8ff 488 /* Wait for ACK/NACK on second byte of 10 bit address */
bogdanm 0:9b334a45a8ff 489 /******************************************************/
bogdanm 0:9b334a45a8ff 490 case i2cStateAddrWF2ndAckNack:
bogdanm 0:9b334a45a8ff 491 if (pending & I2C_IF_NACK)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 i2c->IFC = I2C_IFC_NACK;
bogdanm 0:9b334a45a8ff 494 transfer->result = i2cTransferNack;
bogdanm 0:9b334a45a8ff 495 transfer->state = i2cStateWFStopSent;
bogdanm 0:9b334a45a8ff 496 i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 497 }
bogdanm 0:9b334a45a8ff 498 else if (pending & I2C_IF_ACK)
bogdanm 0:9b334a45a8ff 499 {
bogdanm 0:9b334a45a8ff 500 i2c->IFC = I2C_IFC_ACK;
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* If using plain read sequence with 10 bit address, switch to send */
bogdanm 0:9b334a45a8ff 503 /* repeated start. */
bogdanm 0:9b334a45a8ff 504 if (seq->flags & I2C_FLAG_READ)
bogdanm 0:9b334a45a8ff 505 {
bogdanm 0:9b334a45a8ff 506 transfer->state = i2cStateRStartAddrSend;
bogdanm 0:9b334a45a8ff 507 }
bogdanm 0:9b334a45a8ff 508 /* Otherwise expected to write 0 or more bytes */
bogdanm 0:9b334a45a8ff 509 else
bogdanm 0:9b334a45a8ff 510 {
bogdanm 0:9b334a45a8ff 511 transfer->state = i2cStateDataSend;
bogdanm 0:9b334a45a8ff 512 }
bogdanm 0:9b334a45a8ff 513 continue;
bogdanm 0:9b334a45a8ff 514 }
bogdanm 0:9b334a45a8ff 515 goto done;
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /*******************************/
bogdanm 0:9b334a45a8ff 518 /* Send repeated start+address */
bogdanm 0:9b334a45a8ff 519 /*******************************/
bogdanm 0:9b334a45a8ff 520 case i2cStateRStartAddrSend:
bogdanm 0:9b334a45a8ff 521 if (seq->flags & I2C_FLAG_10BIT_ADDR)
bogdanm 0:9b334a45a8ff 522 {
bogdanm 0:9b334a45a8ff 523 tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
bogdanm 0:9b334a45a8ff 524 }
bogdanm 0:9b334a45a8ff 525 else
bogdanm 0:9b334a45a8ff 526 {
bogdanm 0:9b334a45a8ff 527 tmp = seq->addr & 0xfe;
bogdanm 0:9b334a45a8ff 528 }
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /* If this is a write+read combined sequence, then read is about to start */
bogdanm 0:9b334a45a8ff 531 if (seq->flags & I2C_FLAG_WRITE_READ)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 /* Indicate read request */
bogdanm 0:9b334a45a8ff 534 tmp |= 1;
bogdanm 0:9b334a45a8ff 535 }
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 transfer->state = i2cStateRAddrWFAckNack;
bogdanm 0:9b334a45a8ff 538 /* We have to write START cmd first since repeated start, otherwise */
bogdanm 0:9b334a45a8ff 539 /* data would be sent first. */
bogdanm 0:9b334a45a8ff 540 i2c->CMD = I2C_CMD_START;
bogdanm 0:9b334a45a8ff 541 i2c->TXDATA = tmp;
bogdanm 0:9b334a45a8ff 542 goto done;
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /**********************************************************************/
bogdanm 0:9b334a45a8ff 545 /* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
bogdanm 0:9b334a45a8ff 546 /**********************************************************************/
bogdanm 0:9b334a45a8ff 547 case i2cStateRAddrWFAckNack:
bogdanm 0:9b334a45a8ff 548 if (pending & I2C_IF_NACK)
bogdanm 0:9b334a45a8ff 549 {
bogdanm 0:9b334a45a8ff 550 i2c->IFC = I2C_IFC_NACK;
bogdanm 0:9b334a45a8ff 551 transfer->result = i2cTransferNack;
bogdanm 0:9b334a45a8ff 552 transfer->state = i2cStateWFStopSent;
bogdanm 0:9b334a45a8ff 553 i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 554 }
bogdanm 0:9b334a45a8ff 555 else if (pending & I2C_IF_ACK)
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 i2c->IFC = I2C_IFC_ACK;
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Determine whether receiving or sending data */
bogdanm 0:9b334a45a8ff 560 if (seq->flags & I2C_FLAG_WRITE_READ)
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 transfer->state = i2cStateWFData;
bogdanm 0:9b334a45a8ff 563 }
bogdanm 0:9b334a45a8ff 564 else
bogdanm 0:9b334a45a8ff 565 {
bogdanm 0:9b334a45a8ff 566 transfer->state = i2cStateDataSend;
bogdanm 0:9b334a45a8ff 567 continue;
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 goto done;
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /*****************************/
bogdanm 0:9b334a45a8ff 573 /* Send a data byte to slave */
bogdanm 0:9b334a45a8ff 574 /*****************************/
bogdanm 0:9b334a45a8ff 575 case i2cStateDataSend:
bogdanm 0:9b334a45a8ff 576 /* Reached end of data buffer? */
bogdanm 0:9b334a45a8ff 577 if (transfer->offset >= seq->buf[transfer->bufIndx].len)
bogdanm 0:9b334a45a8ff 578 {
bogdanm 0:9b334a45a8ff 579 /* Move to next message part */
bogdanm 0:9b334a45a8ff 580 transfer->offset = 0;
bogdanm 0:9b334a45a8ff 581 transfer->bufIndx++;
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /* Send repeated start when switching to read mode on 2nd buffer */
bogdanm 0:9b334a45a8ff 584 if (seq->flags & I2C_FLAG_WRITE_READ)
bogdanm 0:9b334a45a8ff 585 {
bogdanm 0:9b334a45a8ff 586 transfer->state = i2cStateRStartAddrSend;
bogdanm 0:9b334a45a8ff 587 continue;
bogdanm 0:9b334a45a8ff 588 }
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /* Only writing from one buffer, or finished both buffers */
bogdanm 0:9b334a45a8ff 591 if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1))
bogdanm 0:9b334a45a8ff 592 {
bogdanm 0:9b334a45a8ff 593 transfer->state = i2cStateWFStopSent;
bogdanm 0:9b334a45a8ff 594 i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 595 goto done;
bogdanm 0:9b334a45a8ff 596 }
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /* Reprocess in case next buffer is empty */
bogdanm 0:9b334a45a8ff 599 continue;
bogdanm 0:9b334a45a8ff 600 }
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /* Send byte */
bogdanm 0:9b334a45a8ff 603 i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
bogdanm 0:9b334a45a8ff 604 transfer->state = i2cStateDataWFAckNack;
bogdanm 0:9b334a45a8ff 605 goto done;
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /*********************************************************/
bogdanm 0:9b334a45a8ff 608 /* Wait for ACK/NACK from slave after sending data to it */
bogdanm 0:9b334a45a8ff 609 /*********************************************************/
bogdanm 0:9b334a45a8ff 610 case i2cStateDataWFAckNack:
bogdanm 0:9b334a45a8ff 611 if (pending & I2C_IF_NACK)
bogdanm 0:9b334a45a8ff 612 {
bogdanm 0:9b334a45a8ff 613 i2c->IFC = I2C_IFC_NACK;
bogdanm 0:9b334a45a8ff 614 transfer->result = i2cTransferNack;
bogdanm 0:9b334a45a8ff 615 transfer->state = i2cStateWFStopSent;
bogdanm 0:9b334a45a8ff 616 i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 617 }
bogdanm 0:9b334a45a8ff 618 else if (pending & I2C_IF_ACK)
bogdanm 0:9b334a45a8ff 619 {
bogdanm 0:9b334a45a8ff 620 i2c->IFC = I2C_IFC_ACK;
bogdanm 0:9b334a45a8ff 621 transfer->state = i2cStateDataSend;
bogdanm 0:9b334a45a8ff 622 continue;
bogdanm 0:9b334a45a8ff 623 }
bogdanm 0:9b334a45a8ff 624 goto done;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /****************************/
bogdanm 0:9b334a45a8ff 627 /* Wait for data from slave */
bogdanm 0:9b334a45a8ff 628 /****************************/
bogdanm 0:9b334a45a8ff 629 case i2cStateWFData:
bogdanm 0:9b334a45a8ff 630 if (pending & I2C_IF_RXDATAV)
bogdanm 0:9b334a45a8ff 631 {
bogdanm 0:9b334a45a8ff 632 uint8_t data;
bogdanm 0:9b334a45a8ff 633 unsigned int rxLen = seq->buf[transfer->bufIndx].len;
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /* Must read out data in order to not block further progress */
bogdanm 0:9b334a45a8ff 636 data = (uint8_t)(i2c->RXDATA);
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /* Make sure not storing beyond end of buffer just in case */
bogdanm 0:9b334a45a8ff 639 if (transfer->offset < rxLen)
bogdanm 0:9b334a45a8ff 640 {
bogdanm 0:9b334a45a8ff 641 seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
bogdanm 0:9b334a45a8ff 642 }
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* If we have read all requested data, then the sequence should end */
bogdanm 0:9b334a45a8ff 645 if (transfer->offset >= rxLen)
bogdanm 0:9b334a45a8ff 646 {
bogdanm 0:9b334a45a8ff 647 /* If there is only one byte to receive we need to transmit the
bogdanm 0:9b334a45a8ff 648 NACK now, before the stop. */
bogdanm 0:9b334a45a8ff 649 if (1 == rxLen)
bogdanm 0:9b334a45a8ff 650 {
bogdanm 0:9b334a45a8ff 651 i2c->CMD = I2C_CMD_NACK;
bogdanm 0:9b334a45a8ff 652 }
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 transfer->state = i2cStateWFStopSent;
bogdanm 0:9b334a45a8ff 655 i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 656 }
bogdanm 0:9b334a45a8ff 657 else
bogdanm 0:9b334a45a8ff 658 {
bogdanm 0:9b334a45a8ff 659 /* Send ACK and wait for next byte */
bogdanm 0:9b334a45a8ff 660 i2c->CMD = I2C_CMD_ACK;
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 if ( (1<rxLen) && (transfer->offset == (rxLen-1)) )
bogdanm 0:9b334a45a8ff 663 {
bogdanm 0:9b334a45a8ff 664 /* If there is more than one byte to receive and this is the next
bogdanm 0:9b334a45a8ff 665 to last byte we need to transmit the NACK now, before receiving
bogdanm 0:9b334a45a8ff 666 the last byte. */
bogdanm 0:9b334a45a8ff 667 i2c->CMD = I2C_CMD_NACK;
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670 }
bogdanm 0:9b334a45a8ff 671 goto done;
bogdanm 0:9b334a45a8ff 672
bogdanm 0:9b334a45a8ff 673 /***********************************/
bogdanm 0:9b334a45a8ff 674 /* Wait for STOP to have been sent */
bogdanm 0:9b334a45a8ff 675 /***********************************/
bogdanm 0:9b334a45a8ff 676 case i2cStateWFStopSent:
bogdanm 0:9b334a45a8ff 677 if (pending & I2C_IF_MSTOP)
bogdanm 0:9b334a45a8ff 678 {
bogdanm 0:9b334a45a8ff 679 i2c->IFC = I2C_IFC_MSTOP;
bogdanm 0:9b334a45a8ff 680 transfer->state = i2cStateDone;
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682 goto done;
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /******************************/
bogdanm 0:9b334a45a8ff 685 /* Unexpected state, SW fault */
bogdanm 0:9b334a45a8ff 686 /******************************/
bogdanm 0:9b334a45a8ff 687 default:
bogdanm 0:9b334a45a8ff 688 transfer->result = i2cTransferSwFault;
bogdanm 0:9b334a45a8ff 689 transfer->state = i2cStateDone;
bogdanm 0:9b334a45a8ff 690 goto done;
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692 }
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 done:
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 if (transfer->state == i2cStateDone)
bogdanm 0:9b334a45a8ff 697 {
bogdanm 0:9b334a45a8ff 698 /* Disable interrupt sources when done */
bogdanm 0:9b334a45a8ff 699 i2c->IEN = 0;
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Update result unless some fault already occurred */
bogdanm 0:9b334a45a8ff 702 if (transfer->result == i2cTransferInProgress)
bogdanm 0:9b334a45a8ff 703 {
bogdanm 0:9b334a45a8ff 704 transfer->result = i2cTransferDone;
bogdanm 0:9b334a45a8ff 705 }
bogdanm 0:9b334a45a8ff 706 }
bogdanm 0:9b334a45a8ff 707 /* Until transfer is done keep returning i2cTransferInProgress */
bogdanm 0:9b334a45a8ff 708 else
bogdanm 0:9b334a45a8ff 709 {
bogdanm 0:9b334a45a8ff 710 return(i2cTransferInProgress);
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 return transfer->result;
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 718 * @brief
bogdanm 0:9b334a45a8ff 719 * Prepare and start an I2C transfer (single master mode only).
bogdanm 0:9b334a45a8ff 720 *
bogdanm 0:9b334a45a8ff 721 * @details
bogdanm 0:9b334a45a8ff 722 * This function must be invoked in order to start an I2C transfer
bogdanm 0:9b334a45a8ff 723 * sequence. In order to actually complete the transfer, I2C_Transfer() must
bogdanm 0:9b334a45a8ff 724 * be used either in polled mode or by adding a small driver wrapper utilizing
bogdanm 0:9b334a45a8ff 725 * interrupts.
bogdanm 0:9b334a45a8ff 726 *
bogdanm 0:9b334a45a8ff 727 * @note
bogdanm 0:9b334a45a8ff 728 * Only single master mode is supported.
bogdanm 0:9b334a45a8ff 729 *
bogdanm 0:9b334a45a8ff 730 * @param[in] i2c
bogdanm 0:9b334a45a8ff 731 * Pointer to I2C peripheral register block.
bogdanm 0:9b334a45a8ff 732 *
bogdanm 0:9b334a45a8ff 733 * @param[in] seq
bogdanm 0:9b334a45a8ff 734 * Pointer to sequence structure defining the I2C transfer to take place. The
bogdanm 0:9b334a45a8ff 735 * referenced structure must exist until the transfer has fully completed.
bogdanm 0:9b334a45a8ff 736 *
bogdanm 0:9b334a45a8ff 737 * @return
bogdanm 0:9b334a45a8ff 738 * Returns status for ongoing transfer:
bogdanm 0:9b334a45a8ff 739 * @li #i2cTransferInProgress - indicates that transfer not finished.
bogdanm 0:9b334a45a8ff 740 * @li otherwise some sort of error has occurred.
bogdanm 0:9b334a45a8ff 741 ******************************************************************************/
bogdanm 0:9b334a45a8ff 742 I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
bogdanm 0:9b334a45a8ff 743 I2C_TransferSeq_TypeDef *seq)
bogdanm 0:9b334a45a8ff 744 {
bogdanm 0:9b334a45a8ff 745 I2C_Transfer_TypeDef *transfer;
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 EFM_ASSERT(I2C_REF_VALID(i2c));
bogdanm 0:9b334a45a8ff 748 EFM_ASSERT(seq);
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /* Support up to 2 I2C buses */
bogdanm 0:9b334a45a8ff 751 if (i2c == I2C0)
bogdanm 0:9b334a45a8ff 752 {
bogdanm 0:9b334a45a8ff 753 transfer = i2cTransfer;
bogdanm 0:9b334a45a8ff 754 }
bogdanm 0:9b334a45a8ff 755 #if (I2C_COUNT > 1)
bogdanm 0:9b334a45a8ff 756 else if (i2c == I2C1)
bogdanm 0:9b334a45a8ff 757 {
bogdanm 0:9b334a45a8ff 758 transfer = i2cTransfer + 1;
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760 #endif
bogdanm 0:9b334a45a8ff 761 else
bogdanm 0:9b334a45a8ff 762 {
bogdanm 0:9b334a45a8ff 763 return(i2cTransferUsageFault);
bogdanm 0:9b334a45a8ff 764 }
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 /* Check if in busy state. Since this SW assumes single master, we can */
bogdanm 0:9b334a45a8ff 767 /* just issue an abort. The BUSY state is normal after a reset. */
bogdanm 0:9b334a45a8ff 768 if (i2c->STATE & I2C_STATE_BUSY)
bogdanm 0:9b334a45a8ff 769 {
bogdanm 0:9b334a45a8ff 770 i2c->CMD = I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772
bogdanm 0:9b334a45a8ff 773 /* Make sure user is not trying to read 0 bytes, it is not */
bogdanm 0:9b334a45a8ff 774 /* possible according to I2C spec, since slave will always start */
bogdanm 0:9b334a45a8ff 775 /* sending first byte ACK on address. The read operation can */
bogdanm 0:9b334a45a8ff 776 /* only be stopped by NACKing a received byte, ie minimum 1 byte. */
bogdanm 0:9b334a45a8ff 777 if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) ||
bogdanm 0:9b334a45a8ff 778 ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
bogdanm 0:9b334a45a8ff 779 )
bogdanm 0:9b334a45a8ff 780 {
bogdanm 0:9b334a45a8ff 781 return(i2cTransferUsageFault);
bogdanm 0:9b334a45a8ff 782 }
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* Prepare for a transfer */
bogdanm 0:9b334a45a8ff 785 transfer->state = i2cStateStartAddrSend;
bogdanm 0:9b334a45a8ff 786 transfer->result = i2cTransferInProgress;
bogdanm 0:9b334a45a8ff 787 transfer->offset = 0;
bogdanm 0:9b334a45a8ff 788 transfer->bufIndx = 0;
bogdanm 0:9b334a45a8ff 789 transfer->seq = seq;
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 /* Ensure buffers are empty */
bogdanm 0:9b334a45a8ff 792 i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
bogdanm 0:9b334a45a8ff 793 if (i2c->IF & I2C_IF_RXDATAV)
bogdanm 0:9b334a45a8ff 794 {
bogdanm 0:9b334a45a8ff 795 (void)i2c->RXDATA;
bogdanm 0:9b334a45a8ff 796 }
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /* Clear all pending interrupts prior to starting transfer. */
bogdanm 0:9b334a45a8ff 799 i2c->IFC = _I2C_IFC_MASK;
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /* Enable those interrupts we are interested in throughout transfer. */
bogdanm 0:9b334a45a8ff 802 /* Notice that the I2C interrupt must also be enabled in the NVIC, but */
bogdanm 0:9b334a45a8ff 803 /* that is left for an additional driver wrapper. */
bogdanm 0:9b334a45a8ff 804 i2c->IEN = I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP |
bogdanm 0:9b334a45a8ff 805 I2C_IF_RXDATAV | I2C_IF_ERRORS;
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 /* Start transfer */
bogdanm 0:9b334a45a8ff 808 return(I2C_Transfer(i2c));
bogdanm 0:9b334a45a8ff 809 }
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 /** @} (end addtogroup I2C) */
bogdanm 0:9b334a45a8ff 812 /** @} (end addtogroup EM_Library) */
bogdanm 0:9b334a45a8ff 813 #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */