Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/MKL26Z4.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processors: MKL26Z128VFM4
bogdanm 0:9b334a45a8ff 4 ** MKL26Z64VFM4
bogdanm 0:9b334a45a8ff 5 ** MKL26Z32VM4
bogdanm 0:9b334a45a8ff 6 ** MKL26Z128VFT4
bogdanm 0:9b334a45a8ff 7 ** MKL26Z64VFT4
bogdanm 0:9b334a45a8ff 8 ** MKL26Z32VFT4
bogdanm 0:9b334a45a8ff 9 ** MKL26Z256VLH4
bogdanm 0:9b334a45a8ff 10 ** MKL26Z128VLH4
bogdanm 0:9b334a45a8ff 11 ** MKL26Z64VLH4
bogdanm 0:9b334a45a8ff 12 ** MKL26Z32VLH4
bogdanm 0:9b334a45a8ff 13 ** MKL26Z256VLK4
bogdanm 0:9b334a45a8ff 14 ** MKL26Z256VLL4
bogdanm 0:9b334a45a8ff 15 ** MKL26Z128VLL4
bogdanm 0:9b334a45a8ff 16 ** MKL26Z256VMC4
bogdanm 0:9b334a45a8ff 17 ** MKL26Z128VMC4
bogdanm 0:9b334a45a8ff 18 **
bogdanm 0:9b334a45a8ff 19 ** Compilers: ARM Compiler
bogdanm 0:9b334a45a8ff 20 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 21 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 22 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 23 **
bogdanm 0:9b334a45a8ff 24 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
bogdanm 0:9b334a45a8ff 25 ** Version: rev. 1.0, 2012-12-12
bogdanm 0:9b334a45a8ff 26 **
bogdanm 0:9b334a45a8ff 27 ** Abstract:
bogdanm 0:9b334a45a8ff 28 ** CMSIS Peripheral Access Layer for MKL26Z4
bogdanm 0:9b334a45a8ff 29 **
bogdanm 0:9b334a45a8ff 30 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
bogdanm 0:9b334a45a8ff 31 **
bogdanm 0:9b334a45a8ff 32 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 33 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 34 **
bogdanm 0:9b334a45a8ff 35 ** Revisions:
bogdanm 0:9b334a45a8ff 36 ** - rev. 1.0 (2012-12-12)
bogdanm 0:9b334a45a8ff 37 ** Initial version.
bogdanm 0:9b334a45a8ff 38 **
bogdanm 0:9b334a45a8ff 39 ** ###################################################################
bogdanm 0:9b334a45a8ff 40 */
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 /**
bogdanm 0:9b334a45a8ff 43 * @file MKL26Z4.h
bogdanm 0:9b334a45a8ff 44 * @version 1.0
bogdanm 0:9b334a45a8ff 45 * @date 2012-12-12
bogdanm 0:9b334a45a8ff 46 * @brief CMSIS Peripheral Access Layer for MKL26Z4
bogdanm 0:9b334a45a8ff 47 *
bogdanm 0:9b334a45a8ff 48 * CMSIS Peripheral Access Layer for MKL26Z4
bogdanm 0:9b334a45a8ff 49 */
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 #if !defined(MKL26Z4_H_)
bogdanm 0:9b334a45a8ff 52 #define MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 /** Memory map major version (memory maps with equal major version number are
bogdanm 0:9b334a45a8ff 55 * compatible) */
bogdanm 0:9b334a45a8ff 56 #define MCU_MEM_MAP_VERSION 0x0100u
bogdanm 0:9b334a45a8ff 57 /** Memory map minor version */
bogdanm 0:9b334a45a8ff 58 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 62 -- Interrupt vector numbers
bogdanm 0:9b334a45a8ff 63 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /**
bogdanm 0:9b334a45a8ff 66 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
bogdanm 0:9b334a45a8ff 67 * @{
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /** Interrupt Number Definitions */
bogdanm 0:9b334a45a8ff 71 typedef enum IRQn {
bogdanm 0:9b334a45a8ff 72 /* Core interrupts */
bogdanm 0:9b334a45a8ff 73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /* Device specific interrupts */
bogdanm 0:9b334a45a8ff 80 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 82 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 83 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 84 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
bogdanm 0:9b334a45a8ff 85 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
bogdanm 0:9b334a45a8ff 86 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
bogdanm 0:9b334a45a8ff 87 LLW_IRQn = 7, /**< Low Leakage Wakeup */
bogdanm 0:9b334a45a8ff 88 I2C0_IRQn = 8, /**< I2C0 interrupt */
bogdanm 0:9b334a45a8ff 89 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
bogdanm 0:9b334a45a8ff 90 SPI0_IRQn = 10, /**< SPI0 interrupt */
bogdanm 0:9b334a45a8ff 91 SPI1_IRQn = 11, /**< SPI1 interrupt */
bogdanm 0:9b334a45a8ff 92 UART0_IRQn = 12, /**< UART0 status/error interrupt */
bogdanm 0:9b334a45a8ff 93 UART1_IRQn = 13, /**< UART1 status/error interrupt */
bogdanm 0:9b334a45a8ff 94 UART2_IRQn = 14, /**< UART2 status/error interrupt */
bogdanm 0:9b334a45a8ff 95 ADC0_IRQn = 15, /**< ADC0 interrupt */
bogdanm 0:9b334a45a8ff 96 CMP0_IRQn = 16, /**< CMP0 interrupt */
bogdanm 0:9b334a45a8ff 97 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
bogdanm 0:9b334a45a8ff 98 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
bogdanm 0:9b334a45a8ff 99 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
bogdanm 0:9b334a45a8ff 100 RTC_IRQn = 20, /**< RTC interrupt */
bogdanm 0:9b334a45a8ff 101 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
bogdanm 0:9b334a45a8ff 102 PIT_IRQn = 22, /**< PIT timer interrupt */
bogdanm 0:9b334a45a8ff 103 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
bogdanm 0:9b334a45a8ff 104 USB0_IRQn = 24, /**< USB0 interrupt */
bogdanm 0:9b334a45a8ff 105 DAC0_IRQn = 25, /**< DAC0 interrupt */
bogdanm 0:9b334a45a8ff 106 TSI0_IRQn = 26, /**< TSI0 interrupt */
bogdanm 0:9b334a45a8ff 107 MCG_IRQn = 27, /**< MCG interrupt */
bogdanm 0:9b334a45a8ff 108 LPTimer_IRQn = 28, /**< LPTimer interrupt */
bogdanm 0:9b334a45a8ff 109 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
bogdanm 0:9b334a45a8ff 110 PORTA_IRQn = 30, /**< Port A interrupt */
bogdanm 0:9b334a45a8ff 111 PORTD_IRQn = 31 /**< Port D interrupt */
bogdanm 0:9b334a45a8ff 112 } IRQn_Type;
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /**
bogdanm 0:9b334a45a8ff 115 * @}
bogdanm 0:9b334a45a8ff 116 */ /* end of group Interrupt_vector_numbers */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 120 -- Cortex M0 Core Configuration
bogdanm 0:9b334a45a8ff 121 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /**
bogdanm 0:9b334a45a8ff 124 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
bogdanm 0:9b334a45a8ff 125 * @{
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
bogdanm 0:9b334a45a8ff 129 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
bogdanm 0:9b334a45a8ff 130 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
bogdanm 0:9b334a45a8ff 131 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
bogdanm 0:9b334a45a8ff 132 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
bogdanm 0:9b334a45a8ff 135 #include "system_MKL26Z4.h" /* Device specific configuration file */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @}
bogdanm 0:9b334a45a8ff 139 */ /* end of group Cortex_Core_Configuration */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 143 -- Device Peripheral Access Layer
bogdanm 0:9b334a45a8ff 144 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /**
bogdanm 0:9b334a45a8ff 147 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /*
bogdanm 0:9b334a45a8ff 153 ** Start of section using anonymous unions
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 157 #pragma push
bogdanm 0:9b334a45a8ff 158 #pragma anon_unions
bogdanm 0:9b334a45a8ff 159 #elif defined(__CWCC__)
bogdanm 0:9b334a45a8ff 160 #pragma push
bogdanm 0:9b334a45a8ff 161 #pragma cpp_extensions on
bogdanm 0:9b334a45a8ff 162 #elif defined(__GNUC__)
bogdanm 0:9b334a45a8ff 163 /* anonymous unions are enabled by default */
bogdanm 0:9b334a45a8ff 164 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 165 #pragma language=extended
bogdanm 0:9b334a45a8ff 166 #else
bogdanm 0:9b334a45a8ff 167 #error Not supported compiler type
bogdanm 0:9b334a45a8ff 168 #endif
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 171 -- ADC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 172 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 176 * @{
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /** ADC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 180 typedef struct {
bogdanm 0:9b334a45a8ff 181 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 182 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
bogdanm 0:9b334a45a8ff 183 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
bogdanm 0:9b334a45a8ff 184 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
bogdanm 0:9b334a45a8ff 185 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
bogdanm 0:9b334a45a8ff 186 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
bogdanm 0:9b334a45a8ff 187 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
bogdanm 0:9b334a45a8ff 188 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
bogdanm 0:9b334a45a8ff 189 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
bogdanm 0:9b334a45a8ff 190 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
bogdanm 0:9b334a45a8ff 191 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
bogdanm 0:9b334a45a8ff 192 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
bogdanm 0:9b334a45a8ff 193 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
bogdanm 0:9b334a45a8ff 194 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
bogdanm 0:9b334a45a8ff 195 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
bogdanm 0:9b334a45a8ff 196 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
bogdanm 0:9b334a45a8ff 197 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
bogdanm 0:9b334a45a8ff 198 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
bogdanm 0:9b334a45a8ff 199 uint8_t RESERVED_0[4];
bogdanm 0:9b334a45a8ff 200 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
bogdanm 0:9b334a45a8ff 201 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
bogdanm 0:9b334a45a8ff 203 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
bogdanm 0:9b334a45a8ff 204 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
bogdanm 0:9b334a45a8ff 205 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
bogdanm 0:9b334a45a8ff 206 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
bogdanm 0:9b334a45a8ff 207 } ADC_Type;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 210 -- ADC Register Masks
bogdanm 0:9b334a45a8ff 211 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /**
bogdanm 0:9b334a45a8ff 214 * @addtogroup ADC_Register_Masks ADC Register Masks
bogdanm 0:9b334a45a8ff 215 * @{
bogdanm 0:9b334a45a8ff 216 */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /* SC1 Bit Fields */
bogdanm 0:9b334a45a8ff 219 #define ADC_SC1_ADCH_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 220 #define ADC_SC1_ADCH_SHIFT 0
bogdanm 0:9b334a45a8ff 221 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
bogdanm 0:9b334a45a8ff 222 #define ADC_SC1_DIFF_MASK 0x20u
bogdanm 0:9b334a45a8ff 223 #define ADC_SC1_DIFF_SHIFT 5
bogdanm 0:9b334a45a8ff 224 #define ADC_SC1_AIEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 225 #define ADC_SC1_AIEN_SHIFT 6
bogdanm 0:9b334a45a8ff 226 #define ADC_SC1_COCO_MASK 0x80u
bogdanm 0:9b334a45a8ff 227 #define ADC_SC1_COCO_SHIFT 7
bogdanm 0:9b334a45a8ff 228 /* CFG1 Bit Fields */
bogdanm 0:9b334a45a8ff 229 #define ADC_CFG1_ADICLK_MASK 0x3u
bogdanm 0:9b334a45a8ff 230 #define ADC_CFG1_ADICLK_SHIFT 0
bogdanm 0:9b334a45a8ff 231 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
bogdanm 0:9b334a45a8ff 232 #define ADC_CFG1_MODE_MASK 0xCu
bogdanm 0:9b334a45a8ff 233 #define ADC_CFG1_MODE_SHIFT 2
bogdanm 0:9b334a45a8ff 234 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
bogdanm 0:9b334a45a8ff 235 #define ADC_CFG1_ADLSMP_MASK 0x10u
bogdanm 0:9b334a45a8ff 236 #define ADC_CFG1_ADLSMP_SHIFT 4
bogdanm 0:9b334a45a8ff 237 #define ADC_CFG1_ADIV_MASK 0x60u
bogdanm 0:9b334a45a8ff 238 #define ADC_CFG1_ADIV_SHIFT 5
bogdanm 0:9b334a45a8ff 239 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
bogdanm 0:9b334a45a8ff 240 #define ADC_CFG1_ADLPC_MASK 0x80u
bogdanm 0:9b334a45a8ff 241 #define ADC_CFG1_ADLPC_SHIFT 7
bogdanm 0:9b334a45a8ff 242 /* CFG2 Bit Fields */
bogdanm 0:9b334a45a8ff 243 #define ADC_CFG2_ADLSTS_MASK 0x3u
bogdanm 0:9b334a45a8ff 244 #define ADC_CFG2_ADLSTS_SHIFT 0
bogdanm 0:9b334a45a8ff 245 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
bogdanm 0:9b334a45a8ff 246 #define ADC_CFG2_ADHSC_MASK 0x4u
bogdanm 0:9b334a45a8ff 247 #define ADC_CFG2_ADHSC_SHIFT 2
bogdanm 0:9b334a45a8ff 248 #define ADC_CFG2_ADACKEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 249 #define ADC_CFG2_ADACKEN_SHIFT 3
bogdanm 0:9b334a45a8ff 250 #define ADC_CFG2_MUXSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 251 #define ADC_CFG2_MUXSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 252 /* R Bit Fields */
bogdanm 0:9b334a45a8ff 253 #define ADC_R_D_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 254 #define ADC_R_D_SHIFT 0
bogdanm 0:9b334a45a8ff 255 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
bogdanm 0:9b334a45a8ff 256 /* CV1 Bit Fields */
bogdanm 0:9b334a45a8ff 257 #define ADC_CV1_CV_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 258 #define ADC_CV1_CV_SHIFT 0
bogdanm 0:9b334a45a8ff 259 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
bogdanm 0:9b334a45a8ff 260 /* CV2 Bit Fields */
bogdanm 0:9b334a45a8ff 261 #define ADC_CV2_CV_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 262 #define ADC_CV2_CV_SHIFT 0
bogdanm 0:9b334a45a8ff 263 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
bogdanm 0:9b334a45a8ff 264 /* SC2 Bit Fields */
bogdanm 0:9b334a45a8ff 265 #define ADC_SC2_REFSEL_MASK 0x3u
bogdanm 0:9b334a45a8ff 266 #define ADC_SC2_REFSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 267 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
bogdanm 0:9b334a45a8ff 268 #define ADC_SC2_DMAEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 269 #define ADC_SC2_DMAEN_SHIFT 2
bogdanm 0:9b334a45a8ff 270 #define ADC_SC2_ACREN_MASK 0x8u
bogdanm 0:9b334a45a8ff 271 #define ADC_SC2_ACREN_SHIFT 3
bogdanm 0:9b334a45a8ff 272 #define ADC_SC2_ACFGT_MASK 0x10u
bogdanm 0:9b334a45a8ff 273 #define ADC_SC2_ACFGT_SHIFT 4
bogdanm 0:9b334a45a8ff 274 #define ADC_SC2_ACFE_MASK 0x20u
bogdanm 0:9b334a45a8ff 275 #define ADC_SC2_ACFE_SHIFT 5
bogdanm 0:9b334a45a8ff 276 #define ADC_SC2_ADTRG_MASK 0x40u
bogdanm 0:9b334a45a8ff 277 #define ADC_SC2_ADTRG_SHIFT 6
bogdanm 0:9b334a45a8ff 278 #define ADC_SC2_ADACT_MASK 0x80u
bogdanm 0:9b334a45a8ff 279 #define ADC_SC2_ADACT_SHIFT 7
bogdanm 0:9b334a45a8ff 280 /* SC3 Bit Fields */
bogdanm 0:9b334a45a8ff 281 #define ADC_SC3_AVGS_MASK 0x3u
bogdanm 0:9b334a45a8ff 282 #define ADC_SC3_AVGS_SHIFT 0
bogdanm 0:9b334a45a8ff 283 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
bogdanm 0:9b334a45a8ff 284 #define ADC_SC3_AVGE_MASK 0x4u
bogdanm 0:9b334a45a8ff 285 #define ADC_SC3_AVGE_SHIFT 2
bogdanm 0:9b334a45a8ff 286 #define ADC_SC3_ADCO_MASK 0x8u
bogdanm 0:9b334a45a8ff 287 #define ADC_SC3_ADCO_SHIFT 3
bogdanm 0:9b334a45a8ff 288 #define ADC_SC3_CALF_MASK 0x40u
bogdanm 0:9b334a45a8ff 289 #define ADC_SC3_CALF_SHIFT 6
bogdanm 0:9b334a45a8ff 290 #define ADC_SC3_CAL_MASK 0x80u
bogdanm 0:9b334a45a8ff 291 #define ADC_SC3_CAL_SHIFT 7
bogdanm 0:9b334a45a8ff 292 /* OFS Bit Fields */
bogdanm 0:9b334a45a8ff 293 #define ADC_OFS_OFS_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 294 #define ADC_OFS_OFS_SHIFT 0
bogdanm 0:9b334a45a8ff 295 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
bogdanm 0:9b334a45a8ff 296 /* PG Bit Fields */
bogdanm 0:9b334a45a8ff 297 #define ADC_PG_PG_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 298 #define ADC_PG_PG_SHIFT 0
bogdanm 0:9b334a45a8ff 299 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
bogdanm 0:9b334a45a8ff 300 /* MG Bit Fields */
bogdanm 0:9b334a45a8ff 301 #define ADC_MG_MG_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 302 #define ADC_MG_MG_SHIFT 0
bogdanm 0:9b334a45a8ff 303 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
bogdanm 0:9b334a45a8ff 304 /* CLPD Bit Fields */
bogdanm 0:9b334a45a8ff 305 #define ADC_CLPD_CLPD_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 306 #define ADC_CLPD_CLPD_SHIFT 0
bogdanm 0:9b334a45a8ff 307 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
bogdanm 0:9b334a45a8ff 308 /* CLPS Bit Fields */
bogdanm 0:9b334a45a8ff 309 #define ADC_CLPS_CLPS_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 310 #define ADC_CLPS_CLPS_SHIFT 0
bogdanm 0:9b334a45a8ff 311 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
bogdanm 0:9b334a45a8ff 312 /* CLP4 Bit Fields */
bogdanm 0:9b334a45a8ff 313 #define ADC_CLP4_CLP4_MASK 0x3FFu
bogdanm 0:9b334a45a8ff 314 #define ADC_CLP4_CLP4_SHIFT 0
bogdanm 0:9b334a45a8ff 315 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
bogdanm 0:9b334a45a8ff 316 /* CLP3 Bit Fields */
bogdanm 0:9b334a45a8ff 317 #define ADC_CLP3_CLP3_MASK 0x1FFu
bogdanm 0:9b334a45a8ff 318 #define ADC_CLP3_CLP3_SHIFT 0
bogdanm 0:9b334a45a8ff 319 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
bogdanm 0:9b334a45a8ff 320 /* CLP2 Bit Fields */
bogdanm 0:9b334a45a8ff 321 #define ADC_CLP2_CLP2_MASK 0xFFu
bogdanm 0:9b334a45a8ff 322 #define ADC_CLP2_CLP2_SHIFT 0
bogdanm 0:9b334a45a8ff 323 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
bogdanm 0:9b334a45a8ff 324 /* CLP1 Bit Fields */
bogdanm 0:9b334a45a8ff 325 #define ADC_CLP1_CLP1_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 326 #define ADC_CLP1_CLP1_SHIFT 0
bogdanm 0:9b334a45a8ff 327 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
bogdanm 0:9b334a45a8ff 328 /* CLP0 Bit Fields */
bogdanm 0:9b334a45a8ff 329 #define ADC_CLP0_CLP0_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 330 #define ADC_CLP0_CLP0_SHIFT 0
bogdanm 0:9b334a45a8ff 331 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
bogdanm 0:9b334a45a8ff 332 /* CLMD Bit Fields */
bogdanm 0:9b334a45a8ff 333 #define ADC_CLMD_CLMD_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 334 #define ADC_CLMD_CLMD_SHIFT 0
bogdanm 0:9b334a45a8ff 335 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
bogdanm 0:9b334a45a8ff 336 /* CLMS Bit Fields */
bogdanm 0:9b334a45a8ff 337 #define ADC_CLMS_CLMS_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 338 #define ADC_CLMS_CLMS_SHIFT 0
bogdanm 0:9b334a45a8ff 339 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
bogdanm 0:9b334a45a8ff 340 /* CLM4 Bit Fields */
bogdanm 0:9b334a45a8ff 341 #define ADC_CLM4_CLM4_MASK 0x3FFu
bogdanm 0:9b334a45a8ff 342 #define ADC_CLM4_CLM4_SHIFT 0
bogdanm 0:9b334a45a8ff 343 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
bogdanm 0:9b334a45a8ff 344 /* CLM3 Bit Fields */
bogdanm 0:9b334a45a8ff 345 #define ADC_CLM3_CLM3_MASK 0x1FFu
bogdanm 0:9b334a45a8ff 346 #define ADC_CLM3_CLM3_SHIFT 0
bogdanm 0:9b334a45a8ff 347 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
bogdanm 0:9b334a45a8ff 348 /* CLM2 Bit Fields */
bogdanm 0:9b334a45a8ff 349 #define ADC_CLM2_CLM2_MASK 0xFFu
bogdanm 0:9b334a45a8ff 350 #define ADC_CLM2_CLM2_SHIFT 0
bogdanm 0:9b334a45a8ff 351 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
bogdanm 0:9b334a45a8ff 352 /* CLM1 Bit Fields */
bogdanm 0:9b334a45a8ff 353 #define ADC_CLM1_CLM1_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 354 #define ADC_CLM1_CLM1_SHIFT 0
bogdanm 0:9b334a45a8ff 355 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
bogdanm 0:9b334a45a8ff 356 /* CLM0 Bit Fields */
bogdanm 0:9b334a45a8ff 357 #define ADC_CLM0_CLM0_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 358 #define ADC_CLM0_CLM0_SHIFT 0
bogdanm 0:9b334a45a8ff 359 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /**
bogdanm 0:9b334a45a8ff 362 * @}
bogdanm 0:9b334a45a8ff 363 */ /* end of group ADC_Register_Masks */
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* ADC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 367 /** Peripheral ADC0 base address */
bogdanm 0:9b334a45a8ff 368 #define ADC0_BASE (0x4003B000u)
bogdanm 0:9b334a45a8ff 369 /** Peripheral ADC0 base pointer */
bogdanm 0:9b334a45a8ff 370 #define ADC0 ((ADC_Type *)ADC0_BASE)
bogdanm 0:9b334a45a8ff 371 /** Array initializer of ADC peripheral base pointers */
bogdanm 0:9b334a45a8ff 372 #define ADC_BASES { ADC0 }
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /**
bogdanm 0:9b334a45a8ff 375 * @}
bogdanm 0:9b334a45a8ff 376 */ /* end of group ADC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 380 -- CMP Peripheral Access Layer
bogdanm 0:9b334a45a8ff 381 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /**
bogdanm 0:9b334a45a8ff 384 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
bogdanm 0:9b334a45a8ff 385 * @{
bogdanm 0:9b334a45a8ff 386 */
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /** CMP - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 389 typedef struct {
bogdanm 0:9b334a45a8ff 390 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
bogdanm 0:9b334a45a8ff 391 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
bogdanm 0:9b334a45a8ff 392 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 393 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 394 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 395 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 396 } CMP_Type;
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 399 -- CMP Register Masks
bogdanm 0:9b334a45a8ff 400 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /**
bogdanm 0:9b334a45a8ff 403 * @addtogroup CMP_Register_Masks CMP Register Masks
bogdanm 0:9b334a45a8ff 404 * @{
bogdanm 0:9b334a45a8ff 405 */
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* CR0 Bit Fields */
bogdanm 0:9b334a45a8ff 408 #define CMP_CR0_HYSTCTR_MASK 0x3u
bogdanm 0:9b334a45a8ff 409 #define CMP_CR0_HYSTCTR_SHIFT 0
bogdanm 0:9b334a45a8ff 410 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
bogdanm 0:9b334a45a8ff 411 #define CMP_CR0_FILTER_CNT_MASK 0x70u
bogdanm 0:9b334a45a8ff 412 #define CMP_CR0_FILTER_CNT_SHIFT 4
bogdanm 0:9b334a45a8ff 413 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
bogdanm 0:9b334a45a8ff 414 /* CR1 Bit Fields */
bogdanm 0:9b334a45a8ff 415 #define CMP_CR1_EN_MASK 0x1u
bogdanm 0:9b334a45a8ff 416 #define CMP_CR1_EN_SHIFT 0
bogdanm 0:9b334a45a8ff 417 #define CMP_CR1_OPE_MASK 0x2u
bogdanm 0:9b334a45a8ff 418 #define CMP_CR1_OPE_SHIFT 1
bogdanm 0:9b334a45a8ff 419 #define CMP_CR1_COS_MASK 0x4u
bogdanm 0:9b334a45a8ff 420 #define CMP_CR1_COS_SHIFT 2
bogdanm 0:9b334a45a8ff 421 #define CMP_CR1_INV_MASK 0x8u
bogdanm 0:9b334a45a8ff 422 #define CMP_CR1_INV_SHIFT 3
bogdanm 0:9b334a45a8ff 423 #define CMP_CR1_PMODE_MASK 0x10u
bogdanm 0:9b334a45a8ff 424 #define CMP_CR1_PMODE_SHIFT 4
bogdanm 0:9b334a45a8ff 425 #define CMP_CR1_TRIGM_MASK 0x20u
bogdanm 0:9b334a45a8ff 426 #define CMP_CR1_TRIGM_SHIFT 5
bogdanm 0:9b334a45a8ff 427 #define CMP_CR1_WE_MASK 0x40u
bogdanm 0:9b334a45a8ff 428 #define CMP_CR1_WE_SHIFT 6
bogdanm 0:9b334a45a8ff 429 #define CMP_CR1_SE_MASK 0x80u
bogdanm 0:9b334a45a8ff 430 #define CMP_CR1_SE_SHIFT 7
bogdanm 0:9b334a45a8ff 431 /* FPR Bit Fields */
bogdanm 0:9b334a45a8ff 432 #define CMP_FPR_FILT_PER_MASK 0xFFu
bogdanm 0:9b334a45a8ff 433 #define CMP_FPR_FILT_PER_SHIFT 0
bogdanm 0:9b334a45a8ff 434 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
bogdanm 0:9b334a45a8ff 435 /* SCR Bit Fields */
bogdanm 0:9b334a45a8ff 436 #define CMP_SCR_COUT_MASK 0x1u
bogdanm 0:9b334a45a8ff 437 #define CMP_SCR_COUT_SHIFT 0
bogdanm 0:9b334a45a8ff 438 #define CMP_SCR_CFF_MASK 0x2u
bogdanm 0:9b334a45a8ff 439 #define CMP_SCR_CFF_SHIFT 1
bogdanm 0:9b334a45a8ff 440 #define CMP_SCR_CFR_MASK 0x4u
bogdanm 0:9b334a45a8ff 441 #define CMP_SCR_CFR_SHIFT 2
bogdanm 0:9b334a45a8ff 442 #define CMP_SCR_IEF_MASK 0x8u
bogdanm 0:9b334a45a8ff 443 #define CMP_SCR_IEF_SHIFT 3
bogdanm 0:9b334a45a8ff 444 #define CMP_SCR_IER_MASK 0x10u
bogdanm 0:9b334a45a8ff 445 #define CMP_SCR_IER_SHIFT 4
bogdanm 0:9b334a45a8ff 446 #define CMP_SCR_DMAEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 447 #define CMP_SCR_DMAEN_SHIFT 6
bogdanm 0:9b334a45a8ff 448 /* DACCR Bit Fields */
bogdanm 0:9b334a45a8ff 449 #define CMP_DACCR_VOSEL_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 450 #define CMP_DACCR_VOSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 451 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
bogdanm 0:9b334a45a8ff 452 #define CMP_DACCR_VRSEL_MASK 0x40u
bogdanm 0:9b334a45a8ff 453 #define CMP_DACCR_VRSEL_SHIFT 6
bogdanm 0:9b334a45a8ff 454 #define CMP_DACCR_DACEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 455 #define CMP_DACCR_DACEN_SHIFT 7
bogdanm 0:9b334a45a8ff 456 /* MUXCR Bit Fields */
bogdanm 0:9b334a45a8ff 457 #define CMP_MUXCR_MSEL_MASK 0x7u
bogdanm 0:9b334a45a8ff 458 #define CMP_MUXCR_MSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 459 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
bogdanm 0:9b334a45a8ff 460 #define CMP_MUXCR_PSEL_MASK 0x38u
bogdanm 0:9b334a45a8ff 461 #define CMP_MUXCR_PSEL_SHIFT 3
bogdanm 0:9b334a45a8ff 462 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
bogdanm 0:9b334a45a8ff 463 #define CMP_MUXCR_PSTM_MASK 0x80u
bogdanm 0:9b334a45a8ff 464 #define CMP_MUXCR_PSTM_SHIFT 7
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @}
bogdanm 0:9b334a45a8ff 468 */ /* end of group CMP_Register_Masks */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /* CMP - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 472 /** Peripheral CMP0 base address */
bogdanm 0:9b334a45a8ff 473 #define CMP0_BASE (0x40073000u)
bogdanm 0:9b334a45a8ff 474 /** Peripheral CMP0 base pointer */
bogdanm 0:9b334a45a8ff 475 #define CMP0 ((CMP_Type *)CMP0_BASE)
bogdanm 0:9b334a45a8ff 476 /** Array initializer of CMP peripheral base pointers */
bogdanm 0:9b334a45a8ff 477 #define CMP_BASES { CMP0 }
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /**
bogdanm 0:9b334a45a8ff 480 * @}
bogdanm 0:9b334a45a8ff 481 */ /* end of group CMP_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 485 -- DAC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 486 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /**
bogdanm 0:9b334a45a8ff 489 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 490 * @{
bogdanm 0:9b334a45a8ff 491 */
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /** DAC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 494 typedef struct {
bogdanm 0:9b334a45a8ff 495 struct { /* offset: 0x0, array step: 0x2 */
bogdanm 0:9b334a45a8ff 496 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
bogdanm 0:9b334a45a8ff 497 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
bogdanm 0:9b334a45a8ff 498 } DAT[2];
bogdanm 0:9b334a45a8ff 499 uint8_t RESERVED_0[28];
bogdanm 0:9b334a45a8ff 500 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
bogdanm 0:9b334a45a8ff 501 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
bogdanm 0:9b334a45a8ff 502 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
bogdanm 0:9b334a45a8ff 503 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
bogdanm 0:9b334a45a8ff 504 } DAC_Type;
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 507 -- DAC Register Masks
bogdanm 0:9b334a45a8ff 508 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /**
bogdanm 0:9b334a45a8ff 511 * @addtogroup DAC_Register_Masks DAC Register Masks
bogdanm 0:9b334a45a8ff 512 * @{
bogdanm 0:9b334a45a8ff 513 */
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /* DATL Bit Fields */
bogdanm 0:9b334a45a8ff 516 #define DAC_DATL_DATA0_MASK 0xFFu
bogdanm 0:9b334a45a8ff 517 #define DAC_DATL_DATA0_SHIFT 0
bogdanm 0:9b334a45a8ff 518 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
bogdanm 0:9b334a45a8ff 519 /* DATH Bit Fields */
bogdanm 0:9b334a45a8ff 520 #define DAC_DATH_DATA1_MASK 0xFu
bogdanm 0:9b334a45a8ff 521 #define DAC_DATH_DATA1_SHIFT 0
bogdanm 0:9b334a45a8ff 522 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
bogdanm 0:9b334a45a8ff 523 /* SR Bit Fields */
bogdanm 0:9b334a45a8ff 524 #define DAC_SR_DACBFRPBF_MASK 0x1u
bogdanm 0:9b334a45a8ff 525 #define DAC_SR_DACBFRPBF_SHIFT 0
bogdanm 0:9b334a45a8ff 526 #define DAC_SR_DACBFRPTF_MASK 0x2u
bogdanm 0:9b334a45a8ff 527 #define DAC_SR_DACBFRPTF_SHIFT 1
bogdanm 0:9b334a45a8ff 528 /* C0 Bit Fields */
bogdanm 0:9b334a45a8ff 529 #define DAC_C0_DACBBIEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 530 #define DAC_C0_DACBBIEN_SHIFT 0
bogdanm 0:9b334a45a8ff 531 #define DAC_C0_DACBTIEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 532 #define DAC_C0_DACBTIEN_SHIFT 1
bogdanm 0:9b334a45a8ff 533 #define DAC_C0_LPEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 534 #define DAC_C0_LPEN_SHIFT 3
bogdanm 0:9b334a45a8ff 535 #define DAC_C0_DACSWTRG_MASK 0x10u
bogdanm 0:9b334a45a8ff 536 #define DAC_C0_DACSWTRG_SHIFT 4
bogdanm 0:9b334a45a8ff 537 #define DAC_C0_DACTRGSEL_MASK 0x20u
bogdanm 0:9b334a45a8ff 538 #define DAC_C0_DACTRGSEL_SHIFT 5
bogdanm 0:9b334a45a8ff 539 #define DAC_C0_DACRFS_MASK 0x40u
bogdanm 0:9b334a45a8ff 540 #define DAC_C0_DACRFS_SHIFT 6
bogdanm 0:9b334a45a8ff 541 #define DAC_C0_DACEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 542 #define DAC_C0_DACEN_SHIFT 7
bogdanm 0:9b334a45a8ff 543 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 544 #define DAC_C1_DACBFEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 545 #define DAC_C1_DACBFEN_SHIFT 0
bogdanm 0:9b334a45a8ff 546 #define DAC_C1_DACBFMD_MASK 0x4u
bogdanm 0:9b334a45a8ff 547 #define DAC_C1_DACBFMD_SHIFT 2
bogdanm 0:9b334a45a8ff 548 #define DAC_C1_DMAEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 549 #define DAC_C1_DMAEN_SHIFT 7
bogdanm 0:9b334a45a8ff 550 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 551 #define DAC_C2_DACBFUP_MASK 0x1u
bogdanm 0:9b334a45a8ff 552 #define DAC_C2_DACBFUP_SHIFT 0
bogdanm 0:9b334a45a8ff 553 #define DAC_C2_DACBFRP_MASK 0x10u
bogdanm 0:9b334a45a8ff 554 #define DAC_C2_DACBFRP_SHIFT 4
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /**
bogdanm 0:9b334a45a8ff 557 * @}
bogdanm 0:9b334a45a8ff 558 */ /* end of group DAC_Register_Masks */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /* DAC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 562 /** Peripheral DAC0 base address */
bogdanm 0:9b334a45a8ff 563 #define DAC0_BASE (0x4003F000u)
bogdanm 0:9b334a45a8ff 564 /** Peripheral DAC0 base pointer */
bogdanm 0:9b334a45a8ff 565 #define DAC0 ((DAC_Type *)DAC0_BASE)
bogdanm 0:9b334a45a8ff 566 /** Array initializer of DAC peripheral base pointers */
bogdanm 0:9b334a45a8ff 567 #define DAC_BASES { DAC0 }
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 /**
bogdanm 0:9b334a45a8ff 570 * @}
bogdanm 0:9b334a45a8ff 571 */ /* end of group DAC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 575 -- DMA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 576 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 /**
bogdanm 0:9b334a45a8ff 579 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 580 * @{
bogdanm 0:9b334a45a8ff 581 */
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /** DMA - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 584 typedef struct {
bogdanm 0:9b334a45a8ff 585 uint8_t RESERVED_0[256];
bogdanm 0:9b334a45a8ff 586 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 587 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 588 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
bogdanm 0:9b334a45a8ff 589 union { /* offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 590 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 591 struct { /* offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 592 uint8_t RESERVED_0[3];
bogdanm 0:9b334a45a8ff 593 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
bogdanm 0:9b334a45a8ff 594 } DMA_DSR_ACCESS8BIT;
bogdanm 0:9b334a45a8ff 595 };
bogdanm 0:9b334a45a8ff 596 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
bogdanm 0:9b334a45a8ff 597 } DMA[4];
bogdanm 0:9b334a45a8ff 598 } DMA_Type;
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 601 -- DMA Register Masks
bogdanm 0:9b334a45a8ff 602 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 /**
bogdanm 0:9b334a45a8ff 605 * @addtogroup DMA_Register_Masks DMA Register Masks
bogdanm 0:9b334a45a8ff 606 * @{
bogdanm 0:9b334a45a8ff 607 */
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 /* SAR Bit Fields */
bogdanm 0:9b334a45a8ff 610 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 611 #define DMA_SAR_SAR_SHIFT 0
bogdanm 0:9b334a45a8ff 612 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
bogdanm 0:9b334a45a8ff 613 /* DAR Bit Fields */
bogdanm 0:9b334a45a8ff 614 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 615 #define DMA_DAR_DAR_SHIFT 0
bogdanm 0:9b334a45a8ff 616 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
bogdanm 0:9b334a45a8ff 617 /* DSR_BCR Bit Fields */
bogdanm 0:9b334a45a8ff 618 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
bogdanm 0:9b334a45a8ff 619 #define DMA_DSR_BCR_BCR_SHIFT 0
bogdanm 0:9b334a45a8ff 620 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
bogdanm 0:9b334a45a8ff 621 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 622 #define DMA_DSR_BCR_DONE_SHIFT 24
bogdanm 0:9b334a45a8ff 623 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 624 #define DMA_DSR_BCR_BSY_SHIFT 25
bogdanm 0:9b334a45a8ff 625 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 626 #define DMA_DSR_BCR_REQ_SHIFT 26
bogdanm 0:9b334a45a8ff 627 #define DMA_DSR_BCR_BED_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 628 #define DMA_DSR_BCR_BED_SHIFT 28
bogdanm 0:9b334a45a8ff 629 #define DMA_DSR_BCR_BES_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 630 #define DMA_DSR_BCR_BES_SHIFT 29
bogdanm 0:9b334a45a8ff 631 #define DMA_DSR_BCR_CE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 632 #define DMA_DSR_BCR_CE_SHIFT 30
bogdanm 0:9b334a45a8ff 633 /* DCR Bit Fields */
bogdanm 0:9b334a45a8ff 634 #define DMA_DCR_LCH2_MASK 0x3u
bogdanm 0:9b334a45a8ff 635 #define DMA_DCR_LCH2_SHIFT 0
bogdanm 0:9b334a45a8ff 636 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
bogdanm 0:9b334a45a8ff 637 #define DMA_DCR_LCH1_MASK 0xCu
bogdanm 0:9b334a45a8ff 638 #define DMA_DCR_LCH1_SHIFT 2
bogdanm 0:9b334a45a8ff 639 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
bogdanm 0:9b334a45a8ff 640 #define DMA_DCR_LINKCC_MASK 0x30u
bogdanm 0:9b334a45a8ff 641 #define DMA_DCR_LINKCC_SHIFT 4
bogdanm 0:9b334a45a8ff 642 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
bogdanm 0:9b334a45a8ff 643 #define DMA_DCR_D_REQ_MASK 0x80u
bogdanm 0:9b334a45a8ff 644 #define DMA_DCR_D_REQ_SHIFT 7
bogdanm 0:9b334a45a8ff 645 #define DMA_DCR_DMOD_MASK 0xF00u
bogdanm 0:9b334a45a8ff 646 #define DMA_DCR_DMOD_SHIFT 8
bogdanm 0:9b334a45a8ff 647 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
bogdanm 0:9b334a45a8ff 648 #define DMA_DCR_SMOD_MASK 0xF000u
bogdanm 0:9b334a45a8ff 649 #define DMA_DCR_SMOD_SHIFT 12
bogdanm 0:9b334a45a8ff 650 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
bogdanm 0:9b334a45a8ff 651 #define DMA_DCR_START_MASK 0x10000u
bogdanm 0:9b334a45a8ff 652 #define DMA_DCR_START_SHIFT 16
bogdanm 0:9b334a45a8ff 653 #define DMA_DCR_DSIZE_MASK 0x60000u
bogdanm 0:9b334a45a8ff 654 #define DMA_DCR_DSIZE_SHIFT 17
bogdanm 0:9b334a45a8ff 655 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
bogdanm 0:9b334a45a8ff 656 #define DMA_DCR_DINC_MASK 0x80000u
bogdanm 0:9b334a45a8ff 657 #define DMA_DCR_DINC_SHIFT 19
bogdanm 0:9b334a45a8ff 658 #define DMA_DCR_SSIZE_MASK 0x300000u
bogdanm 0:9b334a45a8ff 659 #define DMA_DCR_SSIZE_SHIFT 20
bogdanm 0:9b334a45a8ff 660 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
bogdanm 0:9b334a45a8ff 661 #define DMA_DCR_SINC_MASK 0x400000u
bogdanm 0:9b334a45a8ff 662 #define DMA_DCR_SINC_SHIFT 22
bogdanm 0:9b334a45a8ff 663 #define DMA_DCR_EADREQ_MASK 0x800000u
bogdanm 0:9b334a45a8ff 664 #define DMA_DCR_EADREQ_SHIFT 23
bogdanm 0:9b334a45a8ff 665 #define DMA_DCR_AA_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 666 #define DMA_DCR_AA_SHIFT 28
bogdanm 0:9b334a45a8ff 667 #define DMA_DCR_CS_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 668 #define DMA_DCR_CS_SHIFT 29
bogdanm 0:9b334a45a8ff 669 #define DMA_DCR_ERQ_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 670 #define DMA_DCR_ERQ_SHIFT 30
bogdanm 0:9b334a45a8ff 671 #define DMA_DCR_EINT_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 672 #define DMA_DCR_EINT_SHIFT 31
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /**
bogdanm 0:9b334a45a8ff 675 * @}
bogdanm 0:9b334a45a8ff 676 */ /* end of group DMA_Register_Masks */
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 /* DMA - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 680 /** Peripheral DMA base address */
bogdanm 0:9b334a45a8ff 681 #define DMA_BASE (0x40008000u)
bogdanm 0:9b334a45a8ff 682 /** Peripheral DMA base pointer */
bogdanm 0:9b334a45a8ff 683 #define DMA0 ((DMA_Type *)DMA_BASE)
bogdanm 0:9b334a45a8ff 684 /** Array initializer of DMA peripheral base pointers */
bogdanm 0:9b334a45a8ff 685 #define DMA_BASES { DMA0 }
bogdanm 0:9b334a45a8ff 686
bogdanm 0:9b334a45a8ff 687 /**
bogdanm 0:9b334a45a8ff 688 * @}
bogdanm 0:9b334a45a8ff 689 */ /* end of group DMA_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691
bogdanm 0:9b334a45a8ff 692 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 693 -- DMAMUX Peripheral Access Layer
bogdanm 0:9b334a45a8ff 694 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /**
bogdanm 0:9b334a45a8ff 697 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
bogdanm 0:9b334a45a8ff 698 * @{
bogdanm 0:9b334a45a8ff 699 */
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /** DMAMUX - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 702 typedef struct {
bogdanm 0:9b334a45a8ff 703 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
bogdanm 0:9b334a45a8ff 704 } DMAMUX_Type;
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 707 -- DMAMUX Register Masks
bogdanm 0:9b334a45a8ff 708 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 /**
bogdanm 0:9b334a45a8ff 711 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
bogdanm 0:9b334a45a8ff 712 * @{
bogdanm 0:9b334a45a8ff 713 */
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* CHCFG Bit Fields */
bogdanm 0:9b334a45a8ff 716 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 717 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
bogdanm 0:9b334a45a8ff 718 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
bogdanm 0:9b334a45a8ff 719 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
bogdanm 0:9b334a45a8ff 720 #define DMAMUX_CHCFG_TRIG_SHIFT 6
bogdanm 0:9b334a45a8ff 721 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
bogdanm 0:9b334a45a8ff 722 #define DMAMUX_CHCFG_ENBL_SHIFT 7
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 /**
bogdanm 0:9b334a45a8ff 725 * @}
bogdanm 0:9b334a45a8ff 726 */ /* end of group DMAMUX_Register_Masks */
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 /* DMAMUX - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 730 /** Peripheral DMAMUX0 base address */
bogdanm 0:9b334a45a8ff 731 #define DMAMUX0_BASE (0x40021000u)
bogdanm 0:9b334a45a8ff 732 /** Peripheral DMAMUX0 base pointer */
bogdanm 0:9b334a45a8ff 733 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
bogdanm 0:9b334a45a8ff 734 /** Array initializer of DMAMUX peripheral base pointers */
bogdanm 0:9b334a45a8ff 735 #define DMAMUX_BASES { DMAMUX0 }
bogdanm 0:9b334a45a8ff 736
bogdanm 0:9b334a45a8ff 737 /**
bogdanm 0:9b334a45a8ff 738 * @}
bogdanm 0:9b334a45a8ff 739 */ /* end of group DMAMUX_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 740
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 743 -- FGPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 744 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 /**
bogdanm 0:9b334a45a8ff 747 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 748 * @{
bogdanm 0:9b334a45a8ff 749 */
bogdanm 0:9b334a45a8ff 750
bogdanm 0:9b334a45a8ff 751 /** FGPIO - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 752 typedef struct {
bogdanm 0:9b334a45a8ff 753 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 754 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 755 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 756 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 757 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 758 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 759 } FGPIO_Type;
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 762 -- FGPIO Register Masks
bogdanm 0:9b334a45a8ff 763 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 /**
bogdanm 0:9b334a45a8ff 766 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
bogdanm 0:9b334a45a8ff 767 * @{
bogdanm 0:9b334a45a8ff 768 */
bogdanm 0:9b334a45a8ff 769
bogdanm 0:9b334a45a8ff 770 /* PDOR Bit Fields */
bogdanm 0:9b334a45a8ff 771 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 772 #define FGPIO_PDOR_PDO_SHIFT 0
bogdanm 0:9b334a45a8ff 773 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
bogdanm 0:9b334a45a8ff 774 /* PSOR Bit Fields */
bogdanm 0:9b334a45a8ff 775 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 776 #define FGPIO_PSOR_PTSO_SHIFT 0
bogdanm 0:9b334a45a8ff 777 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
bogdanm 0:9b334a45a8ff 778 /* PCOR Bit Fields */
bogdanm 0:9b334a45a8ff 779 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 780 #define FGPIO_PCOR_PTCO_SHIFT 0
bogdanm 0:9b334a45a8ff 781 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
bogdanm 0:9b334a45a8ff 782 /* PTOR Bit Fields */
bogdanm 0:9b334a45a8ff 783 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 784 #define FGPIO_PTOR_PTTO_SHIFT 0
bogdanm 0:9b334a45a8ff 785 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
bogdanm 0:9b334a45a8ff 786 /* PDIR Bit Fields */
bogdanm 0:9b334a45a8ff 787 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 788 #define FGPIO_PDIR_PDI_SHIFT 0
bogdanm 0:9b334a45a8ff 789 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
bogdanm 0:9b334a45a8ff 790 /* PDDR Bit Fields */
bogdanm 0:9b334a45a8ff 791 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 792 #define FGPIO_PDDR_PDD_SHIFT 0
bogdanm 0:9b334a45a8ff 793 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /**
bogdanm 0:9b334a45a8ff 796 * @}
bogdanm 0:9b334a45a8ff 797 */ /* end of group FGPIO_Register_Masks */
bogdanm 0:9b334a45a8ff 798
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /* FGPIO - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 801 /** Peripheral FPTA base address */
bogdanm 0:9b334a45a8ff 802 #define FPTA_BASE (0xF80FF000u)
bogdanm 0:9b334a45a8ff 803 /** Peripheral FPTA base pointer */
bogdanm 0:9b334a45a8ff 804 #define FPTA ((FGPIO_Type *)FPTA_BASE)
bogdanm 0:9b334a45a8ff 805 /** Peripheral FPTB base address */
bogdanm 0:9b334a45a8ff 806 #define FPTB_BASE (0xF80FF040u)
bogdanm 0:9b334a45a8ff 807 /** Peripheral FPTB base pointer */
bogdanm 0:9b334a45a8ff 808 #define FPTB ((FGPIO_Type *)FPTB_BASE)
bogdanm 0:9b334a45a8ff 809 /** Peripheral FPTC base address */
bogdanm 0:9b334a45a8ff 810 #define FPTC_BASE (0xF80FF080u)
bogdanm 0:9b334a45a8ff 811 /** Peripheral FPTC base pointer */
bogdanm 0:9b334a45a8ff 812 #define FPTC ((FGPIO_Type *)FPTC_BASE)
bogdanm 0:9b334a45a8ff 813 /** Peripheral FPTD base address */
bogdanm 0:9b334a45a8ff 814 #define FPTD_BASE (0xF80FF0C0u)
bogdanm 0:9b334a45a8ff 815 /** Peripheral FPTD base pointer */
bogdanm 0:9b334a45a8ff 816 #define FPTD ((FGPIO_Type *)FPTD_BASE)
bogdanm 0:9b334a45a8ff 817 /** Peripheral FPTE base address */
bogdanm 0:9b334a45a8ff 818 #define FPTE_BASE (0xF80FF100u)
bogdanm 0:9b334a45a8ff 819 /** Peripheral FPTE base pointer */
bogdanm 0:9b334a45a8ff 820 #define FPTE ((FGPIO_Type *)FPTE_BASE)
bogdanm 0:9b334a45a8ff 821 /** Array initializer of FGPIO peripheral base pointers */
bogdanm 0:9b334a45a8ff 822 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
bogdanm 0:9b334a45a8ff 823
bogdanm 0:9b334a45a8ff 824 /**
bogdanm 0:9b334a45a8ff 825 * @}
bogdanm 0:9b334a45a8ff 826 */ /* end of group FGPIO_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 830 -- FTFA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 831 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /**
bogdanm 0:9b334a45a8ff 834 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 835 * @{
bogdanm 0:9b334a45a8ff 836 */
bogdanm 0:9b334a45a8ff 837
bogdanm 0:9b334a45a8ff 838 /** FTFA - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 839 typedef struct {
bogdanm 0:9b334a45a8ff 840 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 841 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 842 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 843 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 844 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
bogdanm 0:9b334a45a8ff 845 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
bogdanm 0:9b334a45a8ff 846 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
bogdanm 0:9b334a45a8ff 847 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
bogdanm 0:9b334a45a8ff 848 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
bogdanm 0:9b334a45a8ff 849 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
bogdanm 0:9b334a45a8ff 850 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
bogdanm 0:9b334a45a8ff 851 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
bogdanm 0:9b334a45a8ff 852 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
bogdanm 0:9b334a45a8ff 853 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
bogdanm 0:9b334a45a8ff 854 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
bogdanm 0:9b334a45a8ff 855 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
bogdanm 0:9b334a45a8ff 856 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
bogdanm 0:9b334a45a8ff 857 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
bogdanm 0:9b334a45a8ff 858 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
bogdanm 0:9b334a45a8ff 859 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
bogdanm 0:9b334a45a8ff 860 } FTFA_Type;
bogdanm 0:9b334a45a8ff 861
bogdanm 0:9b334a45a8ff 862 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 863 -- FTFA Register Masks
bogdanm 0:9b334a45a8ff 864 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 /**
bogdanm 0:9b334a45a8ff 867 * @addtogroup FTFA_Register_Masks FTFA Register Masks
bogdanm 0:9b334a45a8ff 868 * @{
bogdanm 0:9b334a45a8ff 869 */
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /* FSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 872 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
bogdanm 0:9b334a45a8ff 873 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
bogdanm 0:9b334a45a8ff 874 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
bogdanm 0:9b334a45a8ff 875 #define FTFA_FSTAT_FPVIOL_SHIFT 4
bogdanm 0:9b334a45a8ff 876 #define FTFA_FSTAT_ACCERR_MASK 0x20u
bogdanm 0:9b334a45a8ff 877 #define FTFA_FSTAT_ACCERR_SHIFT 5
bogdanm 0:9b334a45a8ff 878 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
bogdanm 0:9b334a45a8ff 879 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
bogdanm 0:9b334a45a8ff 880 #define FTFA_FSTAT_CCIF_MASK 0x80u
bogdanm 0:9b334a45a8ff 881 #define FTFA_FSTAT_CCIF_SHIFT 7
bogdanm 0:9b334a45a8ff 882 /* FCNFG Bit Fields */
bogdanm 0:9b334a45a8ff 883 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
bogdanm 0:9b334a45a8ff 884 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
bogdanm 0:9b334a45a8ff 885 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
bogdanm 0:9b334a45a8ff 886 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
bogdanm 0:9b334a45a8ff 887 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 888 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
bogdanm 0:9b334a45a8ff 889 #define FTFA_FCNFG_CCIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 890 #define FTFA_FCNFG_CCIE_SHIFT 7
bogdanm 0:9b334a45a8ff 891 /* FSEC Bit Fields */
bogdanm 0:9b334a45a8ff 892 #define FTFA_FSEC_SEC_MASK 0x3u
bogdanm 0:9b334a45a8ff 893 #define FTFA_FSEC_SEC_SHIFT 0
bogdanm 0:9b334a45a8ff 894 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
bogdanm 0:9b334a45a8ff 895 #define FTFA_FSEC_FSLACC_MASK 0xCu
bogdanm 0:9b334a45a8ff 896 #define FTFA_FSEC_FSLACC_SHIFT 2
bogdanm 0:9b334a45a8ff 897 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
bogdanm 0:9b334a45a8ff 898 #define FTFA_FSEC_MEEN_MASK 0x30u
bogdanm 0:9b334a45a8ff 899 #define FTFA_FSEC_MEEN_SHIFT 4
bogdanm 0:9b334a45a8ff 900 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
bogdanm 0:9b334a45a8ff 901 #define FTFA_FSEC_KEYEN_MASK 0xC0u
bogdanm 0:9b334a45a8ff 902 #define FTFA_FSEC_KEYEN_SHIFT 6
bogdanm 0:9b334a45a8ff 903 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
bogdanm 0:9b334a45a8ff 904 /* FOPT Bit Fields */
bogdanm 0:9b334a45a8ff 905 #define FTFA_FOPT_OPT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 906 #define FTFA_FOPT_OPT_SHIFT 0
bogdanm 0:9b334a45a8ff 907 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
bogdanm 0:9b334a45a8ff 908 /* FCCOB3 Bit Fields */
bogdanm 0:9b334a45a8ff 909 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 910 #define FTFA_FCCOB3_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 911 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 912 /* FCCOB2 Bit Fields */
bogdanm 0:9b334a45a8ff 913 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 914 #define FTFA_FCCOB2_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 915 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 916 /* FCCOB1 Bit Fields */
bogdanm 0:9b334a45a8ff 917 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 918 #define FTFA_FCCOB1_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 919 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 920 /* FCCOB0 Bit Fields */
bogdanm 0:9b334a45a8ff 921 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 922 #define FTFA_FCCOB0_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 923 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 924 /* FCCOB7 Bit Fields */
bogdanm 0:9b334a45a8ff 925 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 926 #define FTFA_FCCOB7_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 927 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 928 /* FCCOB6 Bit Fields */
bogdanm 0:9b334a45a8ff 929 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 930 #define FTFA_FCCOB6_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 931 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 932 /* FCCOB5 Bit Fields */
bogdanm 0:9b334a45a8ff 933 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 934 #define FTFA_FCCOB5_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 935 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 936 /* FCCOB4 Bit Fields */
bogdanm 0:9b334a45a8ff 937 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 938 #define FTFA_FCCOB4_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 939 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 940 /* FCCOBB Bit Fields */
bogdanm 0:9b334a45a8ff 941 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 942 #define FTFA_FCCOBB_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 943 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 944 /* FCCOBA Bit Fields */
bogdanm 0:9b334a45a8ff 945 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 946 #define FTFA_FCCOBA_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 947 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 948 /* FCCOB9 Bit Fields */
bogdanm 0:9b334a45a8ff 949 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 950 #define FTFA_FCCOB9_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 951 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 952 /* FCCOB8 Bit Fields */
bogdanm 0:9b334a45a8ff 953 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 954 #define FTFA_FCCOB8_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 955 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 956 /* FPROT3 Bit Fields */
bogdanm 0:9b334a45a8ff 957 #define FTFA_FPROT3_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 958 #define FTFA_FPROT3_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 959 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
bogdanm 0:9b334a45a8ff 960 /* FPROT2 Bit Fields */
bogdanm 0:9b334a45a8ff 961 #define FTFA_FPROT2_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 962 #define FTFA_FPROT2_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 963 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
bogdanm 0:9b334a45a8ff 964 /* FPROT1 Bit Fields */
bogdanm 0:9b334a45a8ff 965 #define FTFA_FPROT1_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 966 #define FTFA_FPROT1_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 967 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
bogdanm 0:9b334a45a8ff 968 /* FPROT0 Bit Fields */
bogdanm 0:9b334a45a8ff 969 #define FTFA_FPROT0_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 970 #define FTFA_FPROT0_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 971 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 /**
bogdanm 0:9b334a45a8ff 974 * @}
bogdanm 0:9b334a45a8ff 975 */ /* end of group FTFA_Register_Masks */
bogdanm 0:9b334a45a8ff 976
bogdanm 0:9b334a45a8ff 977
bogdanm 0:9b334a45a8ff 978 /* FTFA - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 979 /** Peripheral FTFA base address */
bogdanm 0:9b334a45a8ff 980 #define FTFA_BASE (0x40020000u)
bogdanm 0:9b334a45a8ff 981 /** Peripheral FTFA base pointer */
bogdanm 0:9b334a45a8ff 982 #define FTFA ((FTFA_Type *)FTFA_BASE)
bogdanm 0:9b334a45a8ff 983 /** Array initializer of FTFA peripheral base pointers */
bogdanm 0:9b334a45a8ff 984 #define FTFA_BASES { FTFA }
bogdanm 0:9b334a45a8ff 985
bogdanm 0:9b334a45a8ff 986 /**
bogdanm 0:9b334a45a8ff 987 * @}
bogdanm 0:9b334a45a8ff 988 */ /* end of group FTFA_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 989
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 992 -- GPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 993 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 994
bogdanm 0:9b334a45a8ff 995 /**
bogdanm 0:9b334a45a8ff 996 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 997 * @{
bogdanm 0:9b334a45a8ff 998 */
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /** GPIO - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1001 typedef struct {
bogdanm 0:9b334a45a8ff 1002 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1003 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1004 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1005 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1006 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 1007 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 1008 } GPIO_Type;
bogdanm 0:9b334a45a8ff 1009
bogdanm 0:9b334a45a8ff 1010 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1011 -- GPIO Register Masks
bogdanm 0:9b334a45a8ff 1012 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1013
bogdanm 0:9b334a45a8ff 1014 /**
bogdanm 0:9b334a45a8ff 1015 * @addtogroup GPIO_Register_Masks GPIO Register Masks
bogdanm 0:9b334a45a8ff 1016 * @{
bogdanm 0:9b334a45a8ff 1017 */
bogdanm 0:9b334a45a8ff 1018
bogdanm 0:9b334a45a8ff 1019 /* PDOR Bit Fields */
bogdanm 0:9b334a45a8ff 1020 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1021 #define GPIO_PDOR_PDO_SHIFT 0
bogdanm 0:9b334a45a8ff 1022 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
bogdanm 0:9b334a45a8ff 1023 /* PSOR Bit Fields */
bogdanm 0:9b334a45a8ff 1024 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1025 #define GPIO_PSOR_PTSO_SHIFT 0
bogdanm 0:9b334a45a8ff 1026 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
bogdanm 0:9b334a45a8ff 1027 /* PCOR Bit Fields */
bogdanm 0:9b334a45a8ff 1028 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1029 #define GPIO_PCOR_PTCO_SHIFT 0
bogdanm 0:9b334a45a8ff 1030 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
bogdanm 0:9b334a45a8ff 1031 /* PTOR Bit Fields */
bogdanm 0:9b334a45a8ff 1032 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1033 #define GPIO_PTOR_PTTO_SHIFT 0
bogdanm 0:9b334a45a8ff 1034 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
bogdanm 0:9b334a45a8ff 1035 /* PDIR Bit Fields */
bogdanm 0:9b334a45a8ff 1036 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1037 #define GPIO_PDIR_PDI_SHIFT 0
bogdanm 0:9b334a45a8ff 1038 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
bogdanm 0:9b334a45a8ff 1039 /* PDDR Bit Fields */
bogdanm 0:9b334a45a8ff 1040 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1041 #define GPIO_PDDR_PDD_SHIFT 0
bogdanm 0:9b334a45a8ff 1042 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /**
bogdanm 0:9b334a45a8ff 1045 * @}
bogdanm 0:9b334a45a8ff 1046 */ /* end of group GPIO_Register_Masks */
bogdanm 0:9b334a45a8ff 1047
bogdanm 0:9b334a45a8ff 1048
bogdanm 0:9b334a45a8ff 1049 /* GPIO - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1050 /** Peripheral PTA base address */
bogdanm 0:9b334a45a8ff 1051 #define PTA_BASE (0x400FF000u)
bogdanm 0:9b334a45a8ff 1052 /** Peripheral PTA base pointer */
bogdanm 0:9b334a45a8ff 1053 #define PTA ((GPIO_Type *)PTA_BASE)
bogdanm 0:9b334a45a8ff 1054 /** Peripheral PTB base address */
bogdanm 0:9b334a45a8ff 1055 #define PTB_BASE (0x400FF040u)
bogdanm 0:9b334a45a8ff 1056 /** Peripheral PTB base pointer */
bogdanm 0:9b334a45a8ff 1057 #define PTB ((GPIO_Type *)PTB_BASE)
bogdanm 0:9b334a45a8ff 1058 /** Peripheral PTC base address */
bogdanm 0:9b334a45a8ff 1059 #define PTC_BASE (0x400FF080u)
bogdanm 0:9b334a45a8ff 1060 /** Peripheral PTC base pointer */
bogdanm 0:9b334a45a8ff 1061 #define PTC ((GPIO_Type *)PTC_BASE)
bogdanm 0:9b334a45a8ff 1062 /** Peripheral PTD base address */
bogdanm 0:9b334a45a8ff 1063 #define PTD_BASE (0x400FF0C0u)
bogdanm 0:9b334a45a8ff 1064 /** Peripheral PTD base pointer */
bogdanm 0:9b334a45a8ff 1065 #define PTD ((GPIO_Type *)PTD_BASE)
bogdanm 0:9b334a45a8ff 1066 /** Peripheral PTE base address */
bogdanm 0:9b334a45a8ff 1067 #define PTE_BASE (0x400FF100u)
bogdanm 0:9b334a45a8ff 1068 /** Peripheral PTE base pointer */
bogdanm 0:9b334a45a8ff 1069 #define PTE ((GPIO_Type *)PTE_BASE)
bogdanm 0:9b334a45a8ff 1070 /** Array initializer of GPIO peripheral base pointers */
bogdanm 0:9b334a45a8ff 1071 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
bogdanm 0:9b334a45a8ff 1072
bogdanm 0:9b334a45a8ff 1073 /**
bogdanm 0:9b334a45a8ff 1074 * @}
bogdanm 0:9b334a45a8ff 1075 */ /* end of group GPIO_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1076
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1079 -- I2C Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1080 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1081
bogdanm 0:9b334a45a8ff 1082 /**
bogdanm 0:9b334a45a8ff 1083 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1084 * @{
bogdanm 0:9b334a45a8ff 1085 */
bogdanm 0:9b334a45a8ff 1086
bogdanm 0:9b334a45a8ff 1087 /** I2C - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1088 typedef struct {
bogdanm 0:9b334a45a8ff 1089 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1090 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 1091 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
bogdanm 0:9b334a45a8ff 1092 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 1093 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1094 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
bogdanm 0:9b334a45a8ff 1095 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
bogdanm 0:9b334a45a8ff 1096 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 1097 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1098 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
bogdanm 0:9b334a45a8ff 1099 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
bogdanm 0:9b334a45a8ff 1100 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
bogdanm 0:9b334a45a8ff 1101 } I2C_Type;
bogdanm 0:9b334a45a8ff 1102
bogdanm 0:9b334a45a8ff 1103 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1104 -- I2C Register Masks
bogdanm 0:9b334a45a8ff 1105 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1106
bogdanm 0:9b334a45a8ff 1107 /**
bogdanm 0:9b334a45a8ff 1108 * @addtogroup I2C_Register_Masks I2C Register Masks
bogdanm 0:9b334a45a8ff 1109 * @{
bogdanm 0:9b334a45a8ff 1110 */
bogdanm 0:9b334a45a8ff 1111
bogdanm 0:9b334a45a8ff 1112 /* A1 Bit Fields */
bogdanm 0:9b334a45a8ff 1113 #define I2C_A1_AD_MASK 0xFEu
bogdanm 0:9b334a45a8ff 1114 #define I2C_A1_AD_SHIFT 1
bogdanm 0:9b334a45a8ff 1115 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
bogdanm 0:9b334a45a8ff 1116 /* F Bit Fields */
bogdanm 0:9b334a45a8ff 1117 #define I2C_F_ICR_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 1118 #define I2C_F_ICR_SHIFT 0
bogdanm 0:9b334a45a8ff 1119 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
bogdanm 0:9b334a45a8ff 1120 #define I2C_F_MULT_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1121 #define I2C_F_MULT_SHIFT 6
bogdanm 0:9b334a45a8ff 1122 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
bogdanm 0:9b334a45a8ff 1123 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 1124 #define I2C_C1_DMAEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 1125 #define I2C_C1_DMAEN_SHIFT 0
bogdanm 0:9b334a45a8ff 1126 #define I2C_C1_WUEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 1127 #define I2C_C1_WUEN_SHIFT 1
bogdanm 0:9b334a45a8ff 1128 #define I2C_C1_RSTA_MASK 0x4u
bogdanm 0:9b334a45a8ff 1129 #define I2C_C1_RSTA_SHIFT 2
bogdanm 0:9b334a45a8ff 1130 #define I2C_C1_TXAK_MASK 0x8u
bogdanm 0:9b334a45a8ff 1131 #define I2C_C1_TXAK_SHIFT 3
bogdanm 0:9b334a45a8ff 1132 #define I2C_C1_TX_MASK 0x10u
bogdanm 0:9b334a45a8ff 1133 #define I2C_C1_TX_SHIFT 4
bogdanm 0:9b334a45a8ff 1134 #define I2C_C1_MST_MASK 0x20u
bogdanm 0:9b334a45a8ff 1135 #define I2C_C1_MST_SHIFT 5
bogdanm 0:9b334a45a8ff 1136 #define I2C_C1_IICIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 1137 #define I2C_C1_IICIE_SHIFT 6
bogdanm 0:9b334a45a8ff 1138 #define I2C_C1_IICEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1139 #define I2C_C1_IICEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1140 /* S Bit Fields */
bogdanm 0:9b334a45a8ff 1141 #define I2C_S_RXAK_MASK 0x1u
bogdanm 0:9b334a45a8ff 1142 #define I2C_S_RXAK_SHIFT 0
bogdanm 0:9b334a45a8ff 1143 #define I2C_S_IICIF_MASK 0x2u
bogdanm 0:9b334a45a8ff 1144 #define I2C_S_IICIF_SHIFT 1
bogdanm 0:9b334a45a8ff 1145 #define I2C_S_SRW_MASK 0x4u
bogdanm 0:9b334a45a8ff 1146 #define I2C_S_SRW_SHIFT 2
bogdanm 0:9b334a45a8ff 1147 #define I2C_S_RAM_MASK 0x8u
bogdanm 0:9b334a45a8ff 1148 #define I2C_S_RAM_SHIFT 3
bogdanm 0:9b334a45a8ff 1149 #define I2C_S_ARBL_MASK 0x10u
bogdanm 0:9b334a45a8ff 1150 #define I2C_S_ARBL_SHIFT 4
bogdanm 0:9b334a45a8ff 1151 #define I2C_S_BUSY_MASK 0x20u
bogdanm 0:9b334a45a8ff 1152 #define I2C_S_BUSY_SHIFT 5
bogdanm 0:9b334a45a8ff 1153 #define I2C_S_IAAS_MASK 0x40u
bogdanm 0:9b334a45a8ff 1154 #define I2C_S_IAAS_SHIFT 6
bogdanm 0:9b334a45a8ff 1155 #define I2C_S_TCF_MASK 0x80u
bogdanm 0:9b334a45a8ff 1156 #define I2C_S_TCF_SHIFT 7
bogdanm 0:9b334a45a8ff 1157 /* D Bit Fields */
bogdanm 0:9b334a45a8ff 1158 #define I2C_D_DATA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1159 #define I2C_D_DATA_SHIFT 0
bogdanm 0:9b334a45a8ff 1160 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
bogdanm 0:9b334a45a8ff 1161 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 1162 #define I2C_C2_AD_MASK 0x7u
bogdanm 0:9b334a45a8ff 1163 #define I2C_C2_AD_SHIFT 0
bogdanm 0:9b334a45a8ff 1164 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
bogdanm 0:9b334a45a8ff 1165 #define I2C_C2_RMEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 1166 #define I2C_C2_RMEN_SHIFT 3
bogdanm 0:9b334a45a8ff 1167 #define I2C_C2_SBRC_MASK 0x10u
bogdanm 0:9b334a45a8ff 1168 #define I2C_C2_SBRC_SHIFT 4
bogdanm 0:9b334a45a8ff 1169 #define I2C_C2_HDRS_MASK 0x20u
bogdanm 0:9b334a45a8ff 1170 #define I2C_C2_HDRS_SHIFT 5
bogdanm 0:9b334a45a8ff 1171 #define I2C_C2_ADEXT_MASK 0x40u
bogdanm 0:9b334a45a8ff 1172 #define I2C_C2_ADEXT_SHIFT 6
bogdanm 0:9b334a45a8ff 1173 #define I2C_C2_GCAEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1174 #define I2C_C2_GCAEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1175 /* FLT Bit Fields */
bogdanm 0:9b334a45a8ff 1176 #define I2C_FLT_FLT_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 1177 #define I2C_FLT_FLT_SHIFT 0
bogdanm 0:9b334a45a8ff 1178 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
bogdanm 0:9b334a45a8ff 1179 #define I2C_FLT_STOPIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 1180 #define I2C_FLT_STOPIE_SHIFT 5
bogdanm 0:9b334a45a8ff 1181 #define I2C_FLT_STOPF_MASK 0x40u
bogdanm 0:9b334a45a8ff 1182 #define I2C_FLT_STOPF_SHIFT 6
bogdanm 0:9b334a45a8ff 1183 #define I2C_FLT_SHEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1184 #define I2C_FLT_SHEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1185 /* RA Bit Fields */
bogdanm 0:9b334a45a8ff 1186 #define I2C_RA_RAD_MASK 0xFEu
bogdanm 0:9b334a45a8ff 1187 #define I2C_RA_RAD_SHIFT 1
bogdanm 0:9b334a45a8ff 1188 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
bogdanm 0:9b334a45a8ff 1189 /* SMB Bit Fields */
bogdanm 0:9b334a45a8ff 1190 #define I2C_SMB_SHTF2IE_MASK 0x1u
bogdanm 0:9b334a45a8ff 1191 #define I2C_SMB_SHTF2IE_SHIFT 0
bogdanm 0:9b334a45a8ff 1192 #define I2C_SMB_SHTF2_MASK 0x2u
bogdanm 0:9b334a45a8ff 1193 #define I2C_SMB_SHTF2_SHIFT 1
bogdanm 0:9b334a45a8ff 1194 #define I2C_SMB_SHTF1_MASK 0x4u
bogdanm 0:9b334a45a8ff 1195 #define I2C_SMB_SHTF1_SHIFT 2
bogdanm 0:9b334a45a8ff 1196 #define I2C_SMB_SLTF_MASK 0x8u
bogdanm 0:9b334a45a8ff 1197 #define I2C_SMB_SLTF_SHIFT 3
bogdanm 0:9b334a45a8ff 1198 #define I2C_SMB_TCKSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 1199 #define I2C_SMB_TCKSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 1200 #define I2C_SMB_SIICAEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 1201 #define I2C_SMB_SIICAEN_SHIFT 5
bogdanm 0:9b334a45a8ff 1202 #define I2C_SMB_ALERTEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 1203 #define I2C_SMB_ALERTEN_SHIFT 6
bogdanm 0:9b334a45a8ff 1204 #define I2C_SMB_FACK_MASK 0x80u
bogdanm 0:9b334a45a8ff 1205 #define I2C_SMB_FACK_SHIFT 7
bogdanm 0:9b334a45a8ff 1206 /* A2 Bit Fields */
bogdanm 0:9b334a45a8ff 1207 #define I2C_A2_SAD_MASK 0xFEu
bogdanm 0:9b334a45a8ff 1208 #define I2C_A2_SAD_SHIFT 1
bogdanm 0:9b334a45a8ff 1209 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
bogdanm 0:9b334a45a8ff 1210 /* SLTH Bit Fields */
bogdanm 0:9b334a45a8ff 1211 #define I2C_SLTH_SSLT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1212 #define I2C_SLTH_SSLT_SHIFT 0
bogdanm 0:9b334a45a8ff 1213 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
bogdanm 0:9b334a45a8ff 1214 /* SLTL Bit Fields */
bogdanm 0:9b334a45a8ff 1215 #define I2C_SLTL_SSLT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1216 #define I2C_SLTL_SSLT_SHIFT 0
bogdanm 0:9b334a45a8ff 1217 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
bogdanm 0:9b334a45a8ff 1218
bogdanm 0:9b334a45a8ff 1219 /**
bogdanm 0:9b334a45a8ff 1220 * @}
bogdanm 0:9b334a45a8ff 1221 */ /* end of group I2C_Register_Masks */
bogdanm 0:9b334a45a8ff 1222
bogdanm 0:9b334a45a8ff 1223
bogdanm 0:9b334a45a8ff 1224 /* I2C - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1225 /** Peripheral I2C0 base address */
bogdanm 0:9b334a45a8ff 1226 #define I2C0_BASE (0x40066000u)
bogdanm 0:9b334a45a8ff 1227 /** Peripheral I2C0 base pointer */
bogdanm 0:9b334a45a8ff 1228 #define I2C0 ((I2C_Type *)I2C0_BASE)
bogdanm 0:9b334a45a8ff 1229 /** Peripheral I2C1 base address */
bogdanm 0:9b334a45a8ff 1230 #define I2C1_BASE (0x40067000u)
bogdanm 0:9b334a45a8ff 1231 /** Peripheral I2C1 base pointer */
bogdanm 0:9b334a45a8ff 1232 #define I2C1 ((I2C_Type *)I2C1_BASE)
bogdanm 0:9b334a45a8ff 1233 /** Array initializer of I2C peripheral base pointers */
bogdanm 0:9b334a45a8ff 1234 #define I2C_BASES { I2C0, I2C1 }
bogdanm 0:9b334a45a8ff 1235
bogdanm 0:9b334a45a8ff 1236 /**
bogdanm 0:9b334a45a8ff 1237 * @}
bogdanm 0:9b334a45a8ff 1238 */ /* end of group I2C_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1239
bogdanm 0:9b334a45a8ff 1240
bogdanm 0:9b334a45a8ff 1241 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1242 -- I2S Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1243 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1244
bogdanm 0:9b334a45a8ff 1245 /**
bogdanm 0:9b334a45a8ff 1246 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1247 * @{
bogdanm 0:9b334a45a8ff 1248 */
bogdanm 0:9b334a45a8ff 1249
bogdanm 0:9b334a45a8ff 1250 /** I2S - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1251 typedef struct {
bogdanm 0:9b334a45a8ff 1252 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1253 uint8_t RESERVED_0[4];
bogdanm 0:9b334a45a8ff 1254 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1255 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1256 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 1257 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 1258 uint8_t RESERVED_1[8];
bogdanm 0:9b334a45a8ff 1259 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1260 uint8_t RESERVED_2[60];
bogdanm 0:9b334a45a8ff 1261 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
bogdanm 0:9b334a45a8ff 1262 uint8_t RESERVED_3[28];
bogdanm 0:9b334a45a8ff 1263 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
bogdanm 0:9b334a45a8ff 1264 uint8_t RESERVED_4[4];
bogdanm 0:9b334a45a8ff 1265 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
bogdanm 0:9b334a45a8ff 1266 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
bogdanm 0:9b334a45a8ff 1267 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
bogdanm 0:9b334a45a8ff 1268 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
bogdanm 0:9b334a45a8ff 1269 uint8_t RESERVED_5[8];
bogdanm 0:9b334a45a8ff 1270 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1271 uint8_t RESERVED_6[60];
bogdanm 0:9b334a45a8ff 1272 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
bogdanm 0:9b334a45a8ff 1273 uint8_t RESERVED_7[28];
bogdanm 0:9b334a45a8ff 1274 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
bogdanm 0:9b334a45a8ff 1275 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
bogdanm 0:9b334a45a8ff 1276 } I2S_Type;
bogdanm 0:9b334a45a8ff 1277
bogdanm 0:9b334a45a8ff 1278 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1279 -- I2S Register Masks
bogdanm 0:9b334a45a8ff 1280 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1281
bogdanm 0:9b334a45a8ff 1282 /**
bogdanm 0:9b334a45a8ff 1283 * @addtogroup I2S_Register_Masks I2S Register Masks
bogdanm 0:9b334a45a8ff 1284 * @{
bogdanm 0:9b334a45a8ff 1285 */
bogdanm 0:9b334a45a8ff 1286
bogdanm 0:9b334a45a8ff 1287 /* TCSR Bit Fields */
bogdanm 0:9b334a45a8ff 1288 #define I2S_TCSR_FWDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 1289 #define I2S_TCSR_FWDE_SHIFT 1
bogdanm 0:9b334a45a8ff 1290 #define I2S_TCSR_FWIE_MASK 0x200u
bogdanm 0:9b334a45a8ff 1291 #define I2S_TCSR_FWIE_SHIFT 9
bogdanm 0:9b334a45a8ff 1292 #define I2S_TCSR_FEIE_MASK 0x400u
bogdanm 0:9b334a45a8ff 1293 #define I2S_TCSR_FEIE_SHIFT 10
bogdanm 0:9b334a45a8ff 1294 #define I2S_TCSR_SEIE_MASK 0x800u
bogdanm 0:9b334a45a8ff 1295 #define I2S_TCSR_SEIE_SHIFT 11
bogdanm 0:9b334a45a8ff 1296 #define I2S_TCSR_WSIE_MASK 0x1000u
bogdanm 0:9b334a45a8ff 1297 #define I2S_TCSR_WSIE_SHIFT 12
bogdanm 0:9b334a45a8ff 1298 #define I2S_TCSR_FWF_MASK 0x20000u
bogdanm 0:9b334a45a8ff 1299 #define I2S_TCSR_FWF_SHIFT 17
bogdanm 0:9b334a45a8ff 1300 #define I2S_TCSR_FEF_MASK 0x40000u
bogdanm 0:9b334a45a8ff 1301 #define I2S_TCSR_FEF_SHIFT 18
bogdanm 0:9b334a45a8ff 1302 #define I2S_TCSR_SEF_MASK 0x80000u
bogdanm 0:9b334a45a8ff 1303 #define I2S_TCSR_SEF_SHIFT 19
bogdanm 0:9b334a45a8ff 1304 #define I2S_TCSR_WSF_MASK 0x100000u
bogdanm 0:9b334a45a8ff 1305 #define I2S_TCSR_WSF_SHIFT 20
bogdanm 0:9b334a45a8ff 1306 #define I2S_TCSR_SR_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1307 #define I2S_TCSR_SR_SHIFT 24
bogdanm 0:9b334a45a8ff 1308 #define I2S_TCSR_FR_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1309 #define I2S_TCSR_FR_SHIFT 25
bogdanm 0:9b334a45a8ff 1310 #define I2S_TCSR_BCE_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 1311 #define I2S_TCSR_BCE_SHIFT 28
bogdanm 0:9b334a45a8ff 1312 #define I2S_TCSR_DBGE_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 1313 #define I2S_TCSR_DBGE_SHIFT 29
bogdanm 0:9b334a45a8ff 1314 #define I2S_TCSR_STOPE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 1315 #define I2S_TCSR_STOPE_SHIFT 30
bogdanm 0:9b334a45a8ff 1316 #define I2S_TCSR_TE_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1317 #define I2S_TCSR_TE_SHIFT 31
bogdanm 0:9b334a45a8ff 1318 /* TCR2 Bit Fields */
bogdanm 0:9b334a45a8ff 1319 #define I2S_TCR2_DIV_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1320 #define I2S_TCR2_DIV_SHIFT 0
bogdanm 0:9b334a45a8ff 1321 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
bogdanm 0:9b334a45a8ff 1322 #define I2S_TCR2_BCD_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1323 #define I2S_TCR2_BCD_SHIFT 24
bogdanm 0:9b334a45a8ff 1324 #define I2S_TCR2_BCP_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1325 #define I2S_TCR2_BCP_SHIFT 25
bogdanm 0:9b334a45a8ff 1326 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
bogdanm 0:9b334a45a8ff 1327 #define I2S_TCR2_CLKMODE_SHIFT 26
bogdanm 0:9b334a45a8ff 1328 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
bogdanm 0:9b334a45a8ff 1329 /* TCR3 Bit Fields */
bogdanm 0:9b334a45a8ff 1330 #define I2S_TCR3_WDFL_MASK 0x1u
bogdanm 0:9b334a45a8ff 1331 #define I2S_TCR3_WDFL_SHIFT 0
bogdanm 0:9b334a45a8ff 1332 #define I2S_TCR3_TCE_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1333 #define I2S_TCR3_TCE_SHIFT 16
bogdanm 0:9b334a45a8ff 1334 /* TCR4 Bit Fields */
bogdanm 0:9b334a45a8ff 1335 #define I2S_TCR4_FSD_MASK 0x1u
bogdanm 0:9b334a45a8ff 1336 #define I2S_TCR4_FSD_SHIFT 0
bogdanm 0:9b334a45a8ff 1337 #define I2S_TCR4_FSP_MASK 0x2u
bogdanm 0:9b334a45a8ff 1338 #define I2S_TCR4_FSP_SHIFT 1
bogdanm 0:9b334a45a8ff 1339 #define I2S_TCR4_FSE_MASK 0x8u
bogdanm 0:9b334a45a8ff 1340 #define I2S_TCR4_FSE_SHIFT 3
bogdanm 0:9b334a45a8ff 1341 #define I2S_TCR4_MF_MASK 0x10u
bogdanm 0:9b334a45a8ff 1342 #define I2S_TCR4_MF_SHIFT 4
bogdanm 0:9b334a45a8ff 1343 #define I2S_TCR4_SYWD_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1344 #define I2S_TCR4_SYWD_SHIFT 8
bogdanm 0:9b334a45a8ff 1345 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
bogdanm 0:9b334a45a8ff 1346 #define I2S_TCR4_FRSZ_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1347 #define I2S_TCR4_FRSZ_SHIFT 16
bogdanm 0:9b334a45a8ff 1348 /* TCR5 Bit Fields */
bogdanm 0:9b334a45a8ff 1349 #define I2S_TCR5_FBT_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1350 #define I2S_TCR5_FBT_SHIFT 8
bogdanm 0:9b334a45a8ff 1351 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
bogdanm 0:9b334a45a8ff 1352 #define I2S_TCR5_W0W_MASK 0x1F0000u
bogdanm 0:9b334a45a8ff 1353 #define I2S_TCR5_W0W_SHIFT 16
bogdanm 0:9b334a45a8ff 1354 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
bogdanm 0:9b334a45a8ff 1355 #define I2S_TCR5_WNW_MASK 0x1F000000u
bogdanm 0:9b334a45a8ff 1356 #define I2S_TCR5_WNW_SHIFT 24
bogdanm 0:9b334a45a8ff 1357 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
bogdanm 0:9b334a45a8ff 1358 /* TDR Bit Fields */
bogdanm 0:9b334a45a8ff 1359 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1360 #define I2S_TDR_TDR_SHIFT 0
bogdanm 0:9b334a45a8ff 1361 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
bogdanm 0:9b334a45a8ff 1362 /* TMR Bit Fields */
bogdanm 0:9b334a45a8ff 1363 #define I2S_TMR_TWM_MASK 0x3u
bogdanm 0:9b334a45a8ff 1364 #define I2S_TMR_TWM_SHIFT 0
bogdanm 0:9b334a45a8ff 1365 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
bogdanm 0:9b334a45a8ff 1366 /* RCSR Bit Fields */
bogdanm 0:9b334a45a8ff 1367 #define I2S_RCSR_FWDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 1368 #define I2S_RCSR_FWDE_SHIFT 1
bogdanm 0:9b334a45a8ff 1369 #define I2S_RCSR_FWIE_MASK 0x200u
bogdanm 0:9b334a45a8ff 1370 #define I2S_RCSR_FWIE_SHIFT 9
bogdanm 0:9b334a45a8ff 1371 #define I2S_RCSR_FEIE_MASK 0x400u
bogdanm 0:9b334a45a8ff 1372 #define I2S_RCSR_FEIE_SHIFT 10
bogdanm 0:9b334a45a8ff 1373 #define I2S_RCSR_SEIE_MASK 0x800u
bogdanm 0:9b334a45a8ff 1374 #define I2S_RCSR_SEIE_SHIFT 11
bogdanm 0:9b334a45a8ff 1375 #define I2S_RCSR_WSIE_MASK 0x1000u
bogdanm 0:9b334a45a8ff 1376 #define I2S_RCSR_WSIE_SHIFT 12
bogdanm 0:9b334a45a8ff 1377 #define I2S_RCSR_FWF_MASK 0x20000u
bogdanm 0:9b334a45a8ff 1378 #define I2S_RCSR_FWF_SHIFT 17
bogdanm 0:9b334a45a8ff 1379 #define I2S_RCSR_FEF_MASK 0x40000u
bogdanm 0:9b334a45a8ff 1380 #define I2S_RCSR_FEF_SHIFT 18
bogdanm 0:9b334a45a8ff 1381 #define I2S_RCSR_SEF_MASK 0x80000u
bogdanm 0:9b334a45a8ff 1382 #define I2S_RCSR_SEF_SHIFT 19
bogdanm 0:9b334a45a8ff 1383 #define I2S_RCSR_WSF_MASK 0x100000u
bogdanm 0:9b334a45a8ff 1384 #define I2S_RCSR_WSF_SHIFT 20
bogdanm 0:9b334a45a8ff 1385 #define I2S_RCSR_SR_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1386 #define I2S_RCSR_SR_SHIFT 24
bogdanm 0:9b334a45a8ff 1387 #define I2S_RCSR_FR_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1388 #define I2S_RCSR_FR_SHIFT 25
bogdanm 0:9b334a45a8ff 1389 #define I2S_RCSR_BCE_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 1390 #define I2S_RCSR_BCE_SHIFT 28
bogdanm 0:9b334a45a8ff 1391 #define I2S_RCSR_DBGE_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 1392 #define I2S_RCSR_DBGE_SHIFT 29
bogdanm 0:9b334a45a8ff 1393 #define I2S_RCSR_STOPE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 1394 #define I2S_RCSR_STOPE_SHIFT 30
bogdanm 0:9b334a45a8ff 1395 #define I2S_RCSR_RE_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1396 #define I2S_RCSR_RE_SHIFT 31
bogdanm 0:9b334a45a8ff 1397 /* RCR2 Bit Fields */
bogdanm 0:9b334a45a8ff 1398 #define I2S_RCR2_DIV_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1399 #define I2S_RCR2_DIV_SHIFT 0
bogdanm 0:9b334a45a8ff 1400 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
bogdanm 0:9b334a45a8ff 1401 #define I2S_RCR2_BCD_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1402 #define I2S_RCR2_BCD_SHIFT 24
bogdanm 0:9b334a45a8ff 1403 #define I2S_RCR2_BCP_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1404 #define I2S_RCR2_BCP_SHIFT 25
bogdanm 0:9b334a45a8ff 1405 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
bogdanm 0:9b334a45a8ff 1406 #define I2S_RCR2_CLKMODE_SHIFT 26
bogdanm 0:9b334a45a8ff 1407 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
bogdanm 0:9b334a45a8ff 1408 /* RCR3 Bit Fields */
bogdanm 0:9b334a45a8ff 1409 #define I2S_RCR3_WDFL_MASK 0x1u
bogdanm 0:9b334a45a8ff 1410 #define I2S_RCR3_WDFL_SHIFT 0
bogdanm 0:9b334a45a8ff 1411 #define I2S_RCR3_RCE_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1412 #define I2S_RCR3_RCE_SHIFT 16
bogdanm 0:9b334a45a8ff 1413 /* RCR4 Bit Fields */
bogdanm 0:9b334a45a8ff 1414 #define I2S_RCR4_FSD_MASK 0x1u
bogdanm 0:9b334a45a8ff 1415 #define I2S_RCR4_FSD_SHIFT 0
bogdanm 0:9b334a45a8ff 1416 #define I2S_RCR4_FSP_MASK 0x2u
bogdanm 0:9b334a45a8ff 1417 #define I2S_RCR4_FSP_SHIFT 1
bogdanm 0:9b334a45a8ff 1418 #define I2S_RCR4_FSE_MASK 0x8u
bogdanm 0:9b334a45a8ff 1419 #define I2S_RCR4_FSE_SHIFT 3
bogdanm 0:9b334a45a8ff 1420 #define I2S_RCR4_MF_MASK 0x10u
bogdanm 0:9b334a45a8ff 1421 #define I2S_RCR4_MF_SHIFT 4
bogdanm 0:9b334a45a8ff 1422 #define I2S_RCR4_SYWD_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1423 #define I2S_RCR4_SYWD_SHIFT 8
bogdanm 0:9b334a45a8ff 1424 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
bogdanm 0:9b334a45a8ff 1425 #define I2S_RCR4_FRSZ_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1426 #define I2S_RCR4_FRSZ_SHIFT 16
bogdanm 0:9b334a45a8ff 1427 /* RCR5 Bit Fields */
bogdanm 0:9b334a45a8ff 1428 #define I2S_RCR5_FBT_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1429 #define I2S_RCR5_FBT_SHIFT 8
bogdanm 0:9b334a45a8ff 1430 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
bogdanm 0:9b334a45a8ff 1431 #define I2S_RCR5_W0W_MASK 0x1F0000u
bogdanm 0:9b334a45a8ff 1432 #define I2S_RCR5_W0W_SHIFT 16
bogdanm 0:9b334a45a8ff 1433 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
bogdanm 0:9b334a45a8ff 1434 #define I2S_RCR5_WNW_MASK 0x1F000000u
bogdanm 0:9b334a45a8ff 1435 #define I2S_RCR5_WNW_SHIFT 24
bogdanm 0:9b334a45a8ff 1436 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
bogdanm 0:9b334a45a8ff 1437 /* RDR Bit Fields */
bogdanm 0:9b334a45a8ff 1438 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1439 #define I2S_RDR_RDR_SHIFT 0
bogdanm 0:9b334a45a8ff 1440 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
bogdanm 0:9b334a45a8ff 1441 /* RMR Bit Fields */
bogdanm 0:9b334a45a8ff 1442 #define I2S_RMR_RWM_MASK 0x3u
bogdanm 0:9b334a45a8ff 1443 #define I2S_RMR_RWM_SHIFT 0
bogdanm 0:9b334a45a8ff 1444 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
bogdanm 0:9b334a45a8ff 1445 /* MCR Bit Fields */
bogdanm 0:9b334a45a8ff 1446 #define I2S_MCR_MICS_MASK 0x3000000u
bogdanm 0:9b334a45a8ff 1447 #define I2S_MCR_MICS_SHIFT 24
bogdanm 0:9b334a45a8ff 1448 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
bogdanm 0:9b334a45a8ff 1449 #define I2S_MCR_MOE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 1450 #define I2S_MCR_MOE_SHIFT 30
bogdanm 0:9b334a45a8ff 1451 #define I2S_MCR_DUF_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1452 #define I2S_MCR_DUF_SHIFT 31
bogdanm 0:9b334a45a8ff 1453 /* MDR Bit Fields */
bogdanm 0:9b334a45a8ff 1454 #define I2S_MDR_DIVIDE_MASK 0xFFFu
bogdanm 0:9b334a45a8ff 1455 #define I2S_MDR_DIVIDE_SHIFT 0
bogdanm 0:9b334a45a8ff 1456 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
bogdanm 0:9b334a45a8ff 1457 #define I2S_MDR_FRACT_MASK 0xFF000u
bogdanm 0:9b334a45a8ff 1458 #define I2S_MDR_FRACT_SHIFT 12
bogdanm 0:9b334a45a8ff 1459 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
bogdanm 0:9b334a45a8ff 1460
bogdanm 0:9b334a45a8ff 1461 /**
bogdanm 0:9b334a45a8ff 1462 * @}
bogdanm 0:9b334a45a8ff 1463 */ /* end of group I2S_Register_Masks */
bogdanm 0:9b334a45a8ff 1464
bogdanm 0:9b334a45a8ff 1465
bogdanm 0:9b334a45a8ff 1466 /* I2S - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1467 /** Peripheral I2S0 base address */
bogdanm 0:9b334a45a8ff 1468 #define I2S0_BASE (0x4002F000u)
bogdanm 0:9b334a45a8ff 1469 /** Peripheral I2S0 base pointer */
bogdanm 0:9b334a45a8ff 1470 #define I2S0 ((I2S_Type *)I2S0_BASE)
bogdanm 0:9b334a45a8ff 1471 /** Array initializer of I2S peripheral base pointers */
bogdanm 0:9b334a45a8ff 1472 #define I2S_BASES { I2S0 }
bogdanm 0:9b334a45a8ff 1473
bogdanm 0:9b334a45a8ff 1474 /**
bogdanm 0:9b334a45a8ff 1475 * @}
bogdanm 0:9b334a45a8ff 1476 */ /* end of group I2S_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1477
bogdanm 0:9b334a45a8ff 1478
bogdanm 0:9b334a45a8ff 1479 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1480 -- LLWU Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1481 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1482
bogdanm 0:9b334a45a8ff 1483 /**
bogdanm 0:9b334a45a8ff 1484 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1485 * @{
bogdanm 0:9b334a45a8ff 1486 */
bogdanm 0:9b334a45a8ff 1487
bogdanm 0:9b334a45a8ff 1488 /** LLWU - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1489 typedef struct {
bogdanm 0:9b334a45a8ff 1490 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1491 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 1492 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 1493 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 1494 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1495 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 1496 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
bogdanm 0:9b334a45a8ff 1497 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 1498 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1499 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
bogdanm 0:9b334a45a8ff 1500 } LLWU_Type;
bogdanm 0:9b334a45a8ff 1501
bogdanm 0:9b334a45a8ff 1502 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1503 -- LLWU Register Masks
bogdanm 0:9b334a45a8ff 1504 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1505
bogdanm 0:9b334a45a8ff 1506 /**
bogdanm 0:9b334a45a8ff 1507 * @addtogroup LLWU_Register_Masks LLWU Register Masks
bogdanm 0:9b334a45a8ff 1508 * @{
bogdanm 0:9b334a45a8ff 1509 */
bogdanm 0:9b334a45a8ff 1510
bogdanm 0:9b334a45a8ff 1511 /* PE1 Bit Fields */
bogdanm 0:9b334a45a8ff 1512 #define LLWU_PE1_WUPE0_MASK 0x3u
bogdanm 0:9b334a45a8ff 1513 #define LLWU_PE1_WUPE0_SHIFT 0
bogdanm 0:9b334a45a8ff 1514 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
bogdanm 0:9b334a45a8ff 1515 #define LLWU_PE1_WUPE1_MASK 0xCu
bogdanm 0:9b334a45a8ff 1516 #define LLWU_PE1_WUPE1_SHIFT 2
bogdanm 0:9b334a45a8ff 1517 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
bogdanm 0:9b334a45a8ff 1518 #define LLWU_PE1_WUPE2_MASK 0x30u
bogdanm 0:9b334a45a8ff 1519 #define LLWU_PE1_WUPE2_SHIFT 4
bogdanm 0:9b334a45a8ff 1520 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
bogdanm 0:9b334a45a8ff 1521 #define LLWU_PE1_WUPE3_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1522 #define LLWU_PE1_WUPE3_SHIFT 6
bogdanm 0:9b334a45a8ff 1523 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
bogdanm 0:9b334a45a8ff 1524 /* PE2 Bit Fields */
bogdanm 0:9b334a45a8ff 1525 #define LLWU_PE2_WUPE4_MASK 0x3u
bogdanm 0:9b334a45a8ff 1526 #define LLWU_PE2_WUPE4_SHIFT 0
bogdanm 0:9b334a45a8ff 1527 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
bogdanm 0:9b334a45a8ff 1528 #define LLWU_PE2_WUPE5_MASK 0xCu
bogdanm 0:9b334a45a8ff 1529 #define LLWU_PE2_WUPE5_SHIFT 2
bogdanm 0:9b334a45a8ff 1530 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
bogdanm 0:9b334a45a8ff 1531 #define LLWU_PE2_WUPE6_MASK 0x30u
bogdanm 0:9b334a45a8ff 1532 #define LLWU_PE2_WUPE6_SHIFT 4
bogdanm 0:9b334a45a8ff 1533 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
bogdanm 0:9b334a45a8ff 1534 #define LLWU_PE2_WUPE7_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1535 #define LLWU_PE2_WUPE7_SHIFT 6
bogdanm 0:9b334a45a8ff 1536 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
bogdanm 0:9b334a45a8ff 1537 /* PE3 Bit Fields */
bogdanm 0:9b334a45a8ff 1538 #define LLWU_PE3_WUPE8_MASK 0x3u
bogdanm 0:9b334a45a8ff 1539 #define LLWU_PE3_WUPE8_SHIFT 0
bogdanm 0:9b334a45a8ff 1540 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
bogdanm 0:9b334a45a8ff 1541 #define LLWU_PE3_WUPE9_MASK 0xCu
bogdanm 0:9b334a45a8ff 1542 #define LLWU_PE3_WUPE9_SHIFT 2
bogdanm 0:9b334a45a8ff 1543 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
bogdanm 0:9b334a45a8ff 1544 #define LLWU_PE3_WUPE10_MASK 0x30u
bogdanm 0:9b334a45a8ff 1545 #define LLWU_PE3_WUPE10_SHIFT 4
bogdanm 0:9b334a45a8ff 1546 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
bogdanm 0:9b334a45a8ff 1547 #define LLWU_PE3_WUPE11_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1548 #define LLWU_PE3_WUPE11_SHIFT 6
bogdanm 0:9b334a45a8ff 1549 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
bogdanm 0:9b334a45a8ff 1550 /* PE4 Bit Fields */
bogdanm 0:9b334a45a8ff 1551 #define LLWU_PE4_WUPE12_MASK 0x3u
bogdanm 0:9b334a45a8ff 1552 #define LLWU_PE4_WUPE12_SHIFT 0
bogdanm 0:9b334a45a8ff 1553 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
bogdanm 0:9b334a45a8ff 1554 #define LLWU_PE4_WUPE13_MASK 0xCu
bogdanm 0:9b334a45a8ff 1555 #define LLWU_PE4_WUPE13_SHIFT 2
bogdanm 0:9b334a45a8ff 1556 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
bogdanm 0:9b334a45a8ff 1557 #define LLWU_PE4_WUPE14_MASK 0x30u
bogdanm 0:9b334a45a8ff 1558 #define LLWU_PE4_WUPE14_SHIFT 4
bogdanm 0:9b334a45a8ff 1559 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
bogdanm 0:9b334a45a8ff 1560 #define LLWU_PE4_WUPE15_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1561 #define LLWU_PE4_WUPE15_SHIFT 6
bogdanm 0:9b334a45a8ff 1562 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
bogdanm 0:9b334a45a8ff 1563 /* ME Bit Fields */
bogdanm 0:9b334a45a8ff 1564 #define LLWU_ME_WUME0_MASK 0x1u
bogdanm 0:9b334a45a8ff 1565 #define LLWU_ME_WUME0_SHIFT 0
bogdanm 0:9b334a45a8ff 1566 #define LLWU_ME_WUME1_MASK 0x2u
bogdanm 0:9b334a45a8ff 1567 #define LLWU_ME_WUME1_SHIFT 1
bogdanm 0:9b334a45a8ff 1568 #define LLWU_ME_WUME2_MASK 0x4u
bogdanm 0:9b334a45a8ff 1569 #define LLWU_ME_WUME2_SHIFT 2
bogdanm 0:9b334a45a8ff 1570 #define LLWU_ME_WUME3_MASK 0x8u
bogdanm 0:9b334a45a8ff 1571 #define LLWU_ME_WUME3_SHIFT 3
bogdanm 0:9b334a45a8ff 1572 #define LLWU_ME_WUME4_MASK 0x10u
bogdanm 0:9b334a45a8ff 1573 #define LLWU_ME_WUME4_SHIFT 4
bogdanm 0:9b334a45a8ff 1574 #define LLWU_ME_WUME5_MASK 0x20u
bogdanm 0:9b334a45a8ff 1575 #define LLWU_ME_WUME5_SHIFT 5
bogdanm 0:9b334a45a8ff 1576 #define LLWU_ME_WUME6_MASK 0x40u
bogdanm 0:9b334a45a8ff 1577 #define LLWU_ME_WUME6_SHIFT 6
bogdanm 0:9b334a45a8ff 1578 #define LLWU_ME_WUME7_MASK 0x80u
bogdanm 0:9b334a45a8ff 1579 #define LLWU_ME_WUME7_SHIFT 7
bogdanm 0:9b334a45a8ff 1580 /* F1 Bit Fields */
bogdanm 0:9b334a45a8ff 1581 #define LLWU_F1_WUF0_MASK 0x1u
bogdanm 0:9b334a45a8ff 1582 #define LLWU_F1_WUF0_SHIFT 0
bogdanm 0:9b334a45a8ff 1583 #define LLWU_F1_WUF1_MASK 0x2u
bogdanm 0:9b334a45a8ff 1584 #define LLWU_F1_WUF1_SHIFT 1
bogdanm 0:9b334a45a8ff 1585 #define LLWU_F1_WUF2_MASK 0x4u
bogdanm 0:9b334a45a8ff 1586 #define LLWU_F1_WUF2_SHIFT 2
bogdanm 0:9b334a45a8ff 1587 #define LLWU_F1_WUF3_MASK 0x8u
bogdanm 0:9b334a45a8ff 1588 #define LLWU_F1_WUF3_SHIFT 3
bogdanm 0:9b334a45a8ff 1589 #define LLWU_F1_WUF4_MASK 0x10u
bogdanm 0:9b334a45a8ff 1590 #define LLWU_F1_WUF4_SHIFT 4
bogdanm 0:9b334a45a8ff 1591 #define LLWU_F1_WUF5_MASK 0x20u
bogdanm 0:9b334a45a8ff 1592 #define LLWU_F1_WUF5_SHIFT 5
bogdanm 0:9b334a45a8ff 1593 #define LLWU_F1_WUF6_MASK 0x40u
bogdanm 0:9b334a45a8ff 1594 #define LLWU_F1_WUF6_SHIFT 6
bogdanm 0:9b334a45a8ff 1595 #define LLWU_F1_WUF7_MASK 0x80u
bogdanm 0:9b334a45a8ff 1596 #define LLWU_F1_WUF7_SHIFT 7
bogdanm 0:9b334a45a8ff 1597 /* F2 Bit Fields */
bogdanm 0:9b334a45a8ff 1598 #define LLWU_F2_WUF8_MASK 0x1u
bogdanm 0:9b334a45a8ff 1599 #define LLWU_F2_WUF8_SHIFT 0
bogdanm 0:9b334a45a8ff 1600 #define LLWU_F2_WUF9_MASK 0x2u
bogdanm 0:9b334a45a8ff 1601 #define LLWU_F2_WUF9_SHIFT 1
bogdanm 0:9b334a45a8ff 1602 #define LLWU_F2_WUF10_MASK 0x4u
bogdanm 0:9b334a45a8ff 1603 #define LLWU_F2_WUF10_SHIFT 2
bogdanm 0:9b334a45a8ff 1604 #define LLWU_F2_WUF11_MASK 0x8u
bogdanm 0:9b334a45a8ff 1605 #define LLWU_F2_WUF11_SHIFT 3
bogdanm 0:9b334a45a8ff 1606 #define LLWU_F2_WUF12_MASK 0x10u
bogdanm 0:9b334a45a8ff 1607 #define LLWU_F2_WUF12_SHIFT 4
bogdanm 0:9b334a45a8ff 1608 #define LLWU_F2_WUF13_MASK 0x20u
bogdanm 0:9b334a45a8ff 1609 #define LLWU_F2_WUF13_SHIFT 5
bogdanm 0:9b334a45a8ff 1610 #define LLWU_F2_WUF14_MASK 0x40u
bogdanm 0:9b334a45a8ff 1611 #define LLWU_F2_WUF14_SHIFT 6
bogdanm 0:9b334a45a8ff 1612 #define LLWU_F2_WUF15_MASK 0x80u
bogdanm 0:9b334a45a8ff 1613 #define LLWU_F2_WUF15_SHIFT 7
bogdanm 0:9b334a45a8ff 1614 /* F3 Bit Fields */
bogdanm 0:9b334a45a8ff 1615 #define LLWU_F3_MWUF0_MASK 0x1u
bogdanm 0:9b334a45a8ff 1616 #define LLWU_F3_MWUF0_SHIFT 0
bogdanm 0:9b334a45a8ff 1617 #define LLWU_F3_MWUF1_MASK 0x2u
bogdanm 0:9b334a45a8ff 1618 #define LLWU_F3_MWUF1_SHIFT 1
bogdanm 0:9b334a45a8ff 1619 #define LLWU_F3_MWUF2_MASK 0x4u
bogdanm 0:9b334a45a8ff 1620 #define LLWU_F3_MWUF2_SHIFT 2
bogdanm 0:9b334a45a8ff 1621 #define LLWU_F3_MWUF3_MASK 0x8u
bogdanm 0:9b334a45a8ff 1622 #define LLWU_F3_MWUF3_SHIFT 3
bogdanm 0:9b334a45a8ff 1623 #define LLWU_F3_MWUF4_MASK 0x10u
bogdanm 0:9b334a45a8ff 1624 #define LLWU_F3_MWUF4_SHIFT 4
bogdanm 0:9b334a45a8ff 1625 #define LLWU_F3_MWUF5_MASK 0x20u
bogdanm 0:9b334a45a8ff 1626 #define LLWU_F3_MWUF5_SHIFT 5
bogdanm 0:9b334a45a8ff 1627 #define LLWU_F3_MWUF6_MASK 0x40u
bogdanm 0:9b334a45a8ff 1628 #define LLWU_F3_MWUF6_SHIFT 6
bogdanm 0:9b334a45a8ff 1629 #define LLWU_F3_MWUF7_MASK 0x80u
bogdanm 0:9b334a45a8ff 1630 #define LLWU_F3_MWUF7_SHIFT 7
bogdanm 0:9b334a45a8ff 1631 /* FILT1 Bit Fields */
bogdanm 0:9b334a45a8ff 1632 #define LLWU_FILT1_FILTSEL_MASK 0xFu
bogdanm 0:9b334a45a8ff 1633 #define LLWU_FILT1_FILTSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 1634 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
bogdanm 0:9b334a45a8ff 1635 #define LLWU_FILT1_FILTE_MASK 0x60u
bogdanm 0:9b334a45a8ff 1636 #define LLWU_FILT1_FILTE_SHIFT 5
bogdanm 0:9b334a45a8ff 1637 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
bogdanm 0:9b334a45a8ff 1638 #define LLWU_FILT1_FILTF_MASK 0x80u
bogdanm 0:9b334a45a8ff 1639 #define LLWU_FILT1_FILTF_SHIFT 7
bogdanm 0:9b334a45a8ff 1640 /* FILT2 Bit Fields */
bogdanm 0:9b334a45a8ff 1641 #define LLWU_FILT2_FILTSEL_MASK 0xFu
bogdanm 0:9b334a45a8ff 1642 #define LLWU_FILT2_FILTSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 1643 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
bogdanm 0:9b334a45a8ff 1644 #define LLWU_FILT2_FILTE_MASK 0x60u
bogdanm 0:9b334a45a8ff 1645 #define LLWU_FILT2_FILTE_SHIFT 5
bogdanm 0:9b334a45a8ff 1646 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
bogdanm 0:9b334a45a8ff 1647 #define LLWU_FILT2_FILTF_MASK 0x80u
bogdanm 0:9b334a45a8ff 1648 #define LLWU_FILT2_FILTF_SHIFT 7
bogdanm 0:9b334a45a8ff 1649
bogdanm 0:9b334a45a8ff 1650 /**
bogdanm 0:9b334a45a8ff 1651 * @}
bogdanm 0:9b334a45a8ff 1652 */ /* end of group LLWU_Register_Masks */
bogdanm 0:9b334a45a8ff 1653
bogdanm 0:9b334a45a8ff 1654
bogdanm 0:9b334a45a8ff 1655 /* LLWU - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1656 /** Peripheral LLWU base address */
bogdanm 0:9b334a45a8ff 1657 #define LLWU_BASE (0x4007C000u)
bogdanm 0:9b334a45a8ff 1658 /** Peripheral LLWU base pointer */
bogdanm 0:9b334a45a8ff 1659 #define LLWU ((LLWU_Type *)LLWU_BASE)
bogdanm 0:9b334a45a8ff 1660 /** Array initializer of LLWU peripheral base pointers */
bogdanm 0:9b334a45a8ff 1661 #define LLWU_BASES { LLWU }
bogdanm 0:9b334a45a8ff 1662
bogdanm 0:9b334a45a8ff 1663 /**
bogdanm 0:9b334a45a8ff 1664 * @}
bogdanm 0:9b334a45a8ff 1665 */ /* end of group LLWU_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1666
bogdanm 0:9b334a45a8ff 1667
bogdanm 0:9b334a45a8ff 1668 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1669 -- LPTMR Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1670 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1671
bogdanm 0:9b334a45a8ff 1672 /**
bogdanm 0:9b334a45a8ff 1673 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1674 * @{
bogdanm 0:9b334a45a8ff 1675 */
bogdanm 0:9b334a45a8ff 1676
bogdanm 0:9b334a45a8ff 1677 /** LPTMR - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1678 typedef struct {
bogdanm 0:9b334a45a8ff 1679 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1680 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1681 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1682 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1683 } LPTMR_Type;
bogdanm 0:9b334a45a8ff 1684
bogdanm 0:9b334a45a8ff 1685 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1686 -- LPTMR Register Masks
bogdanm 0:9b334a45a8ff 1687 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1688
bogdanm 0:9b334a45a8ff 1689 /**
bogdanm 0:9b334a45a8ff 1690 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
bogdanm 0:9b334a45a8ff 1691 * @{
bogdanm 0:9b334a45a8ff 1692 */
bogdanm 0:9b334a45a8ff 1693
bogdanm 0:9b334a45a8ff 1694 /* CSR Bit Fields */
bogdanm 0:9b334a45a8ff 1695 #define LPTMR_CSR_TEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 1696 #define LPTMR_CSR_TEN_SHIFT 0
bogdanm 0:9b334a45a8ff 1697 #define LPTMR_CSR_TMS_MASK 0x2u
bogdanm 0:9b334a45a8ff 1698 #define LPTMR_CSR_TMS_SHIFT 1
bogdanm 0:9b334a45a8ff 1699 #define LPTMR_CSR_TFC_MASK 0x4u
bogdanm 0:9b334a45a8ff 1700 #define LPTMR_CSR_TFC_SHIFT 2
bogdanm 0:9b334a45a8ff 1701 #define LPTMR_CSR_TPP_MASK 0x8u
bogdanm 0:9b334a45a8ff 1702 #define LPTMR_CSR_TPP_SHIFT 3
bogdanm 0:9b334a45a8ff 1703 #define LPTMR_CSR_TPS_MASK 0x30u
bogdanm 0:9b334a45a8ff 1704 #define LPTMR_CSR_TPS_SHIFT 4
bogdanm 0:9b334a45a8ff 1705 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
bogdanm 0:9b334a45a8ff 1706 #define LPTMR_CSR_TIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 1707 #define LPTMR_CSR_TIE_SHIFT 6
bogdanm 0:9b334a45a8ff 1708 #define LPTMR_CSR_TCF_MASK 0x80u
bogdanm 0:9b334a45a8ff 1709 #define LPTMR_CSR_TCF_SHIFT 7
bogdanm 0:9b334a45a8ff 1710 /* PSR Bit Fields */
bogdanm 0:9b334a45a8ff 1711 #define LPTMR_PSR_PCS_MASK 0x3u
bogdanm 0:9b334a45a8ff 1712 #define LPTMR_PSR_PCS_SHIFT 0
bogdanm 0:9b334a45a8ff 1713 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
bogdanm 0:9b334a45a8ff 1714 #define LPTMR_PSR_PBYP_MASK 0x4u
bogdanm 0:9b334a45a8ff 1715 #define LPTMR_PSR_PBYP_SHIFT 2
bogdanm 0:9b334a45a8ff 1716 #define LPTMR_PSR_PRESCALE_MASK 0x78u
bogdanm 0:9b334a45a8ff 1717 #define LPTMR_PSR_PRESCALE_SHIFT 3
bogdanm 0:9b334a45a8ff 1718 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
bogdanm 0:9b334a45a8ff 1719 /* CMR Bit Fields */
bogdanm 0:9b334a45a8ff 1720 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 1721 #define LPTMR_CMR_COMPARE_SHIFT 0
bogdanm 0:9b334a45a8ff 1722 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
bogdanm 0:9b334a45a8ff 1723 /* CNR Bit Fields */
bogdanm 0:9b334a45a8ff 1724 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 1725 #define LPTMR_CNR_COUNTER_SHIFT 0
bogdanm 0:9b334a45a8ff 1726 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
bogdanm 0:9b334a45a8ff 1727
bogdanm 0:9b334a45a8ff 1728 /**
bogdanm 0:9b334a45a8ff 1729 * @}
bogdanm 0:9b334a45a8ff 1730 */ /* end of group LPTMR_Register_Masks */
bogdanm 0:9b334a45a8ff 1731
bogdanm 0:9b334a45a8ff 1732
bogdanm 0:9b334a45a8ff 1733 /* LPTMR - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1734 /** Peripheral LPTMR0 base address */
bogdanm 0:9b334a45a8ff 1735 #define LPTMR0_BASE (0x40040000u)
bogdanm 0:9b334a45a8ff 1736 /** Peripheral LPTMR0 base pointer */
bogdanm 0:9b334a45a8ff 1737 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
bogdanm 0:9b334a45a8ff 1738 /** Array initializer of LPTMR peripheral base pointers */
bogdanm 0:9b334a45a8ff 1739 #define LPTMR_BASES { LPTMR0 }
bogdanm 0:9b334a45a8ff 1740
bogdanm 0:9b334a45a8ff 1741 /**
bogdanm 0:9b334a45a8ff 1742 * @}
bogdanm 0:9b334a45a8ff 1743 */ /* end of group LPTMR_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1744
bogdanm 0:9b334a45a8ff 1745
bogdanm 0:9b334a45a8ff 1746 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1747 -- MCG Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1748 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1749
bogdanm 0:9b334a45a8ff 1750 /**
bogdanm 0:9b334a45a8ff 1751 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1752 * @{
bogdanm 0:9b334a45a8ff 1753 */
bogdanm 0:9b334a45a8ff 1754
bogdanm 0:9b334a45a8ff 1755 /** MCG - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1756 typedef struct {
bogdanm 0:9b334a45a8ff 1757 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1758 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 1759 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 1760 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 1761 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1762 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 1763 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
bogdanm 0:9b334a45a8ff 1764 uint8_t RESERVED_0[1];
bogdanm 0:9b334a45a8ff 1765 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1766 uint8_t RESERVED_1[1];
bogdanm 0:9b334a45a8ff 1767 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
bogdanm 0:9b334a45a8ff 1768 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
bogdanm 0:9b334a45a8ff 1769 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1770 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
bogdanm 0:9b334a45a8ff 1771 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
bogdanm 0:9b334a45a8ff 1772 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
bogdanm 0:9b334a45a8ff 1773 } MCG_Type;
bogdanm 0:9b334a45a8ff 1774
bogdanm 0:9b334a45a8ff 1775 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1776 -- MCG Register Masks
bogdanm 0:9b334a45a8ff 1777 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1778
bogdanm 0:9b334a45a8ff 1779 /**
bogdanm 0:9b334a45a8ff 1780 * @addtogroup MCG_Register_Masks MCG Register Masks
bogdanm 0:9b334a45a8ff 1781 * @{
bogdanm 0:9b334a45a8ff 1782 */
bogdanm 0:9b334a45a8ff 1783
bogdanm 0:9b334a45a8ff 1784 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 1785 #define MCG_C1_IREFSTEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 1786 #define MCG_C1_IREFSTEN_SHIFT 0
bogdanm 0:9b334a45a8ff 1787 #define MCG_C1_IRCLKEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 1788 #define MCG_C1_IRCLKEN_SHIFT 1
bogdanm 0:9b334a45a8ff 1789 #define MCG_C1_IREFS_MASK 0x4u
bogdanm 0:9b334a45a8ff 1790 #define MCG_C1_IREFS_SHIFT 2
bogdanm 0:9b334a45a8ff 1791 #define MCG_C1_FRDIV_MASK 0x38u
bogdanm 0:9b334a45a8ff 1792 #define MCG_C1_FRDIV_SHIFT 3
bogdanm 0:9b334a45a8ff 1793 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
bogdanm 0:9b334a45a8ff 1794 #define MCG_C1_CLKS_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1795 #define MCG_C1_CLKS_SHIFT 6
bogdanm 0:9b334a45a8ff 1796 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
bogdanm 0:9b334a45a8ff 1797 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 1798 #define MCG_C2_IRCS_MASK 0x1u
bogdanm 0:9b334a45a8ff 1799 #define MCG_C2_IRCS_SHIFT 0
bogdanm 0:9b334a45a8ff 1800 #define MCG_C2_LP_MASK 0x2u
bogdanm 0:9b334a45a8ff 1801 #define MCG_C2_LP_SHIFT 1
bogdanm 0:9b334a45a8ff 1802 #define MCG_C2_EREFS0_MASK 0x4u
bogdanm 0:9b334a45a8ff 1803 #define MCG_C2_EREFS0_SHIFT 2
bogdanm 0:9b334a45a8ff 1804 #define MCG_C2_HGO0_MASK 0x8u
bogdanm 0:9b334a45a8ff 1805 #define MCG_C2_HGO0_SHIFT 3
bogdanm 0:9b334a45a8ff 1806 #define MCG_C2_RANGE0_MASK 0x30u
bogdanm 0:9b334a45a8ff 1807 #define MCG_C2_RANGE0_SHIFT 4
bogdanm 0:9b334a45a8ff 1808 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
bogdanm 0:9b334a45a8ff 1809 #define MCG_C2_FCFTRIM_MASK 0x40u
bogdanm 0:9b334a45a8ff 1810 #define MCG_C2_FCFTRIM_SHIFT 6
bogdanm 0:9b334a45a8ff 1811 #define MCG_C2_LOCRE0_MASK 0x80u
bogdanm 0:9b334a45a8ff 1812 #define MCG_C2_LOCRE0_SHIFT 7
bogdanm 0:9b334a45a8ff 1813 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 1814 #define MCG_C3_SCTRIM_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1815 #define MCG_C3_SCTRIM_SHIFT 0
bogdanm 0:9b334a45a8ff 1816 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
bogdanm 0:9b334a45a8ff 1817 /* C4 Bit Fields */
bogdanm 0:9b334a45a8ff 1818 #define MCG_C4_SCFTRIM_MASK 0x1u
bogdanm 0:9b334a45a8ff 1819 #define MCG_C4_SCFTRIM_SHIFT 0
bogdanm 0:9b334a45a8ff 1820 #define MCG_C4_FCTRIM_MASK 0x1Eu
bogdanm 0:9b334a45a8ff 1821 #define MCG_C4_FCTRIM_SHIFT 1
bogdanm 0:9b334a45a8ff 1822 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
bogdanm 0:9b334a45a8ff 1823 #define MCG_C4_DRST_DRS_MASK 0x60u
bogdanm 0:9b334a45a8ff 1824 #define MCG_C4_DRST_DRS_SHIFT 5
bogdanm 0:9b334a45a8ff 1825 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
bogdanm 0:9b334a45a8ff 1826 #define MCG_C4_DMX32_MASK 0x80u
bogdanm 0:9b334a45a8ff 1827 #define MCG_C4_DMX32_SHIFT 7
bogdanm 0:9b334a45a8ff 1828 /* C5 Bit Fields */
bogdanm 0:9b334a45a8ff 1829 #define MCG_C5_PRDIV0_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 1830 #define MCG_C5_PRDIV0_SHIFT 0
bogdanm 0:9b334a45a8ff 1831 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
bogdanm 0:9b334a45a8ff 1832 #define MCG_C5_PLLSTEN0_MASK 0x20u
bogdanm 0:9b334a45a8ff 1833 #define MCG_C5_PLLSTEN0_SHIFT 5
bogdanm 0:9b334a45a8ff 1834 #define MCG_C5_PLLCLKEN0_MASK 0x40u
bogdanm 0:9b334a45a8ff 1835 #define MCG_C5_PLLCLKEN0_SHIFT 6
bogdanm 0:9b334a45a8ff 1836 /* C6 Bit Fields */
bogdanm 0:9b334a45a8ff 1837 #define MCG_C6_VDIV0_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 1838 #define MCG_C6_VDIV0_SHIFT 0
bogdanm 0:9b334a45a8ff 1839 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
bogdanm 0:9b334a45a8ff 1840 #define MCG_C6_CME0_MASK 0x20u
bogdanm 0:9b334a45a8ff 1841 #define MCG_C6_CME0_SHIFT 5
bogdanm 0:9b334a45a8ff 1842 #define MCG_C6_PLLS_MASK 0x40u
bogdanm 0:9b334a45a8ff 1843 #define MCG_C6_PLLS_SHIFT 6
bogdanm 0:9b334a45a8ff 1844 #define MCG_C6_LOLIE0_MASK 0x80u
bogdanm 0:9b334a45a8ff 1845 #define MCG_C6_LOLIE0_SHIFT 7
bogdanm 0:9b334a45a8ff 1846 /* S Bit Fields */
bogdanm 0:9b334a45a8ff 1847 #define MCG_S_IRCST_MASK 0x1u
bogdanm 0:9b334a45a8ff 1848 #define MCG_S_IRCST_SHIFT 0
bogdanm 0:9b334a45a8ff 1849 #define MCG_S_OSCINIT0_MASK 0x2u
bogdanm 0:9b334a45a8ff 1850 #define MCG_S_OSCINIT0_SHIFT 1
bogdanm 0:9b334a45a8ff 1851 #define MCG_S_CLKST_MASK 0xCu
bogdanm 0:9b334a45a8ff 1852 #define MCG_S_CLKST_SHIFT 2
bogdanm 0:9b334a45a8ff 1853 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
bogdanm 0:9b334a45a8ff 1854 #define MCG_S_IREFST_MASK 0x10u
bogdanm 0:9b334a45a8ff 1855 #define MCG_S_IREFST_SHIFT 4
bogdanm 0:9b334a45a8ff 1856 #define MCG_S_PLLST_MASK 0x20u
bogdanm 0:9b334a45a8ff 1857 #define MCG_S_PLLST_SHIFT 5
bogdanm 0:9b334a45a8ff 1858 #define MCG_S_LOCK0_MASK 0x40u
bogdanm 0:9b334a45a8ff 1859 #define MCG_S_LOCK0_SHIFT 6
bogdanm 0:9b334a45a8ff 1860 #define MCG_S_LOLS_MASK 0x80u
bogdanm 0:9b334a45a8ff 1861 #define MCG_S_LOLS_SHIFT 7
bogdanm 0:9b334a45a8ff 1862 /* SC Bit Fields */
bogdanm 0:9b334a45a8ff 1863 #define MCG_SC_LOCS0_MASK 0x1u
bogdanm 0:9b334a45a8ff 1864 #define MCG_SC_LOCS0_SHIFT 0
bogdanm 0:9b334a45a8ff 1865 #define MCG_SC_FCRDIV_MASK 0xEu
bogdanm 0:9b334a45a8ff 1866 #define MCG_SC_FCRDIV_SHIFT 1
bogdanm 0:9b334a45a8ff 1867 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
bogdanm 0:9b334a45a8ff 1868 #define MCG_SC_FLTPRSRV_MASK 0x10u
bogdanm 0:9b334a45a8ff 1869 #define MCG_SC_FLTPRSRV_SHIFT 4
bogdanm 0:9b334a45a8ff 1870 #define MCG_SC_ATMF_MASK 0x20u
bogdanm 0:9b334a45a8ff 1871 #define MCG_SC_ATMF_SHIFT 5
bogdanm 0:9b334a45a8ff 1872 #define MCG_SC_ATMS_MASK 0x40u
bogdanm 0:9b334a45a8ff 1873 #define MCG_SC_ATMS_SHIFT 6
bogdanm 0:9b334a45a8ff 1874 #define MCG_SC_ATME_MASK 0x80u
bogdanm 0:9b334a45a8ff 1875 #define MCG_SC_ATME_SHIFT 7
bogdanm 0:9b334a45a8ff 1876 /* ATCVH Bit Fields */
bogdanm 0:9b334a45a8ff 1877 #define MCG_ATCVH_ATCVH_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1878 #define MCG_ATCVH_ATCVH_SHIFT 0
bogdanm 0:9b334a45a8ff 1879 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
bogdanm 0:9b334a45a8ff 1880 /* ATCVL Bit Fields */
bogdanm 0:9b334a45a8ff 1881 #define MCG_ATCVL_ATCVL_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1882 #define MCG_ATCVL_ATCVL_SHIFT 0
bogdanm 0:9b334a45a8ff 1883 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
bogdanm 0:9b334a45a8ff 1884 /* C8 Bit Fields */
bogdanm 0:9b334a45a8ff 1885 #define MCG_C8_LOLRE_MASK 0x40u
bogdanm 0:9b334a45a8ff 1886 #define MCG_C8_LOLRE_SHIFT 6
bogdanm 0:9b334a45a8ff 1887
bogdanm 0:9b334a45a8ff 1888 /**
bogdanm 0:9b334a45a8ff 1889 * @}
bogdanm 0:9b334a45a8ff 1890 */ /* end of group MCG_Register_Masks */
bogdanm 0:9b334a45a8ff 1891
bogdanm 0:9b334a45a8ff 1892
bogdanm 0:9b334a45a8ff 1893 /* MCG - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1894 /** Peripheral MCG base address */
bogdanm 0:9b334a45a8ff 1895 #define MCG_BASE (0x40064000u)
bogdanm 0:9b334a45a8ff 1896 /** Peripheral MCG base pointer */
bogdanm 0:9b334a45a8ff 1897 #define MCG ((MCG_Type *)MCG_BASE)
bogdanm 0:9b334a45a8ff 1898 /** Array initializer of MCG peripheral base pointers */
bogdanm 0:9b334a45a8ff 1899 #define MCG_BASES { MCG }
bogdanm 0:9b334a45a8ff 1900
bogdanm 0:9b334a45a8ff 1901 /**
bogdanm 0:9b334a45a8ff 1902 * @}
bogdanm 0:9b334a45a8ff 1903 */ /* end of group MCG_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1904
bogdanm 0:9b334a45a8ff 1905
bogdanm 0:9b334a45a8ff 1906 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1907 -- MCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1908 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1909
bogdanm 0:9b334a45a8ff 1910 /**
bogdanm 0:9b334a45a8ff 1911 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1912 * @{
bogdanm 0:9b334a45a8ff 1913 */
bogdanm 0:9b334a45a8ff 1914
bogdanm 0:9b334a45a8ff 1915 /** MCM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1916 typedef struct {
bogdanm 0:9b334a45a8ff 1917 uint8_t RESERVED_0[8];
bogdanm 0:9b334a45a8ff 1918 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1919 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
bogdanm 0:9b334a45a8ff 1920 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1921 uint8_t RESERVED_1[48];
bogdanm 0:9b334a45a8ff 1922 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
bogdanm 0:9b334a45a8ff 1923 } MCM_Type;
bogdanm 0:9b334a45a8ff 1924
bogdanm 0:9b334a45a8ff 1925 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1926 -- MCM Register Masks
bogdanm 0:9b334a45a8ff 1927 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1928
bogdanm 0:9b334a45a8ff 1929 /**
bogdanm 0:9b334a45a8ff 1930 * @addtogroup MCM_Register_Masks MCM Register Masks
bogdanm 0:9b334a45a8ff 1931 * @{
bogdanm 0:9b334a45a8ff 1932 */
bogdanm 0:9b334a45a8ff 1933
bogdanm 0:9b334a45a8ff 1934 /* PLASC Bit Fields */
bogdanm 0:9b334a45a8ff 1935 #define MCM_PLASC_ASC_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1936 #define MCM_PLASC_ASC_SHIFT 0
bogdanm 0:9b334a45a8ff 1937 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
bogdanm 0:9b334a45a8ff 1938 /* PLAMC Bit Fields */
bogdanm 0:9b334a45a8ff 1939 #define MCM_PLAMC_AMC_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1940 #define MCM_PLAMC_AMC_SHIFT 0
bogdanm 0:9b334a45a8ff 1941 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
bogdanm 0:9b334a45a8ff 1942 /* PLACR Bit Fields */
bogdanm 0:9b334a45a8ff 1943 #define MCM_PLACR_ARB_MASK 0x200u
bogdanm 0:9b334a45a8ff 1944 #define MCM_PLACR_ARB_SHIFT 9
bogdanm 0:9b334a45a8ff 1945 #define MCM_PLACR_CFCC_MASK 0x400u
bogdanm 0:9b334a45a8ff 1946 #define MCM_PLACR_CFCC_SHIFT 10
bogdanm 0:9b334a45a8ff 1947 #define MCM_PLACR_DFCDA_MASK 0x800u
bogdanm 0:9b334a45a8ff 1948 #define MCM_PLACR_DFCDA_SHIFT 11
bogdanm 0:9b334a45a8ff 1949 #define MCM_PLACR_DFCIC_MASK 0x1000u
bogdanm 0:9b334a45a8ff 1950 #define MCM_PLACR_DFCIC_SHIFT 12
bogdanm 0:9b334a45a8ff 1951 #define MCM_PLACR_DFCC_MASK 0x2000u
bogdanm 0:9b334a45a8ff 1952 #define MCM_PLACR_DFCC_SHIFT 13
bogdanm 0:9b334a45a8ff 1953 #define MCM_PLACR_EFDS_MASK 0x4000u
bogdanm 0:9b334a45a8ff 1954 #define MCM_PLACR_EFDS_SHIFT 14
bogdanm 0:9b334a45a8ff 1955 #define MCM_PLACR_DFCS_MASK 0x8000u
bogdanm 0:9b334a45a8ff 1956 #define MCM_PLACR_DFCS_SHIFT 15
bogdanm 0:9b334a45a8ff 1957 #define MCM_PLACR_ESFC_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1958 #define MCM_PLACR_ESFC_SHIFT 16
bogdanm 0:9b334a45a8ff 1959 /* CPO Bit Fields */
bogdanm 0:9b334a45a8ff 1960 #define MCM_CPO_CPOREQ_MASK 0x1u
bogdanm 0:9b334a45a8ff 1961 #define MCM_CPO_CPOREQ_SHIFT 0
bogdanm 0:9b334a45a8ff 1962 #define MCM_CPO_CPOACK_MASK 0x2u
bogdanm 0:9b334a45a8ff 1963 #define MCM_CPO_CPOACK_SHIFT 1
bogdanm 0:9b334a45a8ff 1964 #define MCM_CPO_CPOWOI_MASK 0x4u
bogdanm 0:9b334a45a8ff 1965 #define MCM_CPO_CPOWOI_SHIFT 2
bogdanm 0:9b334a45a8ff 1966
bogdanm 0:9b334a45a8ff 1967 /**
bogdanm 0:9b334a45a8ff 1968 * @}
bogdanm 0:9b334a45a8ff 1969 */ /* end of group MCM_Register_Masks */
bogdanm 0:9b334a45a8ff 1970
bogdanm 0:9b334a45a8ff 1971
bogdanm 0:9b334a45a8ff 1972 /* MCM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1973 /** Peripheral MCM base address */
bogdanm 0:9b334a45a8ff 1974 #define MCM_BASE (0xF0003000u)
bogdanm 0:9b334a45a8ff 1975 /** Peripheral MCM base pointer */
bogdanm 0:9b334a45a8ff 1976 #define MCM ((MCM_Type *)MCM_BASE)
bogdanm 0:9b334a45a8ff 1977 /** Array initializer of MCM peripheral base pointers */
bogdanm 0:9b334a45a8ff 1978 #define MCM_BASES { MCM }
bogdanm 0:9b334a45a8ff 1979
bogdanm 0:9b334a45a8ff 1980 /**
bogdanm 0:9b334a45a8ff 1981 * @}
bogdanm 0:9b334a45a8ff 1982 */ /* end of group MCM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1983
bogdanm 0:9b334a45a8ff 1984
bogdanm 0:9b334a45a8ff 1985 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1986 -- MTB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1987 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1988
bogdanm 0:9b334a45a8ff 1989 /**
bogdanm 0:9b334a45a8ff 1990 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1991 * @{
bogdanm 0:9b334a45a8ff 1992 */
bogdanm 0:9b334a45a8ff 1993
bogdanm 0:9b334a45a8ff 1994 /** MTB - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1995 typedef struct {
bogdanm 0:9b334a45a8ff 1996 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1997 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1998 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1999 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 2000 uint8_t RESERVED_0[3824];
bogdanm 0:9b334a45a8ff 2001 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
bogdanm 0:9b334a45a8ff 2002 uint8_t RESERVED_1[156];
bogdanm 0:9b334a45a8ff 2003 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
bogdanm 0:9b334a45a8ff 2004 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
bogdanm 0:9b334a45a8ff 2005 uint8_t RESERVED_2[8];
bogdanm 0:9b334a45a8ff 2006 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
bogdanm 0:9b334a45a8ff 2007 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
bogdanm 0:9b334a45a8ff 2008 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
bogdanm 0:9b334a45a8ff 2009 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
bogdanm 0:9b334a45a8ff 2010 uint8_t RESERVED_3[8];
bogdanm 0:9b334a45a8ff 2011 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 0:9b334a45a8ff 2012 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 0:9b334a45a8ff 2013 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2014 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2015 } MTB_Type;
bogdanm 0:9b334a45a8ff 2016
bogdanm 0:9b334a45a8ff 2017 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2018 -- MTB Register Masks
bogdanm 0:9b334a45a8ff 2019 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2020
bogdanm 0:9b334a45a8ff 2021 /**
bogdanm 0:9b334a45a8ff 2022 * @addtogroup MTB_Register_Masks MTB Register Masks
bogdanm 0:9b334a45a8ff 2023 * @{
bogdanm 0:9b334a45a8ff 2024 */
bogdanm 0:9b334a45a8ff 2025
bogdanm 0:9b334a45a8ff 2026 /* POSITION Bit Fields */
bogdanm 0:9b334a45a8ff 2027 #define MTB_POSITION_WRAP_MASK 0x4u
bogdanm 0:9b334a45a8ff 2028 #define MTB_POSITION_WRAP_SHIFT 2
bogdanm 0:9b334a45a8ff 2029 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
bogdanm 0:9b334a45a8ff 2030 #define MTB_POSITION_POINTER_SHIFT 3
bogdanm 0:9b334a45a8ff 2031 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
bogdanm 0:9b334a45a8ff 2032 /* MASTER Bit Fields */
bogdanm 0:9b334a45a8ff 2033 #define MTB_MASTER_MASK_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 2034 #define MTB_MASTER_MASK_SHIFT 0
bogdanm 0:9b334a45a8ff 2035 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
bogdanm 0:9b334a45a8ff 2036 #define MTB_MASTER_TSTARTEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 2037 #define MTB_MASTER_TSTARTEN_SHIFT 5
bogdanm 0:9b334a45a8ff 2038 #define MTB_MASTER_TSTOPEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 2039 #define MTB_MASTER_TSTOPEN_SHIFT 6
bogdanm 0:9b334a45a8ff 2040 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
bogdanm 0:9b334a45a8ff 2041 #define MTB_MASTER_SFRWPRIV_SHIFT 7
bogdanm 0:9b334a45a8ff 2042 #define MTB_MASTER_RAMPRIV_MASK 0x100u
bogdanm 0:9b334a45a8ff 2043 #define MTB_MASTER_RAMPRIV_SHIFT 8
bogdanm 0:9b334a45a8ff 2044 #define MTB_MASTER_HALTREQ_MASK 0x200u
bogdanm 0:9b334a45a8ff 2045 #define MTB_MASTER_HALTREQ_SHIFT 9
bogdanm 0:9b334a45a8ff 2046 #define MTB_MASTER_EN_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 2047 #define MTB_MASTER_EN_SHIFT 31
bogdanm 0:9b334a45a8ff 2048 /* FLOW Bit Fields */
bogdanm 0:9b334a45a8ff 2049 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
bogdanm 0:9b334a45a8ff 2050 #define MTB_FLOW_AUTOSTOP_SHIFT 0
bogdanm 0:9b334a45a8ff 2051 #define MTB_FLOW_AUTOHALT_MASK 0x2u
bogdanm 0:9b334a45a8ff 2052 #define MTB_FLOW_AUTOHALT_SHIFT 1
bogdanm 0:9b334a45a8ff 2053 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
bogdanm 0:9b334a45a8ff 2054 #define MTB_FLOW_WATERMARK_SHIFT 3
bogdanm 0:9b334a45a8ff 2055 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
bogdanm 0:9b334a45a8ff 2056 /* BASE Bit Fields */
bogdanm 0:9b334a45a8ff 2057 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2058 #define MTB_BASE_BASEADDR_SHIFT 0
bogdanm 0:9b334a45a8ff 2059 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
bogdanm 0:9b334a45a8ff 2060 /* MODECTRL Bit Fields */
bogdanm 0:9b334a45a8ff 2061 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2062 #define MTB_MODECTRL_MODECTRL_SHIFT 0
bogdanm 0:9b334a45a8ff 2063 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
bogdanm 0:9b334a45a8ff 2064 /* TAGSET Bit Fields */
bogdanm 0:9b334a45a8ff 2065 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2066 #define MTB_TAGSET_TAGSET_SHIFT 0
bogdanm 0:9b334a45a8ff 2067 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
bogdanm 0:9b334a45a8ff 2068 /* TAGCLEAR Bit Fields */
bogdanm 0:9b334a45a8ff 2069 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2070 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
bogdanm 0:9b334a45a8ff 2071 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
bogdanm 0:9b334a45a8ff 2072 /* LOCKACCESS Bit Fields */
bogdanm 0:9b334a45a8ff 2073 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2074 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
bogdanm 0:9b334a45a8ff 2075 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
bogdanm 0:9b334a45a8ff 2076 /* LOCKSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 2077 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2078 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
bogdanm 0:9b334a45a8ff 2079 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
bogdanm 0:9b334a45a8ff 2080 /* AUTHSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 2081 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
bogdanm 0:9b334a45a8ff 2082 #define MTB_AUTHSTAT_BIT0_SHIFT 0
bogdanm 0:9b334a45a8ff 2083 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
bogdanm 0:9b334a45a8ff 2084 #define MTB_AUTHSTAT_BIT1_SHIFT 1
bogdanm 0:9b334a45a8ff 2085 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
bogdanm 0:9b334a45a8ff 2086 #define MTB_AUTHSTAT_BIT2_SHIFT 2
bogdanm 0:9b334a45a8ff 2087 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
bogdanm 0:9b334a45a8ff 2088 #define MTB_AUTHSTAT_BIT3_SHIFT 3
bogdanm 0:9b334a45a8ff 2089 /* DEVICEARCH Bit Fields */
bogdanm 0:9b334a45a8ff 2090 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2091 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
bogdanm 0:9b334a45a8ff 2092 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
bogdanm 0:9b334a45a8ff 2093 /* DEVICECFG Bit Fields */
bogdanm 0:9b334a45a8ff 2094 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2095 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 0:9b334a45a8ff 2096 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
bogdanm 0:9b334a45a8ff 2097 /* DEVICETYPID Bit Fields */
bogdanm 0:9b334a45a8ff 2098 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2099 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 0:9b334a45a8ff 2100 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 0:9b334a45a8ff 2101 /* PERIPHID Bit Fields */
bogdanm 0:9b334a45a8ff 2102 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2103 #define MTB_PERIPHID_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2104 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2105 /* COMPID Bit Fields */
bogdanm 0:9b334a45a8ff 2106 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2107 #define MTB_COMPID_COMPID_SHIFT 0
bogdanm 0:9b334a45a8ff 2108 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
bogdanm 0:9b334a45a8ff 2109
bogdanm 0:9b334a45a8ff 2110 /**
bogdanm 0:9b334a45a8ff 2111 * @}
bogdanm 0:9b334a45a8ff 2112 */ /* end of group MTB_Register_Masks */
bogdanm 0:9b334a45a8ff 2113
bogdanm 0:9b334a45a8ff 2114
bogdanm 0:9b334a45a8ff 2115 /* MTB - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2116 /** Peripheral MTB base address */
bogdanm 0:9b334a45a8ff 2117 #define MTB_BASE (0xF0000000u)
bogdanm 0:9b334a45a8ff 2118 /** Peripheral MTB base pointer */
bogdanm 0:9b334a45a8ff 2119 #define MTB ((MTB_Type *)MTB_BASE)
bogdanm 0:9b334a45a8ff 2120 /** Array initializer of MTB peripheral base pointers */
bogdanm 0:9b334a45a8ff 2121 #define MTB_BASES { MTB }
bogdanm 0:9b334a45a8ff 2122
bogdanm 0:9b334a45a8ff 2123 /**
bogdanm 0:9b334a45a8ff 2124 * @}
bogdanm 0:9b334a45a8ff 2125 */ /* end of group MTB_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2126
bogdanm 0:9b334a45a8ff 2127
bogdanm 0:9b334a45a8ff 2128 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2129 -- MTBDWT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2130 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2131
bogdanm 0:9b334a45a8ff 2132 /**
bogdanm 0:9b334a45a8ff 2133 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2134 * @{
bogdanm 0:9b334a45a8ff 2135 */
bogdanm 0:9b334a45a8ff 2136
bogdanm 0:9b334a45a8ff 2137 /** MTBDWT - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2138 typedef struct {
bogdanm 0:9b334a45a8ff 2139 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2140 uint8_t RESERVED_0[28];
bogdanm 0:9b334a45a8ff 2141 struct { /* offset: 0x20, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2142 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2143 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2144 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2145 uint8_t RESERVED_0[4];
bogdanm 0:9b334a45a8ff 2146 } COMPARATOR[2];
bogdanm 0:9b334a45a8ff 2147 uint8_t RESERVED_1[448];
bogdanm 0:9b334a45a8ff 2148 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
bogdanm 0:9b334a45a8ff 2149 uint8_t RESERVED_2[3524];
bogdanm 0:9b334a45a8ff 2150 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 0:9b334a45a8ff 2151 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 0:9b334a45a8ff 2152 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2153 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2154 } MTBDWT_Type;
bogdanm 0:9b334a45a8ff 2155
bogdanm 0:9b334a45a8ff 2156 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2157 -- MTBDWT Register Masks
bogdanm 0:9b334a45a8ff 2158 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2159
bogdanm 0:9b334a45a8ff 2160 /**
bogdanm 0:9b334a45a8ff 2161 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
bogdanm 0:9b334a45a8ff 2162 * @{
bogdanm 0:9b334a45a8ff 2163 */
bogdanm 0:9b334a45a8ff 2164
bogdanm 0:9b334a45a8ff 2165 /* CTRL Bit Fields */
bogdanm 0:9b334a45a8ff 2166 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
bogdanm 0:9b334a45a8ff 2167 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
bogdanm 0:9b334a45a8ff 2168 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
bogdanm 0:9b334a45a8ff 2169 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 2170 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
bogdanm 0:9b334a45a8ff 2171 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
bogdanm 0:9b334a45a8ff 2172 /* COMP Bit Fields */
bogdanm 0:9b334a45a8ff 2173 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2174 #define MTBDWT_COMP_COMP_SHIFT 0
bogdanm 0:9b334a45a8ff 2175 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
bogdanm 0:9b334a45a8ff 2176 /* MASK Bit Fields */
bogdanm 0:9b334a45a8ff 2177 #define MTBDWT_MASK_MASK_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 2178 #define MTBDWT_MASK_MASK_SHIFT 0
bogdanm 0:9b334a45a8ff 2179 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
bogdanm 0:9b334a45a8ff 2180 /* FCT Bit Fields */
bogdanm 0:9b334a45a8ff 2181 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
bogdanm 0:9b334a45a8ff 2182 #define MTBDWT_FCT_FUNCTION_SHIFT 0
bogdanm 0:9b334a45a8ff 2183 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
bogdanm 0:9b334a45a8ff 2184 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
bogdanm 0:9b334a45a8ff 2185 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
bogdanm 0:9b334a45a8ff 2186 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
bogdanm 0:9b334a45a8ff 2187 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
bogdanm 0:9b334a45a8ff 2188 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
bogdanm 0:9b334a45a8ff 2189 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
bogdanm 0:9b334a45a8ff 2190 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
bogdanm 0:9b334a45a8ff 2191 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
bogdanm 0:9b334a45a8ff 2192 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 2193 #define MTBDWT_FCT_MATCHED_SHIFT 24
bogdanm 0:9b334a45a8ff 2194 /* TBCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 2195 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
bogdanm 0:9b334a45a8ff 2196 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
bogdanm 0:9b334a45a8ff 2197 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
bogdanm 0:9b334a45a8ff 2198 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
bogdanm 0:9b334a45a8ff 2199 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 2200 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
bogdanm 0:9b334a45a8ff 2201 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
bogdanm 0:9b334a45a8ff 2202 /* DEVICECFG Bit Fields */
bogdanm 0:9b334a45a8ff 2203 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2204 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 0:9b334a45a8ff 2205 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
bogdanm 0:9b334a45a8ff 2206 /* DEVICETYPID Bit Fields */
bogdanm 0:9b334a45a8ff 2207 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2208 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 0:9b334a45a8ff 2209 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 0:9b334a45a8ff 2210 /* PERIPHID Bit Fields */
bogdanm 0:9b334a45a8ff 2211 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2212 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2213 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2214 /* COMPID Bit Fields */
bogdanm 0:9b334a45a8ff 2215 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2216 #define MTBDWT_COMPID_COMPID_SHIFT 0
bogdanm 0:9b334a45a8ff 2217 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
bogdanm 0:9b334a45a8ff 2218
bogdanm 0:9b334a45a8ff 2219 /**
bogdanm 0:9b334a45a8ff 2220 * @}
bogdanm 0:9b334a45a8ff 2221 */ /* end of group MTBDWT_Register_Masks */
bogdanm 0:9b334a45a8ff 2222
bogdanm 0:9b334a45a8ff 2223
bogdanm 0:9b334a45a8ff 2224 /* MTBDWT - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2225 /** Peripheral MTBDWT base address */
bogdanm 0:9b334a45a8ff 2226 #define MTBDWT_BASE (0xF0001000u)
bogdanm 0:9b334a45a8ff 2227 /** Peripheral MTBDWT base pointer */
bogdanm 0:9b334a45a8ff 2228 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
bogdanm 0:9b334a45a8ff 2229 /** Array initializer of MTBDWT peripheral base pointers */
bogdanm 0:9b334a45a8ff 2230 #define MTBDWT_BASES { MTBDWT }
bogdanm 0:9b334a45a8ff 2231
bogdanm 0:9b334a45a8ff 2232 /**
bogdanm 0:9b334a45a8ff 2233 * @}
bogdanm 0:9b334a45a8ff 2234 */ /* end of group MTBDWT_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2235
bogdanm 0:9b334a45a8ff 2236
bogdanm 0:9b334a45a8ff 2237 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2238 -- NV Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2239 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2240
bogdanm 0:9b334a45a8ff 2241 /**
bogdanm 0:9b334a45a8ff 2242 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2243 * @{
bogdanm 0:9b334a45a8ff 2244 */
bogdanm 0:9b334a45a8ff 2245
bogdanm 0:9b334a45a8ff 2246 /** NV - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2247 typedef struct {
bogdanm 0:9b334a45a8ff 2248 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
bogdanm 0:9b334a45a8ff 2249 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
bogdanm 0:9b334a45a8ff 2250 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
bogdanm 0:9b334a45a8ff 2251 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
bogdanm 0:9b334a45a8ff 2252 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
bogdanm 0:9b334a45a8ff 2253 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
bogdanm 0:9b334a45a8ff 2254 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
bogdanm 0:9b334a45a8ff 2255 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
bogdanm 0:9b334a45a8ff 2256 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 2257 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
bogdanm 0:9b334a45a8ff 2258 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
bogdanm 0:9b334a45a8ff 2259 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
bogdanm 0:9b334a45a8ff 2260 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 2261 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
bogdanm 0:9b334a45a8ff 2262 } NV_Type;
bogdanm 0:9b334a45a8ff 2263
bogdanm 0:9b334a45a8ff 2264 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2265 -- NV Register Masks
bogdanm 0:9b334a45a8ff 2266 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2267
bogdanm 0:9b334a45a8ff 2268 /**
bogdanm 0:9b334a45a8ff 2269 * @addtogroup NV_Register_Masks NV Register Masks
bogdanm 0:9b334a45a8ff 2270 * @{
bogdanm 0:9b334a45a8ff 2271 */
bogdanm 0:9b334a45a8ff 2272
bogdanm 0:9b334a45a8ff 2273 /* BACKKEY3 Bit Fields */
bogdanm 0:9b334a45a8ff 2274 #define NV_BACKKEY3_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2275 #define NV_BACKKEY3_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2276 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
bogdanm 0:9b334a45a8ff 2277 /* BACKKEY2 Bit Fields */
bogdanm 0:9b334a45a8ff 2278 #define NV_BACKKEY2_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2279 #define NV_BACKKEY2_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2280 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
bogdanm 0:9b334a45a8ff 2281 /* BACKKEY1 Bit Fields */
bogdanm 0:9b334a45a8ff 2282 #define NV_BACKKEY1_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2283 #define NV_BACKKEY1_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2284 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
bogdanm 0:9b334a45a8ff 2285 /* BACKKEY0 Bit Fields */
bogdanm 0:9b334a45a8ff 2286 #define NV_BACKKEY0_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2287 #define NV_BACKKEY0_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2288 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
bogdanm 0:9b334a45a8ff 2289 /* BACKKEY7 Bit Fields */
bogdanm 0:9b334a45a8ff 2290 #define NV_BACKKEY7_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2291 #define NV_BACKKEY7_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2292 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
bogdanm 0:9b334a45a8ff 2293 /* BACKKEY6 Bit Fields */
bogdanm 0:9b334a45a8ff 2294 #define NV_BACKKEY6_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2295 #define NV_BACKKEY6_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2296 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
bogdanm 0:9b334a45a8ff 2297 /* BACKKEY5 Bit Fields */
bogdanm 0:9b334a45a8ff 2298 #define NV_BACKKEY5_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2299 #define NV_BACKKEY5_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2300 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
bogdanm 0:9b334a45a8ff 2301 /* BACKKEY4 Bit Fields */
bogdanm 0:9b334a45a8ff 2302 #define NV_BACKKEY4_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2303 #define NV_BACKKEY4_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 2304 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
bogdanm 0:9b334a45a8ff 2305 /* FPROT3 Bit Fields */
bogdanm 0:9b334a45a8ff 2306 #define NV_FPROT3_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2307 #define NV_FPROT3_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 2308 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
bogdanm 0:9b334a45a8ff 2309 /* FPROT2 Bit Fields */
bogdanm 0:9b334a45a8ff 2310 #define NV_FPROT2_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2311 #define NV_FPROT2_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 2312 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
bogdanm 0:9b334a45a8ff 2313 /* FPROT1 Bit Fields */
bogdanm 0:9b334a45a8ff 2314 #define NV_FPROT1_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2315 #define NV_FPROT1_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 2316 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
bogdanm 0:9b334a45a8ff 2317 /* FPROT0 Bit Fields */
bogdanm 0:9b334a45a8ff 2318 #define NV_FPROT0_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2319 #define NV_FPROT0_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 2320 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
bogdanm 0:9b334a45a8ff 2321 /* FSEC Bit Fields */
bogdanm 0:9b334a45a8ff 2322 #define NV_FSEC_SEC_MASK 0x3u
bogdanm 0:9b334a45a8ff 2323 #define NV_FSEC_SEC_SHIFT 0
bogdanm 0:9b334a45a8ff 2324 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
bogdanm 0:9b334a45a8ff 2325 #define NV_FSEC_FSLACC_MASK 0xCu
bogdanm 0:9b334a45a8ff 2326 #define NV_FSEC_FSLACC_SHIFT 2
bogdanm 0:9b334a45a8ff 2327 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
bogdanm 0:9b334a45a8ff 2328 #define NV_FSEC_MEEN_MASK 0x30u
bogdanm 0:9b334a45a8ff 2329 #define NV_FSEC_MEEN_SHIFT 4
bogdanm 0:9b334a45a8ff 2330 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
bogdanm 0:9b334a45a8ff 2331 #define NV_FSEC_KEYEN_MASK 0xC0u
bogdanm 0:9b334a45a8ff 2332 #define NV_FSEC_KEYEN_SHIFT 6
bogdanm 0:9b334a45a8ff 2333 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
bogdanm 0:9b334a45a8ff 2334 /* FOPT Bit Fields */
bogdanm 0:9b334a45a8ff 2335 #define NV_FOPT_LPBOOT0_MASK 0x1u
bogdanm 0:9b334a45a8ff 2336 #define NV_FOPT_LPBOOT0_SHIFT 0
bogdanm 0:9b334a45a8ff 2337 #define NV_FOPT_NMI_DIS_MASK 0x4u
bogdanm 0:9b334a45a8ff 2338 #define NV_FOPT_NMI_DIS_SHIFT 2
bogdanm 0:9b334a45a8ff 2339 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
bogdanm 0:9b334a45a8ff 2340 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
bogdanm 0:9b334a45a8ff 2341 #define NV_FOPT_LPBOOT1_MASK 0x10u
bogdanm 0:9b334a45a8ff 2342 #define NV_FOPT_LPBOOT1_SHIFT 4
bogdanm 0:9b334a45a8ff 2343 #define NV_FOPT_FAST_INIT_MASK 0x20u
bogdanm 0:9b334a45a8ff 2344 #define NV_FOPT_FAST_INIT_SHIFT 5
bogdanm 0:9b334a45a8ff 2345
bogdanm 0:9b334a45a8ff 2346 /**
bogdanm 0:9b334a45a8ff 2347 * @}
bogdanm 0:9b334a45a8ff 2348 */ /* end of group NV_Register_Masks */
bogdanm 0:9b334a45a8ff 2349
bogdanm 0:9b334a45a8ff 2350
bogdanm 0:9b334a45a8ff 2351 /* NV - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2352 /** Peripheral FTFA_FlashConfig base address */
bogdanm 0:9b334a45a8ff 2353 #define FTFA_FlashConfig_BASE (0x400u)
bogdanm 0:9b334a45a8ff 2354 /** Peripheral FTFA_FlashConfig base pointer */
bogdanm 0:9b334a45a8ff 2355 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
bogdanm 0:9b334a45a8ff 2356 /** Array initializer of NV peripheral base pointers */
bogdanm 0:9b334a45a8ff 2357 #define NV_BASES { FTFA_FlashConfig }
bogdanm 0:9b334a45a8ff 2358
bogdanm 0:9b334a45a8ff 2359 /**
bogdanm 0:9b334a45a8ff 2360 * @}
bogdanm 0:9b334a45a8ff 2361 */ /* end of group NV_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2362
bogdanm 0:9b334a45a8ff 2363
bogdanm 0:9b334a45a8ff 2364 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2365 -- OSC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2366 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2367
bogdanm 0:9b334a45a8ff 2368 /**
bogdanm 0:9b334a45a8ff 2369 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2370 * @{
bogdanm 0:9b334a45a8ff 2371 */
bogdanm 0:9b334a45a8ff 2372
bogdanm 0:9b334a45a8ff 2373 /** OSC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2374 typedef struct {
bogdanm 0:9b334a45a8ff 2375 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2376 } OSC_Type;
bogdanm 0:9b334a45a8ff 2377
bogdanm 0:9b334a45a8ff 2378 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2379 -- OSC Register Masks
bogdanm 0:9b334a45a8ff 2380 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2381
bogdanm 0:9b334a45a8ff 2382 /**
bogdanm 0:9b334a45a8ff 2383 * @addtogroup OSC_Register_Masks OSC Register Masks
bogdanm 0:9b334a45a8ff 2384 * @{
bogdanm 0:9b334a45a8ff 2385 */
bogdanm 0:9b334a45a8ff 2386
bogdanm 0:9b334a45a8ff 2387 /* CR Bit Fields */
bogdanm 0:9b334a45a8ff 2388 #define OSC_CR_SC16P_MASK 0x1u
bogdanm 0:9b334a45a8ff 2389 #define OSC_CR_SC16P_SHIFT 0
bogdanm 0:9b334a45a8ff 2390 #define OSC_CR_SC8P_MASK 0x2u
bogdanm 0:9b334a45a8ff 2391 #define OSC_CR_SC8P_SHIFT 1
bogdanm 0:9b334a45a8ff 2392 #define OSC_CR_SC4P_MASK 0x4u
bogdanm 0:9b334a45a8ff 2393 #define OSC_CR_SC4P_SHIFT 2
bogdanm 0:9b334a45a8ff 2394 #define OSC_CR_SC2P_MASK 0x8u
bogdanm 0:9b334a45a8ff 2395 #define OSC_CR_SC2P_SHIFT 3
bogdanm 0:9b334a45a8ff 2396 #define OSC_CR_EREFSTEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 2397 #define OSC_CR_EREFSTEN_SHIFT 5
bogdanm 0:9b334a45a8ff 2398 #define OSC_CR_ERCLKEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 2399 #define OSC_CR_ERCLKEN_SHIFT 7
bogdanm 0:9b334a45a8ff 2400
bogdanm 0:9b334a45a8ff 2401 /**
bogdanm 0:9b334a45a8ff 2402 * @}
bogdanm 0:9b334a45a8ff 2403 */ /* end of group OSC_Register_Masks */
bogdanm 0:9b334a45a8ff 2404
bogdanm 0:9b334a45a8ff 2405
bogdanm 0:9b334a45a8ff 2406 /* OSC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2407 /** Peripheral OSC0 base address */
bogdanm 0:9b334a45a8ff 2408 #define OSC0_BASE (0x40065000u)
bogdanm 0:9b334a45a8ff 2409 /** Peripheral OSC0 base pointer */
bogdanm 0:9b334a45a8ff 2410 #define OSC0 ((OSC_Type *)OSC0_BASE)
bogdanm 0:9b334a45a8ff 2411 /** Array initializer of OSC peripheral base pointers */
bogdanm 0:9b334a45a8ff 2412 #define OSC_BASES { OSC0 }
bogdanm 0:9b334a45a8ff 2413
bogdanm 0:9b334a45a8ff 2414 /**
bogdanm 0:9b334a45a8ff 2415 * @}
bogdanm 0:9b334a45a8ff 2416 */ /* end of group OSC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2417
bogdanm 0:9b334a45a8ff 2418
bogdanm 0:9b334a45a8ff 2419 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2420 -- PIT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2421 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2422
bogdanm 0:9b334a45a8ff 2423 /**
bogdanm 0:9b334a45a8ff 2424 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2425 * @{
bogdanm 0:9b334a45a8ff 2426 */
bogdanm 0:9b334a45a8ff 2427
bogdanm 0:9b334a45a8ff 2428 /** PIT - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2429 typedef struct {
bogdanm 0:9b334a45a8ff 2430 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2431 uint8_t RESERVED_0[220];
bogdanm 0:9b334a45a8ff 2432 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
bogdanm 0:9b334a45a8ff 2433 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
bogdanm 0:9b334a45a8ff 2434 uint8_t RESERVED_1[24];
bogdanm 0:9b334a45a8ff 2435 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2436 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2437 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2438 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2439 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
bogdanm 0:9b334a45a8ff 2440 } CHANNEL[2];
bogdanm 0:9b334a45a8ff 2441 } PIT_Type;
bogdanm 0:9b334a45a8ff 2442
bogdanm 0:9b334a45a8ff 2443 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2444 -- PIT Register Masks
bogdanm 0:9b334a45a8ff 2445 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2446
bogdanm 0:9b334a45a8ff 2447 /**
bogdanm 0:9b334a45a8ff 2448 * @addtogroup PIT_Register_Masks PIT Register Masks
bogdanm 0:9b334a45a8ff 2449 * @{
bogdanm 0:9b334a45a8ff 2450 */
bogdanm 0:9b334a45a8ff 2451
bogdanm 0:9b334a45a8ff 2452 /* MCR Bit Fields */
bogdanm 0:9b334a45a8ff 2453 #define PIT_MCR_FRZ_MASK 0x1u
bogdanm 0:9b334a45a8ff 2454 #define PIT_MCR_FRZ_SHIFT 0
bogdanm 0:9b334a45a8ff 2455 #define PIT_MCR_MDIS_MASK 0x2u
bogdanm 0:9b334a45a8ff 2456 #define PIT_MCR_MDIS_SHIFT 1
bogdanm 0:9b334a45a8ff 2457 /* LTMR64H Bit Fields */
bogdanm 0:9b334a45a8ff 2458 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2459 #define PIT_LTMR64H_LTH_SHIFT 0
bogdanm 0:9b334a45a8ff 2460 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
bogdanm 0:9b334a45a8ff 2461 /* LTMR64L Bit Fields */
bogdanm 0:9b334a45a8ff 2462 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2463 #define PIT_LTMR64L_LTL_SHIFT 0
bogdanm 0:9b334a45a8ff 2464 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
bogdanm 0:9b334a45a8ff 2465 /* LDVAL Bit Fields */
bogdanm 0:9b334a45a8ff 2466 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2467 #define PIT_LDVAL_TSV_SHIFT 0
bogdanm 0:9b334a45a8ff 2468 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
bogdanm 0:9b334a45a8ff 2469 /* CVAL Bit Fields */
bogdanm 0:9b334a45a8ff 2470 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2471 #define PIT_CVAL_TVL_SHIFT 0
bogdanm 0:9b334a45a8ff 2472 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
bogdanm 0:9b334a45a8ff 2473 /* TCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 2474 #define PIT_TCTRL_TEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 2475 #define PIT_TCTRL_TEN_SHIFT 0
bogdanm 0:9b334a45a8ff 2476 #define PIT_TCTRL_TIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 2477 #define PIT_TCTRL_TIE_SHIFT 1
bogdanm 0:9b334a45a8ff 2478 #define PIT_TCTRL_CHN_MASK 0x4u
bogdanm 0:9b334a45a8ff 2479 #define PIT_TCTRL_CHN_SHIFT 2
bogdanm 0:9b334a45a8ff 2480 /* TFLG Bit Fields */
bogdanm 0:9b334a45a8ff 2481 #define PIT_TFLG_TIF_MASK 0x1u
bogdanm 0:9b334a45a8ff 2482 #define PIT_TFLG_TIF_SHIFT 0
bogdanm 0:9b334a45a8ff 2483
bogdanm 0:9b334a45a8ff 2484 /**
bogdanm 0:9b334a45a8ff 2485 * @}
bogdanm 0:9b334a45a8ff 2486 */ /* end of group PIT_Register_Masks */
bogdanm 0:9b334a45a8ff 2487
bogdanm 0:9b334a45a8ff 2488
bogdanm 0:9b334a45a8ff 2489 /* PIT - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2490 /** Peripheral PIT base address */
bogdanm 0:9b334a45a8ff 2491 #define PIT_BASE (0x40037000u)
bogdanm 0:9b334a45a8ff 2492 /** Peripheral PIT base pointer */
bogdanm 0:9b334a45a8ff 2493 #define PIT ((PIT_Type *)PIT_BASE)
bogdanm 0:9b334a45a8ff 2494 /** Array initializer of PIT peripheral base pointers */
bogdanm 0:9b334a45a8ff 2495 #define PIT_BASES { PIT }
bogdanm 0:9b334a45a8ff 2496
bogdanm 0:9b334a45a8ff 2497 /**
bogdanm 0:9b334a45a8ff 2498 * @}
bogdanm 0:9b334a45a8ff 2499 */ /* end of group PIT_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2500
bogdanm 0:9b334a45a8ff 2501
bogdanm 0:9b334a45a8ff 2502 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2503 -- PMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2504 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2505
bogdanm 0:9b334a45a8ff 2506 /**
bogdanm 0:9b334a45a8ff 2507 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2508 * @{
bogdanm 0:9b334a45a8ff 2509 */
bogdanm 0:9b334a45a8ff 2510
bogdanm 0:9b334a45a8ff 2511 /** PMC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2512 typedef struct {
bogdanm 0:9b334a45a8ff 2513 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2514 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 2515 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 2516 } PMC_Type;
bogdanm 0:9b334a45a8ff 2517
bogdanm 0:9b334a45a8ff 2518 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2519 -- PMC Register Masks
bogdanm 0:9b334a45a8ff 2520 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2521
bogdanm 0:9b334a45a8ff 2522 /**
bogdanm 0:9b334a45a8ff 2523 * @addtogroup PMC_Register_Masks PMC Register Masks
bogdanm 0:9b334a45a8ff 2524 * @{
bogdanm 0:9b334a45a8ff 2525 */
bogdanm 0:9b334a45a8ff 2526
bogdanm 0:9b334a45a8ff 2527 /* LVDSC1 Bit Fields */
bogdanm 0:9b334a45a8ff 2528 #define PMC_LVDSC1_LVDV_MASK 0x3u
bogdanm 0:9b334a45a8ff 2529 #define PMC_LVDSC1_LVDV_SHIFT 0
bogdanm 0:9b334a45a8ff 2530 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
bogdanm 0:9b334a45a8ff 2531 #define PMC_LVDSC1_LVDRE_MASK 0x10u
bogdanm 0:9b334a45a8ff 2532 #define PMC_LVDSC1_LVDRE_SHIFT 4
bogdanm 0:9b334a45a8ff 2533 #define PMC_LVDSC1_LVDIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 2534 #define PMC_LVDSC1_LVDIE_SHIFT 5
bogdanm 0:9b334a45a8ff 2535 #define PMC_LVDSC1_LVDACK_MASK 0x40u
bogdanm 0:9b334a45a8ff 2536 #define PMC_LVDSC1_LVDACK_SHIFT 6
bogdanm 0:9b334a45a8ff 2537 #define PMC_LVDSC1_LVDF_MASK 0x80u
bogdanm 0:9b334a45a8ff 2538 #define PMC_LVDSC1_LVDF_SHIFT 7
bogdanm 0:9b334a45a8ff 2539 /* LVDSC2 Bit Fields */
bogdanm 0:9b334a45a8ff 2540 #define PMC_LVDSC2_LVWV_MASK 0x3u
bogdanm 0:9b334a45a8ff 2541 #define PMC_LVDSC2_LVWV_SHIFT 0
bogdanm 0:9b334a45a8ff 2542 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
bogdanm 0:9b334a45a8ff 2543 #define PMC_LVDSC2_LVWIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 2544 #define PMC_LVDSC2_LVWIE_SHIFT 5
bogdanm 0:9b334a45a8ff 2545 #define PMC_LVDSC2_LVWACK_MASK 0x40u
bogdanm 0:9b334a45a8ff 2546 #define PMC_LVDSC2_LVWACK_SHIFT 6
bogdanm 0:9b334a45a8ff 2547 #define PMC_LVDSC2_LVWF_MASK 0x80u
bogdanm 0:9b334a45a8ff 2548 #define PMC_LVDSC2_LVWF_SHIFT 7
bogdanm 0:9b334a45a8ff 2549 /* REGSC Bit Fields */
bogdanm 0:9b334a45a8ff 2550 #define PMC_REGSC_BGBE_MASK 0x1u
bogdanm 0:9b334a45a8ff 2551 #define PMC_REGSC_BGBE_SHIFT 0
bogdanm 0:9b334a45a8ff 2552 #define PMC_REGSC_REGONS_MASK 0x4u
bogdanm 0:9b334a45a8ff 2553 #define PMC_REGSC_REGONS_SHIFT 2
bogdanm 0:9b334a45a8ff 2554 #define PMC_REGSC_ACKISO_MASK 0x8u
bogdanm 0:9b334a45a8ff 2555 #define PMC_REGSC_ACKISO_SHIFT 3
bogdanm 0:9b334a45a8ff 2556 #define PMC_REGSC_BGEN_MASK 0x10u
bogdanm 0:9b334a45a8ff 2557 #define PMC_REGSC_BGEN_SHIFT 4
bogdanm 0:9b334a45a8ff 2558
bogdanm 0:9b334a45a8ff 2559 /**
bogdanm 0:9b334a45a8ff 2560 * @}
bogdanm 0:9b334a45a8ff 2561 */ /* end of group PMC_Register_Masks */
bogdanm 0:9b334a45a8ff 2562
bogdanm 0:9b334a45a8ff 2563
bogdanm 0:9b334a45a8ff 2564 /* PMC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2565 /** Peripheral PMC base address */
bogdanm 0:9b334a45a8ff 2566 #define PMC_BASE (0x4007D000u)
bogdanm 0:9b334a45a8ff 2567 /** Peripheral PMC base pointer */
bogdanm 0:9b334a45a8ff 2568 #define PMC ((PMC_Type *)PMC_BASE)
bogdanm 0:9b334a45a8ff 2569 /** Array initializer of PMC peripheral base pointers */
bogdanm 0:9b334a45a8ff 2570 #define PMC_BASES { PMC }
bogdanm 0:9b334a45a8ff 2571
bogdanm 0:9b334a45a8ff 2572 /**
bogdanm 0:9b334a45a8ff 2573 * @}
bogdanm 0:9b334a45a8ff 2574 */ /* end of group PMC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2575
bogdanm 0:9b334a45a8ff 2576
bogdanm 0:9b334a45a8ff 2577 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2578 -- PORT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2579 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2580
bogdanm 0:9b334a45a8ff 2581 /**
bogdanm 0:9b334a45a8ff 2582 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2583 * @{
bogdanm 0:9b334a45a8ff 2584 */
bogdanm 0:9b334a45a8ff 2585
bogdanm 0:9b334a45a8ff 2586 /** PORT - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2587 typedef struct {
bogdanm 0:9b334a45a8ff 2588 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2589 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
bogdanm 0:9b334a45a8ff 2590 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
bogdanm 0:9b334a45a8ff 2591 uint8_t RESERVED_0[24];
bogdanm 0:9b334a45a8ff 2592 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
bogdanm 0:9b334a45a8ff 2593 } PORT_Type;
bogdanm 0:9b334a45a8ff 2594
bogdanm 0:9b334a45a8ff 2595 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2596 -- PORT Register Masks
bogdanm 0:9b334a45a8ff 2597 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2598
bogdanm 0:9b334a45a8ff 2599 /**
bogdanm 0:9b334a45a8ff 2600 * @addtogroup PORT_Register_Masks PORT Register Masks
bogdanm 0:9b334a45a8ff 2601 * @{
bogdanm 0:9b334a45a8ff 2602 */
bogdanm 0:9b334a45a8ff 2603
bogdanm 0:9b334a45a8ff 2604 /* PCR Bit Fields */
bogdanm 0:9b334a45a8ff 2605 #define PORT_PCR_PS_MASK 0x1u
bogdanm 0:9b334a45a8ff 2606 #define PORT_PCR_PS_SHIFT 0
bogdanm 0:9b334a45a8ff 2607 #define PORT_PCR_PE_MASK 0x2u
bogdanm 0:9b334a45a8ff 2608 #define PORT_PCR_PE_SHIFT 1
bogdanm 0:9b334a45a8ff 2609 #define PORT_PCR_SRE_MASK 0x4u
bogdanm 0:9b334a45a8ff 2610 #define PORT_PCR_SRE_SHIFT 2
bogdanm 0:9b334a45a8ff 2611 #define PORT_PCR_PFE_MASK 0x10u
bogdanm 0:9b334a45a8ff 2612 #define PORT_PCR_PFE_SHIFT 4
bogdanm 0:9b334a45a8ff 2613 #define PORT_PCR_DSE_MASK 0x40u
bogdanm 0:9b334a45a8ff 2614 #define PORT_PCR_DSE_SHIFT 6
bogdanm 0:9b334a45a8ff 2615 #define PORT_PCR_MUX_MASK 0x700u
bogdanm 0:9b334a45a8ff 2616 #define PORT_PCR_MUX_SHIFT 8
bogdanm 0:9b334a45a8ff 2617 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
bogdanm 0:9b334a45a8ff 2618 #define PORT_PCR_IRQC_MASK 0xF0000u
bogdanm 0:9b334a45a8ff 2619 #define PORT_PCR_IRQC_SHIFT 16
bogdanm 0:9b334a45a8ff 2620 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
bogdanm 0:9b334a45a8ff 2621 #define PORT_PCR_ISF_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 2622 #define PORT_PCR_ISF_SHIFT 24
bogdanm 0:9b334a45a8ff 2623 /* GPCLR Bit Fields */
bogdanm 0:9b334a45a8ff 2624 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 2625 #define PORT_GPCLR_GPWD_SHIFT 0
bogdanm 0:9b334a45a8ff 2626 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
bogdanm 0:9b334a45a8ff 2627 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
bogdanm 0:9b334a45a8ff 2628 #define PORT_GPCLR_GPWE_SHIFT 16
bogdanm 0:9b334a45a8ff 2629 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
bogdanm 0:9b334a45a8ff 2630 /* GPCHR Bit Fields */
bogdanm 0:9b334a45a8ff 2631 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 2632 #define PORT_GPCHR_GPWD_SHIFT 0
bogdanm 0:9b334a45a8ff 2633 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
bogdanm 0:9b334a45a8ff 2634 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
bogdanm 0:9b334a45a8ff 2635 #define PORT_GPCHR_GPWE_SHIFT 16
bogdanm 0:9b334a45a8ff 2636 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
bogdanm 0:9b334a45a8ff 2637 /* ISFR Bit Fields */
bogdanm 0:9b334a45a8ff 2638 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2639 #define PORT_ISFR_ISF_SHIFT 0
bogdanm 0:9b334a45a8ff 2640 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
bogdanm 0:9b334a45a8ff 2641
bogdanm 0:9b334a45a8ff 2642 /**
bogdanm 0:9b334a45a8ff 2643 * @}
bogdanm 0:9b334a45a8ff 2644 */ /* end of group PORT_Register_Masks */
bogdanm 0:9b334a45a8ff 2645
bogdanm 0:9b334a45a8ff 2646
bogdanm 0:9b334a45a8ff 2647 /* PORT - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2648 /** Peripheral PORTA base address */
bogdanm 0:9b334a45a8ff 2649 #define PORTA_BASE (0x40049000u)
bogdanm 0:9b334a45a8ff 2650 /** Peripheral PORTA base pointer */
bogdanm 0:9b334a45a8ff 2651 #define PORTA ((PORT_Type *)PORTA_BASE)
bogdanm 0:9b334a45a8ff 2652 /** Peripheral PORTB base address */
bogdanm 0:9b334a45a8ff 2653 #define PORTB_BASE (0x4004A000u)
bogdanm 0:9b334a45a8ff 2654 /** Peripheral PORTB base pointer */
bogdanm 0:9b334a45a8ff 2655 #define PORTB ((PORT_Type *)PORTB_BASE)
bogdanm 0:9b334a45a8ff 2656 /** Peripheral PORTC base address */
bogdanm 0:9b334a45a8ff 2657 #define PORTC_BASE (0x4004B000u)
bogdanm 0:9b334a45a8ff 2658 /** Peripheral PORTC base pointer */
bogdanm 0:9b334a45a8ff 2659 #define PORTC ((PORT_Type *)PORTC_BASE)
bogdanm 0:9b334a45a8ff 2660 /** Peripheral PORTD base address */
bogdanm 0:9b334a45a8ff 2661 #define PORTD_BASE (0x4004C000u)
bogdanm 0:9b334a45a8ff 2662 /** Peripheral PORTD base pointer */
bogdanm 0:9b334a45a8ff 2663 #define PORTD ((PORT_Type *)PORTD_BASE)
bogdanm 0:9b334a45a8ff 2664 /** Peripheral PORTE base address */
bogdanm 0:9b334a45a8ff 2665 #define PORTE_BASE (0x4004D000u)
bogdanm 0:9b334a45a8ff 2666 /** Peripheral PORTE base pointer */
bogdanm 0:9b334a45a8ff 2667 #define PORTE ((PORT_Type *)PORTE_BASE)
bogdanm 0:9b334a45a8ff 2668 /** Array initializer of PORT peripheral base pointers */
bogdanm 0:9b334a45a8ff 2669 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
bogdanm 0:9b334a45a8ff 2670
bogdanm 0:9b334a45a8ff 2671 /**
bogdanm 0:9b334a45a8ff 2672 * @}
bogdanm 0:9b334a45a8ff 2673 */ /* end of group PORT_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2674
bogdanm 0:9b334a45a8ff 2675
bogdanm 0:9b334a45a8ff 2676 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2677 -- RCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2678 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2679
bogdanm 0:9b334a45a8ff 2680 /**
bogdanm 0:9b334a45a8ff 2681 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2682 * @{
bogdanm 0:9b334a45a8ff 2683 */
bogdanm 0:9b334a45a8ff 2684
bogdanm 0:9b334a45a8ff 2685 /** RCM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2686 typedef struct {
bogdanm 0:9b334a45a8ff 2687 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2688 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
bogdanm 0:9b334a45a8ff 2689 uint8_t RESERVED_0[2];
bogdanm 0:9b334a45a8ff 2690 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 2691 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 2692 } RCM_Type;
bogdanm 0:9b334a45a8ff 2693
bogdanm 0:9b334a45a8ff 2694 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2695 -- RCM Register Masks
bogdanm 0:9b334a45a8ff 2696 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2697
bogdanm 0:9b334a45a8ff 2698 /**
bogdanm 0:9b334a45a8ff 2699 * @addtogroup RCM_Register_Masks RCM Register Masks
bogdanm 0:9b334a45a8ff 2700 * @{
bogdanm 0:9b334a45a8ff 2701 */
bogdanm 0:9b334a45a8ff 2702
bogdanm 0:9b334a45a8ff 2703 /* SRS0 Bit Fields */
bogdanm 0:9b334a45a8ff 2704 #define RCM_SRS0_WAKEUP_MASK 0x1u
bogdanm 0:9b334a45a8ff 2705 #define RCM_SRS0_WAKEUP_SHIFT 0
bogdanm 0:9b334a45a8ff 2706 #define RCM_SRS0_LVD_MASK 0x2u
bogdanm 0:9b334a45a8ff 2707 #define RCM_SRS0_LVD_SHIFT 1
bogdanm 0:9b334a45a8ff 2708 #define RCM_SRS0_LOC_MASK 0x4u
bogdanm 0:9b334a45a8ff 2709 #define RCM_SRS0_LOC_SHIFT 2
bogdanm 0:9b334a45a8ff 2710 #define RCM_SRS0_LOL_MASK 0x8u
bogdanm 0:9b334a45a8ff 2711 #define RCM_SRS0_LOL_SHIFT 3
bogdanm 0:9b334a45a8ff 2712 #define RCM_SRS0_WDOG_MASK 0x20u
bogdanm 0:9b334a45a8ff 2713 #define RCM_SRS0_WDOG_SHIFT 5
bogdanm 0:9b334a45a8ff 2714 #define RCM_SRS0_PIN_MASK 0x40u
bogdanm 0:9b334a45a8ff 2715 #define RCM_SRS0_PIN_SHIFT 6
bogdanm 0:9b334a45a8ff 2716 #define RCM_SRS0_POR_MASK 0x80u
bogdanm 0:9b334a45a8ff 2717 #define RCM_SRS0_POR_SHIFT 7
bogdanm 0:9b334a45a8ff 2718 /* SRS1 Bit Fields */
bogdanm 0:9b334a45a8ff 2719 #define RCM_SRS1_LOCKUP_MASK 0x2u
bogdanm 0:9b334a45a8ff 2720 #define RCM_SRS1_LOCKUP_SHIFT 1
bogdanm 0:9b334a45a8ff 2721 #define RCM_SRS1_SW_MASK 0x4u
bogdanm 0:9b334a45a8ff 2722 #define RCM_SRS1_SW_SHIFT 2
bogdanm 0:9b334a45a8ff 2723 #define RCM_SRS1_MDM_AP_MASK 0x8u
bogdanm 0:9b334a45a8ff 2724 #define RCM_SRS1_MDM_AP_SHIFT 3
bogdanm 0:9b334a45a8ff 2725 #define RCM_SRS1_SACKERR_MASK 0x20u
bogdanm 0:9b334a45a8ff 2726 #define RCM_SRS1_SACKERR_SHIFT 5
bogdanm 0:9b334a45a8ff 2727 /* RPFC Bit Fields */
bogdanm 0:9b334a45a8ff 2728 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
bogdanm 0:9b334a45a8ff 2729 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
bogdanm 0:9b334a45a8ff 2730 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
bogdanm 0:9b334a45a8ff 2731 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
bogdanm 0:9b334a45a8ff 2732 #define RCM_RPFC_RSTFLTSS_SHIFT 2
bogdanm 0:9b334a45a8ff 2733 /* RPFW Bit Fields */
bogdanm 0:9b334a45a8ff 2734 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 2735 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 2736 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
bogdanm 0:9b334a45a8ff 2737
bogdanm 0:9b334a45a8ff 2738 /**
bogdanm 0:9b334a45a8ff 2739 * @}
bogdanm 0:9b334a45a8ff 2740 */ /* end of group RCM_Register_Masks */
bogdanm 0:9b334a45a8ff 2741
bogdanm 0:9b334a45a8ff 2742
bogdanm 0:9b334a45a8ff 2743 /* RCM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2744 /** Peripheral RCM base address */
bogdanm 0:9b334a45a8ff 2745 #define RCM_BASE (0x4007F000u)
bogdanm 0:9b334a45a8ff 2746 /** Peripheral RCM base pointer */
bogdanm 0:9b334a45a8ff 2747 #define RCM ((RCM_Type *)RCM_BASE)
bogdanm 0:9b334a45a8ff 2748 /** Array initializer of RCM peripheral base pointers */
bogdanm 0:9b334a45a8ff 2749 #define RCM_BASES { RCM }
bogdanm 0:9b334a45a8ff 2750
bogdanm 0:9b334a45a8ff 2751 /**
bogdanm 0:9b334a45a8ff 2752 * @}
bogdanm 0:9b334a45a8ff 2753 */ /* end of group RCM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2754
bogdanm 0:9b334a45a8ff 2755
bogdanm 0:9b334a45a8ff 2756 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2757 -- ROM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2758 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2759
bogdanm 0:9b334a45a8ff 2760 /**
bogdanm 0:9b334a45a8ff 2761 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2762 * @{
bogdanm 0:9b334a45a8ff 2763 */
bogdanm 0:9b334a45a8ff 2764
bogdanm 0:9b334a45a8ff 2765 /** ROM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2766 typedef struct {
bogdanm 0:9b334a45a8ff 2767 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2768 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 2769 uint8_t RESERVED_0[4028];
bogdanm 0:9b334a45a8ff 2770 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
bogdanm 0:9b334a45a8ff 2771 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
bogdanm 0:9b334a45a8ff 2772 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
bogdanm 0:9b334a45a8ff 2773 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
bogdanm 0:9b334a45a8ff 2774 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
bogdanm 0:9b334a45a8ff 2775 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
bogdanm 0:9b334a45a8ff 2776 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
bogdanm 0:9b334a45a8ff 2777 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
bogdanm 0:9b334a45a8ff 2778 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
bogdanm 0:9b334a45a8ff 2779 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 2780 } ROM_Type;
bogdanm 0:9b334a45a8ff 2781
bogdanm 0:9b334a45a8ff 2782 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2783 -- ROM Register Masks
bogdanm 0:9b334a45a8ff 2784 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2785
bogdanm 0:9b334a45a8ff 2786 /**
bogdanm 0:9b334a45a8ff 2787 * @addtogroup ROM_Register_Masks ROM Register Masks
bogdanm 0:9b334a45a8ff 2788 * @{
bogdanm 0:9b334a45a8ff 2789 */
bogdanm 0:9b334a45a8ff 2790
bogdanm 0:9b334a45a8ff 2791 /* ENTRY Bit Fields */
bogdanm 0:9b334a45a8ff 2792 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2793 #define ROM_ENTRY_ENTRY_SHIFT 0
bogdanm 0:9b334a45a8ff 2794 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
bogdanm 0:9b334a45a8ff 2795 /* TABLEMARK Bit Fields */
bogdanm 0:9b334a45a8ff 2796 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2797 #define ROM_TABLEMARK_MARK_SHIFT 0
bogdanm 0:9b334a45a8ff 2798 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
bogdanm 0:9b334a45a8ff 2799 /* SYSACCESS Bit Fields */
bogdanm 0:9b334a45a8ff 2800 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2801 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
bogdanm 0:9b334a45a8ff 2802 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
bogdanm 0:9b334a45a8ff 2803 /* PERIPHID4 Bit Fields */
bogdanm 0:9b334a45a8ff 2804 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2805 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2806 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2807 /* PERIPHID5 Bit Fields */
bogdanm 0:9b334a45a8ff 2808 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2809 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2810 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2811 /* PERIPHID6 Bit Fields */
bogdanm 0:9b334a45a8ff 2812 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2813 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2814 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2815 /* PERIPHID7 Bit Fields */
bogdanm 0:9b334a45a8ff 2816 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2817 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2818 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2819 /* PERIPHID0 Bit Fields */
bogdanm 0:9b334a45a8ff 2820 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2821 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2822 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2823 /* PERIPHID1 Bit Fields */
bogdanm 0:9b334a45a8ff 2824 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2825 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2826 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2827 /* PERIPHID2 Bit Fields */
bogdanm 0:9b334a45a8ff 2828 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2829 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2830 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2831 /* PERIPHID3 Bit Fields */
bogdanm 0:9b334a45a8ff 2832 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2833 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 2834 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 2835 /* COMPID Bit Fields */
bogdanm 0:9b334a45a8ff 2836 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2837 #define ROM_COMPID_COMPID_SHIFT 0
bogdanm 0:9b334a45a8ff 2838 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
bogdanm 0:9b334a45a8ff 2839
bogdanm 0:9b334a45a8ff 2840 /**
bogdanm 0:9b334a45a8ff 2841 * @}
bogdanm 0:9b334a45a8ff 2842 */ /* end of group ROM_Register_Masks */
bogdanm 0:9b334a45a8ff 2843
bogdanm 0:9b334a45a8ff 2844
bogdanm 0:9b334a45a8ff 2845 /* ROM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2846 /** Peripheral ROM base address */
bogdanm 0:9b334a45a8ff 2847 #define ROM_BASE (0xF0002000u)
bogdanm 0:9b334a45a8ff 2848 /** Peripheral ROM base pointer */
bogdanm 0:9b334a45a8ff 2849 #define ROM ((ROM_Type *)ROM_BASE)
bogdanm 0:9b334a45a8ff 2850 /** Array initializer of ROM peripheral base pointers */
bogdanm 0:9b334a45a8ff 2851 #define ROM_BASES { ROM }
bogdanm 0:9b334a45a8ff 2852
bogdanm 0:9b334a45a8ff 2853 /**
bogdanm 0:9b334a45a8ff 2854 * @}
bogdanm 0:9b334a45a8ff 2855 */ /* end of group ROM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2856
bogdanm 0:9b334a45a8ff 2857
bogdanm 0:9b334a45a8ff 2858 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2859 -- RTC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2860 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2861
bogdanm 0:9b334a45a8ff 2862 /**
bogdanm 0:9b334a45a8ff 2863 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2864 * @{
bogdanm 0:9b334a45a8ff 2865 */
bogdanm 0:9b334a45a8ff 2866
bogdanm 0:9b334a45a8ff 2867 /** RTC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2868 typedef struct {
bogdanm 0:9b334a45a8ff 2869 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2870 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 2871 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 2872 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 2873 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 2874 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 2875 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
bogdanm 0:9b334a45a8ff 2876 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
bogdanm 0:9b334a45a8ff 2877 } RTC_Type;
bogdanm 0:9b334a45a8ff 2878
bogdanm 0:9b334a45a8ff 2879 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2880 -- RTC Register Masks
bogdanm 0:9b334a45a8ff 2881 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2882
bogdanm 0:9b334a45a8ff 2883 /**
bogdanm 0:9b334a45a8ff 2884 * @addtogroup RTC_Register_Masks RTC Register Masks
bogdanm 0:9b334a45a8ff 2885 * @{
bogdanm 0:9b334a45a8ff 2886 */
bogdanm 0:9b334a45a8ff 2887
bogdanm 0:9b334a45a8ff 2888 /* TSR Bit Fields */
bogdanm 0:9b334a45a8ff 2889 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2890 #define RTC_TSR_TSR_SHIFT 0
bogdanm 0:9b334a45a8ff 2891 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
bogdanm 0:9b334a45a8ff 2892 /* TPR Bit Fields */
bogdanm 0:9b334a45a8ff 2893 #define RTC_TPR_TPR_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 2894 #define RTC_TPR_TPR_SHIFT 0
bogdanm 0:9b334a45a8ff 2895 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
bogdanm 0:9b334a45a8ff 2896 /* TAR Bit Fields */
bogdanm 0:9b334a45a8ff 2897 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 2898 #define RTC_TAR_TAR_SHIFT 0
bogdanm 0:9b334a45a8ff 2899 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
bogdanm 0:9b334a45a8ff 2900 /* TCR Bit Fields */
bogdanm 0:9b334a45a8ff 2901 #define RTC_TCR_TCR_MASK 0xFFu
bogdanm 0:9b334a45a8ff 2902 #define RTC_TCR_TCR_SHIFT 0
bogdanm 0:9b334a45a8ff 2903 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
bogdanm 0:9b334a45a8ff 2904 #define RTC_TCR_CIR_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 2905 #define RTC_TCR_CIR_SHIFT 8
bogdanm 0:9b334a45a8ff 2906 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
bogdanm 0:9b334a45a8ff 2907 #define RTC_TCR_TCV_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 2908 #define RTC_TCR_TCV_SHIFT 16
bogdanm 0:9b334a45a8ff 2909 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
bogdanm 0:9b334a45a8ff 2910 #define RTC_TCR_CIC_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 2911 #define RTC_TCR_CIC_SHIFT 24
bogdanm 0:9b334a45a8ff 2912 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
bogdanm 0:9b334a45a8ff 2913 /* CR Bit Fields */
bogdanm 0:9b334a45a8ff 2914 #define RTC_CR_SWR_MASK 0x1u
bogdanm 0:9b334a45a8ff 2915 #define RTC_CR_SWR_SHIFT 0
bogdanm 0:9b334a45a8ff 2916 #define RTC_CR_WPE_MASK 0x2u
bogdanm 0:9b334a45a8ff 2917 #define RTC_CR_WPE_SHIFT 1
bogdanm 0:9b334a45a8ff 2918 #define RTC_CR_SUP_MASK 0x4u
bogdanm 0:9b334a45a8ff 2919 #define RTC_CR_SUP_SHIFT 2
bogdanm 0:9b334a45a8ff 2920 #define RTC_CR_UM_MASK 0x8u
bogdanm 0:9b334a45a8ff 2921 #define RTC_CR_UM_SHIFT 3
bogdanm 0:9b334a45a8ff 2922 #define RTC_CR_OSCE_MASK 0x100u
bogdanm 0:9b334a45a8ff 2923 #define RTC_CR_OSCE_SHIFT 8
bogdanm 0:9b334a45a8ff 2924 #define RTC_CR_CLKO_MASK 0x200u
bogdanm 0:9b334a45a8ff 2925 #define RTC_CR_CLKO_SHIFT 9
bogdanm 0:9b334a45a8ff 2926 #define RTC_CR_SC16P_MASK 0x400u
bogdanm 0:9b334a45a8ff 2927 #define RTC_CR_SC16P_SHIFT 10
bogdanm 0:9b334a45a8ff 2928 #define RTC_CR_SC8P_MASK 0x800u
bogdanm 0:9b334a45a8ff 2929 #define RTC_CR_SC8P_SHIFT 11
bogdanm 0:9b334a45a8ff 2930 #define RTC_CR_SC4P_MASK 0x1000u
bogdanm 0:9b334a45a8ff 2931 #define RTC_CR_SC4P_SHIFT 12
bogdanm 0:9b334a45a8ff 2932 #define RTC_CR_SC2P_MASK 0x2000u
bogdanm 0:9b334a45a8ff 2933 #define RTC_CR_SC2P_SHIFT 13
bogdanm 0:9b334a45a8ff 2934 /* SR Bit Fields */
bogdanm 0:9b334a45a8ff 2935 #define RTC_SR_TIF_MASK 0x1u
bogdanm 0:9b334a45a8ff 2936 #define RTC_SR_TIF_SHIFT 0
bogdanm 0:9b334a45a8ff 2937 #define RTC_SR_TOF_MASK 0x2u
bogdanm 0:9b334a45a8ff 2938 #define RTC_SR_TOF_SHIFT 1
bogdanm 0:9b334a45a8ff 2939 #define RTC_SR_TAF_MASK 0x4u
bogdanm 0:9b334a45a8ff 2940 #define RTC_SR_TAF_SHIFT 2
bogdanm 0:9b334a45a8ff 2941 #define RTC_SR_TCE_MASK 0x10u
bogdanm 0:9b334a45a8ff 2942 #define RTC_SR_TCE_SHIFT 4
bogdanm 0:9b334a45a8ff 2943 /* LR Bit Fields */
bogdanm 0:9b334a45a8ff 2944 #define RTC_LR_TCL_MASK 0x8u
bogdanm 0:9b334a45a8ff 2945 #define RTC_LR_TCL_SHIFT 3
bogdanm 0:9b334a45a8ff 2946 #define RTC_LR_CRL_MASK 0x10u
bogdanm 0:9b334a45a8ff 2947 #define RTC_LR_CRL_SHIFT 4
bogdanm 0:9b334a45a8ff 2948 #define RTC_LR_SRL_MASK 0x20u
bogdanm 0:9b334a45a8ff 2949 #define RTC_LR_SRL_SHIFT 5
bogdanm 0:9b334a45a8ff 2950 #define RTC_LR_LRL_MASK 0x40u
bogdanm 0:9b334a45a8ff 2951 #define RTC_LR_LRL_SHIFT 6
bogdanm 0:9b334a45a8ff 2952 /* IER Bit Fields */
bogdanm 0:9b334a45a8ff 2953 #define RTC_IER_TIIE_MASK 0x1u
bogdanm 0:9b334a45a8ff 2954 #define RTC_IER_TIIE_SHIFT 0
bogdanm 0:9b334a45a8ff 2955 #define RTC_IER_TOIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 2956 #define RTC_IER_TOIE_SHIFT 1
bogdanm 0:9b334a45a8ff 2957 #define RTC_IER_TAIE_MASK 0x4u
bogdanm 0:9b334a45a8ff 2958 #define RTC_IER_TAIE_SHIFT 2
bogdanm 0:9b334a45a8ff 2959 #define RTC_IER_TSIE_MASK 0x10u
bogdanm 0:9b334a45a8ff 2960 #define RTC_IER_TSIE_SHIFT 4
bogdanm 0:9b334a45a8ff 2961 #define RTC_IER_WPON_MASK 0x80u
bogdanm 0:9b334a45a8ff 2962 #define RTC_IER_WPON_SHIFT 7
bogdanm 0:9b334a45a8ff 2963
bogdanm 0:9b334a45a8ff 2964 /**
bogdanm 0:9b334a45a8ff 2965 * @}
bogdanm 0:9b334a45a8ff 2966 */ /* end of group RTC_Register_Masks */
bogdanm 0:9b334a45a8ff 2967
bogdanm 0:9b334a45a8ff 2968
bogdanm 0:9b334a45a8ff 2969 /* RTC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2970 /** Peripheral RTC base address */
bogdanm 0:9b334a45a8ff 2971 #define RTC_BASE (0x4003D000u)
bogdanm 0:9b334a45a8ff 2972 /** Peripheral RTC base pointer */
bogdanm 0:9b334a45a8ff 2973 #define RTC ((RTC_Type *)RTC_BASE)
bogdanm 0:9b334a45a8ff 2974 /** Array initializer of RTC peripheral base pointers */
bogdanm 0:9b334a45a8ff 2975 #define RTC_BASES { RTC }
bogdanm 0:9b334a45a8ff 2976
bogdanm 0:9b334a45a8ff 2977 /**
bogdanm 0:9b334a45a8ff 2978 * @}
bogdanm 0:9b334a45a8ff 2979 */ /* end of group RTC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2980
bogdanm 0:9b334a45a8ff 2981
bogdanm 0:9b334a45a8ff 2982 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2983 -- SIM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2984 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2985
bogdanm 0:9b334a45a8ff 2986 /**
bogdanm 0:9b334a45a8ff 2987 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2988 * @{
bogdanm 0:9b334a45a8ff 2989 */
bogdanm 0:9b334a45a8ff 2990
bogdanm 0:9b334a45a8ff 2991 /** SIM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2992 typedef struct {
bogdanm 0:9b334a45a8ff 2993 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2994 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 2995 uint8_t RESERVED_0[4092];
bogdanm 0:9b334a45a8ff 2996 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
bogdanm 0:9b334a45a8ff 2997 uint8_t RESERVED_1[4];
bogdanm 0:9b334a45a8ff 2998 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
bogdanm 0:9b334a45a8ff 2999 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
bogdanm 0:9b334a45a8ff 3000 uint8_t RESERVED_2[4];
bogdanm 0:9b334a45a8ff 3001 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
bogdanm 0:9b334a45a8ff 3002 uint8_t RESERVED_3[8];
bogdanm 0:9b334a45a8ff 3003 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
bogdanm 0:9b334a45a8ff 3004 uint8_t RESERVED_4[12];
bogdanm 0:9b334a45a8ff 3005 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
bogdanm 0:9b334a45a8ff 3006 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
bogdanm 0:9b334a45a8ff 3007 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
bogdanm 0:9b334a45a8ff 3008 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
bogdanm 0:9b334a45a8ff 3009 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
bogdanm 0:9b334a45a8ff 3010 uint8_t RESERVED_5[4];
bogdanm 0:9b334a45a8ff 3011 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
bogdanm 0:9b334a45a8ff 3012 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
bogdanm 0:9b334a45a8ff 3013 uint8_t RESERVED_6[4];
bogdanm 0:9b334a45a8ff 3014 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
bogdanm 0:9b334a45a8ff 3015 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
bogdanm 0:9b334a45a8ff 3016 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
bogdanm 0:9b334a45a8ff 3017 uint8_t RESERVED_7[156];
bogdanm 0:9b334a45a8ff 3018 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
bogdanm 0:9b334a45a8ff 3019 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
bogdanm 0:9b334a45a8ff 3020 } SIM_Type;
bogdanm 0:9b334a45a8ff 3021
bogdanm 0:9b334a45a8ff 3022 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3023 -- SIM Register Masks
bogdanm 0:9b334a45a8ff 3024 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3025
bogdanm 0:9b334a45a8ff 3026 /**
bogdanm 0:9b334a45a8ff 3027 * @addtogroup SIM_Register_Masks SIM Register Masks
bogdanm 0:9b334a45a8ff 3028 * @{
bogdanm 0:9b334a45a8ff 3029 */
bogdanm 0:9b334a45a8ff 3030
bogdanm 0:9b334a45a8ff 3031 /* SOPT1 Bit Fields */
bogdanm 0:9b334a45a8ff 3032 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
bogdanm 0:9b334a45a8ff 3033 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
bogdanm 0:9b334a45a8ff 3034 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
bogdanm 0:9b334a45a8ff 3035 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 3036 #define SIM_SOPT1_USBVSTBY_SHIFT 29
bogdanm 0:9b334a45a8ff 3037 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 3038 #define SIM_SOPT1_USBSSTBY_SHIFT 30
bogdanm 0:9b334a45a8ff 3039 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 3040 #define SIM_SOPT1_USBREGEN_SHIFT 31
bogdanm 0:9b334a45a8ff 3041 /* SOPT1CFG Bit Fields */
bogdanm 0:9b334a45a8ff 3042 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 3043 #define SIM_SOPT1CFG_URWE_SHIFT 24
bogdanm 0:9b334a45a8ff 3044 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 3045 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
bogdanm 0:9b334a45a8ff 3046 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 3047 #define SIM_SOPT1CFG_USSWE_SHIFT 26
bogdanm 0:9b334a45a8ff 3048 /* SOPT2 Bit Fields */
bogdanm 0:9b334a45a8ff 3049 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 3050 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 3051 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
bogdanm 0:9b334a45a8ff 3052 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
bogdanm 0:9b334a45a8ff 3053 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
bogdanm 0:9b334a45a8ff 3054 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
bogdanm 0:9b334a45a8ff 3055 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
bogdanm 0:9b334a45a8ff 3056 #define SIM_SOPT2_USBSRC_MASK 0x40000u
bogdanm 0:9b334a45a8ff 3057 #define SIM_SOPT2_USBSRC_SHIFT 18
bogdanm 0:9b334a45a8ff 3058 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
bogdanm 0:9b334a45a8ff 3059 #define SIM_SOPT2_TPMSRC_SHIFT 24
bogdanm 0:9b334a45a8ff 3060 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
bogdanm 0:9b334a45a8ff 3061 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
bogdanm 0:9b334a45a8ff 3062 #define SIM_SOPT2_UART0SRC_SHIFT 26
bogdanm 0:9b334a45a8ff 3063 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
bogdanm 0:9b334a45a8ff 3064 /* SOPT4 Bit Fields */
bogdanm 0:9b334a45a8ff 3065 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
bogdanm 0:9b334a45a8ff 3066 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
bogdanm 0:9b334a45a8ff 3067 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
bogdanm 0:9b334a45a8ff 3068 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
bogdanm 0:9b334a45a8ff 3069 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
bogdanm 0:9b334a45a8ff 3070 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 3071 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
bogdanm 0:9b334a45a8ff 3072 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 3073 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
bogdanm 0:9b334a45a8ff 3074 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 3075 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
bogdanm 0:9b334a45a8ff 3076 /* SOPT5 Bit Fields */
bogdanm 0:9b334a45a8ff 3077 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
bogdanm 0:9b334a45a8ff 3078 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
bogdanm 0:9b334a45a8ff 3079 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
bogdanm 0:9b334a45a8ff 3080 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
bogdanm 0:9b334a45a8ff 3081 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
bogdanm 0:9b334a45a8ff 3082 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
bogdanm 0:9b334a45a8ff 3083 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
bogdanm 0:9b334a45a8ff 3084 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
bogdanm 0:9b334a45a8ff 3085 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
bogdanm 0:9b334a45a8ff 3086 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
bogdanm 0:9b334a45a8ff 3087 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
bogdanm 0:9b334a45a8ff 3088 #define SIM_SOPT5_UART0ODE_SHIFT 16
bogdanm 0:9b334a45a8ff 3089 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
bogdanm 0:9b334a45a8ff 3090 #define SIM_SOPT5_UART1ODE_SHIFT 17
bogdanm 0:9b334a45a8ff 3091 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
bogdanm 0:9b334a45a8ff 3092 #define SIM_SOPT5_UART2ODE_SHIFT 18
bogdanm 0:9b334a45a8ff 3093 /* SOPT7 Bit Fields */
bogdanm 0:9b334a45a8ff 3094 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
bogdanm 0:9b334a45a8ff 3095 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 3096 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
bogdanm 0:9b334a45a8ff 3097 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 3098 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 3099 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 3100 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
bogdanm 0:9b334a45a8ff 3101 /* SDID Bit Fields */
bogdanm 0:9b334a45a8ff 3102 #define SIM_SDID_PINID_MASK 0xFu
bogdanm 0:9b334a45a8ff 3103 #define SIM_SDID_PINID_SHIFT 0
bogdanm 0:9b334a45a8ff 3104 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
bogdanm 0:9b334a45a8ff 3105 #define SIM_SDID_DIEID_MASK 0xF80u
bogdanm 0:9b334a45a8ff 3106 #define SIM_SDID_DIEID_SHIFT 7
bogdanm 0:9b334a45a8ff 3107 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
bogdanm 0:9b334a45a8ff 3108 #define SIM_SDID_REVID_MASK 0xF000u
bogdanm 0:9b334a45a8ff 3109 #define SIM_SDID_REVID_SHIFT 12
bogdanm 0:9b334a45a8ff 3110 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
bogdanm 0:9b334a45a8ff 3111 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
bogdanm 0:9b334a45a8ff 3112 #define SIM_SDID_SRAMSIZE_SHIFT 16
bogdanm 0:9b334a45a8ff 3113 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
bogdanm 0:9b334a45a8ff 3114 #define SIM_SDID_SERIESID_MASK 0xF00000u
bogdanm 0:9b334a45a8ff 3115 #define SIM_SDID_SERIESID_SHIFT 20
bogdanm 0:9b334a45a8ff 3116 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
bogdanm 0:9b334a45a8ff 3117 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 3118 #define SIM_SDID_SUBFAMID_SHIFT 24
bogdanm 0:9b334a45a8ff 3119 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
bogdanm 0:9b334a45a8ff 3120 #define SIM_SDID_FAMID_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 3121 #define SIM_SDID_FAMID_SHIFT 28
bogdanm 0:9b334a45a8ff 3122 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
bogdanm 0:9b334a45a8ff 3123 /* SCGC4 Bit Fields */
bogdanm 0:9b334a45a8ff 3124 #define SIM_SCGC4_I2C0_MASK 0x40u
bogdanm 0:9b334a45a8ff 3125 #define SIM_SCGC4_I2C0_SHIFT 6
bogdanm 0:9b334a45a8ff 3126 #define SIM_SCGC4_I2C1_MASK 0x80u
bogdanm 0:9b334a45a8ff 3127 #define SIM_SCGC4_I2C1_SHIFT 7
bogdanm 0:9b334a45a8ff 3128 #define SIM_SCGC4_UART0_MASK 0x400u
bogdanm 0:9b334a45a8ff 3129 #define SIM_SCGC4_UART0_SHIFT 10
bogdanm 0:9b334a45a8ff 3130 #define SIM_SCGC4_UART1_MASK 0x800u
bogdanm 0:9b334a45a8ff 3131 #define SIM_SCGC4_UART1_SHIFT 11
bogdanm 0:9b334a45a8ff 3132 #define SIM_SCGC4_UART2_MASK 0x1000u
bogdanm 0:9b334a45a8ff 3133 #define SIM_SCGC4_UART2_SHIFT 12
bogdanm 0:9b334a45a8ff 3134 #define SIM_SCGC4_USBOTG_MASK 0x40000u
bogdanm 0:9b334a45a8ff 3135 #define SIM_SCGC4_USBOTG_SHIFT 18
bogdanm 0:9b334a45a8ff 3136 #define SIM_SCGC4_CMP_MASK 0x80000u
bogdanm 0:9b334a45a8ff 3137 #define SIM_SCGC4_CMP_SHIFT 19
bogdanm 0:9b334a45a8ff 3138 #define SIM_SCGC4_SPI0_MASK 0x400000u
bogdanm 0:9b334a45a8ff 3139 #define SIM_SCGC4_SPI0_SHIFT 22
bogdanm 0:9b334a45a8ff 3140 #define SIM_SCGC4_SPI1_MASK 0x800000u
bogdanm 0:9b334a45a8ff 3141 #define SIM_SCGC4_SPI1_SHIFT 23
bogdanm 0:9b334a45a8ff 3142 /* SCGC5 Bit Fields */
bogdanm 0:9b334a45a8ff 3143 #define SIM_SCGC5_LPTMR_MASK 0x1u
bogdanm 0:9b334a45a8ff 3144 #define SIM_SCGC5_LPTMR_SHIFT 0
bogdanm 0:9b334a45a8ff 3145 #define SIM_SCGC5_TSI_MASK 0x20u
bogdanm 0:9b334a45a8ff 3146 #define SIM_SCGC5_TSI_SHIFT 5
bogdanm 0:9b334a45a8ff 3147 #define SIM_SCGC5_PORTA_MASK 0x200u
bogdanm 0:9b334a45a8ff 3148 #define SIM_SCGC5_PORTA_SHIFT 9
bogdanm 0:9b334a45a8ff 3149 #define SIM_SCGC5_PORTB_MASK 0x400u
bogdanm 0:9b334a45a8ff 3150 #define SIM_SCGC5_PORTB_SHIFT 10
bogdanm 0:9b334a45a8ff 3151 #define SIM_SCGC5_PORTC_MASK 0x800u
bogdanm 0:9b334a45a8ff 3152 #define SIM_SCGC5_PORTC_SHIFT 11
bogdanm 0:9b334a45a8ff 3153 #define SIM_SCGC5_PORTD_MASK 0x1000u
bogdanm 0:9b334a45a8ff 3154 #define SIM_SCGC5_PORTD_SHIFT 12
bogdanm 0:9b334a45a8ff 3155 #define SIM_SCGC5_PORTE_MASK 0x2000u
bogdanm 0:9b334a45a8ff 3156 #define SIM_SCGC5_PORTE_SHIFT 13
bogdanm 0:9b334a45a8ff 3157 /* SCGC6 Bit Fields */
bogdanm 0:9b334a45a8ff 3158 #define SIM_SCGC6_FTF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3159 #define SIM_SCGC6_FTF_SHIFT 0
bogdanm 0:9b334a45a8ff 3160 #define SIM_SCGC6_DMAMUX_MASK 0x2u
bogdanm 0:9b334a45a8ff 3161 #define SIM_SCGC6_DMAMUX_SHIFT 1
bogdanm 0:9b334a45a8ff 3162 #define SIM_SCGC6_I2S_MASK 0x8000u
bogdanm 0:9b334a45a8ff 3163 #define SIM_SCGC6_I2S_SHIFT 15
bogdanm 0:9b334a45a8ff 3164 #define SIM_SCGC6_PIT_MASK 0x800000u
bogdanm 0:9b334a45a8ff 3165 #define SIM_SCGC6_PIT_SHIFT 23
bogdanm 0:9b334a45a8ff 3166 #define SIM_SCGC6_TPM0_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 3167 #define SIM_SCGC6_TPM0_SHIFT 24
bogdanm 0:9b334a45a8ff 3168 #define SIM_SCGC6_TPM1_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 3169 #define SIM_SCGC6_TPM1_SHIFT 25
bogdanm 0:9b334a45a8ff 3170 #define SIM_SCGC6_TPM2_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 3171 #define SIM_SCGC6_TPM2_SHIFT 26
bogdanm 0:9b334a45a8ff 3172 #define SIM_SCGC6_ADC0_MASK 0x8000000u
bogdanm 0:9b334a45a8ff 3173 #define SIM_SCGC6_ADC0_SHIFT 27
bogdanm 0:9b334a45a8ff 3174 #define SIM_SCGC6_RTC_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 3175 #define SIM_SCGC6_RTC_SHIFT 29
bogdanm 0:9b334a45a8ff 3176 #define SIM_SCGC6_DAC0_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 3177 #define SIM_SCGC6_DAC0_SHIFT 31
bogdanm 0:9b334a45a8ff 3178 /* SCGC7 Bit Fields */
bogdanm 0:9b334a45a8ff 3179 #define SIM_SCGC7_DMA_MASK 0x100u
bogdanm 0:9b334a45a8ff 3180 #define SIM_SCGC7_DMA_SHIFT 8
bogdanm 0:9b334a45a8ff 3181 /* CLKDIV1 Bit Fields */
bogdanm 0:9b334a45a8ff 3182 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
bogdanm 0:9b334a45a8ff 3183 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
bogdanm 0:9b334a45a8ff 3184 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
bogdanm 0:9b334a45a8ff 3185 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 3186 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
bogdanm 0:9b334a45a8ff 3187 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
bogdanm 0:9b334a45a8ff 3188 /* FCFG1 Bit Fields */
bogdanm 0:9b334a45a8ff 3189 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
bogdanm 0:9b334a45a8ff 3190 #define SIM_FCFG1_FLASHDIS_SHIFT 0
bogdanm 0:9b334a45a8ff 3191 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3192 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
bogdanm 0:9b334a45a8ff 3193 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 3194 #define SIM_FCFG1_PFSIZE_SHIFT 24
bogdanm 0:9b334a45a8ff 3195 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
bogdanm 0:9b334a45a8ff 3196 /* FCFG2 Bit Fields */
bogdanm 0:9b334a45a8ff 3197 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
bogdanm 0:9b334a45a8ff 3198 #define SIM_FCFG2_MAXADDR1_SHIFT 16
bogdanm 0:9b334a45a8ff 3199 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
bogdanm 0:9b334a45a8ff 3200 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
bogdanm 0:9b334a45a8ff 3201 #define SIM_FCFG2_MAXADDR0_SHIFT 24
bogdanm 0:9b334a45a8ff 3202 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
bogdanm 0:9b334a45a8ff 3203 /* UIDMH Bit Fields */
bogdanm 0:9b334a45a8ff 3204 #define SIM_UIDMH_UID_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3205 #define SIM_UIDMH_UID_SHIFT 0
bogdanm 0:9b334a45a8ff 3206 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
bogdanm 0:9b334a45a8ff 3207 /* UIDML Bit Fields */
bogdanm 0:9b334a45a8ff 3208 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3209 #define SIM_UIDML_UID_SHIFT 0
bogdanm 0:9b334a45a8ff 3210 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
bogdanm 0:9b334a45a8ff 3211 /* UIDL Bit Fields */
bogdanm 0:9b334a45a8ff 3212 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3213 #define SIM_UIDL_UID_SHIFT 0
bogdanm 0:9b334a45a8ff 3214 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
bogdanm 0:9b334a45a8ff 3215 /* COPC Bit Fields */
bogdanm 0:9b334a45a8ff 3216 #define SIM_COPC_COPW_MASK 0x1u
bogdanm 0:9b334a45a8ff 3217 #define SIM_COPC_COPW_SHIFT 0
bogdanm 0:9b334a45a8ff 3218 #define SIM_COPC_COPCLKS_MASK 0x2u
bogdanm 0:9b334a45a8ff 3219 #define SIM_COPC_COPCLKS_SHIFT 1
bogdanm 0:9b334a45a8ff 3220 #define SIM_COPC_COPT_MASK 0xCu
bogdanm 0:9b334a45a8ff 3221 #define SIM_COPC_COPT_SHIFT 2
bogdanm 0:9b334a45a8ff 3222 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
bogdanm 0:9b334a45a8ff 3223 /* SRVCOP Bit Fields */
bogdanm 0:9b334a45a8ff 3224 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3225 #define SIM_SRVCOP_SRVCOP_SHIFT 0
bogdanm 0:9b334a45a8ff 3226 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
bogdanm 0:9b334a45a8ff 3227
bogdanm 0:9b334a45a8ff 3228 /**
bogdanm 0:9b334a45a8ff 3229 * @}
bogdanm 0:9b334a45a8ff 3230 */ /* end of group SIM_Register_Masks */
bogdanm 0:9b334a45a8ff 3231
bogdanm 0:9b334a45a8ff 3232
bogdanm 0:9b334a45a8ff 3233 /* SIM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3234 /** Peripheral SIM base address */
bogdanm 0:9b334a45a8ff 3235 #define SIM_BASE (0x40047000u)
bogdanm 0:9b334a45a8ff 3236 /** Peripheral SIM base pointer */
bogdanm 0:9b334a45a8ff 3237 #define SIM ((SIM_Type *)SIM_BASE)
bogdanm 0:9b334a45a8ff 3238 /** Array initializer of SIM peripheral base pointers */
bogdanm 0:9b334a45a8ff 3239 #define SIM_BASES { SIM }
bogdanm 0:9b334a45a8ff 3240
bogdanm 0:9b334a45a8ff 3241 /**
bogdanm 0:9b334a45a8ff 3242 * @}
bogdanm 0:9b334a45a8ff 3243 */ /* end of group SIM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3244
bogdanm 0:9b334a45a8ff 3245
bogdanm 0:9b334a45a8ff 3246 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3247 -- SMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3248 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3249
bogdanm 0:9b334a45a8ff 3250 /**
bogdanm 0:9b334a45a8ff 3251 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3252 * @{
bogdanm 0:9b334a45a8ff 3253 */
bogdanm 0:9b334a45a8ff 3254
bogdanm 0:9b334a45a8ff 3255 /** SMC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3256 typedef struct {
bogdanm 0:9b334a45a8ff 3257 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3258 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 3259 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 3260 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 3261 } SMC_Type;
bogdanm 0:9b334a45a8ff 3262
bogdanm 0:9b334a45a8ff 3263 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3264 -- SMC Register Masks
bogdanm 0:9b334a45a8ff 3265 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3266
bogdanm 0:9b334a45a8ff 3267 /**
bogdanm 0:9b334a45a8ff 3268 * @addtogroup SMC_Register_Masks SMC Register Masks
bogdanm 0:9b334a45a8ff 3269 * @{
bogdanm 0:9b334a45a8ff 3270 */
bogdanm 0:9b334a45a8ff 3271
bogdanm 0:9b334a45a8ff 3272 /* PMPROT Bit Fields */
bogdanm 0:9b334a45a8ff 3273 #define SMC_PMPROT_AVLLS_MASK 0x2u
bogdanm 0:9b334a45a8ff 3274 #define SMC_PMPROT_AVLLS_SHIFT 1
bogdanm 0:9b334a45a8ff 3275 #define SMC_PMPROT_ALLS_MASK 0x8u
bogdanm 0:9b334a45a8ff 3276 #define SMC_PMPROT_ALLS_SHIFT 3
bogdanm 0:9b334a45a8ff 3277 #define SMC_PMPROT_AVLP_MASK 0x20u
bogdanm 0:9b334a45a8ff 3278 #define SMC_PMPROT_AVLP_SHIFT 5
bogdanm 0:9b334a45a8ff 3279 /* PMCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 3280 #define SMC_PMCTRL_STOPM_MASK 0x7u
bogdanm 0:9b334a45a8ff 3281 #define SMC_PMCTRL_STOPM_SHIFT 0
bogdanm 0:9b334a45a8ff 3282 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
bogdanm 0:9b334a45a8ff 3283 #define SMC_PMCTRL_STOPA_MASK 0x8u
bogdanm 0:9b334a45a8ff 3284 #define SMC_PMCTRL_STOPA_SHIFT 3
bogdanm 0:9b334a45a8ff 3285 #define SMC_PMCTRL_RUNM_MASK 0x60u
bogdanm 0:9b334a45a8ff 3286 #define SMC_PMCTRL_RUNM_SHIFT 5
bogdanm 0:9b334a45a8ff 3287 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
bogdanm 0:9b334a45a8ff 3288 /* STOPCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 3289 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
bogdanm 0:9b334a45a8ff 3290 #define SMC_STOPCTRL_VLLSM_SHIFT 0
bogdanm 0:9b334a45a8ff 3291 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
bogdanm 0:9b334a45a8ff 3292 #define SMC_STOPCTRL_PORPO_MASK 0x20u
bogdanm 0:9b334a45a8ff 3293 #define SMC_STOPCTRL_PORPO_SHIFT 5
bogdanm 0:9b334a45a8ff 3294 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
bogdanm 0:9b334a45a8ff 3295 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
bogdanm 0:9b334a45a8ff 3296 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
bogdanm 0:9b334a45a8ff 3297 /* PMSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 3298 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 3299 #define SMC_PMSTAT_PMSTAT_SHIFT 0
bogdanm 0:9b334a45a8ff 3300 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
bogdanm 0:9b334a45a8ff 3301
bogdanm 0:9b334a45a8ff 3302 /**
bogdanm 0:9b334a45a8ff 3303 * @}
bogdanm 0:9b334a45a8ff 3304 */ /* end of group SMC_Register_Masks */
bogdanm 0:9b334a45a8ff 3305
bogdanm 0:9b334a45a8ff 3306
bogdanm 0:9b334a45a8ff 3307 /* SMC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3308 /** Peripheral SMC base address */
bogdanm 0:9b334a45a8ff 3309 #define SMC_BASE (0x4007E000u)
bogdanm 0:9b334a45a8ff 3310 /** Peripheral SMC base pointer */
bogdanm 0:9b334a45a8ff 3311 #define SMC ((SMC_Type *)SMC_BASE)
bogdanm 0:9b334a45a8ff 3312 /** Array initializer of SMC peripheral base pointers */
bogdanm 0:9b334a45a8ff 3313 #define SMC_BASES { SMC }
bogdanm 0:9b334a45a8ff 3314
bogdanm 0:9b334a45a8ff 3315 /**
bogdanm 0:9b334a45a8ff 3316 * @}
bogdanm 0:9b334a45a8ff 3317 */ /* end of group SMC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3318
bogdanm 0:9b334a45a8ff 3319
bogdanm 0:9b334a45a8ff 3320 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3321 -- SPI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3322 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3323
bogdanm 0:9b334a45a8ff 3324 /**
bogdanm 0:9b334a45a8ff 3325 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3326 * @{
bogdanm 0:9b334a45a8ff 3327 */
bogdanm 0:9b334a45a8ff 3328
bogdanm 0:9b334a45a8ff 3329 /** SPI - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3330 typedef struct {
bogdanm 0:9b334a45a8ff 3331 __I uint8_t S; /**< SPI status register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3332 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 3333 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
bogdanm 0:9b334a45a8ff 3334 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
bogdanm 0:9b334a45a8ff 3335 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3336 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
bogdanm 0:9b334a45a8ff 3337 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
bogdanm 0:9b334a45a8ff 3338 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
bogdanm 0:9b334a45a8ff 3339 uint8_t RESERVED_0[2];
bogdanm 0:9b334a45a8ff 3340 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
bogdanm 0:9b334a45a8ff 3341 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
bogdanm 0:9b334a45a8ff 3342 } SPI_Type;
bogdanm 0:9b334a45a8ff 3343
bogdanm 0:9b334a45a8ff 3344 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3345 -- SPI Register Masks
bogdanm 0:9b334a45a8ff 3346 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3347
bogdanm 0:9b334a45a8ff 3348 /**
bogdanm 0:9b334a45a8ff 3349 * @addtogroup SPI_Register_Masks SPI Register Masks
bogdanm 0:9b334a45a8ff 3350 * @{
bogdanm 0:9b334a45a8ff 3351 */
bogdanm 0:9b334a45a8ff 3352
bogdanm 0:9b334a45a8ff 3353 /* S Bit Fields */
bogdanm 0:9b334a45a8ff 3354 #define SPI_S_RFIFOEF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3355 #define SPI_S_RFIFOEF_SHIFT 0
bogdanm 0:9b334a45a8ff 3356 #define SPI_S_TXFULLF_MASK 0x2u
bogdanm 0:9b334a45a8ff 3357 #define SPI_S_TXFULLF_SHIFT 1
bogdanm 0:9b334a45a8ff 3358 #define SPI_S_TNEAREF_MASK 0x4u
bogdanm 0:9b334a45a8ff 3359 #define SPI_S_TNEAREF_SHIFT 2
bogdanm 0:9b334a45a8ff 3360 #define SPI_S_RNFULLF_MASK 0x8u
bogdanm 0:9b334a45a8ff 3361 #define SPI_S_RNFULLF_SHIFT 3
bogdanm 0:9b334a45a8ff 3362 #define SPI_S_MODF_MASK 0x10u
bogdanm 0:9b334a45a8ff 3363 #define SPI_S_MODF_SHIFT 4
bogdanm 0:9b334a45a8ff 3364 #define SPI_S_SPTEF_MASK 0x20u
bogdanm 0:9b334a45a8ff 3365 #define SPI_S_SPTEF_SHIFT 5
bogdanm 0:9b334a45a8ff 3366 #define SPI_S_SPMF_MASK 0x40u
bogdanm 0:9b334a45a8ff 3367 #define SPI_S_SPMF_SHIFT 6
bogdanm 0:9b334a45a8ff 3368 #define SPI_S_SPRF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3369 #define SPI_S_SPRF_SHIFT 7
bogdanm 0:9b334a45a8ff 3370 /* BR Bit Fields */
bogdanm 0:9b334a45a8ff 3371 #define SPI_BR_SPR_MASK 0xFu
bogdanm 0:9b334a45a8ff 3372 #define SPI_BR_SPR_SHIFT 0
bogdanm 0:9b334a45a8ff 3373 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
bogdanm 0:9b334a45a8ff 3374 #define SPI_BR_SPPR_MASK 0x70u
bogdanm 0:9b334a45a8ff 3375 #define SPI_BR_SPPR_SHIFT 4
bogdanm 0:9b334a45a8ff 3376 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
bogdanm 0:9b334a45a8ff 3377 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 3378 #define SPI_C2_SPC0_MASK 0x1u
bogdanm 0:9b334a45a8ff 3379 #define SPI_C2_SPC0_SHIFT 0
bogdanm 0:9b334a45a8ff 3380 #define SPI_C2_SPISWAI_MASK 0x2u
bogdanm 0:9b334a45a8ff 3381 #define SPI_C2_SPISWAI_SHIFT 1
bogdanm 0:9b334a45a8ff 3382 #define SPI_C2_RXDMAE_MASK 0x4u
bogdanm 0:9b334a45a8ff 3383 #define SPI_C2_RXDMAE_SHIFT 2
bogdanm 0:9b334a45a8ff 3384 #define SPI_C2_BIDIROE_MASK 0x8u
bogdanm 0:9b334a45a8ff 3385 #define SPI_C2_BIDIROE_SHIFT 3
bogdanm 0:9b334a45a8ff 3386 #define SPI_C2_MODFEN_MASK 0x10u
bogdanm 0:9b334a45a8ff 3387 #define SPI_C2_MODFEN_SHIFT 4
bogdanm 0:9b334a45a8ff 3388 #define SPI_C2_TXDMAE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3389 #define SPI_C2_TXDMAE_SHIFT 5
bogdanm 0:9b334a45a8ff 3390 #define SPI_C2_SPIMODE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3391 #define SPI_C2_SPIMODE_SHIFT 6
bogdanm 0:9b334a45a8ff 3392 #define SPI_C2_SPMIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3393 #define SPI_C2_SPMIE_SHIFT 7
bogdanm 0:9b334a45a8ff 3394 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 3395 #define SPI_C1_LSBFE_MASK 0x1u
bogdanm 0:9b334a45a8ff 3396 #define SPI_C1_LSBFE_SHIFT 0
bogdanm 0:9b334a45a8ff 3397 #define SPI_C1_SSOE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3398 #define SPI_C1_SSOE_SHIFT 1
bogdanm 0:9b334a45a8ff 3399 #define SPI_C1_CPHA_MASK 0x4u
bogdanm 0:9b334a45a8ff 3400 #define SPI_C1_CPHA_SHIFT 2
bogdanm 0:9b334a45a8ff 3401 #define SPI_C1_CPOL_MASK 0x8u
bogdanm 0:9b334a45a8ff 3402 #define SPI_C1_CPOL_SHIFT 3
bogdanm 0:9b334a45a8ff 3403 #define SPI_C1_MSTR_MASK 0x10u
bogdanm 0:9b334a45a8ff 3404 #define SPI_C1_MSTR_SHIFT 4
bogdanm 0:9b334a45a8ff 3405 #define SPI_C1_SPTIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3406 #define SPI_C1_SPTIE_SHIFT 5
bogdanm 0:9b334a45a8ff 3407 #define SPI_C1_SPE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3408 #define SPI_C1_SPE_SHIFT 6
bogdanm 0:9b334a45a8ff 3409 #define SPI_C1_SPIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3410 #define SPI_C1_SPIE_SHIFT 7
bogdanm 0:9b334a45a8ff 3411 /* ML Bit Fields */
bogdanm 0:9b334a45a8ff 3412 #define SPI_ML_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3413 #define SPI_ML_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 3414 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
bogdanm 0:9b334a45a8ff 3415 /* MH Bit Fields */
bogdanm 0:9b334a45a8ff 3416 #define SPI_MH_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3417 #define SPI_MH_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 3418 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
bogdanm 0:9b334a45a8ff 3419 /* DL Bit Fields */
bogdanm 0:9b334a45a8ff 3420 #define SPI_DL_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3421 #define SPI_DL_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 3422 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
bogdanm 0:9b334a45a8ff 3423 /* DH Bit Fields */
bogdanm 0:9b334a45a8ff 3424 #define SPI_DH_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3425 #define SPI_DH_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 3426 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
bogdanm 0:9b334a45a8ff 3427 /* CI Bit Fields */
bogdanm 0:9b334a45a8ff 3428 #define SPI_CI_SPRFCI_MASK 0x1u
bogdanm 0:9b334a45a8ff 3429 #define SPI_CI_SPRFCI_SHIFT 0
bogdanm 0:9b334a45a8ff 3430 #define SPI_CI_SPTEFCI_MASK 0x2u
bogdanm 0:9b334a45a8ff 3431 #define SPI_CI_SPTEFCI_SHIFT 1
bogdanm 0:9b334a45a8ff 3432 #define SPI_CI_RNFULLFCI_MASK 0x4u
bogdanm 0:9b334a45a8ff 3433 #define SPI_CI_RNFULLFCI_SHIFT 2
bogdanm 0:9b334a45a8ff 3434 #define SPI_CI_TNEAREFCI_MASK 0x8u
bogdanm 0:9b334a45a8ff 3435 #define SPI_CI_TNEAREFCI_SHIFT 3
bogdanm 0:9b334a45a8ff 3436 #define SPI_CI_RXFOF_MASK 0x10u
bogdanm 0:9b334a45a8ff 3437 #define SPI_CI_RXFOF_SHIFT 4
bogdanm 0:9b334a45a8ff 3438 #define SPI_CI_TXFOF_MASK 0x20u
bogdanm 0:9b334a45a8ff 3439 #define SPI_CI_TXFOF_SHIFT 5
bogdanm 0:9b334a45a8ff 3440 #define SPI_CI_RXFERR_MASK 0x40u
bogdanm 0:9b334a45a8ff 3441 #define SPI_CI_RXFERR_SHIFT 6
bogdanm 0:9b334a45a8ff 3442 #define SPI_CI_TXFERR_MASK 0x80u
bogdanm 0:9b334a45a8ff 3443 #define SPI_CI_TXFERR_SHIFT 7
bogdanm 0:9b334a45a8ff 3444 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 3445 #define SPI_C3_FIFOMODE_MASK 0x1u
bogdanm 0:9b334a45a8ff 3446 #define SPI_C3_FIFOMODE_SHIFT 0
bogdanm 0:9b334a45a8ff 3447 #define SPI_C3_RNFULLIEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 3448 #define SPI_C3_RNFULLIEN_SHIFT 1
bogdanm 0:9b334a45a8ff 3449 #define SPI_C3_TNEARIEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 3450 #define SPI_C3_TNEARIEN_SHIFT 2
bogdanm 0:9b334a45a8ff 3451 #define SPI_C3_INTCLR_MASK 0x8u
bogdanm 0:9b334a45a8ff 3452 #define SPI_C3_INTCLR_SHIFT 3
bogdanm 0:9b334a45a8ff 3453 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
bogdanm 0:9b334a45a8ff 3454 #define SPI_C3_RNFULLF_MARK_SHIFT 4
bogdanm 0:9b334a45a8ff 3455 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
bogdanm 0:9b334a45a8ff 3456 #define SPI_C3_TNEAREF_MARK_SHIFT 5
bogdanm 0:9b334a45a8ff 3457
bogdanm 0:9b334a45a8ff 3458 /**
bogdanm 0:9b334a45a8ff 3459 * @}
bogdanm 0:9b334a45a8ff 3460 */ /* end of group SPI_Register_Masks */
bogdanm 0:9b334a45a8ff 3461
bogdanm 0:9b334a45a8ff 3462
bogdanm 0:9b334a45a8ff 3463 /* SPI - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3464 /** Peripheral SPI0 base address */
bogdanm 0:9b334a45a8ff 3465 #define SPI0_BASE (0x40076000u)
bogdanm 0:9b334a45a8ff 3466 /** Peripheral SPI0 base pointer */
bogdanm 0:9b334a45a8ff 3467 #define SPI0 ((SPI_Type *)SPI0_BASE)
bogdanm 0:9b334a45a8ff 3468 /** Peripheral SPI1 base address */
bogdanm 0:9b334a45a8ff 3469 #define SPI1_BASE (0x40077000u)
bogdanm 0:9b334a45a8ff 3470 /** Peripheral SPI1 base pointer */
bogdanm 0:9b334a45a8ff 3471 #define SPI1 ((SPI_Type *)SPI1_BASE)
bogdanm 0:9b334a45a8ff 3472 /** Array initializer of SPI peripheral base pointers */
bogdanm 0:9b334a45a8ff 3473 #define SPI_BASES { SPI0, SPI1 }
bogdanm 0:9b334a45a8ff 3474
bogdanm 0:9b334a45a8ff 3475 /**
bogdanm 0:9b334a45a8ff 3476 * @}
bogdanm 0:9b334a45a8ff 3477 */ /* end of group SPI_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3478
bogdanm 0:9b334a45a8ff 3479
bogdanm 0:9b334a45a8ff 3480 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3481 -- TPM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3482 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3483
bogdanm 0:9b334a45a8ff 3484 /**
bogdanm 0:9b334a45a8ff 3485 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3486 * @{
bogdanm 0:9b334a45a8ff 3487 */
bogdanm 0:9b334a45a8ff 3488
bogdanm 0:9b334a45a8ff 3489 /** TPM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3490 typedef struct {
bogdanm 0:9b334a45a8ff 3491 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3492 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3493 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3494 struct { /* offset: 0xC, array step: 0x8 */
bogdanm 0:9b334a45a8ff 3495 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
bogdanm 0:9b334a45a8ff 3496 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
bogdanm 0:9b334a45a8ff 3497 } CONTROLS[6];
bogdanm 0:9b334a45a8ff 3498 uint8_t RESERVED_0[20];
bogdanm 0:9b334a45a8ff 3499 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
bogdanm 0:9b334a45a8ff 3500 uint8_t RESERVED_1[48];
bogdanm 0:9b334a45a8ff 3501 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
bogdanm 0:9b334a45a8ff 3502 } TPM_Type;
bogdanm 0:9b334a45a8ff 3503
bogdanm 0:9b334a45a8ff 3504 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3505 -- TPM Register Masks
bogdanm 0:9b334a45a8ff 3506 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3507
bogdanm 0:9b334a45a8ff 3508 /**
bogdanm 0:9b334a45a8ff 3509 * @addtogroup TPM_Register_Masks TPM Register Masks
bogdanm 0:9b334a45a8ff 3510 * @{
bogdanm 0:9b334a45a8ff 3511 */
bogdanm 0:9b334a45a8ff 3512
bogdanm 0:9b334a45a8ff 3513 /* SC Bit Fields */
bogdanm 0:9b334a45a8ff 3514 #define TPM_SC_PS_MASK 0x7u
bogdanm 0:9b334a45a8ff 3515 #define TPM_SC_PS_SHIFT 0
bogdanm 0:9b334a45a8ff 3516 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
bogdanm 0:9b334a45a8ff 3517 #define TPM_SC_CMOD_MASK 0x18u
bogdanm 0:9b334a45a8ff 3518 #define TPM_SC_CMOD_SHIFT 3
bogdanm 0:9b334a45a8ff 3519 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
bogdanm 0:9b334a45a8ff 3520 #define TPM_SC_CPWMS_MASK 0x20u
bogdanm 0:9b334a45a8ff 3521 #define TPM_SC_CPWMS_SHIFT 5
bogdanm 0:9b334a45a8ff 3522 #define TPM_SC_TOIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3523 #define TPM_SC_TOIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3524 #define TPM_SC_TOF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3525 #define TPM_SC_TOF_SHIFT 7
bogdanm 0:9b334a45a8ff 3526 #define TPM_SC_DMA_MASK 0x100u
bogdanm 0:9b334a45a8ff 3527 #define TPM_SC_DMA_SHIFT 8
bogdanm 0:9b334a45a8ff 3528 /* CNT Bit Fields */
bogdanm 0:9b334a45a8ff 3529 #define TPM_CNT_COUNT_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3530 #define TPM_CNT_COUNT_SHIFT 0
bogdanm 0:9b334a45a8ff 3531 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
bogdanm 0:9b334a45a8ff 3532 /* MOD Bit Fields */
bogdanm 0:9b334a45a8ff 3533 #define TPM_MOD_MOD_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3534 #define TPM_MOD_MOD_SHIFT 0
bogdanm 0:9b334a45a8ff 3535 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
bogdanm 0:9b334a45a8ff 3536 /* CnSC Bit Fields */
bogdanm 0:9b334a45a8ff 3537 #define TPM_CnSC_DMA_MASK 0x1u
bogdanm 0:9b334a45a8ff 3538 #define TPM_CnSC_DMA_SHIFT 0
bogdanm 0:9b334a45a8ff 3539 #define TPM_CnSC_ELSA_MASK 0x4u
bogdanm 0:9b334a45a8ff 3540 #define TPM_CnSC_ELSA_SHIFT 2
bogdanm 0:9b334a45a8ff 3541 #define TPM_CnSC_ELSB_MASK 0x8u
bogdanm 0:9b334a45a8ff 3542 #define TPM_CnSC_ELSB_SHIFT 3
bogdanm 0:9b334a45a8ff 3543 #define TPM_CnSC_MSA_MASK 0x10u
bogdanm 0:9b334a45a8ff 3544 #define TPM_CnSC_MSA_SHIFT 4
bogdanm 0:9b334a45a8ff 3545 #define TPM_CnSC_MSB_MASK 0x20u
bogdanm 0:9b334a45a8ff 3546 #define TPM_CnSC_MSB_SHIFT 5
bogdanm 0:9b334a45a8ff 3547 #define TPM_CnSC_CHIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3548 #define TPM_CnSC_CHIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3549 #define TPM_CnSC_CHF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3550 #define TPM_CnSC_CHF_SHIFT 7
bogdanm 0:9b334a45a8ff 3551 /* CnV Bit Fields */
bogdanm 0:9b334a45a8ff 3552 #define TPM_CnV_VAL_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3553 #define TPM_CnV_VAL_SHIFT 0
bogdanm 0:9b334a45a8ff 3554 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
bogdanm 0:9b334a45a8ff 3555 /* STATUS Bit Fields */
bogdanm 0:9b334a45a8ff 3556 #define TPM_STATUS_CH0F_MASK 0x1u
bogdanm 0:9b334a45a8ff 3557 #define TPM_STATUS_CH0F_SHIFT 0
bogdanm 0:9b334a45a8ff 3558 #define TPM_STATUS_CH1F_MASK 0x2u
bogdanm 0:9b334a45a8ff 3559 #define TPM_STATUS_CH1F_SHIFT 1
bogdanm 0:9b334a45a8ff 3560 #define TPM_STATUS_CH2F_MASK 0x4u
bogdanm 0:9b334a45a8ff 3561 #define TPM_STATUS_CH2F_SHIFT 2
bogdanm 0:9b334a45a8ff 3562 #define TPM_STATUS_CH3F_MASK 0x8u
bogdanm 0:9b334a45a8ff 3563 #define TPM_STATUS_CH3F_SHIFT 3
bogdanm 0:9b334a45a8ff 3564 #define TPM_STATUS_CH4F_MASK 0x10u
bogdanm 0:9b334a45a8ff 3565 #define TPM_STATUS_CH4F_SHIFT 4
bogdanm 0:9b334a45a8ff 3566 #define TPM_STATUS_CH5F_MASK 0x20u
bogdanm 0:9b334a45a8ff 3567 #define TPM_STATUS_CH5F_SHIFT 5
bogdanm 0:9b334a45a8ff 3568 #define TPM_STATUS_TOF_MASK 0x100u
bogdanm 0:9b334a45a8ff 3569 #define TPM_STATUS_TOF_SHIFT 8
bogdanm 0:9b334a45a8ff 3570 /* CONF Bit Fields */
bogdanm 0:9b334a45a8ff 3571 #define TPM_CONF_DOZEEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 3572 #define TPM_CONF_DOZEEN_SHIFT 5
bogdanm 0:9b334a45a8ff 3573 #define TPM_CONF_DBGMODE_MASK 0xC0u
bogdanm 0:9b334a45a8ff 3574 #define TPM_CONF_DBGMODE_SHIFT 6
bogdanm 0:9b334a45a8ff 3575 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
bogdanm 0:9b334a45a8ff 3576 #define TPM_CONF_GTBEEN_MASK 0x200u
bogdanm 0:9b334a45a8ff 3577 #define TPM_CONF_GTBEEN_SHIFT 9
bogdanm 0:9b334a45a8ff 3578 #define TPM_CONF_CSOT_MASK 0x10000u
bogdanm 0:9b334a45a8ff 3579 #define TPM_CONF_CSOT_SHIFT 16
bogdanm 0:9b334a45a8ff 3580 #define TPM_CONF_CSOO_MASK 0x20000u
bogdanm 0:9b334a45a8ff 3581 #define TPM_CONF_CSOO_SHIFT 17
bogdanm 0:9b334a45a8ff 3582 #define TPM_CONF_CROT_MASK 0x40000u
bogdanm 0:9b334a45a8ff 3583 #define TPM_CONF_CROT_SHIFT 18
bogdanm 0:9b334a45a8ff 3584 #define TPM_CONF_TRGSEL_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 3585 #define TPM_CONF_TRGSEL_SHIFT 24
bogdanm 0:9b334a45a8ff 3586 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
bogdanm 0:9b334a45a8ff 3587
bogdanm 0:9b334a45a8ff 3588 /**
bogdanm 0:9b334a45a8ff 3589 * @}
bogdanm 0:9b334a45a8ff 3590 */ /* end of group TPM_Register_Masks */
bogdanm 0:9b334a45a8ff 3591
bogdanm 0:9b334a45a8ff 3592
bogdanm 0:9b334a45a8ff 3593 /* TPM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3594 /** Peripheral TPM0 base address */
bogdanm 0:9b334a45a8ff 3595 #define TPM0_BASE (0x40038000u)
bogdanm 0:9b334a45a8ff 3596 /** Peripheral TPM0 base pointer */
bogdanm 0:9b334a45a8ff 3597 #define TPM0 ((TPM_Type *)TPM0_BASE)
bogdanm 0:9b334a45a8ff 3598 /** Peripheral TPM1 base address */
bogdanm 0:9b334a45a8ff 3599 #define TPM1_BASE (0x40039000u)
bogdanm 0:9b334a45a8ff 3600 /** Peripheral TPM1 base pointer */
bogdanm 0:9b334a45a8ff 3601 #define TPM1 ((TPM_Type *)TPM1_BASE)
bogdanm 0:9b334a45a8ff 3602 /** Peripheral TPM2 base address */
bogdanm 0:9b334a45a8ff 3603 #define TPM2_BASE (0x4003A000u)
bogdanm 0:9b334a45a8ff 3604 /** Peripheral TPM2 base pointer */
bogdanm 0:9b334a45a8ff 3605 #define TPM2 ((TPM_Type *)TPM2_BASE)
bogdanm 0:9b334a45a8ff 3606 /** Array initializer of TPM peripheral base pointers */
bogdanm 0:9b334a45a8ff 3607 #define TPM_BASES { TPM0, TPM1, TPM2 }
bogdanm 0:9b334a45a8ff 3608
bogdanm 0:9b334a45a8ff 3609 /**
bogdanm 0:9b334a45a8ff 3610 * @}
bogdanm 0:9b334a45a8ff 3611 */ /* end of group TPM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3612
bogdanm 0:9b334a45a8ff 3613
bogdanm 0:9b334a45a8ff 3614 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3615 -- TSI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3616 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3617
bogdanm 0:9b334a45a8ff 3618 /**
bogdanm 0:9b334a45a8ff 3619 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3620 * @{
bogdanm 0:9b334a45a8ff 3621 */
bogdanm 0:9b334a45a8ff 3622
bogdanm 0:9b334a45a8ff 3623 /** TSI - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3624 typedef struct {
bogdanm 0:9b334a45a8ff 3625 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3626 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3627 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3628 } TSI_Type;
bogdanm 0:9b334a45a8ff 3629
bogdanm 0:9b334a45a8ff 3630 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3631 -- TSI Register Masks
bogdanm 0:9b334a45a8ff 3632 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3633
bogdanm 0:9b334a45a8ff 3634 /**
bogdanm 0:9b334a45a8ff 3635 * @addtogroup TSI_Register_Masks TSI Register Masks
bogdanm 0:9b334a45a8ff 3636 * @{
bogdanm 0:9b334a45a8ff 3637 */
bogdanm 0:9b334a45a8ff 3638
bogdanm 0:9b334a45a8ff 3639 /* GENCS Bit Fields */
bogdanm 0:9b334a45a8ff 3640 #define TSI_GENCS_CURSW_MASK 0x2u
bogdanm 0:9b334a45a8ff 3641 #define TSI_GENCS_CURSW_SHIFT 1
bogdanm 0:9b334a45a8ff 3642 #define TSI_GENCS_EOSF_MASK 0x4u
bogdanm 0:9b334a45a8ff 3643 #define TSI_GENCS_EOSF_SHIFT 2
bogdanm 0:9b334a45a8ff 3644 #define TSI_GENCS_SCNIP_MASK 0x8u
bogdanm 0:9b334a45a8ff 3645 #define TSI_GENCS_SCNIP_SHIFT 3
bogdanm 0:9b334a45a8ff 3646 #define TSI_GENCS_STM_MASK 0x10u
bogdanm 0:9b334a45a8ff 3647 #define TSI_GENCS_STM_SHIFT 4
bogdanm 0:9b334a45a8ff 3648 #define TSI_GENCS_STPE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3649 #define TSI_GENCS_STPE_SHIFT 5
bogdanm 0:9b334a45a8ff 3650 #define TSI_GENCS_TSIIEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 3651 #define TSI_GENCS_TSIIEN_SHIFT 6
bogdanm 0:9b334a45a8ff 3652 #define TSI_GENCS_TSIEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 3653 #define TSI_GENCS_TSIEN_SHIFT 7
bogdanm 0:9b334a45a8ff 3654 #define TSI_GENCS_NSCN_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 3655 #define TSI_GENCS_NSCN_SHIFT 8
bogdanm 0:9b334a45a8ff 3656 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
bogdanm 0:9b334a45a8ff 3657 #define TSI_GENCS_PS_MASK 0xE000u
bogdanm 0:9b334a45a8ff 3658 #define TSI_GENCS_PS_SHIFT 13
bogdanm 0:9b334a45a8ff 3659 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
bogdanm 0:9b334a45a8ff 3660 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
bogdanm 0:9b334a45a8ff 3661 #define TSI_GENCS_EXTCHRG_SHIFT 16
bogdanm 0:9b334a45a8ff 3662 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
bogdanm 0:9b334a45a8ff 3663 #define TSI_GENCS_DVOLT_MASK 0x180000u
bogdanm 0:9b334a45a8ff 3664 #define TSI_GENCS_DVOLT_SHIFT 19
bogdanm 0:9b334a45a8ff 3665 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
bogdanm 0:9b334a45a8ff 3666 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
bogdanm 0:9b334a45a8ff 3667 #define TSI_GENCS_REFCHRG_SHIFT 21
bogdanm 0:9b334a45a8ff 3668 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
bogdanm 0:9b334a45a8ff 3669 #define TSI_GENCS_MODE_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 3670 #define TSI_GENCS_MODE_SHIFT 24
bogdanm 0:9b334a45a8ff 3671 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
bogdanm 0:9b334a45a8ff 3672 #define TSI_GENCS_ESOR_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 3673 #define TSI_GENCS_ESOR_SHIFT 28
bogdanm 0:9b334a45a8ff 3674 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 3675 #define TSI_GENCS_OUTRGF_SHIFT 31
bogdanm 0:9b334a45a8ff 3676 /* DATA Bit Fields */
bogdanm 0:9b334a45a8ff 3677 #define TSI_DATA_TSICNT_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3678 #define TSI_DATA_TSICNT_SHIFT 0
bogdanm 0:9b334a45a8ff 3679 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
bogdanm 0:9b334a45a8ff 3680 #define TSI_DATA_SWTS_MASK 0x400000u
bogdanm 0:9b334a45a8ff 3681 #define TSI_DATA_SWTS_SHIFT 22
bogdanm 0:9b334a45a8ff 3682 #define TSI_DATA_DMAEN_MASK 0x800000u
bogdanm 0:9b334a45a8ff 3683 #define TSI_DATA_DMAEN_SHIFT 23
bogdanm 0:9b334a45a8ff 3684 #define TSI_DATA_TSICH_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 3685 #define TSI_DATA_TSICH_SHIFT 28
bogdanm 0:9b334a45a8ff 3686 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
bogdanm 0:9b334a45a8ff 3687 /* TSHD Bit Fields */
bogdanm 0:9b334a45a8ff 3688 #define TSI_TSHD_THRESL_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3689 #define TSI_TSHD_THRESL_SHIFT 0
bogdanm 0:9b334a45a8ff 3690 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
bogdanm 0:9b334a45a8ff 3691 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
bogdanm 0:9b334a45a8ff 3692 #define TSI_TSHD_THRESH_SHIFT 16
bogdanm 0:9b334a45a8ff 3693 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
bogdanm 0:9b334a45a8ff 3694
bogdanm 0:9b334a45a8ff 3695 /**
bogdanm 0:9b334a45a8ff 3696 * @}
bogdanm 0:9b334a45a8ff 3697 */ /* end of group TSI_Register_Masks */
bogdanm 0:9b334a45a8ff 3698
bogdanm 0:9b334a45a8ff 3699
bogdanm 0:9b334a45a8ff 3700 /* TSI - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3701 /** Peripheral TSI0 base address */
bogdanm 0:9b334a45a8ff 3702 #define TSI0_BASE (0x40045000u)
bogdanm 0:9b334a45a8ff 3703 /** Peripheral TSI0 base pointer */
bogdanm 0:9b334a45a8ff 3704 #define TSI0 ((TSI_Type *)TSI0_BASE)
bogdanm 0:9b334a45a8ff 3705 /** Array initializer of TSI peripheral base pointers */
bogdanm 0:9b334a45a8ff 3706 #define TSI_BASES { TSI0 }
bogdanm 0:9b334a45a8ff 3707
bogdanm 0:9b334a45a8ff 3708 /**
bogdanm 0:9b334a45a8ff 3709 * @}
bogdanm 0:9b334a45a8ff 3710 */ /* end of group TSI_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3711
bogdanm 0:9b334a45a8ff 3712
bogdanm 0:9b334a45a8ff 3713 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3714 -- UART Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3715 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3716
bogdanm 0:9b334a45a8ff 3717 /**
bogdanm 0:9b334a45a8ff 3718 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3719 * @{
bogdanm 0:9b334a45a8ff 3720 */
bogdanm 0:9b334a45a8ff 3721
bogdanm 0:9b334a45a8ff 3722 /** UART - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3723 typedef struct {
bogdanm 0:9b334a45a8ff 3724 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3725 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
bogdanm 0:9b334a45a8ff 3726 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 0:9b334a45a8ff 3727 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 0:9b334a45a8ff 3728 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3729 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 0:9b334a45a8ff 3730 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 0:9b334a45a8ff 3731 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 3732 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3733 } UART_Type;
bogdanm 0:9b334a45a8ff 3734
bogdanm 0:9b334a45a8ff 3735 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3736 -- UART Register Masks
bogdanm 0:9b334a45a8ff 3737 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3738
bogdanm 0:9b334a45a8ff 3739 /**
bogdanm 0:9b334a45a8ff 3740 * @addtogroup UART_Register_Masks UART Register Masks
bogdanm 0:9b334a45a8ff 3741 * @{
bogdanm 0:9b334a45a8ff 3742 */
bogdanm 0:9b334a45a8ff 3743
bogdanm 0:9b334a45a8ff 3744 /* BDH Bit Fields */
bogdanm 0:9b334a45a8ff 3745 #define UART_BDH_SBR_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 3746 #define UART_BDH_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 3747 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
bogdanm 0:9b334a45a8ff 3748 #define UART_BDH_SBNS_MASK 0x20u
bogdanm 0:9b334a45a8ff 3749 #define UART_BDH_SBNS_SHIFT 5
bogdanm 0:9b334a45a8ff 3750 #define UART_BDH_RXEDGIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3751 #define UART_BDH_RXEDGIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3752 #define UART_BDH_LBKDIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3753 #define UART_BDH_LBKDIE_SHIFT 7
bogdanm 0:9b334a45a8ff 3754 /* BDL Bit Fields */
bogdanm 0:9b334a45a8ff 3755 #define UART_BDL_SBR_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3756 #define UART_BDL_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 3757 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
bogdanm 0:9b334a45a8ff 3758 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 3759 #define UART_C1_PT_MASK 0x1u
bogdanm 0:9b334a45a8ff 3760 #define UART_C1_PT_SHIFT 0
bogdanm 0:9b334a45a8ff 3761 #define UART_C1_PE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3762 #define UART_C1_PE_SHIFT 1
bogdanm 0:9b334a45a8ff 3763 #define UART_C1_ILT_MASK 0x4u
bogdanm 0:9b334a45a8ff 3764 #define UART_C1_ILT_SHIFT 2
bogdanm 0:9b334a45a8ff 3765 #define UART_C1_WAKE_MASK 0x8u
bogdanm 0:9b334a45a8ff 3766 #define UART_C1_WAKE_SHIFT 3
bogdanm 0:9b334a45a8ff 3767 #define UART_C1_M_MASK 0x10u
bogdanm 0:9b334a45a8ff 3768 #define UART_C1_M_SHIFT 4
bogdanm 0:9b334a45a8ff 3769 #define UART_C1_RSRC_MASK 0x20u
bogdanm 0:9b334a45a8ff 3770 #define UART_C1_RSRC_SHIFT 5
bogdanm 0:9b334a45a8ff 3771 #define UART_C1_UARTSWAI_MASK 0x40u
bogdanm 0:9b334a45a8ff 3772 #define UART_C1_UARTSWAI_SHIFT 6
bogdanm 0:9b334a45a8ff 3773 #define UART_C1_LOOPS_MASK 0x80u
bogdanm 0:9b334a45a8ff 3774 #define UART_C1_LOOPS_SHIFT 7
bogdanm 0:9b334a45a8ff 3775 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 3776 #define UART_C2_SBK_MASK 0x1u
bogdanm 0:9b334a45a8ff 3777 #define UART_C2_SBK_SHIFT 0
bogdanm 0:9b334a45a8ff 3778 #define UART_C2_RWU_MASK 0x2u
bogdanm 0:9b334a45a8ff 3779 #define UART_C2_RWU_SHIFT 1
bogdanm 0:9b334a45a8ff 3780 #define UART_C2_RE_MASK 0x4u
bogdanm 0:9b334a45a8ff 3781 #define UART_C2_RE_SHIFT 2
bogdanm 0:9b334a45a8ff 3782 #define UART_C2_TE_MASK 0x8u
bogdanm 0:9b334a45a8ff 3783 #define UART_C2_TE_SHIFT 3
bogdanm 0:9b334a45a8ff 3784 #define UART_C2_ILIE_MASK 0x10u
bogdanm 0:9b334a45a8ff 3785 #define UART_C2_ILIE_SHIFT 4
bogdanm 0:9b334a45a8ff 3786 #define UART_C2_RIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3787 #define UART_C2_RIE_SHIFT 5
bogdanm 0:9b334a45a8ff 3788 #define UART_C2_TCIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3789 #define UART_C2_TCIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3790 #define UART_C2_TIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3791 #define UART_C2_TIE_SHIFT 7
bogdanm 0:9b334a45a8ff 3792 /* S1 Bit Fields */
bogdanm 0:9b334a45a8ff 3793 #define UART_S1_PF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3794 #define UART_S1_PF_SHIFT 0
bogdanm 0:9b334a45a8ff 3795 #define UART_S1_FE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3796 #define UART_S1_FE_SHIFT 1
bogdanm 0:9b334a45a8ff 3797 #define UART_S1_NF_MASK 0x4u
bogdanm 0:9b334a45a8ff 3798 #define UART_S1_NF_SHIFT 2
bogdanm 0:9b334a45a8ff 3799 #define UART_S1_OR_MASK 0x8u
bogdanm 0:9b334a45a8ff 3800 #define UART_S1_OR_SHIFT 3
bogdanm 0:9b334a45a8ff 3801 #define UART_S1_IDLE_MASK 0x10u
bogdanm 0:9b334a45a8ff 3802 #define UART_S1_IDLE_SHIFT 4
bogdanm 0:9b334a45a8ff 3803 #define UART_S1_RDRF_MASK 0x20u
bogdanm 0:9b334a45a8ff 3804 #define UART_S1_RDRF_SHIFT 5
bogdanm 0:9b334a45a8ff 3805 #define UART_S1_TC_MASK 0x40u
bogdanm 0:9b334a45a8ff 3806 #define UART_S1_TC_SHIFT 6
bogdanm 0:9b334a45a8ff 3807 #define UART_S1_TDRE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3808 #define UART_S1_TDRE_SHIFT 7
bogdanm 0:9b334a45a8ff 3809 /* S2 Bit Fields */
bogdanm 0:9b334a45a8ff 3810 #define UART_S2_RAF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3811 #define UART_S2_RAF_SHIFT 0
bogdanm 0:9b334a45a8ff 3812 #define UART_S2_LBKDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3813 #define UART_S2_LBKDE_SHIFT 1
bogdanm 0:9b334a45a8ff 3814 #define UART_S2_BRK13_MASK 0x4u
bogdanm 0:9b334a45a8ff 3815 #define UART_S2_BRK13_SHIFT 2
bogdanm 0:9b334a45a8ff 3816 #define UART_S2_RWUID_MASK 0x8u
bogdanm 0:9b334a45a8ff 3817 #define UART_S2_RWUID_SHIFT 3
bogdanm 0:9b334a45a8ff 3818 #define UART_S2_RXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 3819 #define UART_S2_RXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 3820 #define UART_S2_RXEDGIF_MASK 0x40u
bogdanm 0:9b334a45a8ff 3821 #define UART_S2_RXEDGIF_SHIFT 6
bogdanm 0:9b334a45a8ff 3822 #define UART_S2_LBKDIF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3823 #define UART_S2_LBKDIF_SHIFT 7
bogdanm 0:9b334a45a8ff 3824 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 3825 #define UART_C3_PEIE_MASK 0x1u
bogdanm 0:9b334a45a8ff 3826 #define UART_C3_PEIE_SHIFT 0
bogdanm 0:9b334a45a8ff 3827 #define UART_C3_FEIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3828 #define UART_C3_FEIE_SHIFT 1
bogdanm 0:9b334a45a8ff 3829 #define UART_C3_NEIE_MASK 0x4u
bogdanm 0:9b334a45a8ff 3830 #define UART_C3_NEIE_SHIFT 2
bogdanm 0:9b334a45a8ff 3831 #define UART_C3_ORIE_MASK 0x8u
bogdanm 0:9b334a45a8ff 3832 #define UART_C3_ORIE_SHIFT 3
bogdanm 0:9b334a45a8ff 3833 #define UART_C3_TXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 3834 #define UART_C3_TXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 3835 #define UART_C3_TXDIR_MASK 0x20u
bogdanm 0:9b334a45a8ff 3836 #define UART_C3_TXDIR_SHIFT 5
bogdanm 0:9b334a45a8ff 3837 #define UART_C3_T8_MASK 0x40u
bogdanm 0:9b334a45a8ff 3838 #define UART_C3_T8_SHIFT 6
bogdanm 0:9b334a45a8ff 3839 #define UART_C3_R8_MASK 0x80u
bogdanm 0:9b334a45a8ff 3840 #define UART_C3_R8_SHIFT 7
bogdanm 0:9b334a45a8ff 3841 /* D Bit Fields */
bogdanm 0:9b334a45a8ff 3842 #define UART_D_R0T0_MASK 0x1u
bogdanm 0:9b334a45a8ff 3843 #define UART_D_R0T0_SHIFT 0
bogdanm 0:9b334a45a8ff 3844 #define UART_D_R1T1_MASK 0x2u
bogdanm 0:9b334a45a8ff 3845 #define UART_D_R1T1_SHIFT 1
bogdanm 0:9b334a45a8ff 3846 #define UART_D_R2T2_MASK 0x4u
bogdanm 0:9b334a45a8ff 3847 #define UART_D_R2T2_SHIFT 2
bogdanm 0:9b334a45a8ff 3848 #define UART_D_R3T3_MASK 0x8u
bogdanm 0:9b334a45a8ff 3849 #define UART_D_R3T3_SHIFT 3
bogdanm 0:9b334a45a8ff 3850 #define UART_D_R4T4_MASK 0x10u
bogdanm 0:9b334a45a8ff 3851 #define UART_D_R4T4_SHIFT 4
bogdanm 0:9b334a45a8ff 3852 #define UART_D_R5T5_MASK 0x20u
bogdanm 0:9b334a45a8ff 3853 #define UART_D_R5T5_SHIFT 5
bogdanm 0:9b334a45a8ff 3854 #define UART_D_R6T6_MASK 0x40u
bogdanm 0:9b334a45a8ff 3855 #define UART_D_R6T6_SHIFT 6
bogdanm 0:9b334a45a8ff 3856 #define UART_D_R7T7_MASK 0x80u
bogdanm 0:9b334a45a8ff 3857 #define UART_D_R7T7_SHIFT 7
bogdanm 0:9b334a45a8ff 3858 /* C4 Bit Fields */
bogdanm 0:9b334a45a8ff 3859 #define UART_C4_RDMAS_MASK 0x20u
bogdanm 0:9b334a45a8ff 3860 #define UART_C4_RDMAS_SHIFT 5
bogdanm 0:9b334a45a8ff 3861 #define UART_C4_TDMAS_MASK 0x80u
bogdanm 0:9b334a45a8ff 3862 #define UART_C4_TDMAS_SHIFT 7
bogdanm 0:9b334a45a8ff 3863
bogdanm 0:9b334a45a8ff 3864 /**
bogdanm 0:9b334a45a8ff 3865 * @}
bogdanm 0:9b334a45a8ff 3866 */ /* end of group UART_Register_Masks */
bogdanm 0:9b334a45a8ff 3867
bogdanm 0:9b334a45a8ff 3868
bogdanm 0:9b334a45a8ff 3869 /* UART - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3870 /** Peripheral UART1 base address */
bogdanm 0:9b334a45a8ff 3871 #define UART1_BASE (0x4006B000u)
bogdanm 0:9b334a45a8ff 3872 /** Peripheral UART1 base pointer */
bogdanm 0:9b334a45a8ff 3873 #define UART1 ((UART_Type *)UART1_BASE)
bogdanm 0:9b334a45a8ff 3874 /** Peripheral UART2 base address */
bogdanm 0:9b334a45a8ff 3875 #define UART2_BASE (0x4006C000u)
bogdanm 0:9b334a45a8ff 3876 /** Peripheral UART2 base pointer */
bogdanm 0:9b334a45a8ff 3877 #define UART2 ((UART_Type *)UART2_BASE)
bogdanm 0:9b334a45a8ff 3878 /** Array initializer of UART peripheral base pointers */
bogdanm 0:9b334a45a8ff 3879 #define UART_BASES { UART1, UART2 }
bogdanm 0:9b334a45a8ff 3880
bogdanm 0:9b334a45a8ff 3881 /**
bogdanm 0:9b334a45a8ff 3882 * @}
bogdanm 0:9b334a45a8ff 3883 */ /* end of group UART_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3884
bogdanm 0:9b334a45a8ff 3885
bogdanm 0:9b334a45a8ff 3886 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3887 -- UART0 Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3888 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3889
bogdanm 0:9b334a45a8ff 3890 /**
bogdanm 0:9b334a45a8ff 3891 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3892 * @{
bogdanm 0:9b334a45a8ff 3893 */
bogdanm 0:9b334a45a8ff 3894
bogdanm 0:9b334a45a8ff 3895 /** UART0 - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3896 typedef struct {
bogdanm 0:9b334a45a8ff 3897 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3898 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
bogdanm 0:9b334a45a8ff 3899 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 0:9b334a45a8ff 3900 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 0:9b334a45a8ff 3901 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3902 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 0:9b334a45a8ff 3903 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 0:9b334a45a8ff 3904 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 3905 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3906 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
bogdanm 0:9b334a45a8ff 3907 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
bogdanm 0:9b334a45a8ff 3908 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
bogdanm 0:9b334a45a8ff 3909 } UART0_Type;
bogdanm 0:9b334a45a8ff 3910
bogdanm 0:9b334a45a8ff 3911 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3912 -- UART0 Register Masks
bogdanm 0:9b334a45a8ff 3913 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3914
bogdanm 0:9b334a45a8ff 3915 /**
bogdanm 0:9b334a45a8ff 3916 * @addtogroup UART0_Register_Masks UART0 Register Masks
bogdanm 0:9b334a45a8ff 3917 * @{
bogdanm 0:9b334a45a8ff 3918 */
bogdanm 0:9b334a45a8ff 3919
bogdanm 0:9b334a45a8ff 3920 /* BDH Bit Fields */
bogdanm 0:9b334a45a8ff 3921 #define UART0_BDH_SBR_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 3922 #define UART0_BDH_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 3923 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
bogdanm 0:9b334a45a8ff 3924 #define UART0_BDH_SBNS_MASK 0x20u
bogdanm 0:9b334a45a8ff 3925 #define UART0_BDH_SBNS_SHIFT 5
bogdanm 0:9b334a45a8ff 3926 #define UART0_BDH_RXEDGIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3927 #define UART0_BDH_RXEDGIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3928 #define UART0_BDH_LBKDIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3929 #define UART0_BDH_LBKDIE_SHIFT 7
bogdanm 0:9b334a45a8ff 3930 /* BDL Bit Fields */
bogdanm 0:9b334a45a8ff 3931 #define UART0_BDL_SBR_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3932 #define UART0_BDL_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 3933 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
bogdanm 0:9b334a45a8ff 3934 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 3935 #define UART0_C1_PT_MASK 0x1u
bogdanm 0:9b334a45a8ff 3936 #define UART0_C1_PT_SHIFT 0
bogdanm 0:9b334a45a8ff 3937 #define UART0_C1_PE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3938 #define UART0_C1_PE_SHIFT 1
bogdanm 0:9b334a45a8ff 3939 #define UART0_C1_ILT_MASK 0x4u
bogdanm 0:9b334a45a8ff 3940 #define UART0_C1_ILT_SHIFT 2
bogdanm 0:9b334a45a8ff 3941 #define UART0_C1_WAKE_MASK 0x8u
bogdanm 0:9b334a45a8ff 3942 #define UART0_C1_WAKE_SHIFT 3
bogdanm 0:9b334a45a8ff 3943 #define UART0_C1_M_MASK 0x10u
bogdanm 0:9b334a45a8ff 3944 #define UART0_C1_M_SHIFT 4
bogdanm 0:9b334a45a8ff 3945 #define UART0_C1_RSRC_MASK 0x20u
bogdanm 0:9b334a45a8ff 3946 #define UART0_C1_RSRC_SHIFT 5
bogdanm 0:9b334a45a8ff 3947 #define UART0_C1_DOZEEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 3948 #define UART0_C1_DOZEEN_SHIFT 6
bogdanm 0:9b334a45a8ff 3949 #define UART0_C1_LOOPS_MASK 0x80u
bogdanm 0:9b334a45a8ff 3950 #define UART0_C1_LOOPS_SHIFT 7
bogdanm 0:9b334a45a8ff 3951 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 3952 #define UART0_C2_SBK_MASK 0x1u
bogdanm 0:9b334a45a8ff 3953 #define UART0_C2_SBK_SHIFT 0
bogdanm 0:9b334a45a8ff 3954 #define UART0_C2_RWU_MASK 0x2u
bogdanm 0:9b334a45a8ff 3955 #define UART0_C2_RWU_SHIFT 1
bogdanm 0:9b334a45a8ff 3956 #define UART0_C2_RE_MASK 0x4u
bogdanm 0:9b334a45a8ff 3957 #define UART0_C2_RE_SHIFT 2
bogdanm 0:9b334a45a8ff 3958 #define UART0_C2_TE_MASK 0x8u
bogdanm 0:9b334a45a8ff 3959 #define UART0_C2_TE_SHIFT 3
bogdanm 0:9b334a45a8ff 3960 #define UART0_C2_ILIE_MASK 0x10u
bogdanm 0:9b334a45a8ff 3961 #define UART0_C2_ILIE_SHIFT 4
bogdanm 0:9b334a45a8ff 3962 #define UART0_C2_RIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3963 #define UART0_C2_RIE_SHIFT 5
bogdanm 0:9b334a45a8ff 3964 #define UART0_C2_TCIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3965 #define UART0_C2_TCIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3966 #define UART0_C2_TIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3967 #define UART0_C2_TIE_SHIFT 7
bogdanm 0:9b334a45a8ff 3968 /* S1 Bit Fields */
bogdanm 0:9b334a45a8ff 3969 #define UART0_S1_PF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3970 #define UART0_S1_PF_SHIFT 0
bogdanm 0:9b334a45a8ff 3971 #define UART0_S1_FE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3972 #define UART0_S1_FE_SHIFT 1
bogdanm 0:9b334a45a8ff 3973 #define UART0_S1_NF_MASK 0x4u
bogdanm 0:9b334a45a8ff 3974 #define UART0_S1_NF_SHIFT 2
bogdanm 0:9b334a45a8ff 3975 #define UART0_S1_OR_MASK 0x8u
bogdanm 0:9b334a45a8ff 3976 #define UART0_S1_OR_SHIFT 3
bogdanm 0:9b334a45a8ff 3977 #define UART0_S1_IDLE_MASK 0x10u
bogdanm 0:9b334a45a8ff 3978 #define UART0_S1_IDLE_SHIFT 4
bogdanm 0:9b334a45a8ff 3979 #define UART0_S1_RDRF_MASK 0x20u
bogdanm 0:9b334a45a8ff 3980 #define UART0_S1_RDRF_SHIFT 5
bogdanm 0:9b334a45a8ff 3981 #define UART0_S1_TC_MASK 0x40u
bogdanm 0:9b334a45a8ff 3982 #define UART0_S1_TC_SHIFT 6
bogdanm 0:9b334a45a8ff 3983 #define UART0_S1_TDRE_MASK 0x80u
bogdanm 0:9b334a45a8ff 3984 #define UART0_S1_TDRE_SHIFT 7
bogdanm 0:9b334a45a8ff 3985 /* S2 Bit Fields */
bogdanm 0:9b334a45a8ff 3986 #define UART0_S2_RAF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3987 #define UART0_S2_RAF_SHIFT 0
bogdanm 0:9b334a45a8ff 3988 #define UART0_S2_LBKDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3989 #define UART0_S2_LBKDE_SHIFT 1
bogdanm 0:9b334a45a8ff 3990 #define UART0_S2_BRK13_MASK 0x4u
bogdanm 0:9b334a45a8ff 3991 #define UART0_S2_BRK13_SHIFT 2
bogdanm 0:9b334a45a8ff 3992 #define UART0_S2_RWUID_MASK 0x8u
bogdanm 0:9b334a45a8ff 3993 #define UART0_S2_RWUID_SHIFT 3
bogdanm 0:9b334a45a8ff 3994 #define UART0_S2_RXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 3995 #define UART0_S2_RXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 3996 #define UART0_S2_MSBF_MASK 0x20u
bogdanm 0:9b334a45a8ff 3997 #define UART0_S2_MSBF_SHIFT 5
bogdanm 0:9b334a45a8ff 3998 #define UART0_S2_RXEDGIF_MASK 0x40u
bogdanm 0:9b334a45a8ff 3999 #define UART0_S2_RXEDGIF_SHIFT 6
bogdanm 0:9b334a45a8ff 4000 #define UART0_S2_LBKDIF_MASK 0x80u
bogdanm 0:9b334a45a8ff 4001 #define UART0_S2_LBKDIF_SHIFT 7
bogdanm 0:9b334a45a8ff 4002 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 4003 #define UART0_C3_PEIE_MASK 0x1u
bogdanm 0:9b334a45a8ff 4004 #define UART0_C3_PEIE_SHIFT 0
bogdanm 0:9b334a45a8ff 4005 #define UART0_C3_FEIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 4006 #define UART0_C3_FEIE_SHIFT 1
bogdanm 0:9b334a45a8ff 4007 #define UART0_C3_NEIE_MASK 0x4u
bogdanm 0:9b334a45a8ff 4008 #define UART0_C3_NEIE_SHIFT 2
bogdanm 0:9b334a45a8ff 4009 #define UART0_C3_ORIE_MASK 0x8u
bogdanm 0:9b334a45a8ff 4010 #define UART0_C3_ORIE_SHIFT 3
bogdanm 0:9b334a45a8ff 4011 #define UART0_C3_TXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 4012 #define UART0_C3_TXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 4013 #define UART0_C3_TXDIR_MASK 0x20u
bogdanm 0:9b334a45a8ff 4014 #define UART0_C3_TXDIR_SHIFT 5
bogdanm 0:9b334a45a8ff 4015 #define UART0_C3_R9T8_MASK 0x40u
bogdanm 0:9b334a45a8ff 4016 #define UART0_C3_R9T8_SHIFT 6
bogdanm 0:9b334a45a8ff 4017 #define UART0_C3_R8T9_MASK 0x80u
bogdanm 0:9b334a45a8ff 4018 #define UART0_C3_R8T9_SHIFT 7
bogdanm 0:9b334a45a8ff 4019 /* D Bit Fields */
bogdanm 0:9b334a45a8ff 4020 #define UART0_D_R0T0_MASK 0x1u
bogdanm 0:9b334a45a8ff 4021 #define UART0_D_R0T0_SHIFT 0
bogdanm 0:9b334a45a8ff 4022 #define UART0_D_R1T1_MASK 0x2u
bogdanm 0:9b334a45a8ff 4023 #define UART0_D_R1T1_SHIFT 1
bogdanm 0:9b334a45a8ff 4024 #define UART0_D_R2T2_MASK 0x4u
bogdanm 0:9b334a45a8ff 4025 #define UART0_D_R2T2_SHIFT 2
bogdanm 0:9b334a45a8ff 4026 #define UART0_D_R3T3_MASK 0x8u
bogdanm 0:9b334a45a8ff 4027 #define UART0_D_R3T3_SHIFT 3
bogdanm 0:9b334a45a8ff 4028 #define UART0_D_R4T4_MASK 0x10u
bogdanm 0:9b334a45a8ff 4029 #define UART0_D_R4T4_SHIFT 4
bogdanm 0:9b334a45a8ff 4030 #define UART0_D_R5T5_MASK 0x20u
bogdanm 0:9b334a45a8ff 4031 #define UART0_D_R5T5_SHIFT 5
bogdanm 0:9b334a45a8ff 4032 #define UART0_D_R6T6_MASK 0x40u
bogdanm 0:9b334a45a8ff 4033 #define UART0_D_R6T6_SHIFT 6
bogdanm 0:9b334a45a8ff 4034 #define UART0_D_R7T7_MASK 0x80u
bogdanm 0:9b334a45a8ff 4035 #define UART0_D_R7T7_SHIFT 7
bogdanm 0:9b334a45a8ff 4036 /* MA1 Bit Fields */
bogdanm 0:9b334a45a8ff 4037 #define UART0_MA1_MA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4038 #define UART0_MA1_MA_SHIFT 0
bogdanm 0:9b334a45a8ff 4039 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
bogdanm 0:9b334a45a8ff 4040 /* MA2 Bit Fields */
bogdanm 0:9b334a45a8ff 4041 #define UART0_MA2_MA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4042 #define UART0_MA2_MA_SHIFT 0
bogdanm 0:9b334a45a8ff 4043 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
bogdanm 0:9b334a45a8ff 4044 /* C4 Bit Fields */
bogdanm 0:9b334a45a8ff 4045 #define UART0_C4_OSR_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 4046 #define UART0_C4_OSR_SHIFT 0
bogdanm 0:9b334a45a8ff 4047 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
bogdanm 0:9b334a45a8ff 4048 #define UART0_C4_M10_MASK 0x20u
bogdanm 0:9b334a45a8ff 4049 #define UART0_C4_M10_SHIFT 5
bogdanm 0:9b334a45a8ff 4050 #define UART0_C4_MAEN2_MASK 0x40u
bogdanm 0:9b334a45a8ff 4051 #define UART0_C4_MAEN2_SHIFT 6
bogdanm 0:9b334a45a8ff 4052 #define UART0_C4_MAEN1_MASK 0x80u
bogdanm 0:9b334a45a8ff 4053 #define UART0_C4_MAEN1_SHIFT 7
bogdanm 0:9b334a45a8ff 4054 /* C5 Bit Fields */
bogdanm 0:9b334a45a8ff 4055 #define UART0_C5_RESYNCDIS_MASK 0x1u
bogdanm 0:9b334a45a8ff 4056 #define UART0_C5_RESYNCDIS_SHIFT 0
bogdanm 0:9b334a45a8ff 4057 #define UART0_C5_BOTHEDGE_MASK 0x2u
bogdanm 0:9b334a45a8ff 4058 #define UART0_C5_BOTHEDGE_SHIFT 1
bogdanm 0:9b334a45a8ff 4059 #define UART0_C5_RDMAE_MASK 0x20u
bogdanm 0:9b334a45a8ff 4060 #define UART0_C5_RDMAE_SHIFT 5
bogdanm 0:9b334a45a8ff 4061 #define UART0_C5_TDMAE_MASK 0x80u
bogdanm 0:9b334a45a8ff 4062 #define UART0_C5_TDMAE_SHIFT 7
bogdanm 0:9b334a45a8ff 4063
bogdanm 0:9b334a45a8ff 4064 /**
bogdanm 0:9b334a45a8ff 4065 * @}
bogdanm 0:9b334a45a8ff 4066 */ /* end of group UART0_Register_Masks */
bogdanm 0:9b334a45a8ff 4067
bogdanm 0:9b334a45a8ff 4068
bogdanm 0:9b334a45a8ff 4069 /* UART0 - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4070 /** Peripheral UART0 base address */
bogdanm 0:9b334a45a8ff 4071 #define UART0_BASE (0x4006A000u)
bogdanm 0:9b334a45a8ff 4072 /** Peripheral UART0 base pointer */
bogdanm 0:9b334a45a8ff 4073 #define UART0 ((UART0_Type *)UART0_BASE)
bogdanm 0:9b334a45a8ff 4074 /** Array initializer of UART0 peripheral base pointers */
bogdanm 0:9b334a45a8ff 4075 #define UART0_BASES { UART0 }
bogdanm 0:9b334a45a8ff 4076
bogdanm 0:9b334a45a8ff 4077 /**
bogdanm 0:9b334a45a8ff 4078 * @}
bogdanm 0:9b334a45a8ff 4079 */ /* end of group UART0_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4080
bogdanm 0:9b334a45a8ff 4081
bogdanm 0:9b334a45a8ff 4082 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4083 -- USB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4084 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4085
bogdanm 0:9b334a45a8ff 4086 /**
bogdanm 0:9b334a45a8ff 4087 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4088 * @{
bogdanm 0:9b334a45a8ff 4089 */
bogdanm 0:9b334a45a8ff 4090
bogdanm 0:9b334a45a8ff 4091 /** USB - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4092 typedef struct {
bogdanm 0:9b334a45a8ff 4093 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4094 uint8_t RESERVED_0[3];
bogdanm 0:9b334a45a8ff 4095 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4096 uint8_t RESERVED_1[3];
bogdanm 0:9b334a45a8ff 4097 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 4098 uint8_t RESERVED_2[3];
bogdanm 0:9b334a45a8ff 4099 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
bogdanm 0:9b334a45a8ff 4100 uint8_t RESERVED_3[3];
bogdanm 0:9b334a45a8ff 4101 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 4102 uint8_t RESERVED_4[3];
bogdanm 0:9b334a45a8ff 4103 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 4104 uint8_t RESERVED_5[3];
bogdanm 0:9b334a45a8ff 4105 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
bogdanm 0:9b334a45a8ff 4106 uint8_t RESERVED_6[3];
bogdanm 0:9b334a45a8ff 4107 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
bogdanm 0:9b334a45a8ff 4108 uint8_t RESERVED_7[99];
bogdanm 0:9b334a45a8ff 4109 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
bogdanm 0:9b334a45a8ff 4110 uint8_t RESERVED_8[3];
bogdanm 0:9b334a45a8ff 4111 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
bogdanm 0:9b334a45a8ff 4112 uint8_t RESERVED_9[3];
bogdanm 0:9b334a45a8ff 4113 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
bogdanm 0:9b334a45a8ff 4114 uint8_t RESERVED_10[3];
bogdanm 0:9b334a45a8ff 4115 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
bogdanm 0:9b334a45a8ff 4116 uint8_t RESERVED_11[3];
bogdanm 0:9b334a45a8ff 4117 __I uint8_t STAT; /**< Status register, offset: 0x90 */
bogdanm 0:9b334a45a8ff 4118 uint8_t RESERVED_12[3];
bogdanm 0:9b334a45a8ff 4119 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
bogdanm 0:9b334a45a8ff 4120 uint8_t RESERVED_13[3];
bogdanm 0:9b334a45a8ff 4121 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
bogdanm 0:9b334a45a8ff 4122 uint8_t RESERVED_14[3];
bogdanm 0:9b334a45a8ff 4123 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
bogdanm 0:9b334a45a8ff 4124 uint8_t RESERVED_15[3];
bogdanm 0:9b334a45a8ff 4125 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
bogdanm 0:9b334a45a8ff 4126 uint8_t RESERVED_16[3];
bogdanm 0:9b334a45a8ff 4127 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
bogdanm 0:9b334a45a8ff 4128 uint8_t RESERVED_17[3];
bogdanm 0:9b334a45a8ff 4129 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
bogdanm 0:9b334a45a8ff 4130 uint8_t RESERVED_18[3];
bogdanm 0:9b334a45a8ff 4131 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
bogdanm 0:9b334a45a8ff 4132 uint8_t RESERVED_19[3];
bogdanm 0:9b334a45a8ff 4133 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
bogdanm 0:9b334a45a8ff 4134 uint8_t RESERVED_20[3];
bogdanm 0:9b334a45a8ff 4135 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
bogdanm 0:9b334a45a8ff 4136 uint8_t RESERVED_21[11];
bogdanm 0:9b334a45a8ff 4137 struct { /* offset: 0xC0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 4138 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 4139 uint8_t RESERVED_0[3];
bogdanm 0:9b334a45a8ff 4140 } ENDPOINT[16];
bogdanm 0:9b334a45a8ff 4141 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
bogdanm 0:9b334a45a8ff 4142 uint8_t RESERVED_22[3];
bogdanm 0:9b334a45a8ff 4143 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
bogdanm 0:9b334a45a8ff 4144 uint8_t RESERVED_23[3];
bogdanm 0:9b334a45a8ff 4145 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
bogdanm 0:9b334a45a8ff 4146 uint8_t RESERVED_24[3];
bogdanm 0:9b334a45a8ff 4147 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
bogdanm 0:9b334a45a8ff 4148 uint8_t RESERVED_25[7];
bogdanm 0:9b334a45a8ff 4149 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
bogdanm 0:9b334a45a8ff 4150 } USB_Type;
bogdanm 0:9b334a45a8ff 4151
bogdanm 0:9b334a45a8ff 4152 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4153 -- USB Register Masks
bogdanm 0:9b334a45a8ff 4154 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4155
bogdanm 0:9b334a45a8ff 4156 /**
bogdanm 0:9b334a45a8ff 4157 * @addtogroup USB_Register_Masks USB Register Masks
bogdanm 0:9b334a45a8ff 4158 * @{
bogdanm 0:9b334a45a8ff 4159 */
bogdanm 0:9b334a45a8ff 4160
bogdanm 0:9b334a45a8ff 4161 /* PERID Bit Fields */
bogdanm 0:9b334a45a8ff 4162 #define USB_PERID_ID_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 4163 #define USB_PERID_ID_SHIFT 0
bogdanm 0:9b334a45a8ff 4164 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
bogdanm 0:9b334a45a8ff 4165 /* IDCOMP Bit Fields */
bogdanm 0:9b334a45a8ff 4166 #define USB_IDCOMP_NID_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 4167 #define USB_IDCOMP_NID_SHIFT 0
bogdanm 0:9b334a45a8ff 4168 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
bogdanm 0:9b334a45a8ff 4169 /* REV Bit Fields */
bogdanm 0:9b334a45a8ff 4170 #define USB_REV_REV_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4171 #define USB_REV_REV_SHIFT 0
bogdanm 0:9b334a45a8ff 4172 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
bogdanm 0:9b334a45a8ff 4173 /* ADDINFO Bit Fields */
bogdanm 0:9b334a45a8ff 4174 #define USB_ADDINFO_IEHOST_MASK 0x1u
bogdanm 0:9b334a45a8ff 4175 #define USB_ADDINFO_IEHOST_SHIFT 0
bogdanm 0:9b334a45a8ff 4176 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
bogdanm 0:9b334a45a8ff 4177 #define USB_ADDINFO_IRQNUM_SHIFT 3
bogdanm 0:9b334a45a8ff 4178 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
bogdanm 0:9b334a45a8ff 4179 /* OTGISTAT Bit Fields */
bogdanm 0:9b334a45a8ff 4180 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
bogdanm 0:9b334a45a8ff 4181 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
bogdanm 0:9b334a45a8ff 4182 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
bogdanm 0:9b334a45a8ff 4183 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
bogdanm 0:9b334a45a8ff 4184 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
bogdanm 0:9b334a45a8ff 4185 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
bogdanm 0:9b334a45a8ff 4186 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
bogdanm 0:9b334a45a8ff 4187 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
bogdanm 0:9b334a45a8ff 4188 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
bogdanm 0:9b334a45a8ff 4189 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
bogdanm 0:9b334a45a8ff 4190 #define USB_OTGISTAT_IDCHG_MASK 0x80u
bogdanm 0:9b334a45a8ff 4191 #define USB_OTGISTAT_IDCHG_SHIFT 7
bogdanm 0:9b334a45a8ff 4192 /* OTGICR Bit Fields */
bogdanm 0:9b334a45a8ff 4193 #define USB_OTGICR_AVBUSEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 4194 #define USB_OTGICR_AVBUSEN_SHIFT 0
bogdanm 0:9b334a45a8ff 4195 #define USB_OTGICR_BSESSEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 4196 #define USB_OTGICR_BSESSEN_SHIFT 2
bogdanm 0:9b334a45a8ff 4197 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 4198 #define USB_OTGICR_SESSVLDEN_SHIFT 3
bogdanm 0:9b334a45a8ff 4199 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 4200 #define USB_OTGICR_LINESTATEEN_SHIFT 5
bogdanm 0:9b334a45a8ff 4201 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 4202 #define USB_OTGICR_ONEMSECEN_SHIFT 6
bogdanm 0:9b334a45a8ff 4203 #define USB_OTGICR_IDEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 4204 #define USB_OTGICR_IDEN_SHIFT 7
bogdanm 0:9b334a45a8ff 4205 /* OTGSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 4206 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
bogdanm 0:9b334a45a8ff 4207 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
bogdanm 0:9b334a45a8ff 4208 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
bogdanm 0:9b334a45a8ff 4209 #define USB_OTGSTAT_BSESSEND_SHIFT 2
bogdanm 0:9b334a45a8ff 4210 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
bogdanm 0:9b334a45a8ff 4211 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
bogdanm 0:9b334a45a8ff 4212 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
bogdanm 0:9b334a45a8ff 4213 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
bogdanm 0:9b334a45a8ff 4214 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 4215 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
bogdanm 0:9b334a45a8ff 4216 #define USB_OTGSTAT_ID_MASK 0x80u
bogdanm 0:9b334a45a8ff 4217 #define USB_OTGSTAT_ID_SHIFT 7
bogdanm 0:9b334a45a8ff 4218 /* OTGCTL Bit Fields */
bogdanm 0:9b334a45a8ff 4219 #define USB_OTGCTL_OTGEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 4220 #define USB_OTGCTL_OTGEN_SHIFT 2
bogdanm 0:9b334a45a8ff 4221 #define USB_OTGCTL_DMLOW_MASK 0x10u
bogdanm 0:9b334a45a8ff 4222 #define USB_OTGCTL_DMLOW_SHIFT 4
bogdanm 0:9b334a45a8ff 4223 #define USB_OTGCTL_DPLOW_MASK 0x20u
bogdanm 0:9b334a45a8ff 4224 #define USB_OTGCTL_DPLOW_SHIFT 5
bogdanm 0:9b334a45a8ff 4225 #define USB_OTGCTL_DPHIGH_MASK 0x80u
bogdanm 0:9b334a45a8ff 4226 #define USB_OTGCTL_DPHIGH_SHIFT 7
bogdanm 0:9b334a45a8ff 4227 /* ISTAT Bit Fields */
bogdanm 0:9b334a45a8ff 4228 #define USB_ISTAT_USBRST_MASK 0x1u
bogdanm 0:9b334a45a8ff 4229 #define USB_ISTAT_USBRST_SHIFT 0
bogdanm 0:9b334a45a8ff 4230 #define USB_ISTAT_ERROR_MASK 0x2u
bogdanm 0:9b334a45a8ff 4231 #define USB_ISTAT_ERROR_SHIFT 1
bogdanm 0:9b334a45a8ff 4232 #define USB_ISTAT_SOFTOK_MASK 0x4u
bogdanm 0:9b334a45a8ff 4233 #define USB_ISTAT_SOFTOK_SHIFT 2
bogdanm 0:9b334a45a8ff 4234 #define USB_ISTAT_TOKDNE_MASK 0x8u
bogdanm 0:9b334a45a8ff 4235 #define USB_ISTAT_TOKDNE_SHIFT 3
bogdanm 0:9b334a45a8ff 4236 #define USB_ISTAT_SLEEP_MASK 0x10u
bogdanm 0:9b334a45a8ff 4237 #define USB_ISTAT_SLEEP_SHIFT 4
bogdanm 0:9b334a45a8ff 4238 #define USB_ISTAT_RESUME_MASK 0x20u
bogdanm 0:9b334a45a8ff 4239 #define USB_ISTAT_RESUME_SHIFT 5
bogdanm 0:9b334a45a8ff 4240 #define USB_ISTAT_ATTACH_MASK 0x40u
bogdanm 0:9b334a45a8ff 4241 #define USB_ISTAT_ATTACH_SHIFT 6
bogdanm 0:9b334a45a8ff 4242 #define USB_ISTAT_STALL_MASK 0x80u
bogdanm 0:9b334a45a8ff 4243 #define USB_ISTAT_STALL_SHIFT 7
bogdanm 0:9b334a45a8ff 4244 /* INTEN Bit Fields */
bogdanm 0:9b334a45a8ff 4245 #define USB_INTEN_USBRSTEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 4246 #define USB_INTEN_USBRSTEN_SHIFT 0
bogdanm 0:9b334a45a8ff 4247 #define USB_INTEN_ERROREN_MASK 0x2u
bogdanm 0:9b334a45a8ff 4248 #define USB_INTEN_ERROREN_SHIFT 1
bogdanm 0:9b334a45a8ff 4249 #define USB_INTEN_SOFTOKEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 4250 #define USB_INTEN_SOFTOKEN_SHIFT 2
bogdanm 0:9b334a45a8ff 4251 #define USB_INTEN_TOKDNEEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 4252 #define USB_INTEN_TOKDNEEN_SHIFT 3
bogdanm 0:9b334a45a8ff 4253 #define USB_INTEN_SLEEPEN_MASK 0x10u
bogdanm 0:9b334a45a8ff 4254 #define USB_INTEN_SLEEPEN_SHIFT 4
bogdanm 0:9b334a45a8ff 4255 #define USB_INTEN_RESUMEEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 4256 #define USB_INTEN_RESUMEEN_SHIFT 5
bogdanm 0:9b334a45a8ff 4257 #define USB_INTEN_ATTACHEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 4258 #define USB_INTEN_ATTACHEN_SHIFT 6
bogdanm 0:9b334a45a8ff 4259 #define USB_INTEN_STALLEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 4260 #define USB_INTEN_STALLEN_SHIFT 7
bogdanm 0:9b334a45a8ff 4261 /* ERRSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 4262 #define USB_ERRSTAT_PIDERR_MASK 0x1u
bogdanm 0:9b334a45a8ff 4263 #define USB_ERRSTAT_PIDERR_SHIFT 0
bogdanm 0:9b334a45a8ff 4264 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
bogdanm 0:9b334a45a8ff 4265 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
bogdanm 0:9b334a45a8ff 4266 #define USB_ERRSTAT_CRC16_MASK 0x4u
bogdanm 0:9b334a45a8ff 4267 #define USB_ERRSTAT_CRC16_SHIFT 2
bogdanm 0:9b334a45a8ff 4268 #define USB_ERRSTAT_DFN8_MASK 0x8u
bogdanm 0:9b334a45a8ff 4269 #define USB_ERRSTAT_DFN8_SHIFT 3
bogdanm 0:9b334a45a8ff 4270 #define USB_ERRSTAT_BTOERR_MASK 0x10u
bogdanm 0:9b334a45a8ff 4271 #define USB_ERRSTAT_BTOERR_SHIFT 4
bogdanm 0:9b334a45a8ff 4272 #define USB_ERRSTAT_DMAERR_MASK 0x20u
bogdanm 0:9b334a45a8ff 4273 #define USB_ERRSTAT_DMAERR_SHIFT 5
bogdanm 0:9b334a45a8ff 4274 #define USB_ERRSTAT_BTSERR_MASK 0x80u
bogdanm 0:9b334a45a8ff 4275 #define USB_ERRSTAT_BTSERR_SHIFT 7
bogdanm 0:9b334a45a8ff 4276 /* ERREN Bit Fields */
bogdanm 0:9b334a45a8ff 4277 #define USB_ERREN_PIDERREN_MASK 0x1u
bogdanm 0:9b334a45a8ff 4278 #define USB_ERREN_PIDERREN_SHIFT 0
bogdanm 0:9b334a45a8ff 4279 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 4280 #define USB_ERREN_CRC5EOFEN_SHIFT 1
bogdanm 0:9b334a45a8ff 4281 #define USB_ERREN_CRC16EN_MASK 0x4u
bogdanm 0:9b334a45a8ff 4282 #define USB_ERREN_CRC16EN_SHIFT 2
bogdanm 0:9b334a45a8ff 4283 #define USB_ERREN_DFN8EN_MASK 0x8u
bogdanm 0:9b334a45a8ff 4284 #define USB_ERREN_DFN8EN_SHIFT 3
bogdanm 0:9b334a45a8ff 4285 #define USB_ERREN_BTOERREN_MASK 0x10u
bogdanm 0:9b334a45a8ff 4286 #define USB_ERREN_BTOERREN_SHIFT 4
bogdanm 0:9b334a45a8ff 4287 #define USB_ERREN_DMAERREN_MASK 0x20u
bogdanm 0:9b334a45a8ff 4288 #define USB_ERREN_DMAERREN_SHIFT 5
bogdanm 0:9b334a45a8ff 4289 #define USB_ERREN_BTSERREN_MASK 0x80u
bogdanm 0:9b334a45a8ff 4290 #define USB_ERREN_BTSERREN_SHIFT 7
bogdanm 0:9b334a45a8ff 4291 /* STAT Bit Fields */
bogdanm 0:9b334a45a8ff 4292 #define USB_STAT_ODD_MASK 0x4u
bogdanm 0:9b334a45a8ff 4293 #define USB_STAT_ODD_SHIFT 2
bogdanm 0:9b334a45a8ff 4294 #define USB_STAT_TX_MASK 0x8u
bogdanm 0:9b334a45a8ff 4295 #define USB_STAT_TX_SHIFT 3
bogdanm 0:9b334a45a8ff 4296 #define USB_STAT_ENDP_MASK 0xF0u
bogdanm 0:9b334a45a8ff 4297 #define USB_STAT_ENDP_SHIFT 4
bogdanm 0:9b334a45a8ff 4298 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
bogdanm 0:9b334a45a8ff 4299 /* CTL Bit Fields */
bogdanm 0:9b334a45a8ff 4300 #define USB_CTL_USBENSOFEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 4301 #define USB_CTL_USBENSOFEN_SHIFT 0
bogdanm 0:9b334a45a8ff 4302 #define USB_CTL_ODDRST_MASK 0x2u
bogdanm 0:9b334a45a8ff 4303 #define USB_CTL_ODDRST_SHIFT 1
bogdanm 0:9b334a45a8ff 4304 #define USB_CTL_RESUME_MASK 0x4u
bogdanm 0:9b334a45a8ff 4305 #define USB_CTL_RESUME_SHIFT 2
bogdanm 0:9b334a45a8ff 4306 #define USB_CTL_HOSTMODEEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 4307 #define USB_CTL_HOSTMODEEN_SHIFT 3
bogdanm 0:9b334a45a8ff 4308 #define USB_CTL_RESET_MASK 0x10u
bogdanm 0:9b334a45a8ff 4309 #define USB_CTL_RESET_SHIFT 4
bogdanm 0:9b334a45a8ff 4310 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
bogdanm 0:9b334a45a8ff 4311 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
bogdanm 0:9b334a45a8ff 4312 #define USB_CTL_SE0_MASK 0x40u
bogdanm 0:9b334a45a8ff 4313 #define USB_CTL_SE0_SHIFT 6
bogdanm 0:9b334a45a8ff 4314 #define USB_CTL_JSTATE_MASK 0x80u
bogdanm 0:9b334a45a8ff 4315 #define USB_CTL_JSTATE_SHIFT 7
bogdanm 0:9b334a45a8ff 4316 /* ADDR Bit Fields */
bogdanm 0:9b334a45a8ff 4317 #define USB_ADDR_ADDR_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 4318 #define USB_ADDR_ADDR_SHIFT 0
bogdanm 0:9b334a45a8ff 4319 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
bogdanm 0:9b334a45a8ff 4320 #define USB_ADDR_LSEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 4321 #define USB_ADDR_LSEN_SHIFT 7
bogdanm 0:9b334a45a8ff 4322 /* BDTPAGE1 Bit Fields */
bogdanm 0:9b334a45a8ff 4323 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
bogdanm 0:9b334a45a8ff 4324 #define USB_BDTPAGE1_BDTBA_SHIFT 1
bogdanm 0:9b334a45a8ff 4325 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
bogdanm 0:9b334a45a8ff 4326 /* FRMNUML Bit Fields */
bogdanm 0:9b334a45a8ff 4327 #define USB_FRMNUML_FRM_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4328 #define USB_FRMNUML_FRM_SHIFT 0
bogdanm 0:9b334a45a8ff 4329 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
bogdanm 0:9b334a45a8ff 4330 /* FRMNUMH Bit Fields */
bogdanm 0:9b334a45a8ff 4331 #define USB_FRMNUMH_FRM_MASK 0x7u
bogdanm 0:9b334a45a8ff 4332 #define USB_FRMNUMH_FRM_SHIFT 0
bogdanm 0:9b334a45a8ff 4333 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
bogdanm 0:9b334a45a8ff 4334 /* TOKEN Bit Fields */
bogdanm 0:9b334a45a8ff 4335 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
bogdanm 0:9b334a45a8ff 4336 #define USB_TOKEN_TOKENENDPT_SHIFT 0
bogdanm 0:9b334a45a8ff 4337 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
bogdanm 0:9b334a45a8ff 4338 #define USB_TOKEN_TOKENPID_MASK 0xF0u
bogdanm 0:9b334a45a8ff 4339 #define USB_TOKEN_TOKENPID_SHIFT 4
bogdanm 0:9b334a45a8ff 4340 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
bogdanm 0:9b334a45a8ff 4341 /* SOFTHLD Bit Fields */
bogdanm 0:9b334a45a8ff 4342 #define USB_SOFTHLD_CNT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4343 #define USB_SOFTHLD_CNT_SHIFT 0
bogdanm 0:9b334a45a8ff 4344 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
bogdanm 0:9b334a45a8ff 4345 /* BDTPAGE2 Bit Fields */
bogdanm 0:9b334a45a8ff 4346 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4347 #define USB_BDTPAGE2_BDTBA_SHIFT 0
bogdanm 0:9b334a45a8ff 4348 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
bogdanm 0:9b334a45a8ff 4349 /* BDTPAGE3 Bit Fields */
bogdanm 0:9b334a45a8ff 4350 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4351 #define USB_BDTPAGE3_BDTBA_SHIFT 0
bogdanm 0:9b334a45a8ff 4352 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
bogdanm 0:9b334a45a8ff 4353 /* ENDPT Bit Fields */
bogdanm 0:9b334a45a8ff 4354 #define USB_ENDPT_EPHSHK_MASK 0x1u
bogdanm 0:9b334a45a8ff 4355 #define USB_ENDPT_EPHSHK_SHIFT 0
bogdanm 0:9b334a45a8ff 4356 #define USB_ENDPT_EPSTALL_MASK 0x2u
bogdanm 0:9b334a45a8ff 4357 #define USB_ENDPT_EPSTALL_SHIFT 1
bogdanm 0:9b334a45a8ff 4358 #define USB_ENDPT_EPTXEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 4359 #define USB_ENDPT_EPTXEN_SHIFT 2
bogdanm 0:9b334a45a8ff 4360 #define USB_ENDPT_EPRXEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 4361 #define USB_ENDPT_EPRXEN_SHIFT 3
bogdanm 0:9b334a45a8ff 4362 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
bogdanm 0:9b334a45a8ff 4363 #define USB_ENDPT_EPCTLDIS_SHIFT 4
bogdanm 0:9b334a45a8ff 4364 #define USB_ENDPT_RETRYDIS_MASK 0x40u
bogdanm 0:9b334a45a8ff 4365 #define USB_ENDPT_RETRYDIS_SHIFT 6
bogdanm 0:9b334a45a8ff 4366 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
bogdanm 0:9b334a45a8ff 4367 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
bogdanm 0:9b334a45a8ff 4368 /* USBCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 4369 #define USB_USBCTRL_PDE_MASK 0x40u
bogdanm 0:9b334a45a8ff 4370 #define USB_USBCTRL_PDE_SHIFT 6
bogdanm 0:9b334a45a8ff 4371 #define USB_USBCTRL_SUSP_MASK 0x80u
bogdanm 0:9b334a45a8ff 4372 #define USB_USBCTRL_SUSP_SHIFT 7
bogdanm 0:9b334a45a8ff 4373 /* OBSERVE Bit Fields */
bogdanm 0:9b334a45a8ff 4374 #define USB_OBSERVE_DMPD_MASK 0x10u
bogdanm 0:9b334a45a8ff 4375 #define USB_OBSERVE_DMPD_SHIFT 4
bogdanm 0:9b334a45a8ff 4376 #define USB_OBSERVE_DPPD_MASK 0x40u
bogdanm 0:9b334a45a8ff 4377 #define USB_OBSERVE_DPPD_SHIFT 6
bogdanm 0:9b334a45a8ff 4378 #define USB_OBSERVE_DPPU_MASK 0x80u
bogdanm 0:9b334a45a8ff 4379 #define USB_OBSERVE_DPPU_SHIFT 7
bogdanm 0:9b334a45a8ff 4380 /* CONTROL Bit Fields */
bogdanm 0:9b334a45a8ff 4381 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
bogdanm 0:9b334a45a8ff 4382 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
bogdanm 0:9b334a45a8ff 4383 /* USBTRC0 Bit Fields */
bogdanm 0:9b334a45a8ff 4384 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
bogdanm 0:9b334a45a8ff 4385 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
bogdanm 0:9b334a45a8ff 4386 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
bogdanm 0:9b334a45a8ff 4387 #define USB_USBTRC0_SYNC_DET_SHIFT 1
bogdanm 0:9b334a45a8ff 4388 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 4389 #define USB_USBTRC0_USBRESMEN_SHIFT 5
bogdanm 0:9b334a45a8ff 4390 #define USB_USBTRC0_USBRESET_MASK 0x80u
bogdanm 0:9b334a45a8ff 4391 #define USB_USBTRC0_USBRESET_SHIFT 7
bogdanm 0:9b334a45a8ff 4392 /* USBFRMADJUST Bit Fields */
bogdanm 0:9b334a45a8ff 4393 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4394 #define USB_USBFRMADJUST_ADJ_SHIFT 0
bogdanm 0:9b334a45a8ff 4395 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
bogdanm 0:9b334a45a8ff 4396
bogdanm 0:9b334a45a8ff 4397 /**
bogdanm 0:9b334a45a8ff 4398 * @}
bogdanm 0:9b334a45a8ff 4399 */ /* end of group USB_Register_Masks */
bogdanm 0:9b334a45a8ff 4400
bogdanm 0:9b334a45a8ff 4401
bogdanm 0:9b334a45a8ff 4402 /* USB - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4403 /** Peripheral USB0 base address */
bogdanm 0:9b334a45a8ff 4404 #define USB0_BASE (0x40072000u)
bogdanm 0:9b334a45a8ff 4405 /** Peripheral USB0 base pointer */
bogdanm 0:9b334a45a8ff 4406 #define USB0 ((USB_Type *)USB0_BASE)
bogdanm 0:9b334a45a8ff 4407 /** Array initializer of USB peripheral base pointers */
bogdanm 0:9b334a45a8ff 4408 #define USB_BASES { USB0 }
bogdanm 0:9b334a45a8ff 4409
bogdanm 0:9b334a45a8ff 4410 /**
bogdanm 0:9b334a45a8ff 4411 * @}
bogdanm 0:9b334a45a8ff 4412 */ /* end of group USB_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4413
bogdanm 0:9b334a45a8ff 4414
bogdanm 0:9b334a45a8ff 4415 /*
bogdanm 0:9b334a45a8ff 4416 ** End of section using anonymous unions
bogdanm 0:9b334a45a8ff 4417 */
bogdanm 0:9b334a45a8ff 4418
bogdanm 0:9b334a45a8ff 4419 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 4420 #pragma pop
bogdanm 0:9b334a45a8ff 4421 #elif defined(__CWCC__)
bogdanm 0:9b334a45a8ff 4422 #pragma pop
bogdanm 0:9b334a45a8ff 4423 #elif defined(__GNUC__)
bogdanm 0:9b334a45a8ff 4424 /* leave anonymous unions enabled */
bogdanm 0:9b334a45a8ff 4425 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 4426 #pragma language=default
bogdanm 0:9b334a45a8ff 4427 #else
bogdanm 0:9b334a45a8ff 4428 #error Not supported compiler type
bogdanm 0:9b334a45a8ff 4429 #endif
bogdanm 0:9b334a45a8ff 4430
bogdanm 0:9b334a45a8ff 4431 /**
bogdanm 0:9b334a45a8ff 4432 * @}
bogdanm 0:9b334a45a8ff 4433 */ /* end of group Peripheral_access_layer */
bogdanm 0:9b334a45a8ff 4434
bogdanm 0:9b334a45a8ff 4435
bogdanm 0:9b334a45a8ff 4436 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4437 -- Backward Compatibility
bogdanm 0:9b334a45a8ff 4438 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4439
bogdanm 0:9b334a45a8ff 4440 /**
bogdanm 0:9b334a45a8ff 4441 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
bogdanm 0:9b334a45a8ff 4442 * @{
bogdanm 0:9b334a45a8ff 4443 */
bogdanm 0:9b334a45a8ff 4444
bogdanm 0:9b334a45a8ff 4445 /* No backward compatibility issues. */
bogdanm 0:9b334a45a8ff 4446
bogdanm 0:9b334a45a8ff 4447 /**
bogdanm 0:9b334a45a8ff 4448 * @}
bogdanm 0:9b334a45a8ff 4449 */ /* end of group Backward_Compatibility_Symbols */
bogdanm 0:9b334a45a8ff 4450
bogdanm 0:9b334a45a8ff 4451
bogdanm 0:9b334a45a8ff 4452 #endif /* #if !defined(MKL26Z4_H_) */
bogdanm 0:9b334a45a8ff 4453
bogdanm 0:9b334a45a8ff 4454 /* MKL26Z4.h, eof. */