Garage Door Monitor and Opener

Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Introduction

This system implements a simple garage door opener and environmental monitor. The hardware connects to the internet using Wi-Fi then on to the Pelion Device Management Platform which provides device monitoring and secure firmware updates over the air (FOTA). Pelion Device Management provides a flexible set of REST APIs which we will use to communicate to a web application running on an EC-2 instance in AWS. The web application will serve a web page where we can monitor and control our garage..

This project is intended to work on the DISCO-L475VG-IOT01A from ST Microelectronics It implements a simple actuator to drive a relay to simulate pushing the "open" button on older style garage doors which do not use a rolling code interface.

The system is designed to be mounted over the door so that the on board time of flight sensor can be used to detect if the door is open or closed.

The system also monitors temperature, humidity and barometric pressure.

https://os.mbed.com/media/uploads/JimCarver/garageopener.jpg

Hardware Requirements:

DISCO-L475G-IOT01A https://os.mbed.com/platforms/ST-Discovery-L475E-IOT01A/

Seeed Studio Grove Relay module https://www.seeedstudio.com/Grove-Relay.html

Seeed Studio Grove cable, I used this one: https://www.seeedstudio.com/Grove-4-pin-Male-Jumper-to-Grove-4-pin-Conversion-Cable-5-PCs-per-Pack.html

Connect to the PMOD connector like this:

https://os.mbed.com/media/uploads/JimCarver/opener.jpg

This shows how I installed so that the time of flight sensor can detect when the door is open

https://os.mbed.com/media/uploads/JimCarver/opener1.jpg https://os.mbed.com/media/uploads/JimCarver/opener2.jpg

To use the project:

You will also need a Pelion developers account.

I suggest you first use the Pelion quick state to become familiar with Pelion Device Management. https://os.mbed.com/guides/connect-device-to-pelion/1/?board=ST-Discovery-L475E-IOT01A

Web Interface

For my web interface I am running node-red under Ubuntu in an EC2 instance on AWS. This can run for 12 month within the constraints of their free tier. Here is a tutorial: https://nodered.org/docs/getting-started/aws

You will also need to install several node-red add ons:

sudo npm install -g node-red-dashboard

sudo npm install -g node-red-contrib-mbed-cloud

sudo npm istall -g node-red-contrib-moment

After starting node-red import the contents of GarageFlow.txt from the project, pin the flow into the page.

To enable your web app to access your Pelion account you need an API key.

First you will neet to use your Pelion account to create an API key.

https://os.mbed.com/media/uploads/JimCarver/api_portal.jpg

Now we need to apply that API key to your Node-Red flow.

https://os.mbed.com/media/uploads/JimCarver/api_node-red.jpg

Committer:
JimCarver
Date:
Thu Dec 05 19:03:48 2019 +0000
Revision:
37:ec1124e5ec1f
Parent:
28:0e774865873d
Bug fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 28:0e774865873d 1 /**
screamer 28:0e774865873d 2 ******************************************************************************
screamer 28:0e774865873d 3 * @file stm32l475xx.h
screamer 28:0e774865873d 4 * @author MCD Application Team
screamer 28:0e774865873d 5 * @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File.
screamer 28:0e774865873d 6 *
screamer 28:0e774865873d 7 * This file contains:
screamer 28:0e774865873d 8 * - Data structures and the address mapping for all peripherals
screamer 28:0e774865873d 9 * - Peripheral's registers declarations and bits definition
screamer 28:0e774865873d 10 * - Macros to access peripheral’s registers hardware
screamer 28:0e774865873d 11 *
screamer 28:0e774865873d 12 ******************************************************************************
screamer 28:0e774865873d 13 * @attention
screamer 28:0e774865873d 14 *
screamer 28:0e774865873d 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
screamer 28:0e774865873d 16 *
screamer 28:0e774865873d 17 * Redistribution and use in source and binary forms, with or without modification,
screamer 28:0e774865873d 18 * are permitted provided that the following conditions are met:
screamer 28:0e774865873d 19 * 1. Redistributions of source code must retain the above copyright notice,
screamer 28:0e774865873d 20 * this list of conditions and the following disclaimer.
screamer 28:0e774865873d 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
screamer 28:0e774865873d 22 * this list of conditions and the following disclaimer in the documentation
screamer 28:0e774865873d 23 * and/or other materials provided with the distribution.
screamer 28:0e774865873d 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
screamer 28:0e774865873d 25 * may be used to endorse or promote products derived from this software
screamer 28:0e774865873d 26 * without specific prior written permission.
screamer 28:0e774865873d 27 *
screamer 28:0e774865873d 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
screamer 28:0e774865873d 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
screamer 28:0e774865873d 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 28:0e774865873d 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
screamer 28:0e774865873d 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
screamer 28:0e774865873d 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
screamer 28:0e774865873d 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
screamer 28:0e774865873d 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
screamer 28:0e774865873d 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
screamer 28:0e774865873d 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 28:0e774865873d 38 *
screamer 28:0e774865873d 39 ******************************************************************************
screamer 28:0e774865873d 40 */
screamer 28:0e774865873d 41
screamer 28:0e774865873d 42 /** @addtogroup CMSIS_Device
screamer 28:0e774865873d 43 * @{
screamer 28:0e774865873d 44 */
screamer 28:0e774865873d 45
screamer 28:0e774865873d 46 /** @addtogroup stm32l475xx
screamer 28:0e774865873d 47 * @{
screamer 28:0e774865873d 48 */
screamer 28:0e774865873d 49
screamer 28:0e774865873d 50 #ifndef __STM32L475xx_H
screamer 28:0e774865873d 51 #define __STM32L475xx_H
screamer 28:0e774865873d 52
screamer 28:0e774865873d 53 #ifdef __cplusplus
screamer 28:0e774865873d 54 extern "C" {
screamer 28:0e774865873d 55 #endif /* __cplusplus */
screamer 28:0e774865873d 56
screamer 28:0e774865873d 57 /** @addtogroup Configuration_section_for_CMSIS
screamer 28:0e774865873d 58 * @{
screamer 28:0e774865873d 59 */
screamer 28:0e774865873d 60
screamer 28:0e774865873d 61 /**
screamer 28:0e774865873d 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
screamer 28:0e774865873d 63 */
screamer 28:0e774865873d 64 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
screamer 28:0e774865873d 65 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
screamer 28:0e774865873d 66 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
screamer 28:0e774865873d 67 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
screamer 28:0e774865873d 68 #define __FPU_PRESENT 1 /*!< FPU present */
screamer 28:0e774865873d 69
screamer 28:0e774865873d 70 /**
screamer 28:0e774865873d 71 * @}
screamer 28:0e774865873d 72 */
screamer 28:0e774865873d 73
screamer 28:0e774865873d 74 /** @addtogroup Peripheral_interrupt_number_definition
screamer 28:0e774865873d 75 * @{
screamer 28:0e774865873d 76 */
screamer 28:0e774865873d 77
screamer 28:0e774865873d 78 /**
screamer 28:0e774865873d 79 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
screamer 28:0e774865873d 80 * in @ref Library_configuration_section
screamer 28:0e774865873d 81 */
screamer 28:0e774865873d 82 typedef enum
screamer 28:0e774865873d 83 {
screamer 28:0e774865873d 84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
screamer 28:0e774865873d 85 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
screamer 28:0e774865873d 86 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
screamer 28:0e774865873d 87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
screamer 28:0e774865873d 88 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
screamer 28:0e774865873d 89 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
screamer 28:0e774865873d 90 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
screamer 28:0e774865873d 91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
screamer 28:0e774865873d 92 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
screamer 28:0e774865873d 93 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
screamer 28:0e774865873d 94 /****** STM32 specific Interrupt Numbers **********************************************************************/
screamer 28:0e774865873d 95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
screamer 28:0e774865873d 96 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
screamer 28:0e774865873d 97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
screamer 28:0e774865873d 98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
screamer 28:0e774865873d 99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
screamer 28:0e774865873d 100 RCC_IRQn = 5, /*!< RCC global Interrupt */
screamer 28:0e774865873d 101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
screamer 28:0e774865873d 102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
screamer 28:0e774865873d 103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
screamer 28:0e774865873d 104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
screamer 28:0e774865873d 105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
screamer 28:0e774865873d 106 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
screamer 28:0e774865873d 107 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
screamer 28:0e774865873d 108 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
screamer 28:0e774865873d 109 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
screamer 28:0e774865873d 110 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
screamer 28:0e774865873d 111 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
screamer 28:0e774865873d 112 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
screamer 28:0e774865873d 113 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
screamer 28:0e774865873d 114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
screamer 28:0e774865873d 115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
screamer 28:0e774865873d 116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
screamer 28:0e774865873d 117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
screamer 28:0e774865873d 118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
screamer 28:0e774865873d 119 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
screamer 28:0e774865873d 120 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
screamer 28:0e774865873d 121 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
screamer 28:0e774865873d 122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
screamer 28:0e774865873d 123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
screamer 28:0e774865873d 124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
screamer 28:0e774865873d 125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
screamer 28:0e774865873d 126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
screamer 28:0e774865873d 127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
screamer 28:0e774865873d 128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
screamer 28:0e774865873d 129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
screamer 28:0e774865873d 130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
screamer 28:0e774865873d 131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
screamer 28:0e774865873d 132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
screamer 28:0e774865873d 133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
screamer 28:0e774865873d 134 USART3_IRQn = 39, /*!< USART3 global Interrupt */
screamer 28:0e774865873d 135 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
screamer 28:0e774865873d 136 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
screamer 28:0e774865873d 137 DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
screamer 28:0e774865873d 138 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
screamer 28:0e774865873d 139 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
screamer 28:0e774865873d 140 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
screamer 28:0e774865873d 141 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
screamer 28:0e774865873d 142 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
screamer 28:0e774865873d 143 FMC_IRQn = 48, /*!< FMC global Interrupt */
screamer 28:0e774865873d 144 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
screamer 28:0e774865873d 145 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
screamer 28:0e774865873d 146 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
screamer 28:0e774865873d 147 UART4_IRQn = 52, /*!< UART4 global Interrupt */
screamer 28:0e774865873d 148 UART5_IRQn = 53, /*!< UART5 global Interrupt */
screamer 28:0e774865873d 149 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
screamer 28:0e774865873d 150 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
screamer 28:0e774865873d 151 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
screamer 28:0e774865873d 152 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
screamer 28:0e774865873d 153 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
screamer 28:0e774865873d 154 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
screamer 28:0e774865873d 155 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
screamer 28:0e774865873d 156 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
screamer 28:0e774865873d 157 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
screamer 28:0e774865873d 158 DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
screamer 28:0e774865873d 159 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
screamer 28:0e774865873d 160 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
screamer 28:0e774865873d 161 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
screamer 28:0e774865873d 162 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
screamer 28:0e774865873d 163 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
screamer 28:0e774865873d 164 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
screamer 28:0e774865873d 165 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
screamer 28:0e774865873d 166 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
screamer 28:0e774865873d 167 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
screamer 28:0e774865873d 168 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
screamer 28:0e774865873d 169 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
screamer 28:0e774865873d 170 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
screamer 28:0e774865873d 171 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
screamer 28:0e774865873d 172 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
screamer 28:0e774865873d 173 RNG_IRQn = 80, /*!< RNG global interrupt */
screamer 28:0e774865873d 174 FPU_IRQn = 81 /*!< FPU global interrupt */
screamer 28:0e774865873d 175 } IRQn_Type;
screamer 28:0e774865873d 176
screamer 28:0e774865873d 177 /**
screamer 28:0e774865873d 178 * @}
screamer 28:0e774865873d 179 */
screamer 28:0e774865873d 180
screamer 28:0e774865873d 181 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
screamer 28:0e774865873d 182 #include "system_stm32l4xx.h"
screamer 28:0e774865873d 183 #include <stdint.h>
screamer 28:0e774865873d 184
screamer 28:0e774865873d 185 /** @addtogroup Peripheral_registers_structures
screamer 28:0e774865873d 186 * @{
screamer 28:0e774865873d 187 */
screamer 28:0e774865873d 188
screamer 28:0e774865873d 189 /**
screamer 28:0e774865873d 190 * @brief Analog to Digital Converter
screamer 28:0e774865873d 191 */
screamer 28:0e774865873d 192
screamer 28:0e774865873d 193 typedef struct
screamer 28:0e774865873d 194 {
screamer 28:0e774865873d 195 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
screamer 28:0e774865873d 196 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
screamer 28:0e774865873d 197 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
screamer 28:0e774865873d 198 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
screamer 28:0e774865873d 199 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
screamer 28:0e774865873d 200 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
screamer 28:0e774865873d 201 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
screamer 28:0e774865873d 202 uint32_t RESERVED1; /*!< Reserved, 0x1C */
screamer 28:0e774865873d 203 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
screamer 28:0e774865873d 204 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
screamer 28:0e774865873d 205 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
screamer 28:0e774865873d 206 uint32_t RESERVED2; /*!< Reserved, 0x2C */
screamer 28:0e774865873d 207 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
screamer 28:0e774865873d 208 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
screamer 28:0e774865873d 209 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
screamer 28:0e774865873d 210 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
screamer 28:0e774865873d 211 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
screamer 28:0e774865873d 212 uint32_t RESERVED3; /*!< Reserved, 0x44 */
screamer 28:0e774865873d 213 uint32_t RESERVED4; /*!< Reserved, 0x48 */
screamer 28:0e774865873d 214 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
screamer 28:0e774865873d 215 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
screamer 28:0e774865873d 216 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
screamer 28:0e774865873d 217 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
screamer 28:0e774865873d 218 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
screamer 28:0e774865873d 219 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
screamer 28:0e774865873d 220 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
screamer 28:0e774865873d 221 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
screamer 28:0e774865873d 222 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
screamer 28:0e774865873d 223 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
screamer 28:0e774865873d 224 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
screamer 28:0e774865873d 225 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
screamer 28:0e774865873d 226 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
screamer 28:0e774865873d 227 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
screamer 28:0e774865873d 228 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
screamer 28:0e774865873d 229 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
screamer 28:0e774865873d 230 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
screamer 28:0e774865873d 231 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
screamer 28:0e774865873d 232
screamer 28:0e774865873d 233 } ADC_TypeDef;
screamer 28:0e774865873d 234
screamer 28:0e774865873d 235 typedef struct
screamer 28:0e774865873d 236 {
screamer 28:0e774865873d 237 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
screamer 28:0e774865873d 238 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
screamer 28:0e774865873d 239 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
screamer 28:0e774865873d 240 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
screamer 28:0e774865873d 241 } ADC_Common_TypeDef;
screamer 28:0e774865873d 242
screamer 28:0e774865873d 243
screamer 28:0e774865873d 244 /**
screamer 28:0e774865873d 245 * @brief Controller Area Network TxMailBox
screamer 28:0e774865873d 246 */
screamer 28:0e774865873d 247
screamer 28:0e774865873d 248 typedef struct
screamer 28:0e774865873d 249 {
screamer 28:0e774865873d 250 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
screamer 28:0e774865873d 251 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
screamer 28:0e774865873d 252 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
screamer 28:0e774865873d 253 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
screamer 28:0e774865873d 254 } CAN_TxMailBox_TypeDef;
screamer 28:0e774865873d 255
screamer 28:0e774865873d 256 /**
screamer 28:0e774865873d 257 * @brief Controller Area Network FIFOMailBox
screamer 28:0e774865873d 258 */
screamer 28:0e774865873d 259
screamer 28:0e774865873d 260 typedef struct
screamer 28:0e774865873d 261 {
screamer 28:0e774865873d 262 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
screamer 28:0e774865873d 263 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
screamer 28:0e774865873d 264 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
screamer 28:0e774865873d 265 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
screamer 28:0e774865873d 266 } CAN_FIFOMailBox_TypeDef;
screamer 28:0e774865873d 267
screamer 28:0e774865873d 268 /**
screamer 28:0e774865873d 269 * @brief Controller Area Network FilterRegister
screamer 28:0e774865873d 270 */
screamer 28:0e774865873d 271
screamer 28:0e774865873d 272 typedef struct
screamer 28:0e774865873d 273 {
screamer 28:0e774865873d 274 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
screamer 28:0e774865873d 275 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
screamer 28:0e774865873d 276 } CAN_FilterRegister_TypeDef;
screamer 28:0e774865873d 277
screamer 28:0e774865873d 278 /**
screamer 28:0e774865873d 279 * @brief Controller Area Network
screamer 28:0e774865873d 280 */
screamer 28:0e774865873d 281
screamer 28:0e774865873d 282 typedef struct
screamer 28:0e774865873d 283 {
screamer 28:0e774865873d 284 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
screamer 28:0e774865873d 285 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
screamer 28:0e774865873d 286 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
screamer 28:0e774865873d 287 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
screamer 28:0e774865873d 288 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
screamer 28:0e774865873d 289 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
screamer 28:0e774865873d 290 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
screamer 28:0e774865873d 291 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
screamer 28:0e774865873d 292 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
screamer 28:0e774865873d 293 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
screamer 28:0e774865873d 294 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
screamer 28:0e774865873d 295 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
screamer 28:0e774865873d 296 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
screamer 28:0e774865873d 297 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
screamer 28:0e774865873d 298 uint32_t RESERVED2; /*!< Reserved, 0x208 */
screamer 28:0e774865873d 299 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
screamer 28:0e774865873d 300 uint32_t RESERVED3; /*!< Reserved, 0x210 */
screamer 28:0e774865873d 301 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
screamer 28:0e774865873d 302 uint32_t RESERVED4; /*!< Reserved, 0x218 */
screamer 28:0e774865873d 303 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
screamer 28:0e774865873d 304 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
screamer 28:0e774865873d 305 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
screamer 28:0e774865873d 306 } CAN_TypeDef;
screamer 28:0e774865873d 307
screamer 28:0e774865873d 308
screamer 28:0e774865873d 309 /**
screamer 28:0e774865873d 310 * @brief Comparator
screamer 28:0e774865873d 311 */
screamer 28:0e774865873d 312
screamer 28:0e774865873d 313 typedef struct
screamer 28:0e774865873d 314 {
screamer 28:0e774865873d 315 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
screamer 28:0e774865873d 316 } COMP_TypeDef;
screamer 28:0e774865873d 317
screamer 28:0e774865873d 318 typedef struct
screamer 28:0e774865873d 319 {
screamer 28:0e774865873d 320 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
screamer 28:0e774865873d 321 } COMP_Common_TypeDef;
screamer 28:0e774865873d 322
screamer 28:0e774865873d 323 /**
screamer 28:0e774865873d 324 * @brief CRC calculation unit
screamer 28:0e774865873d 325 */
screamer 28:0e774865873d 326
screamer 28:0e774865873d 327 typedef struct
screamer 28:0e774865873d 328 {
screamer 28:0e774865873d 329 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
screamer 28:0e774865873d 330 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
screamer 28:0e774865873d 331 uint8_t RESERVED0; /*!< Reserved, 0x05 */
screamer 28:0e774865873d 332 uint16_t RESERVED1; /*!< Reserved, 0x06 */
screamer 28:0e774865873d 333 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
screamer 28:0e774865873d 334 uint32_t RESERVED2; /*!< Reserved, 0x0C */
screamer 28:0e774865873d 335 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
screamer 28:0e774865873d 336 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
screamer 28:0e774865873d 337 } CRC_TypeDef;
screamer 28:0e774865873d 338
screamer 28:0e774865873d 339 /**
screamer 28:0e774865873d 340 * @brief Digital to Analog Converter
screamer 28:0e774865873d 341 */
screamer 28:0e774865873d 342
screamer 28:0e774865873d 343 typedef struct
screamer 28:0e774865873d 344 {
screamer 28:0e774865873d 345 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
screamer 28:0e774865873d 346 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
screamer 28:0e774865873d 347 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
screamer 28:0e774865873d 348 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
screamer 28:0e774865873d 349 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
screamer 28:0e774865873d 350 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
screamer 28:0e774865873d 351 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
screamer 28:0e774865873d 352 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
screamer 28:0e774865873d 353 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
screamer 28:0e774865873d 354 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
screamer 28:0e774865873d 355 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
screamer 28:0e774865873d 356 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
screamer 28:0e774865873d 357 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
screamer 28:0e774865873d 358 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
screamer 28:0e774865873d 359 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
screamer 28:0e774865873d 360 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
screamer 28:0e774865873d 361 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
screamer 28:0e774865873d 362 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
screamer 28:0e774865873d 363 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
screamer 28:0e774865873d 364 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
screamer 28:0e774865873d 365 } DAC_TypeDef;
screamer 28:0e774865873d 366
screamer 28:0e774865873d 367 /**
screamer 28:0e774865873d 368 * @brief DFSDM module registers
screamer 28:0e774865873d 369 */
screamer 28:0e774865873d 370 typedef struct
screamer 28:0e774865873d 371 {
screamer 28:0e774865873d 372 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
screamer 28:0e774865873d 373 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
screamer 28:0e774865873d 374 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
screamer 28:0e774865873d 375 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
screamer 28:0e774865873d 376 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
screamer 28:0e774865873d 377 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
screamer 28:0e774865873d 378 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
screamer 28:0e774865873d 379 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
screamer 28:0e774865873d 380 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
screamer 28:0e774865873d 381 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
screamer 28:0e774865873d 382 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
screamer 28:0e774865873d 383 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
screamer 28:0e774865873d 384 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
screamer 28:0e774865873d 385 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
screamer 28:0e774865873d 386 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
screamer 28:0e774865873d 387 } DFSDM_Filter_TypeDef;
screamer 28:0e774865873d 388
screamer 28:0e774865873d 389 /**
screamer 28:0e774865873d 390 * @brief DFSDM channel configuration registers
screamer 28:0e774865873d 391 */
screamer 28:0e774865873d 392 typedef struct
screamer 28:0e774865873d 393 {
screamer 28:0e774865873d 394 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
screamer 28:0e774865873d 395 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
screamer 28:0e774865873d 396 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
screamer 28:0e774865873d 397 short circuit detector register, Address offset: 0x08 */
screamer 28:0e774865873d 398 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
screamer 28:0e774865873d 399 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
screamer 28:0e774865873d 400 } DFSDM_Channel_TypeDef;
screamer 28:0e774865873d 401
screamer 28:0e774865873d 402 /**
screamer 28:0e774865873d 403 * @brief Debug MCU
screamer 28:0e774865873d 404 */
screamer 28:0e774865873d 405
screamer 28:0e774865873d 406 typedef struct
screamer 28:0e774865873d 407 {
screamer 28:0e774865873d 408 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
screamer 28:0e774865873d 409 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
screamer 28:0e774865873d 410 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
screamer 28:0e774865873d 411 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
screamer 28:0e774865873d 412 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
screamer 28:0e774865873d 413 } DBGMCU_TypeDef;
screamer 28:0e774865873d 414
screamer 28:0e774865873d 415
screamer 28:0e774865873d 416 /**
screamer 28:0e774865873d 417 * @brief DMA Controller
screamer 28:0e774865873d 418 */
screamer 28:0e774865873d 419
screamer 28:0e774865873d 420 typedef struct
screamer 28:0e774865873d 421 {
screamer 28:0e774865873d 422 __IO uint32_t CCR; /*!< DMA channel x configuration register */
screamer 28:0e774865873d 423 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
screamer 28:0e774865873d 424 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
screamer 28:0e774865873d 425 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
screamer 28:0e774865873d 426 } DMA_Channel_TypeDef;
screamer 28:0e774865873d 427
screamer 28:0e774865873d 428 typedef struct
screamer 28:0e774865873d 429 {
screamer 28:0e774865873d 430 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
screamer 28:0e774865873d 431 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
screamer 28:0e774865873d 432 } DMA_TypeDef;
screamer 28:0e774865873d 433
screamer 28:0e774865873d 434 typedef struct
screamer 28:0e774865873d 435 {
screamer 28:0e774865873d 436 __IO uint32_t CSELR; /*!< DMA channel selection register */
screamer 28:0e774865873d 437 } DMA_Request_TypeDef;
screamer 28:0e774865873d 438
screamer 28:0e774865873d 439 /* Legacy define */
screamer 28:0e774865873d 440 #define DMA_request_TypeDef DMA_Request_TypeDef
screamer 28:0e774865873d 441
screamer 28:0e774865873d 442
screamer 28:0e774865873d 443 /**
screamer 28:0e774865873d 444 * @brief External Interrupt/Event Controller
screamer 28:0e774865873d 445 */
screamer 28:0e774865873d 446
screamer 28:0e774865873d 447 typedef struct
screamer 28:0e774865873d 448 {
screamer 28:0e774865873d 449 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
screamer 28:0e774865873d 450 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
screamer 28:0e774865873d 451 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
screamer 28:0e774865873d 452 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
screamer 28:0e774865873d 453 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
screamer 28:0e774865873d 454 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
screamer 28:0e774865873d 455 uint32_t RESERVED1; /*!< Reserved, 0x18 */
screamer 28:0e774865873d 456 uint32_t RESERVED2; /*!< Reserved, 0x1C */
screamer 28:0e774865873d 457 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
screamer 28:0e774865873d 458 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
screamer 28:0e774865873d 459 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
screamer 28:0e774865873d 460 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
screamer 28:0e774865873d 461 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
screamer 28:0e774865873d 462 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
screamer 28:0e774865873d 463 } EXTI_TypeDef;
screamer 28:0e774865873d 464
screamer 28:0e774865873d 465
screamer 28:0e774865873d 466 /**
screamer 28:0e774865873d 467 * @brief Firewall
screamer 28:0e774865873d 468 */
screamer 28:0e774865873d 469
screamer 28:0e774865873d 470 typedef struct
screamer 28:0e774865873d 471 {
screamer 28:0e774865873d 472 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
screamer 28:0e774865873d 473 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
screamer 28:0e774865873d 474 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
screamer 28:0e774865873d 475 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
screamer 28:0e774865873d 476 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
screamer 28:0e774865873d 477 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
screamer 28:0e774865873d 478 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
screamer 28:0e774865873d 479 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
screamer 28:0e774865873d 480 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
screamer 28:0e774865873d 481 } FIREWALL_TypeDef;
screamer 28:0e774865873d 482
screamer 28:0e774865873d 483
screamer 28:0e774865873d 484 /**
screamer 28:0e774865873d 485 * @brief FLASH Registers
screamer 28:0e774865873d 486 */
screamer 28:0e774865873d 487
screamer 28:0e774865873d 488 typedef struct
screamer 28:0e774865873d 489 {
screamer 28:0e774865873d 490 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
screamer 28:0e774865873d 491 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
screamer 28:0e774865873d 492 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
screamer 28:0e774865873d 493 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
screamer 28:0e774865873d 494 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
screamer 28:0e774865873d 495 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
screamer 28:0e774865873d 496 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
screamer 28:0e774865873d 497 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
screamer 28:0e774865873d 498 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
screamer 28:0e774865873d 499 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
screamer 28:0e774865873d 500 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
screamer 28:0e774865873d 501 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
screamer 28:0e774865873d 502 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
screamer 28:0e774865873d 503 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
screamer 28:0e774865873d 504 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
screamer 28:0e774865873d 505 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
screamer 28:0e774865873d 506 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
screamer 28:0e774865873d 507 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
screamer 28:0e774865873d 508 } FLASH_TypeDef;
screamer 28:0e774865873d 509
screamer 28:0e774865873d 510
screamer 28:0e774865873d 511 /**
screamer 28:0e774865873d 512 * @brief Flexible Memory Controller
screamer 28:0e774865873d 513 */
screamer 28:0e774865873d 514
screamer 28:0e774865873d 515 typedef struct
screamer 28:0e774865873d 516 {
screamer 28:0e774865873d 517 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
screamer 28:0e774865873d 518 } FMC_Bank1_TypeDef;
screamer 28:0e774865873d 519
screamer 28:0e774865873d 520 /**
screamer 28:0e774865873d 521 * @brief Flexible Memory Controller Bank1E
screamer 28:0e774865873d 522 */
screamer 28:0e774865873d 523
screamer 28:0e774865873d 524 typedef struct
screamer 28:0e774865873d 525 {
screamer 28:0e774865873d 526 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
screamer 28:0e774865873d 527 } FMC_Bank1E_TypeDef;
screamer 28:0e774865873d 528
screamer 28:0e774865873d 529 /**
screamer 28:0e774865873d 530 * @brief Flexible Memory Controller Bank3
screamer 28:0e774865873d 531 */
screamer 28:0e774865873d 532
screamer 28:0e774865873d 533 typedef struct
screamer 28:0e774865873d 534 {
screamer 28:0e774865873d 535 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
screamer 28:0e774865873d 536 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
screamer 28:0e774865873d 537 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
screamer 28:0e774865873d 538 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
screamer 28:0e774865873d 539 uint32_t RESERVED0; /*!< Reserved, 0x90 */
screamer 28:0e774865873d 540 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
screamer 28:0e774865873d 541 } FMC_Bank3_TypeDef;
screamer 28:0e774865873d 542
screamer 28:0e774865873d 543 /**
screamer 28:0e774865873d 544 * @brief General Purpose I/O
screamer 28:0e774865873d 545 */
screamer 28:0e774865873d 546
screamer 28:0e774865873d 547 typedef struct
screamer 28:0e774865873d 548 {
screamer 28:0e774865873d 549 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
screamer 28:0e774865873d 550 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
screamer 28:0e774865873d 551 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
screamer 28:0e774865873d 552 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
screamer 28:0e774865873d 553 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
screamer 28:0e774865873d 554 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
screamer 28:0e774865873d 555 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
screamer 28:0e774865873d 556 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
screamer 28:0e774865873d 557 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
screamer 28:0e774865873d 558 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
screamer 28:0e774865873d 559 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
screamer 28:0e774865873d 560
screamer 28:0e774865873d 561 } GPIO_TypeDef;
screamer 28:0e774865873d 562
screamer 28:0e774865873d 563
screamer 28:0e774865873d 564 /**
screamer 28:0e774865873d 565 * @brief Inter-integrated Circuit Interface
screamer 28:0e774865873d 566 */
screamer 28:0e774865873d 567
screamer 28:0e774865873d 568 typedef struct
screamer 28:0e774865873d 569 {
screamer 28:0e774865873d 570 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
screamer 28:0e774865873d 571 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
screamer 28:0e774865873d 572 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
screamer 28:0e774865873d 573 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
screamer 28:0e774865873d 574 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
screamer 28:0e774865873d 575 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
screamer 28:0e774865873d 576 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
screamer 28:0e774865873d 577 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
screamer 28:0e774865873d 578 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
screamer 28:0e774865873d 579 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
screamer 28:0e774865873d 580 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
screamer 28:0e774865873d 581 } I2C_TypeDef;
screamer 28:0e774865873d 582
screamer 28:0e774865873d 583 /**
screamer 28:0e774865873d 584 * @brief Independent WATCHDOG
screamer 28:0e774865873d 585 */
screamer 28:0e774865873d 586
screamer 28:0e774865873d 587 typedef struct
screamer 28:0e774865873d 588 {
screamer 28:0e774865873d 589 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
screamer 28:0e774865873d 590 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
screamer 28:0e774865873d 591 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
screamer 28:0e774865873d 592 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
screamer 28:0e774865873d 593 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
screamer 28:0e774865873d 594 } IWDG_TypeDef;
screamer 28:0e774865873d 595
screamer 28:0e774865873d 596 /**
screamer 28:0e774865873d 597 * @brief LPTIMER
screamer 28:0e774865873d 598 */
screamer 28:0e774865873d 599 typedef struct
screamer 28:0e774865873d 600 {
screamer 28:0e774865873d 601 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
screamer 28:0e774865873d 602 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
screamer 28:0e774865873d 603 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
screamer 28:0e774865873d 604 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
screamer 28:0e774865873d 605 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
screamer 28:0e774865873d 606 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
screamer 28:0e774865873d 607 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
screamer 28:0e774865873d 608 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
screamer 28:0e774865873d 609 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
screamer 28:0e774865873d 610 } LPTIM_TypeDef;
screamer 28:0e774865873d 611
screamer 28:0e774865873d 612 /**
screamer 28:0e774865873d 613 * @brief Operational Amplifier (OPAMP)
screamer 28:0e774865873d 614 */
screamer 28:0e774865873d 615
screamer 28:0e774865873d 616 typedef struct
screamer 28:0e774865873d 617 {
screamer 28:0e774865873d 618 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
screamer 28:0e774865873d 619 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
screamer 28:0e774865873d 620 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
screamer 28:0e774865873d 621 } OPAMP_TypeDef;
screamer 28:0e774865873d 622
screamer 28:0e774865873d 623 typedef struct
screamer 28:0e774865873d 624 {
screamer 28:0e774865873d 625 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
screamer 28:0e774865873d 626 } OPAMP_Common_TypeDef;
screamer 28:0e774865873d 627
screamer 28:0e774865873d 628 /**
screamer 28:0e774865873d 629 * @brief Power Control
screamer 28:0e774865873d 630 */
screamer 28:0e774865873d 631
screamer 28:0e774865873d 632 typedef struct
screamer 28:0e774865873d 633 {
screamer 28:0e774865873d 634 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
screamer 28:0e774865873d 635 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
screamer 28:0e774865873d 636 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
screamer 28:0e774865873d 637 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
screamer 28:0e774865873d 638 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
screamer 28:0e774865873d 639 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
screamer 28:0e774865873d 640 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
screamer 28:0e774865873d 641 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
screamer 28:0e774865873d 642 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
screamer 28:0e774865873d 643 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
screamer 28:0e774865873d 644 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
screamer 28:0e774865873d 645 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
screamer 28:0e774865873d 646 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
screamer 28:0e774865873d 647 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
screamer 28:0e774865873d 648 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
screamer 28:0e774865873d 649 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
screamer 28:0e774865873d 650 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
screamer 28:0e774865873d 651 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
screamer 28:0e774865873d 652 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
screamer 28:0e774865873d 653 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
screamer 28:0e774865873d 654 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
screamer 28:0e774865873d 655 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
screamer 28:0e774865873d 656 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
screamer 28:0e774865873d 657 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
screamer 28:0e774865873d 658 } PWR_TypeDef;
screamer 28:0e774865873d 659
screamer 28:0e774865873d 660
screamer 28:0e774865873d 661 /**
screamer 28:0e774865873d 662 * @brief QUAD Serial Peripheral Interface
screamer 28:0e774865873d 663 */
screamer 28:0e774865873d 664
screamer 28:0e774865873d 665 typedef struct
screamer 28:0e774865873d 666 {
screamer 28:0e774865873d 667 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
screamer 28:0e774865873d 668 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
screamer 28:0e774865873d 669 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
screamer 28:0e774865873d 670 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
screamer 28:0e774865873d 671 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
screamer 28:0e774865873d 672 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
screamer 28:0e774865873d 673 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
screamer 28:0e774865873d 674 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
screamer 28:0e774865873d 675 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
screamer 28:0e774865873d 676 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
screamer 28:0e774865873d 677 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
screamer 28:0e774865873d 678 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
screamer 28:0e774865873d 679 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
screamer 28:0e774865873d 680 } QUADSPI_TypeDef;
screamer 28:0e774865873d 681
screamer 28:0e774865873d 682
screamer 28:0e774865873d 683 /**
screamer 28:0e774865873d 684 * @brief Reset and Clock Control
screamer 28:0e774865873d 685 */
screamer 28:0e774865873d 686
screamer 28:0e774865873d 687 typedef struct
screamer 28:0e774865873d 688 {
screamer 28:0e774865873d 689 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
screamer 28:0e774865873d 690 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
screamer 28:0e774865873d 691 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
screamer 28:0e774865873d 692 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
screamer 28:0e774865873d 693 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
screamer 28:0e774865873d 694 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
screamer 28:0e774865873d 695 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
screamer 28:0e774865873d 696 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
screamer 28:0e774865873d 697 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
screamer 28:0e774865873d 698 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
screamer 28:0e774865873d 699 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
screamer 28:0e774865873d 700 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
screamer 28:0e774865873d 701 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
screamer 28:0e774865873d 702 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
screamer 28:0e774865873d 703 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
screamer 28:0e774865873d 704 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
screamer 28:0e774865873d 705 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
screamer 28:0e774865873d 706 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
screamer 28:0e774865873d 707 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
screamer 28:0e774865873d 708 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
screamer 28:0e774865873d 709 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
screamer 28:0e774865873d 710 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
screamer 28:0e774865873d 711 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
screamer 28:0e774865873d 712 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
screamer 28:0e774865873d 713 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
screamer 28:0e774865873d 714 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
screamer 28:0e774865873d 715 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
screamer 28:0e774865873d 716 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
screamer 28:0e774865873d 717 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
screamer 28:0e774865873d 718 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
screamer 28:0e774865873d 719 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
screamer 28:0e774865873d 720 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
screamer 28:0e774865873d 721 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
screamer 28:0e774865873d 722 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
screamer 28:0e774865873d 723 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
screamer 28:0e774865873d 724 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
screamer 28:0e774865873d 725 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
screamer 28:0e774865873d 726 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
screamer 28:0e774865873d 727 } RCC_TypeDef;
screamer 28:0e774865873d 728
screamer 28:0e774865873d 729 /**
screamer 28:0e774865873d 730 * @brief Real-Time Clock
screamer 28:0e774865873d 731 */
screamer 28:0e774865873d 732
screamer 28:0e774865873d 733 typedef struct
screamer 28:0e774865873d 734 {
screamer 28:0e774865873d 735 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
screamer 28:0e774865873d 736 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
screamer 28:0e774865873d 737 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
screamer 28:0e774865873d 738 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
screamer 28:0e774865873d 739 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
screamer 28:0e774865873d 740 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
screamer 28:0e774865873d 741 uint32_t reserved; /*!< Reserved */
screamer 28:0e774865873d 742 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
screamer 28:0e774865873d 743 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
screamer 28:0e774865873d 744 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
screamer 28:0e774865873d 745 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
screamer 28:0e774865873d 746 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
screamer 28:0e774865873d 747 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
screamer 28:0e774865873d 748 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
screamer 28:0e774865873d 749 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
screamer 28:0e774865873d 750 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
screamer 28:0e774865873d 751 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
screamer 28:0e774865873d 752 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
screamer 28:0e774865873d 753 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
screamer 28:0e774865873d 754 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
screamer 28:0e774865873d 755 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
screamer 28:0e774865873d 756 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
screamer 28:0e774865873d 757 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
screamer 28:0e774865873d 758 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
screamer 28:0e774865873d 759 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
screamer 28:0e774865873d 760 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
screamer 28:0e774865873d 761 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
screamer 28:0e774865873d 762 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
screamer 28:0e774865873d 763 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
screamer 28:0e774865873d 764 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
screamer 28:0e774865873d 765 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
screamer 28:0e774865873d 766 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
screamer 28:0e774865873d 767 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
screamer 28:0e774865873d 768 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
screamer 28:0e774865873d 769 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
screamer 28:0e774865873d 770 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
screamer 28:0e774865873d 771 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
screamer 28:0e774865873d 772 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
screamer 28:0e774865873d 773 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
screamer 28:0e774865873d 774 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
screamer 28:0e774865873d 775 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
screamer 28:0e774865873d 776 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
screamer 28:0e774865873d 777 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
screamer 28:0e774865873d 778 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
screamer 28:0e774865873d 779 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
screamer 28:0e774865873d 780 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
screamer 28:0e774865873d 781 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
screamer 28:0e774865873d 782 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
screamer 28:0e774865873d 783 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
screamer 28:0e774865873d 784 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
screamer 28:0e774865873d 785 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
screamer 28:0e774865873d 786 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
screamer 28:0e774865873d 787 } RTC_TypeDef;
screamer 28:0e774865873d 788
screamer 28:0e774865873d 789
screamer 28:0e774865873d 790 /**
screamer 28:0e774865873d 791 * @brief Serial Audio Interface
screamer 28:0e774865873d 792 */
screamer 28:0e774865873d 793
screamer 28:0e774865873d 794 typedef struct
screamer 28:0e774865873d 795 {
screamer 28:0e774865873d 796 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
screamer 28:0e774865873d 797 } SAI_TypeDef;
screamer 28:0e774865873d 798
screamer 28:0e774865873d 799 typedef struct
screamer 28:0e774865873d 800 {
screamer 28:0e774865873d 801 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
screamer 28:0e774865873d 802 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
screamer 28:0e774865873d 803 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
screamer 28:0e774865873d 804 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
screamer 28:0e774865873d 805 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
screamer 28:0e774865873d 806 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
screamer 28:0e774865873d 807 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
screamer 28:0e774865873d 808 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
screamer 28:0e774865873d 809 } SAI_Block_TypeDef;
screamer 28:0e774865873d 810
screamer 28:0e774865873d 811
screamer 28:0e774865873d 812 /**
screamer 28:0e774865873d 813 * @brief Secure digital input/output Interface
screamer 28:0e774865873d 814 */
screamer 28:0e774865873d 815
screamer 28:0e774865873d 816 typedef struct
screamer 28:0e774865873d 817 {
screamer 28:0e774865873d 818 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
screamer 28:0e774865873d 819 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
screamer 28:0e774865873d 820 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
screamer 28:0e774865873d 821 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
screamer 28:0e774865873d 822 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
screamer 28:0e774865873d 823 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
screamer 28:0e774865873d 824 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
screamer 28:0e774865873d 825 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
screamer 28:0e774865873d 826 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
screamer 28:0e774865873d 827 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
screamer 28:0e774865873d 828 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
screamer 28:0e774865873d 829 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
screamer 28:0e774865873d 830 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
screamer 28:0e774865873d 831 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
screamer 28:0e774865873d 832 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
screamer 28:0e774865873d 833 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
screamer 28:0e774865873d 834 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
screamer 28:0e774865873d 835 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
screamer 28:0e774865873d 836 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
screamer 28:0e774865873d 837 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
screamer 28:0e774865873d 838 } SDMMC_TypeDef;
screamer 28:0e774865873d 839
screamer 28:0e774865873d 840
screamer 28:0e774865873d 841 /**
screamer 28:0e774865873d 842 * @brief Serial Peripheral Interface
screamer 28:0e774865873d 843 */
screamer 28:0e774865873d 844
screamer 28:0e774865873d 845 typedef struct
screamer 28:0e774865873d 846 {
screamer 28:0e774865873d 847 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
screamer 28:0e774865873d 848 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
screamer 28:0e774865873d 849 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
screamer 28:0e774865873d 850 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
screamer 28:0e774865873d 851 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
screamer 28:0e774865873d 852 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
screamer 28:0e774865873d 853 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
screamer 28:0e774865873d 854 } SPI_TypeDef;
screamer 28:0e774865873d 855
screamer 28:0e774865873d 856
screamer 28:0e774865873d 857 /**
screamer 28:0e774865873d 858 * @brief Single Wire Protocol Master Interface SPWMI
screamer 28:0e774865873d 859 */
screamer 28:0e774865873d 860
screamer 28:0e774865873d 861 typedef struct
screamer 28:0e774865873d 862 {
screamer 28:0e774865873d 863 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
screamer 28:0e774865873d 864 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
screamer 28:0e774865873d 865 uint32_t RESERVED1; /*!< Reserved, 0x08 */
screamer 28:0e774865873d 866 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
screamer 28:0e774865873d 867 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
screamer 28:0e774865873d 868 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
screamer 28:0e774865873d 869 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
screamer 28:0e774865873d 870 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
screamer 28:0e774865873d 871 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
screamer 28:0e774865873d 872 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
screamer 28:0e774865873d 873 } SWPMI_TypeDef;
screamer 28:0e774865873d 874
screamer 28:0e774865873d 875
screamer 28:0e774865873d 876 /**
screamer 28:0e774865873d 877 * @brief System configuration controller
screamer 28:0e774865873d 878 */
screamer 28:0e774865873d 879
screamer 28:0e774865873d 880 typedef struct
screamer 28:0e774865873d 881 {
screamer 28:0e774865873d 882 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
screamer 28:0e774865873d 883 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
screamer 28:0e774865873d 884 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
screamer 28:0e774865873d 885 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
screamer 28:0e774865873d 886 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
screamer 28:0e774865873d 887 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
screamer 28:0e774865873d 888 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
screamer 28:0e774865873d 889 } SYSCFG_TypeDef;
screamer 28:0e774865873d 890
screamer 28:0e774865873d 891
screamer 28:0e774865873d 892 /**
screamer 28:0e774865873d 893 * @brief TIM
screamer 28:0e774865873d 894 */
screamer 28:0e774865873d 895
screamer 28:0e774865873d 896 typedef struct
screamer 28:0e774865873d 897 {
screamer 28:0e774865873d 898 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
screamer 28:0e774865873d 899 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
screamer 28:0e774865873d 900 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
screamer 28:0e774865873d 901 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
screamer 28:0e774865873d 902 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
screamer 28:0e774865873d 903 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
screamer 28:0e774865873d 904 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
screamer 28:0e774865873d 905 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
screamer 28:0e774865873d 906 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
screamer 28:0e774865873d 907 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
screamer 28:0e774865873d 908 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
screamer 28:0e774865873d 909 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
screamer 28:0e774865873d 910 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
screamer 28:0e774865873d 911 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
screamer 28:0e774865873d 912 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
screamer 28:0e774865873d 913 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
screamer 28:0e774865873d 914 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
screamer 28:0e774865873d 915 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
screamer 28:0e774865873d 916 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
screamer 28:0e774865873d 917 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
screamer 28:0e774865873d 918 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
screamer 28:0e774865873d 919 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
screamer 28:0e774865873d 920 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
screamer 28:0e774865873d 921 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
screamer 28:0e774865873d 922 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
screamer 28:0e774865873d 923 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
screamer 28:0e774865873d 924 } TIM_TypeDef;
screamer 28:0e774865873d 925
screamer 28:0e774865873d 926
screamer 28:0e774865873d 927 /**
screamer 28:0e774865873d 928 * @brief Touch Sensing Controller (TSC)
screamer 28:0e774865873d 929 */
screamer 28:0e774865873d 930
screamer 28:0e774865873d 931 typedef struct
screamer 28:0e774865873d 932 {
screamer 28:0e774865873d 933 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
screamer 28:0e774865873d 934 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
screamer 28:0e774865873d 935 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
screamer 28:0e774865873d 936 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
screamer 28:0e774865873d 937 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
screamer 28:0e774865873d 938 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
screamer 28:0e774865873d 939 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
screamer 28:0e774865873d 940 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
screamer 28:0e774865873d 941 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
screamer 28:0e774865873d 942 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
screamer 28:0e774865873d 943 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
screamer 28:0e774865873d 944 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
screamer 28:0e774865873d 945 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
screamer 28:0e774865873d 946 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
screamer 28:0e774865873d 947 } TSC_TypeDef;
screamer 28:0e774865873d 948
screamer 28:0e774865873d 949 /**
screamer 28:0e774865873d 950 * @brief Universal Synchronous Asynchronous Receiver Transmitter
screamer 28:0e774865873d 951 */
screamer 28:0e774865873d 952
screamer 28:0e774865873d 953 typedef struct
screamer 28:0e774865873d 954 {
screamer 28:0e774865873d 955 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
screamer 28:0e774865873d 956 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
screamer 28:0e774865873d 957 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
screamer 28:0e774865873d 958 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
screamer 28:0e774865873d 959 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
screamer 28:0e774865873d 960 uint16_t RESERVED2; /*!< Reserved, 0x12 */
screamer 28:0e774865873d 961 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
screamer 28:0e774865873d 962 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
screamer 28:0e774865873d 963 uint16_t RESERVED3; /*!< Reserved, 0x1A */
screamer 28:0e774865873d 964 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
screamer 28:0e774865873d 965 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
screamer 28:0e774865873d 966 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
screamer 28:0e774865873d 967 uint16_t RESERVED4; /*!< Reserved, 0x26 */
screamer 28:0e774865873d 968 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
screamer 28:0e774865873d 969 uint16_t RESERVED5; /*!< Reserved, 0x2A */
screamer 28:0e774865873d 970 } USART_TypeDef;
screamer 28:0e774865873d 971
screamer 28:0e774865873d 972 /**
screamer 28:0e774865873d 973 * @brief VREFBUF
screamer 28:0e774865873d 974 */
screamer 28:0e774865873d 975
screamer 28:0e774865873d 976 typedef struct
screamer 28:0e774865873d 977 {
screamer 28:0e774865873d 978 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
screamer 28:0e774865873d 979 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
screamer 28:0e774865873d 980 } VREFBUF_TypeDef;
screamer 28:0e774865873d 981
screamer 28:0e774865873d 982 /**
screamer 28:0e774865873d 983 * @brief Window WATCHDOG
screamer 28:0e774865873d 984 */
screamer 28:0e774865873d 985
screamer 28:0e774865873d 986 typedef struct
screamer 28:0e774865873d 987 {
screamer 28:0e774865873d 988 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
screamer 28:0e774865873d 989 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
screamer 28:0e774865873d 990 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
screamer 28:0e774865873d 991 } WWDG_TypeDef;
screamer 28:0e774865873d 992
screamer 28:0e774865873d 993 /**
screamer 28:0e774865873d 994 * @brief RNG
screamer 28:0e774865873d 995 */
screamer 28:0e774865873d 996
screamer 28:0e774865873d 997 typedef struct
screamer 28:0e774865873d 998 {
screamer 28:0e774865873d 999 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
screamer 28:0e774865873d 1000 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
screamer 28:0e774865873d 1001 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
screamer 28:0e774865873d 1002 } RNG_TypeDef;
screamer 28:0e774865873d 1003
screamer 28:0e774865873d 1004 /**
screamer 28:0e774865873d 1005 * @brief USB_OTG_Core_register
screamer 28:0e774865873d 1006 */
screamer 28:0e774865873d 1007 typedef struct
screamer 28:0e774865873d 1008 {
screamer 28:0e774865873d 1009 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
screamer 28:0e774865873d 1010 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
screamer 28:0e774865873d 1011 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
screamer 28:0e774865873d 1012 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
screamer 28:0e774865873d 1013 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
screamer 28:0e774865873d 1014 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
screamer 28:0e774865873d 1015 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
screamer 28:0e774865873d 1016 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
screamer 28:0e774865873d 1017 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
screamer 28:0e774865873d 1018 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
screamer 28:0e774865873d 1019 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
screamer 28:0e774865873d 1020 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
screamer 28:0e774865873d 1021 uint32_t Reserved30[2]; /* Reserved 030h*/
screamer 28:0e774865873d 1022 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
screamer 28:0e774865873d 1023 __IO uint32_t CID; /* User ID Register 03Ch*/
screamer 28:0e774865873d 1024 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
screamer 28:0e774865873d 1025 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
screamer 28:0e774865873d 1026 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
screamer 28:0e774865873d 1027 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
screamer 28:0e774865873d 1028 uint32_t Reserved6; /* Reserved 050h*/
screamer 28:0e774865873d 1029 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
screamer 28:0e774865873d 1030 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
screamer 28:0e774865873d 1031 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
screamer 28:0e774865873d 1032 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
screamer 28:0e774865873d 1033 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
screamer 28:0e774865873d 1034 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
screamer 28:0e774865873d 1035 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
screamer 28:0e774865873d 1036 } USB_OTG_GlobalTypeDef;
screamer 28:0e774865873d 1037
screamer 28:0e774865873d 1038 /**
screamer 28:0e774865873d 1039 * @brief USB_OTG_device_Registers
screamer 28:0e774865873d 1040 */
screamer 28:0e774865873d 1041 typedef struct
screamer 28:0e774865873d 1042 {
screamer 28:0e774865873d 1043 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
screamer 28:0e774865873d 1044 __IO uint32_t DCTL; /* dev Control Register 804h*/
screamer 28:0e774865873d 1045 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
screamer 28:0e774865873d 1046 uint32_t Reserved0C; /* Reserved 80Ch*/
screamer 28:0e774865873d 1047 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
screamer 28:0e774865873d 1048 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
screamer 28:0e774865873d 1049 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
screamer 28:0e774865873d 1050 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
screamer 28:0e774865873d 1051 uint32_t Reserved20; /* Reserved 820h*/
screamer 28:0e774865873d 1052 uint32_t Reserved9; /* Reserved 824h*/
screamer 28:0e774865873d 1053 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
screamer 28:0e774865873d 1054 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
screamer 28:0e774865873d 1055 __IO uint32_t DTHRCTL; /* dev thr 830h*/
screamer 28:0e774865873d 1056 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
screamer 28:0e774865873d 1057 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
screamer 28:0e774865873d 1058 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
screamer 28:0e774865873d 1059 uint32_t Reserved40; /* dedicated EP mask 840h*/
screamer 28:0e774865873d 1060 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
screamer 28:0e774865873d 1061 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
screamer 28:0e774865873d 1062 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
screamer 28:0e774865873d 1063 } USB_OTG_DeviceTypeDef;
screamer 28:0e774865873d 1064
screamer 28:0e774865873d 1065 /**
screamer 28:0e774865873d 1066 * @brief USB_OTG_IN_Endpoint-Specific_Register
screamer 28:0e774865873d 1067 */
screamer 28:0e774865873d 1068 typedef struct
screamer 28:0e774865873d 1069 {
screamer 28:0e774865873d 1070 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
screamer 28:0e774865873d 1071 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
screamer 28:0e774865873d 1072 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
screamer 28:0e774865873d 1073 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
screamer 28:0e774865873d 1074 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
screamer 28:0e774865873d 1075 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
screamer 28:0e774865873d 1076 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
screamer 28:0e774865873d 1077 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
screamer 28:0e774865873d 1078 } USB_OTG_INEndpointTypeDef;
screamer 28:0e774865873d 1079
screamer 28:0e774865873d 1080 /**
screamer 28:0e774865873d 1081 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
screamer 28:0e774865873d 1082 */
screamer 28:0e774865873d 1083 typedef struct
screamer 28:0e774865873d 1084 {
screamer 28:0e774865873d 1085 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
screamer 28:0e774865873d 1086 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
screamer 28:0e774865873d 1087 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
screamer 28:0e774865873d 1088 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
screamer 28:0e774865873d 1089 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
screamer 28:0e774865873d 1090 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
screamer 28:0e774865873d 1091 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
screamer 28:0e774865873d 1092 } USB_OTG_OUTEndpointTypeDef;
screamer 28:0e774865873d 1093
screamer 28:0e774865873d 1094 /**
screamer 28:0e774865873d 1095 * @brief USB_OTG_Host_Mode_Register_Structures
screamer 28:0e774865873d 1096 */
screamer 28:0e774865873d 1097 typedef struct
screamer 28:0e774865873d 1098 {
screamer 28:0e774865873d 1099 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
screamer 28:0e774865873d 1100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
screamer 28:0e774865873d 1101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
screamer 28:0e774865873d 1102 uint32_t Reserved40C; /* Reserved 40Ch*/
screamer 28:0e774865873d 1103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
screamer 28:0e774865873d 1104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
screamer 28:0e774865873d 1105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
screamer 28:0e774865873d 1106 } USB_OTG_HostTypeDef;
screamer 28:0e774865873d 1107
screamer 28:0e774865873d 1108 /**
screamer 28:0e774865873d 1109 * @brief USB_OTG_Host_Channel_Specific_Registers
screamer 28:0e774865873d 1110 */
screamer 28:0e774865873d 1111 typedef struct
screamer 28:0e774865873d 1112 {
screamer 28:0e774865873d 1113 __IO uint32_t HCCHAR;
screamer 28:0e774865873d 1114 __IO uint32_t HCSPLT;
screamer 28:0e774865873d 1115 __IO uint32_t HCINT;
screamer 28:0e774865873d 1116 __IO uint32_t HCINTMSK;
screamer 28:0e774865873d 1117 __IO uint32_t HCTSIZ;
screamer 28:0e774865873d 1118 __IO uint32_t HCDMA;
screamer 28:0e774865873d 1119 uint32_t Reserved[2];
screamer 28:0e774865873d 1120 } USB_OTG_HostChannelTypeDef;
screamer 28:0e774865873d 1121
screamer 28:0e774865873d 1122 /**
screamer 28:0e774865873d 1123 * @}
screamer 28:0e774865873d 1124 */
screamer 28:0e774865873d 1125
screamer 28:0e774865873d 1126 /** @addtogroup Peripheral_memory_map
screamer 28:0e774865873d 1127 * @{
screamer 28:0e774865873d 1128 */
screamer 28:0e774865873d 1129 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
screamer 28:0e774865873d 1130 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
screamer 28:0e774865873d 1131 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
screamer 28:0e774865873d 1132 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
screamer 28:0e774865873d 1133 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
screamer 28:0e774865873d 1134 #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
screamer 28:0e774865873d 1135
screamer 28:0e774865873d 1136 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
screamer 28:0e774865873d 1137 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
screamer 28:0e774865873d 1138 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
screamer 28:0e774865873d 1139 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
screamer 28:0e774865873d 1140
screamer 28:0e774865873d 1141 /* Legacy defines */
screamer 28:0e774865873d 1142 #define SRAM_BASE SRAM1_BASE
screamer 28:0e774865873d 1143 #define SRAM_BB_BASE SRAM1_BB_BASE
screamer 28:0e774865873d 1144
screamer 28:0e774865873d 1145 #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
screamer 28:0e774865873d 1146 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
screamer 28:0e774865873d 1147
screamer 28:0e774865873d 1148 /*!< Peripheral memory map */
screamer 28:0e774865873d 1149 #define APB1PERIPH_BASE PERIPH_BASE
screamer 28:0e774865873d 1150 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
screamer 28:0e774865873d 1151 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
screamer 28:0e774865873d 1152 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
screamer 28:0e774865873d 1153
screamer 28:0e774865873d 1154 #define FMC_BANK1 FMC_BASE
screamer 28:0e774865873d 1155 #define FMC_BANK1_1 FMC_BANK1
screamer 28:0e774865873d 1156 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
screamer 28:0e774865873d 1157 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
screamer 28:0e774865873d 1158 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
screamer 28:0e774865873d 1159 #define FMC_BANK3 (FMC_BASE + 0x20000000U)
screamer 28:0e774865873d 1160
screamer 28:0e774865873d 1161 /*!< APB1 peripherals */
screamer 28:0e774865873d 1162 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
screamer 28:0e774865873d 1163 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
screamer 28:0e774865873d 1164 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
screamer 28:0e774865873d 1165 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
screamer 28:0e774865873d 1166 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
screamer 28:0e774865873d 1167 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
screamer 28:0e774865873d 1168 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
screamer 28:0e774865873d 1169 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
screamer 28:0e774865873d 1170 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
screamer 28:0e774865873d 1171 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
screamer 28:0e774865873d 1172 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
screamer 28:0e774865873d 1173 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
screamer 28:0e774865873d 1174 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
screamer 28:0e774865873d 1175 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
screamer 28:0e774865873d 1176 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
screamer 28:0e774865873d 1177 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
screamer 28:0e774865873d 1178 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
screamer 28:0e774865873d 1179 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
screamer 28:0e774865873d 1180 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
screamer 28:0e774865873d 1181 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
screamer 28:0e774865873d 1182 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
screamer 28:0e774865873d 1183 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
screamer 28:0e774865873d 1184 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
screamer 28:0e774865873d 1185 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
screamer 28:0e774865873d 1186 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
screamer 28:0e774865873d 1187 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
screamer 28:0e774865873d 1188 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
screamer 28:0e774865873d 1189 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
screamer 28:0e774865873d 1190 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
screamer 28:0e774865873d 1191
screamer 28:0e774865873d 1192
screamer 28:0e774865873d 1193 /*!< APB2 peripherals */
screamer 28:0e774865873d 1194 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
screamer 28:0e774865873d 1195 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
screamer 28:0e774865873d 1196 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
screamer 28:0e774865873d 1197 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
screamer 28:0e774865873d 1198 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
screamer 28:0e774865873d 1199 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
screamer 28:0e774865873d 1200 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
screamer 28:0e774865873d 1201 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
screamer 28:0e774865873d 1202 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
screamer 28:0e774865873d 1203 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
screamer 28:0e774865873d 1204 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
screamer 28:0e774865873d 1205 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
screamer 28:0e774865873d 1206 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
screamer 28:0e774865873d 1207 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
screamer 28:0e774865873d 1208 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
screamer 28:0e774865873d 1209 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
screamer 28:0e774865873d 1210 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
screamer 28:0e774865873d 1211 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
screamer 28:0e774865873d 1212 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
screamer 28:0e774865873d 1213 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
screamer 28:0e774865873d 1214 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
screamer 28:0e774865873d 1215 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
screamer 28:0e774865873d 1216 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
screamer 28:0e774865873d 1217 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
screamer 28:0e774865873d 1218 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
screamer 28:0e774865873d 1219 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
screamer 28:0e774865873d 1220 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
screamer 28:0e774865873d 1221 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
screamer 28:0e774865873d 1222 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
screamer 28:0e774865873d 1223 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
screamer 28:0e774865873d 1224 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
screamer 28:0e774865873d 1225 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
screamer 28:0e774865873d 1226 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
screamer 28:0e774865873d 1227
screamer 28:0e774865873d 1228 /*!< AHB1 peripherals */
screamer 28:0e774865873d 1229 #define DMA1_BASE (AHB1PERIPH_BASE)
screamer 28:0e774865873d 1230 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
screamer 28:0e774865873d 1231 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
screamer 28:0e774865873d 1232 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
screamer 28:0e774865873d 1233 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
screamer 28:0e774865873d 1234 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
screamer 28:0e774865873d 1235
screamer 28:0e774865873d 1236
screamer 28:0e774865873d 1237 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
screamer 28:0e774865873d 1238 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
screamer 28:0e774865873d 1239 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
screamer 28:0e774865873d 1240 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
screamer 28:0e774865873d 1241 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
screamer 28:0e774865873d 1242 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
screamer 28:0e774865873d 1243 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
screamer 28:0e774865873d 1244 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
screamer 28:0e774865873d 1245
screamer 28:0e774865873d 1246
screamer 28:0e774865873d 1247 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
screamer 28:0e774865873d 1248 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
screamer 28:0e774865873d 1249 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
screamer 28:0e774865873d 1250 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
screamer 28:0e774865873d 1251 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
screamer 28:0e774865873d 1252 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
screamer 28:0e774865873d 1253 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
screamer 28:0e774865873d 1254 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
screamer 28:0e774865873d 1255
screamer 28:0e774865873d 1256
screamer 28:0e774865873d 1257 /*!< AHB2 peripherals */
screamer 28:0e774865873d 1258 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
screamer 28:0e774865873d 1259 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
screamer 28:0e774865873d 1260 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
screamer 28:0e774865873d 1261 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
screamer 28:0e774865873d 1262 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
screamer 28:0e774865873d 1263 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
screamer 28:0e774865873d 1264 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
screamer 28:0e774865873d 1265 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
screamer 28:0e774865873d 1266
screamer 28:0e774865873d 1267 #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
screamer 28:0e774865873d 1268
screamer 28:0e774865873d 1269 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
screamer 28:0e774865873d 1270 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
screamer 28:0e774865873d 1271 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
screamer 28:0e774865873d 1272 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
screamer 28:0e774865873d 1273
screamer 28:0e774865873d 1274
screamer 28:0e774865873d 1275 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
screamer 28:0e774865873d 1276
screamer 28:0e774865873d 1277
screamer 28:0e774865873d 1278 /*!< FMC Banks registers base address */
screamer 28:0e774865873d 1279 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
screamer 28:0e774865873d 1280 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
screamer 28:0e774865873d 1281 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
screamer 28:0e774865873d 1282
screamer 28:0e774865873d 1283 /* Debug MCU registers base address */
screamer 28:0e774865873d 1284 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
screamer 28:0e774865873d 1285
screamer 28:0e774865873d 1286 /*!< USB registers base address */
screamer 28:0e774865873d 1287 #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
screamer 28:0e774865873d 1288
screamer 28:0e774865873d 1289 #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
screamer 28:0e774865873d 1290 #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
screamer 28:0e774865873d 1291 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
screamer 28:0e774865873d 1292 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
screamer 28:0e774865873d 1293 #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
screamer 28:0e774865873d 1294 #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
screamer 28:0e774865873d 1295 #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
screamer 28:0e774865873d 1296 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
screamer 28:0e774865873d 1297 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
screamer 28:0e774865873d 1298 #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
screamer 28:0e774865873d 1299 #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
screamer 28:0e774865873d 1300 #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
screamer 28:0e774865873d 1301
screamer 28:0e774865873d 1302
screamer 28:0e774865873d 1303 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
screamer 28:0e774865873d 1304 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
screamer 28:0e774865873d 1305 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
screamer 28:0e774865873d 1306 /**
screamer 28:0e774865873d 1307 * @}
screamer 28:0e774865873d 1308 */
screamer 28:0e774865873d 1309
screamer 28:0e774865873d 1310 /** @addtogroup Peripheral_declaration
screamer 28:0e774865873d 1311 * @{
screamer 28:0e774865873d 1312 */
screamer 28:0e774865873d 1313 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
screamer 28:0e774865873d 1314 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
screamer 28:0e774865873d 1315 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
screamer 28:0e774865873d 1316 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
screamer 28:0e774865873d 1317 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
screamer 28:0e774865873d 1318 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
screamer 28:0e774865873d 1319 #define RTC ((RTC_TypeDef *) RTC_BASE)
screamer 28:0e774865873d 1320 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
screamer 28:0e774865873d 1321 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
screamer 28:0e774865873d 1322 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
screamer 28:0e774865873d 1323 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
screamer 28:0e774865873d 1324 #define USART2 ((USART_TypeDef *) USART2_BASE)
screamer 28:0e774865873d 1325 #define USART3 ((USART_TypeDef *) USART3_BASE)
screamer 28:0e774865873d 1326 #define UART4 ((USART_TypeDef *) UART4_BASE)
screamer 28:0e774865873d 1327 #define UART5 ((USART_TypeDef *) UART5_BASE)
screamer 28:0e774865873d 1328 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
screamer 28:0e774865873d 1329 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
screamer 28:0e774865873d 1330 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
screamer 28:0e774865873d 1331 //#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API
screamer 28:0e774865873d 1332 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
screamer 28:0e774865873d 1333 #define PWR ((PWR_TypeDef *) PWR_BASE)
screamer 28:0e774865873d 1334 #define DAC ((DAC_TypeDef *) DAC1_BASE)
screamer 28:0e774865873d 1335 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
screamer 28:0e774865873d 1336 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
screamer 28:0e774865873d 1337 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
screamer 28:0e774865873d 1338 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
screamer 28:0e774865873d 1339 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
screamer 28:0e774865873d 1340 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
screamer 28:0e774865873d 1341 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
screamer 28:0e774865873d 1342 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
screamer 28:0e774865873d 1343 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
screamer 28:0e774865873d 1344
screamer 28:0e774865873d 1345 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
screamer 28:0e774865873d 1346 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
screamer 28:0e774865873d 1347 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
screamer 28:0e774865873d 1348 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
screamer 28:0e774865873d 1349 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
screamer 28:0e774865873d 1350 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
screamer 28:0e774865873d 1351 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
screamer 28:0e774865873d 1352 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
screamer 28:0e774865873d 1353 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
screamer 28:0e774865873d 1354 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
screamer 28:0e774865873d 1355 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
screamer 28:0e774865873d 1356 #define USART1 ((USART_TypeDef *) USART1_BASE)
screamer 28:0e774865873d 1357 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
screamer 28:0e774865873d 1358 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
screamer 28:0e774865873d 1359 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
screamer 28:0e774865873d 1360 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
screamer 28:0e774865873d 1361 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
screamer 28:0e774865873d 1362 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
screamer 28:0e774865873d 1363 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
screamer 28:0e774865873d 1364 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
screamer 28:0e774865873d 1365 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
screamer 28:0e774865873d 1366 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
screamer 28:0e774865873d 1367 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
screamer 28:0e774865873d 1368 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
screamer 28:0e774865873d 1369 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
screamer 28:0e774865873d 1370 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
screamer 28:0e774865873d 1371 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
screamer 28:0e774865873d 1372 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
screamer 28:0e774865873d 1373 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
screamer 28:0e774865873d 1374 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
screamer 28:0e774865873d 1375 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
screamer 28:0e774865873d 1376 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
screamer 28:0e774865873d 1377 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
screamer 28:0e774865873d 1378 /* Aliases to keep compatibility after DFSDM renaming */
screamer 28:0e774865873d 1379 #define DFSDM_Channel0 DFSDM1_Channel0
screamer 28:0e774865873d 1380 #define DFSDM_Channel1 DFSDM1_Channel1
screamer 28:0e774865873d 1381 #define DFSDM_Channel2 DFSDM1_Channel2
screamer 28:0e774865873d 1382 #define DFSDM_Channel3 DFSDM1_Channel3
screamer 28:0e774865873d 1383 #define DFSDM_Channel4 DFSDM1_Channel4
screamer 28:0e774865873d 1384 #define DFSDM_Channel5 DFSDM1_Channel5
screamer 28:0e774865873d 1385 #define DFSDM_Channel6 DFSDM1_Channel6
screamer 28:0e774865873d 1386 #define DFSDM_Channel7 DFSDM1_Channel7
screamer 28:0e774865873d 1387 #define DFSDM_Filter0 DFSDM1_Filter0
screamer 28:0e774865873d 1388 #define DFSDM_Filter1 DFSDM1_Filter1
screamer 28:0e774865873d 1389 #define DFSDM_Filter2 DFSDM1_Filter2
screamer 28:0e774865873d 1390 #define DFSDM_Filter3 DFSDM1_Filter3
screamer 28:0e774865873d 1391 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
screamer 28:0e774865873d 1392 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
screamer 28:0e774865873d 1393 #define RCC ((RCC_TypeDef *) RCC_BASE)
screamer 28:0e774865873d 1394 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
screamer 28:0e774865873d 1395 #define CRC ((CRC_TypeDef *) CRC_BASE)
screamer 28:0e774865873d 1396 #define TSC ((TSC_TypeDef *) TSC_BASE)
screamer 28:0e774865873d 1397
screamer 28:0e774865873d 1398 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
screamer 28:0e774865873d 1399 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
screamer 28:0e774865873d 1400 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
screamer 28:0e774865873d 1401 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
screamer 28:0e774865873d 1402 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
screamer 28:0e774865873d 1403 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
screamer 28:0e774865873d 1404 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
screamer 28:0e774865873d 1405 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
screamer 28:0e774865873d 1406 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
screamer 28:0e774865873d 1407 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
screamer 28:0e774865873d 1408 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
screamer 28:0e774865873d 1409 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
screamer 28:0e774865873d 1410 #define RNG ((RNG_TypeDef *) RNG_BASE)
screamer 28:0e774865873d 1411
screamer 28:0e774865873d 1412
screamer 28:0e774865873d 1413 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
screamer 28:0e774865873d 1414 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
screamer 28:0e774865873d 1415 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
screamer 28:0e774865873d 1416 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
screamer 28:0e774865873d 1417 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
screamer 28:0e774865873d 1418 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
screamer 28:0e774865873d 1419 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
screamer 28:0e774865873d 1420 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
screamer 28:0e774865873d 1421
screamer 28:0e774865873d 1422
screamer 28:0e774865873d 1423 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
screamer 28:0e774865873d 1424 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
screamer 28:0e774865873d 1425 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
screamer 28:0e774865873d 1426 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
screamer 28:0e774865873d 1427 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
screamer 28:0e774865873d 1428 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
screamer 28:0e774865873d 1429 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
screamer 28:0e774865873d 1430 #define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
screamer 28:0e774865873d 1431
screamer 28:0e774865873d 1432
screamer 28:0e774865873d 1433 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
screamer 28:0e774865873d 1434 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
screamer 28:0e774865873d 1435 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
screamer 28:0e774865873d 1436
screamer 28:0e774865873d 1437 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
screamer 28:0e774865873d 1438
screamer 28:0e774865873d 1439 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
screamer 28:0e774865873d 1440
screamer 28:0e774865873d 1441 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
screamer 28:0e774865873d 1442 /**
screamer 28:0e774865873d 1443 * @}
screamer 28:0e774865873d 1444 */
screamer 28:0e774865873d 1445
screamer 28:0e774865873d 1446 /** @addtogroup Exported_constants
screamer 28:0e774865873d 1447 * @{
screamer 28:0e774865873d 1448 */
screamer 28:0e774865873d 1449
screamer 28:0e774865873d 1450 /** @addtogroup Peripheral_Registers_Bits_Definition
screamer 28:0e774865873d 1451 * @{
screamer 28:0e774865873d 1452 */
screamer 28:0e774865873d 1453
screamer 28:0e774865873d 1454 /******************************************************************************/
screamer 28:0e774865873d 1455 /* Peripheral Registers_Bits_Definition */
screamer 28:0e774865873d 1456 /******************************************************************************/
screamer 28:0e774865873d 1457
screamer 28:0e774865873d 1458 /******************************************************************************/
screamer 28:0e774865873d 1459 /* */
screamer 28:0e774865873d 1460 /* Analog to Digital Converter */
screamer 28:0e774865873d 1461 /* */
screamer 28:0e774865873d 1462 /******************************************************************************/
screamer 28:0e774865873d 1463
screamer 28:0e774865873d 1464 /*
screamer 28:0e774865873d 1465 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
screamer 28:0e774865873d 1466 */
screamer 28:0e774865873d 1467 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
screamer 28:0e774865873d 1468
screamer 28:0e774865873d 1469 /******************** Bit definition for ADC_ISR register *******************/
screamer 28:0e774865873d 1470 #define ADC_ISR_ADRDY_Pos (0U)
screamer 28:0e774865873d 1471 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1472 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
screamer 28:0e774865873d 1473 #define ADC_ISR_EOSMP_Pos (1U)
screamer 28:0e774865873d 1474 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1475 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
screamer 28:0e774865873d 1476 #define ADC_ISR_EOC_Pos (2U)
screamer 28:0e774865873d 1477 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1478 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
screamer 28:0e774865873d 1479 #define ADC_ISR_EOS_Pos (3U)
screamer 28:0e774865873d 1480 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1481 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
screamer 28:0e774865873d 1482 #define ADC_ISR_OVR_Pos (4U)
screamer 28:0e774865873d 1483 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1484 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
screamer 28:0e774865873d 1485 #define ADC_ISR_JEOC_Pos (5U)
screamer 28:0e774865873d 1486 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1487 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
screamer 28:0e774865873d 1488 #define ADC_ISR_JEOS_Pos (6U)
screamer 28:0e774865873d 1489 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1490 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
screamer 28:0e774865873d 1491 #define ADC_ISR_AWD1_Pos (7U)
screamer 28:0e774865873d 1492 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1493 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
screamer 28:0e774865873d 1494 #define ADC_ISR_AWD2_Pos (8U)
screamer 28:0e774865873d 1495 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1496 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
screamer 28:0e774865873d 1497 #define ADC_ISR_AWD3_Pos (9U)
screamer 28:0e774865873d 1498 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1499 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
screamer 28:0e774865873d 1500 #define ADC_ISR_JQOVF_Pos (10U)
screamer 28:0e774865873d 1501 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1502 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
screamer 28:0e774865873d 1503
screamer 28:0e774865873d 1504 /******************** Bit definition for ADC_IER register *******************/
screamer 28:0e774865873d 1505 #define ADC_IER_ADRDYIE_Pos (0U)
screamer 28:0e774865873d 1506 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1507 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
screamer 28:0e774865873d 1508 #define ADC_IER_EOSMPIE_Pos (1U)
screamer 28:0e774865873d 1509 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1510 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
screamer 28:0e774865873d 1511 #define ADC_IER_EOCIE_Pos (2U)
screamer 28:0e774865873d 1512 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1513 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
screamer 28:0e774865873d 1514 #define ADC_IER_EOSIE_Pos (3U)
screamer 28:0e774865873d 1515 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1516 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
screamer 28:0e774865873d 1517 #define ADC_IER_OVRIE_Pos (4U)
screamer 28:0e774865873d 1518 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1519 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
screamer 28:0e774865873d 1520 #define ADC_IER_JEOCIE_Pos (5U)
screamer 28:0e774865873d 1521 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1522 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
screamer 28:0e774865873d 1523 #define ADC_IER_JEOSIE_Pos (6U)
screamer 28:0e774865873d 1524 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1525 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
screamer 28:0e774865873d 1526 #define ADC_IER_AWD1IE_Pos (7U)
screamer 28:0e774865873d 1527 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1528 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
screamer 28:0e774865873d 1529 #define ADC_IER_AWD2IE_Pos (8U)
screamer 28:0e774865873d 1530 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1531 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
screamer 28:0e774865873d 1532 #define ADC_IER_AWD3IE_Pos (9U)
screamer 28:0e774865873d 1533 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1534 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
screamer 28:0e774865873d 1535 #define ADC_IER_JQOVFIE_Pos (10U)
screamer 28:0e774865873d 1536 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1537 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
screamer 28:0e774865873d 1538
screamer 28:0e774865873d 1539 /* Legacy defines */
screamer 28:0e774865873d 1540 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
screamer 28:0e774865873d 1541 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
screamer 28:0e774865873d 1542 #define ADC_IER_EOC (ADC_IER_EOCIE)
screamer 28:0e774865873d 1543 #define ADC_IER_EOS (ADC_IER_EOSIE)
screamer 28:0e774865873d 1544 #define ADC_IER_OVR (ADC_IER_OVRIE)
screamer 28:0e774865873d 1545 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
screamer 28:0e774865873d 1546 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
screamer 28:0e774865873d 1547 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
screamer 28:0e774865873d 1548 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
screamer 28:0e774865873d 1549 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
screamer 28:0e774865873d 1550 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
screamer 28:0e774865873d 1551
screamer 28:0e774865873d 1552 /******************** Bit definition for ADC_CR register ********************/
screamer 28:0e774865873d 1553 #define ADC_CR_ADEN_Pos (0U)
screamer 28:0e774865873d 1554 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1555 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
screamer 28:0e774865873d 1556 #define ADC_CR_ADDIS_Pos (1U)
screamer 28:0e774865873d 1557 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1558 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
screamer 28:0e774865873d 1559 #define ADC_CR_ADSTART_Pos (2U)
screamer 28:0e774865873d 1560 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1561 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
screamer 28:0e774865873d 1562 #define ADC_CR_JADSTART_Pos (3U)
screamer 28:0e774865873d 1563 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1564 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
screamer 28:0e774865873d 1565 #define ADC_CR_ADSTP_Pos (4U)
screamer 28:0e774865873d 1566 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1567 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
screamer 28:0e774865873d 1568 #define ADC_CR_JADSTP_Pos (5U)
screamer 28:0e774865873d 1569 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1570 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
screamer 28:0e774865873d 1571 #define ADC_CR_ADVREGEN_Pos (28U)
screamer 28:0e774865873d 1572 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 1573 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
screamer 28:0e774865873d 1574 #define ADC_CR_DEEPPWD_Pos (29U)
screamer 28:0e774865873d 1575 #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 1576 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
screamer 28:0e774865873d 1577 #define ADC_CR_ADCALDIF_Pos (30U)
screamer 28:0e774865873d 1578 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 1579 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
screamer 28:0e774865873d 1580 #define ADC_CR_ADCAL_Pos (31U)
screamer 28:0e774865873d 1581 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 1582 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
screamer 28:0e774865873d 1583
screamer 28:0e774865873d 1584 /******************** Bit definition for ADC_CFGR register ******************/
screamer 28:0e774865873d 1585 #define ADC_CFGR_DMAEN_Pos (0U)
screamer 28:0e774865873d 1586 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1587 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
screamer 28:0e774865873d 1588 #define ADC_CFGR_DMACFG_Pos (1U)
screamer 28:0e774865873d 1589 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1590 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
screamer 28:0e774865873d 1591
screamer 28:0e774865873d 1592 #define ADC_CFGR_RES_Pos (3U)
screamer 28:0e774865873d 1593 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
screamer 28:0e774865873d 1594 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
screamer 28:0e774865873d 1595 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1596 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1597
screamer 28:0e774865873d 1598 #define ADC_CFGR_ALIGN_Pos (5U)
screamer 28:0e774865873d 1599 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1600 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
screamer 28:0e774865873d 1601
screamer 28:0e774865873d 1602 #define ADC_CFGR_EXTSEL_Pos (6U)
screamer 28:0e774865873d 1603 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
screamer 28:0e774865873d 1604 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
screamer 28:0e774865873d 1605 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1606 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1607 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1608 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1609
screamer 28:0e774865873d 1610 #define ADC_CFGR_EXTEN_Pos (10U)
screamer 28:0e774865873d 1611 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 1612 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
screamer 28:0e774865873d 1613 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1614 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 1615
screamer 28:0e774865873d 1616 #define ADC_CFGR_OVRMOD_Pos (12U)
screamer 28:0e774865873d 1617 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 1618 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
screamer 28:0e774865873d 1619 #define ADC_CFGR_CONT_Pos (13U)
screamer 28:0e774865873d 1620 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 1621 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
screamer 28:0e774865873d 1622 #define ADC_CFGR_AUTDLY_Pos (14U)
screamer 28:0e774865873d 1623 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 1624 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
screamer 28:0e774865873d 1625
screamer 28:0e774865873d 1626 #define ADC_CFGR_DISCEN_Pos (16U)
screamer 28:0e774865873d 1627 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1628 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
screamer 28:0e774865873d 1629
screamer 28:0e774865873d 1630 #define ADC_CFGR_DISCNUM_Pos (17U)
screamer 28:0e774865873d 1631 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
screamer 28:0e774865873d 1632 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
screamer 28:0e774865873d 1633 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 1634 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1635 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1636
screamer 28:0e774865873d 1637 #define ADC_CFGR_JDISCEN_Pos (20U)
screamer 28:0e774865873d 1638 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1639 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
screamer 28:0e774865873d 1640 #define ADC_CFGR_JQM_Pos (21U)
screamer 28:0e774865873d 1641 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1642 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
screamer 28:0e774865873d 1643 #define ADC_CFGR_AWD1SGL_Pos (22U)
screamer 28:0e774865873d 1644 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1645 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
screamer 28:0e774865873d 1646 #define ADC_CFGR_AWD1EN_Pos (23U)
screamer 28:0e774865873d 1647 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 1648 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
screamer 28:0e774865873d 1649 #define ADC_CFGR_JAWD1EN_Pos (24U)
screamer 28:0e774865873d 1650 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 1651 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
screamer 28:0e774865873d 1652 #define ADC_CFGR_JAUTO_Pos (25U)
screamer 28:0e774865873d 1653 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 1654 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
screamer 28:0e774865873d 1655
screamer 28:0e774865873d 1656 #define ADC_CFGR_AWD1CH_Pos (26U)
screamer 28:0e774865873d 1657 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
screamer 28:0e774865873d 1658 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
screamer 28:0e774865873d 1659 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 1660 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 1661 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 1662 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 1663 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 1664
screamer 28:0e774865873d 1665 #define ADC_CFGR_JQDIS_Pos (31U)
screamer 28:0e774865873d 1666 #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 1667 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
screamer 28:0e774865873d 1668
screamer 28:0e774865873d 1669 /******************** Bit definition for ADC_CFGR2 register *****************/
screamer 28:0e774865873d 1670 #define ADC_CFGR2_ROVSE_Pos (0U)
screamer 28:0e774865873d 1671 #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1672 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
screamer 28:0e774865873d 1673 #define ADC_CFGR2_JOVSE_Pos (1U)
screamer 28:0e774865873d 1674 #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1675 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
screamer 28:0e774865873d 1676
screamer 28:0e774865873d 1677 #define ADC_CFGR2_OVSR_Pos (2U)
screamer 28:0e774865873d 1678 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
screamer 28:0e774865873d 1679 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
screamer 28:0e774865873d 1680 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1681 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1682 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1683
screamer 28:0e774865873d 1684 #define ADC_CFGR2_OVSS_Pos (5U)
screamer 28:0e774865873d 1685 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
screamer 28:0e774865873d 1686 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
screamer 28:0e774865873d 1687 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1688 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1689 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1690 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1691
screamer 28:0e774865873d 1692 #define ADC_CFGR2_TROVS_Pos (9U)
screamer 28:0e774865873d 1693 #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1694 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
screamer 28:0e774865873d 1695 #define ADC_CFGR2_ROVSM_Pos (10U)
screamer 28:0e774865873d 1696 #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1697 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
screamer 28:0e774865873d 1698
screamer 28:0e774865873d 1699 /******************** Bit definition for ADC_SMPR1 register *****************/
screamer 28:0e774865873d 1700 #define ADC_SMPR1_SMP0_Pos (0U)
screamer 28:0e774865873d 1701 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 1702 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
screamer 28:0e774865873d 1703 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1704 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1705 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1706
screamer 28:0e774865873d 1707 #define ADC_SMPR1_SMP1_Pos (3U)
screamer 28:0e774865873d 1708 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
screamer 28:0e774865873d 1709 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
screamer 28:0e774865873d 1710 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1711 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1712 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1713
screamer 28:0e774865873d 1714 #define ADC_SMPR1_SMP2_Pos (6U)
screamer 28:0e774865873d 1715 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
screamer 28:0e774865873d 1716 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
screamer 28:0e774865873d 1717 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1718 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1719 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1720
screamer 28:0e774865873d 1721 #define ADC_SMPR1_SMP3_Pos (9U)
screamer 28:0e774865873d 1722 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
screamer 28:0e774865873d 1723 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
screamer 28:0e774865873d 1724 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1725 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1726 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 1727
screamer 28:0e774865873d 1728 #define ADC_SMPR1_SMP4_Pos (12U)
screamer 28:0e774865873d 1729 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 1730 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
screamer 28:0e774865873d 1731 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 1732 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 1733 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 1734
screamer 28:0e774865873d 1735 #define ADC_SMPR1_SMP5_Pos (15U)
screamer 28:0e774865873d 1736 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
screamer 28:0e774865873d 1737 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
screamer 28:0e774865873d 1738 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 1739 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1740 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 1741
screamer 28:0e774865873d 1742 #define ADC_SMPR1_SMP6_Pos (18U)
screamer 28:0e774865873d 1743 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
screamer 28:0e774865873d 1744 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
screamer 28:0e774865873d 1745 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1746 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1747 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1748
screamer 28:0e774865873d 1749 #define ADC_SMPR1_SMP7_Pos (21U)
screamer 28:0e774865873d 1750 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
screamer 28:0e774865873d 1751 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
screamer 28:0e774865873d 1752 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1753 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1754 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 1755
screamer 28:0e774865873d 1756 #define ADC_SMPR1_SMP8_Pos (24U)
screamer 28:0e774865873d 1757 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
screamer 28:0e774865873d 1758 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
screamer 28:0e774865873d 1759 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 1760 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 1761 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 1762
screamer 28:0e774865873d 1763 #define ADC_SMPR1_SMP9_Pos (27U)
screamer 28:0e774865873d 1764 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
screamer 28:0e774865873d 1765 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
screamer 28:0e774865873d 1766 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 1767 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 1768 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 1769
screamer 28:0e774865873d 1770 /******************** Bit definition for ADC_SMPR2 register *****************/
screamer 28:0e774865873d 1771 #define ADC_SMPR2_SMP10_Pos (0U)
screamer 28:0e774865873d 1772 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 1773 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
screamer 28:0e774865873d 1774 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1775 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1776 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1777
screamer 28:0e774865873d 1778 #define ADC_SMPR2_SMP11_Pos (3U)
screamer 28:0e774865873d 1779 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
screamer 28:0e774865873d 1780 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
screamer 28:0e774865873d 1781 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1782 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1783 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1784
screamer 28:0e774865873d 1785 #define ADC_SMPR2_SMP12_Pos (6U)
screamer 28:0e774865873d 1786 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
screamer 28:0e774865873d 1787 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
screamer 28:0e774865873d 1788 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1789 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1790 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1791
screamer 28:0e774865873d 1792 #define ADC_SMPR2_SMP13_Pos (9U)
screamer 28:0e774865873d 1793 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
screamer 28:0e774865873d 1794 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
screamer 28:0e774865873d 1795 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1796 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1797 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 1798
screamer 28:0e774865873d 1799 #define ADC_SMPR2_SMP14_Pos (12U)
screamer 28:0e774865873d 1800 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 1801 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
screamer 28:0e774865873d 1802 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 1803 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 1804 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 1805
screamer 28:0e774865873d 1806 #define ADC_SMPR2_SMP15_Pos (15U)
screamer 28:0e774865873d 1807 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
screamer 28:0e774865873d 1808 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
screamer 28:0e774865873d 1809 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 1810 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1811 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 1812
screamer 28:0e774865873d 1813 #define ADC_SMPR2_SMP16_Pos (18U)
screamer 28:0e774865873d 1814 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
screamer 28:0e774865873d 1815 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
screamer 28:0e774865873d 1816 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1817 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1818 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1819
screamer 28:0e774865873d 1820 #define ADC_SMPR2_SMP17_Pos (21U)
screamer 28:0e774865873d 1821 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
screamer 28:0e774865873d 1822 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
screamer 28:0e774865873d 1823 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1824 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1825 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 1826
screamer 28:0e774865873d 1827 #define ADC_SMPR2_SMP18_Pos (24U)
screamer 28:0e774865873d 1828 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
screamer 28:0e774865873d 1829 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
screamer 28:0e774865873d 1830 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 1831 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 1832 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 1833
screamer 28:0e774865873d 1834 /******************** Bit definition for ADC_TR1 register *******************/
screamer 28:0e774865873d 1835 #define ADC_TR1_LT1_Pos (0U)
screamer 28:0e774865873d 1836 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 1837 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
screamer 28:0e774865873d 1838 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1839 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1840 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1841 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1842 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1843 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1844 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1845 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1846 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1847 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1848 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1849 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 1850
screamer 28:0e774865873d 1851 #define ADC_TR1_HT1_Pos (16U)
screamer 28:0e774865873d 1852 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
screamer 28:0e774865873d 1853 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
screamer 28:0e774865873d 1854 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1855 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 1856 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1857 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1858 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1859 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1860 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1861 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 1862 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 1863 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 1864 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 1865 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 1866
screamer 28:0e774865873d 1867 /******************** Bit definition for ADC_TR2 register *******************/
screamer 28:0e774865873d 1868 #define ADC_TR2_LT2_Pos (0U)
screamer 28:0e774865873d 1869 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 1870 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
screamer 28:0e774865873d 1871 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1872 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1873 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1874 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1875 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1876 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1877 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1878 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1879
screamer 28:0e774865873d 1880 #define ADC_TR2_HT2_Pos (16U)
screamer 28:0e774865873d 1881 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 1882 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
screamer 28:0e774865873d 1883 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1884 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 1885 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1886 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1887 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1888 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1889 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1890 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 1891
screamer 28:0e774865873d 1892 /******************** Bit definition for ADC_TR3 register *******************/
screamer 28:0e774865873d 1893 #define ADC_TR3_LT3_Pos (0U)
screamer 28:0e774865873d 1894 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 1895 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
screamer 28:0e774865873d 1896 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1897 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1898 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1899 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1900 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1901 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 1902 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1903 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1904
screamer 28:0e774865873d 1905 #define ADC_TR3_HT3_Pos (16U)
screamer 28:0e774865873d 1906 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 1907 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
screamer 28:0e774865873d 1908 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1909 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 1910 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1911 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1912 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1913 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1914 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1915 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 1916
screamer 28:0e774865873d 1917 /******************** Bit definition for ADC_SQR1 register ******************/
screamer 28:0e774865873d 1918 #define ADC_SQR1_L_Pos (0U)
screamer 28:0e774865873d 1919 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 1920 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
screamer 28:0e774865873d 1921 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1922 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1923 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1924 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1925
screamer 28:0e774865873d 1926 #define ADC_SQR1_SQ1_Pos (6U)
screamer 28:0e774865873d 1927 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
screamer 28:0e774865873d 1928 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
screamer 28:0e774865873d 1929 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1930 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1931 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1932 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1933 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1934
screamer 28:0e774865873d 1935 #define ADC_SQR1_SQ2_Pos (12U)
screamer 28:0e774865873d 1936 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
screamer 28:0e774865873d 1937 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
screamer 28:0e774865873d 1938 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 1939 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 1940 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 1941 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 1942 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1943
screamer 28:0e774865873d 1944 #define ADC_SQR1_SQ3_Pos (18U)
screamer 28:0e774865873d 1945 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
screamer 28:0e774865873d 1946 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
screamer 28:0e774865873d 1947 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1948 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1949 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1950 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1951 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1952
screamer 28:0e774865873d 1953 #define ADC_SQR1_SQ4_Pos (24U)
screamer 28:0e774865873d 1954 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
screamer 28:0e774865873d 1955 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
screamer 28:0e774865873d 1956 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 1957 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 1958 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 1959 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 1960 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 1961
screamer 28:0e774865873d 1962 /******************** Bit definition for ADC_SQR2 register ******************/
screamer 28:0e774865873d 1963 #define ADC_SQR2_SQ5_Pos (0U)
screamer 28:0e774865873d 1964 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 1965 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
screamer 28:0e774865873d 1966 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 1967 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 1968 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 1969 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 1970 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 1971
screamer 28:0e774865873d 1972 #define ADC_SQR2_SQ6_Pos (6U)
screamer 28:0e774865873d 1973 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
screamer 28:0e774865873d 1974 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
screamer 28:0e774865873d 1975 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 1976 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 1977 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 1978 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 1979 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 1980
screamer 28:0e774865873d 1981 #define ADC_SQR2_SQ7_Pos (12U)
screamer 28:0e774865873d 1982 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
screamer 28:0e774865873d 1983 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
screamer 28:0e774865873d 1984 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 1985 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 1986 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 1987 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 1988 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 1989
screamer 28:0e774865873d 1990 #define ADC_SQR2_SQ8_Pos (18U)
screamer 28:0e774865873d 1991 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
screamer 28:0e774865873d 1992 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
screamer 28:0e774865873d 1993 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 1994 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 1995 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 1996 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 1997 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 1998
screamer 28:0e774865873d 1999 #define ADC_SQR2_SQ9_Pos (24U)
screamer 28:0e774865873d 2000 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
screamer 28:0e774865873d 2001 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
screamer 28:0e774865873d 2002 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2003 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 2004 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2005 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2006 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2007
screamer 28:0e774865873d 2008 /******************** Bit definition for ADC_SQR3 register ******************/
screamer 28:0e774865873d 2009 #define ADC_SQR3_SQ10_Pos (0U)
screamer 28:0e774865873d 2010 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 2011 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
screamer 28:0e774865873d 2012 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2013 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2014 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2015 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2016 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2017
screamer 28:0e774865873d 2018 #define ADC_SQR3_SQ11_Pos (6U)
screamer 28:0e774865873d 2019 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
screamer 28:0e774865873d 2020 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
screamer 28:0e774865873d 2021 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2022 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2023 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2024 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2025 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2026
screamer 28:0e774865873d 2027 #define ADC_SQR3_SQ12_Pos (12U)
screamer 28:0e774865873d 2028 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
screamer 28:0e774865873d 2029 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
screamer 28:0e774865873d 2030 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2031 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2032 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2033 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2034 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2035
screamer 28:0e774865873d 2036 #define ADC_SQR3_SQ13_Pos (18U)
screamer 28:0e774865873d 2037 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
screamer 28:0e774865873d 2038 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
screamer 28:0e774865873d 2039 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2040 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2041 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2042 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2043 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2044
screamer 28:0e774865873d 2045 #define ADC_SQR3_SQ14_Pos (24U)
screamer 28:0e774865873d 2046 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
screamer 28:0e774865873d 2047 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
screamer 28:0e774865873d 2048 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2049 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 2050 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2051 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2052 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2053
screamer 28:0e774865873d 2054 /******************** Bit definition for ADC_SQR4 register ******************/
screamer 28:0e774865873d 2055 #define ADC_SQR4_SQ15_Pos (0U)
screamer 28:0e774865873d 2056 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 2057 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
screamer 28:0e774865873d 2058 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2059 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2060 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2061 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2062 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2063
screamer 28:0e774865873d 2064 #define ADC_SQR4_SQ16_Pos (6U)
screamer 28:0e774865873d 2065 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
screamer 28:0e774865873d 2066 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
screamer 28:0e774865873d 2067 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2068 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2069 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2070 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2071 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2072
screamer 28:0e774865873d 2073 /******************** Bit definition for ADC_DR register ********************/
screamer 28:0e774865873d 2074 #define ADC_DR_RDATA_Pos (0U)
screamer 28:0e774865873d 2075 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 2076 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
screamer 28:0e774865873d 2077 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2078 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2079 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2080 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2081 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2082 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2083 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2084 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2085 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2086 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2087 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2088 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2089 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2090 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2091 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2092 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2093
screamer 28:0e774865873d 2094 /******************** Bit definition for ADC_JSQR register ******************/
screamer 28:0e774865873d 2095 #define ADC_JSQR_JL_Pos (0U)
screamer 28:0e774865873d 2096 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 2097 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
screamer 28:0e774865873d 2098 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2099 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2100
screamer 28:0e774865873d 2101 #define ADC_JSQR_JEXTSEL_Pos (2U)
screamer 28:0e774865873d 2102 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
screamer 28:0e774865873d 2103 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
screamer 28:0e774865873d 2104 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2105 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2106 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2107 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2108
screamer 28:0e774865873d 2109 #define ADC_JSQR_JEXTEN_Pos (6U)
screamer 28:0e774865873d 2110 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 2111 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
screamer 28:0e774865873d 2112 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2113 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2114
screamer 28:0e774865873d 2115 #define ADC_JSQR_JSQ1_Pos (8U)
screamer 28:0e774865873d 2116 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 2117 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
screamer 28:0e774865873d 2118 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2119 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2120 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2121 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2122 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2123
screamer 28:0e774865873d 2124 #define ADC_JSQR_JSQ2_Pos (14U)
screamer 28:0e774865873d 2125 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
screamer 28:0e774865873d 2126 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
screamer 28:0e774865873d 2127 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2128 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2129 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2130 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2131 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2132
screamer 28:0e774865873d 2133 #define ADC_JSQR_JSQ3_Pos (20U)
screamer 28:0e774865873d 2134 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
screamer 28:0e774865873d 2135 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
screamer 28:0e774865873d 2136 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2137 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2138 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2139 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 2140 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2141
screamer 28:0e774865873d 2142 #define ADC_JSQR_JSQ4_Pos (26U)
screamer 28:0e774865873d 2143 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
screamer 28:0e774865873d 2144 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
screamer 28:0e774865873d 2145 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2146 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2147 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2148 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2149 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2150
screamer 28:0e774865873d 2151 /******************** Bit definition for ADC_OFR1 register ******************/
screamer 28:0e774865873d 2152 #define ADC_OFR1_OFFSET1_Pos (0U)
screamer 28:0e774865873d 2153 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 2154 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
screamer 28:0e774865873d 2155 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2156 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2157 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2158 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2159 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2160 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2161 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2162 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2163 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2164 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2165 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2166 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2167
screamer 28:0e774865873d 2168 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
screamer 28:0e774865873d 2169 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
screamer 28:0e774865873d 2170 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
screamer 28:0e774865873d 2171 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2172 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2173 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2174 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2175 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2176
screamer 28:0e774865873d 2177 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
screamer 28:0e774865873d 2178 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2179 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
screamer 28:0e774865873d 2180
screamer 28:0e774865873d 2181 /******************** Bit definition for ADC_OFR2 register ******************/
screamer 28:0e774865873d 2182 #define ADC_OFR2_OFFSET2_Pos (0U)
screamer 28:0e774865873d 2183 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 2184 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
screamer 28:0e774865873d 2185 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2186 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2187 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2188 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2189 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2190 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2191 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2192 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2193 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2194 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2195 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2196 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2197
screamer 28:0e774865873d 2198 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
screamer 28:0e774865873d 2199 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
screamer 28:0e774865873d 2200 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
screamer 28:0e774865873d 2201 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2202 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2203 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2204 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2205 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2206
screamer 28:0e774865873d 2207 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
screamer 28:0e774865873d 2208 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2209 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
screamer 28:0e774865873d 2210
screamer 28:0e774865873d 2211 /******************** Bit definition for ADC_OFR3 register ******************/
screamer 28:0e774865873d 2212 #define ADC_OFR3_OFFSET3_Pos (0U)
screamer 28:0e774865873d 2213 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 2214 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
screamer 28:0e774865873d 2215 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2216 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2217 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2218 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2219 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2220 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2221 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2222 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2223 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2224 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2225 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2226 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2227
screamer 28:0e774865873d 2228 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
screamer 28:0e774865873d 2229 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
screamer 28:0e774865873d 2230 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
screamer 28:0e774865873d 2231 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2232 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2233 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2234 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2235 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2236
screamer 28:0e774865873d 2237 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
screamer 28:0e774865873d 2238 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2239 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
screamer 28:0e774865873d 2240
screamer 28:0e774865873d 2241 /******************** Bit definition for ADC_OFR4 register ******************/
screamer 28:0e774865873d 2242 #define ADC_OFR4_OFFSET4_Pos (0U)
screamer 28:0e774865873d 2243 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 2244 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
screamer 28:0e774865873d 2245 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2246 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2247 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2248 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2249 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2250 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2251 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2252 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2253 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2254 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2255 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2256 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2257
screamer 28:0e774865873d 2258 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
screamer 28:0e774865873d 2259 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
screamer 28:0e774865873d 2260 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
screamer 28:0e774865873d 2261 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2262 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2263 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2264 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2265 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2266
screamer 28:0e774865873d 2267 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
screamer 28:0e774865873d 2268 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2269 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
screamer 28:0e774865873d 2270
screamer 28:0e774865873d 2271 /******************** Bit definition for ADC_JDR1 register ******************/
screamer 28:0e774865873d 2272 #define ADC_JDR1_JDATA_Pos (0U)
screamer 28:0e774865873d 2273 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 2274 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
screamer 28:0e774865873d 2275 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2276 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2277 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2278 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2279 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2280 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2281 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2282 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2283 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2284 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2285 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2286 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2287 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2288 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2289 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2290 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2291
screamer 28:0e774865873d 2292 /******************** Bit definition for ADC_JDR2 register ******************/
screamer 28:0e774865873d 2293 #define ADC_JDR2_JDATA_Pos (0U)
screamer 28:0e774865873d 2294 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 2295 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
screamer 28:0e774865873d 2296 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2297 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2298 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2299 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2300 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2301 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2302 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2303 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2304 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2305 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2306 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2307 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2308 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2309 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2310 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2311 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2312
screamer 28:0e774865873d 2313 /******************** Bit definition for ADC_JDR3 register ******************/
screamer 28:0e774865873d 2314 #define ADC_JDR3_JDATA_Pos (0U)
screamer 28:0e774865873d 2315 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 2316 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
screamer 28:0e774865873d 2317 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2318 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2319 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2320 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2321 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2322 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2323 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2324 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2325 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2326 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2327 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2328 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2329 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2330 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2331 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2332 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2333
screamer 28:0e774865873d 2334 /******************** Bit definition for ADC_JDR4 register ******************/
screamer 28:0e774865873d 2335 #define ADC_JDR4_JDATA_Pos (0U)
screamer 28:0e774865873d 2336 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 2337 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
screamer 28:0e774865873d 2338 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2339 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2340 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2341 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2342 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2343 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2344 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2345 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2346 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2347 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2348 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2349 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2350 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2351 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2352 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2353 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2354
screamer 28:0e774865873d 2355 /******************** Bit definition for ADC_AWD2CR register ****************/
screamer 28:0e774865873d 2356 #define ADC_AWD2CR_AWD2CH_Pos (0U)
screamer 28:0e774865873d 2357 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 2358 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
screamer 28:0e774865873d 2359 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2360 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2361 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2362 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2363 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2364 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2365 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2366 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2367 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2368 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2369 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2370 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2371 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2372 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2373 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2374 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2375 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2376 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2377 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2378
screamer 28:0e774865873d 2379 /******************** Bit definition for ADC_AWD3CR register ****************/
screamer 28:0e774865873d 2380 #define ADC_AWD3CR_AWD3CH_Pos (0U)
screamer 28:0e774865873d 2381 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 2382 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
screamer 28:0e774865873d 2383 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2384 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2385 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2386 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2387 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2388 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2389 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2390 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2391 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2392 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2393 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2394 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2395 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2396 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2397 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2398 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2399 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2400 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2401 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2402
screamer 28:0e774865873d 2403 /******************** Bit definition for ADC_DIFSEL register ****************/
screamer 28:0e774865873d 2404 #define ADC_DIFSEL_DIFSEL_Pos (0U)
screamer 28:0e774865873d 2405 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 2406 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
screamer 28:0e774865873d 2407 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2408 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2409 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2410 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2411 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2412 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2413 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2414 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2415 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2416 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2417 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2418 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2419 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2420 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2421 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2422 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2423 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2424 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2425 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2426
screamer 28:0e774865873d 2427 /******************** Bit definition for ADC_CALFACT register ***************/
screamer 28:0e774865873d 2428 #define ADC_CALFACT_CALFACT_S_Pos (0U)
screamer 28:0e774865873d 2429 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
screamer 28:0e774865873d 2430 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
screamer 28:0e774865873d 2431 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2432 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2433 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2434 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2435 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2436 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2437 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2438
screamer 28:0e774865873d 2439 #define ADC_CALFACT_CALFACT_D_Pos (16U)
screamer 28:0e774865873d 2440 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
screamer 28:0e774865873d 2441 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
screamer 28:0e774865873d 2442 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2443 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2444 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2445 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2446 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2447 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2448 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2449
screamer 28:0e774865873d 2450 /************************* ADC Common registers *****************************/
screamer 28:0e774865873d 2451 /******************** Bit definition for ADC_CSR register *******************/
screamer 28:0e774865873d 2452 #define ADC_CSR_ADRDY_MST_Pos (0U)
screamer 28:0e774865873d 2453 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2454 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
screamer 28:0e774865873d 2455 #define ADC_CSR_EOSMP_MST_Pos (1U)
screamer 28:0e774865873d 2456 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2457 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
screamer 28:0e774865873d 2458 #define ADC_CSR_EOC_MST_Pos (2U)
screamer 28:0e774865873d 2459 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2460 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
screamer 28:0e774865873d 2461 #define ADC_CSR_EOS_MST_Pos (3U)
screamer 28:0e774865873d 2462 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2463 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
screamer 28:0e774865873d 2464 #define ADC_CSR_OVR_MST_Pos (4U)
screamer 28:0e774865873d 2465 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2466 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
screamer 28:0e774865873d 2467 #define ADC_CSR_JEOC_MST_Pos (5U)
screamer 28:0e774865873d 2468 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2469 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
screamer 28:0e774865873d 2470 #define ADC_CSR_JEOS_MST_Pos (6U)
screamer 28:0e774865873d 2471 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2472 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
screamer 28:0e774865873d 2473 #define ADC_CSR_AWD1_MST_Pos (7U)
screamer 28:0e774865873d 2474 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2475 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
screamer 28:0e774865873d 2476 #define ADC_CSR_AWD2_MST_Pos (8U)
screamer 28:0e774865873d 2477 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2478 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
screamer 28:0e774865873d 2479 #define ADC_CSR_AWD3_MST_Pos (9U)
screamer 28:0e774865873d 2480 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2481 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
screamer 28:0e774865873d 2482 #define ADC_CSR_JQOVF_MST_Pos (10U)
screamer 28:0e774865873d 2483 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2484 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
screamer 28:0e774865873d 2485
screamer 28:0e774865873d 2486 #define ADC_CSR_ADRDY_SLV_Pos (16U)
screamer 28:0e774865873d 2487 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2488 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
screamer 28:0e774865873d 2489 #define ADC_CSR_EOSMP_SLV_Pos (17U)
screamer 28:0e774865873d 2490 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2491 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
screamer 28:0e774865873d 2492 #define ADC_CSR_EOC_SLV_Pos (18U)
screamer 28:0e774865873d 2493 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2494 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
screamer 28:0e774865873d 2495 #define ADC_CSR_EOS_SLV_Pos (19U)
screamer 28:0e774865873d 2496 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2497 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
screamer 28:0e774865873d 2498 #define ADC_CSR_OVR_SLV_Pos (20U)
screamer 28:0e774865873d 2499 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2500 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
screamer 28:0e774865873d 2501 #define ADC_CSR_JEOC_SLV_Pos (21U)
screamer 28:0e774865873d 2502 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2503 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
screamer 28:0e774865873d 2504 #define ADC_CSR_JEOS_SLV_Pos (22U)
screamer 28:0e774865873d 2505 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2506 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
screamer 28:0e774865873d 2507 #define ADC_CSR_AWD1_SLV_Pos (23U)
screamer 28:0e774865873d 2508 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 2509 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
screamer 28:0e774865873d 2510 #define ADC_CSR_AWD2_SLV_Pos (24U)
screamer 28:0e774865873d 2511 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2512 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
screamer 28:0e774865873d 2513 #define ADC_CSR_AWD3_SLV_Pos (25U)
screamer 28:0e774865873d 2514 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 2515 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
screamer 28:0e774865873d 2516 #define ADC_CSR_JQOVF_SLV_Pos (26U)
screamer 28:0e774865873d 2517 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2518 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
screamer 28:0e774865873d 2519
screamer 28:0e774865873d 2520 /******************** Bit definition for ADC_CCR register *******************/
screamer 28:0e774865873d 2521 #define ADC_CCR_DUAL_Pos (0U)
screamer 28:0e774865873d 2522 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 2523 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
screamer 28:0e774865873d 2524 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2525 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2526 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2527 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2528 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2529
screamer 28:0e774865873d 2530 #define ADC_CCR_DELAY_Pos (8U)
screamer 28:0e774865873d 2531 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 2532 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
screamer 28:0e774865873d 2533 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2534 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2535 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2536 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2537
screamer 28:0e774865873d 2538 #define ADC_CCR_DMACFG_Pos (13U)
screamer 28:0e774865873d 2539 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2540 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
screamer 28:0e774865873d 2541
screamer 28:0e774865873d 2542 #define ADC_CCR_MDMA_Pos (14U)
screamer 28:0e774865873d 2543 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 2544 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
screamer 28:0e774865873d 2545 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2546 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2547
screamer 28:0e774865873d 2548 #define ADC_CCR_CKMODE_Pos (16U)
screamer 28:0e774865873d 2549 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 2550 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
screamer 28:0e774865873d 2551 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2552 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2553
screamer 28:0e774865873d 2554 #define ADC_CCR_PRESC_Pos (18U)
screamer 28:0e774865873d 2555 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
screamer 28:0e774865873d 2556 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
screamer 28:0e774865873d 2557 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2558 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2559 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2560 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2561
screamer 28:0e774865873d 2562 #define ADC_CCR_VREFEN_Pos (22U)
screamer 28:0e774865873d 2563 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2564 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
screamer 28:0e774865873d 2565 #define ADC_CCR_TSEN_Pos (23U)
screamer 28:0e774865873d 2566 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 2567 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
screamer 28:0e774865873d 2568 #define ADC_CCR_VBATEN_Pos (24U)
screamer 28:0e774865873d 2569 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2570 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
screamer 28:0e774865873d 2571
screamer 28:0e774865873d 2572 /******************** Bit definition for ADC_CDR register *******************/
screamer 28:0e774865873d 2573 #define ADC_CDR_RDATA_MST_Pos (0U)
screamer 28:0e774865873d 2574 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 2575 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
screamer 28:0e774865873d 2576 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2577 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2578 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2579 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2580 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2581 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2582 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2583 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2584 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2585 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2586 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2587 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2588 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 2589 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 2590 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 2591 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2592
screamer 28:0e774865873d 2593 #define ADC_CDR_RDATA_SLV_Pos (16U)
screamer 28:0e774865873d 2594 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 2595 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
screamer 28:0e774865873d 2596 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2597 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2598 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2599 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2600 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2601 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2602 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2603 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 2604 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2605 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 2606 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2607 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2608 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2609 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2610 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2611 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2612
screamer 28:0e774865873d 2613 /******************************************************************************/
screamer 28:0e774865873d 2614 /* */
screamer 28:0e774865873d 2615 /* Controller Area Network */
screamer 28:0e774865873d 2616 /* */
screamer 28:0e774865873d 2617 /******************************************************************************/
screamer 28:0e774865873d 2618 /*!<CAN control and status registers */
screamer 28:0e774865873d 2619 /******************* Bit definition for CAN_MCR register ********************/
screamer 28:0e774865873d 2620 #define CAN_MCR_INRQ_Pos (0U)
screamer 28:0e774865873d 2621 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2622 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
screamer 28:0e774865873d 2623 #define CAN_MCR_SLEEP_Pos (1U)
screamer 28:0e774865873d 2624 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2625 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
screamer 28:0e774865873d 2626 #define CAN_MCR_TXFP_Pos (2U)
screamer 28:0e774865873d 2627 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2628 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
screamer 28:0e774865873d 2629 #define CAN_MCR_RFLM_Pos (3U)
screamer 28:0e774865873d 2630 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2631 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
screamer 28:0e774865873d 2632 #define CAN_MCR_NART_Pos (4U)
screamer 28:0e774865873d 2633 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2634 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
screamer 28:0e774865873d 2635 #define CAN_MCR_AWUM_Pos (5U)
screamer 28:0e774865873d 2636 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2637 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
screamer 28:0e774865873d 2638 #define CAN_MCR_ABOM_Pos (6U)
screamer 28:0e774865873d 2639 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2640 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
screamer 28:0e774865873d 2641 #define CAN_MCR_TTCM_Pos (7U)
screamer 28:0e774865873d 2642 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2643 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
screamer 28:0e774865873d 2644 #define CAN_MCR_RESET_Pos (15U)
screamer 28:0e774865873d 2645 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2646 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
screamer 28:0e774865873d 2647
screamer 28:0e774865873d 2648 /******************* Bit definition for CAN_MSR register ********************/
screamer 28:0e774865873d 2649 #define CAN_MSR_INAK_Pos (0U)
screamer 28:0e774865873d 2650 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2651 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
screamer 28:0e774865873d 2652 #define CAN_MSR_SLAK_Pos (1U)
screamer 28:0e774865873d 2653 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2654 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
screamer 28:0e774865873d 2655 #define CAN_MSR_ERRI_Pos (2U)
screamer 28:0e774865873d 2656 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2657 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
screamer 28:0e774865873d 2658 #define CAN_MSR_WKUI_Pos (3U)
screamer 28:0e774865873d 2659 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2660 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
screamer 28:0e774865873d 2661 #define CAN_MSR_SLAKI_Pos (4U)
screamer 28:0e774865873d 2662 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2663 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
screamer 28:0e774865873d 2664 #define CAN_MSR_TXM_Pos (8U)
screamer 28:0e774865873d 2665 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2666 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
screamer 28:0e774865873d 2667 #define CAN_MSR_RXM_Pos (9U)
screamer 28:0e774865873d 2668 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2669 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
screamer 28:0e774865873d 2670 #define CAN_MSR_SAMP_Pos (10U)
screamer 28:0e774865873d 2671 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2672 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
screamer 28:0e774865873d 2673 #define CAN_MSR_RX_Pos (11U)
screamer 28:0e774865873d 2674 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2675 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
screamer 28:0e774865873d 2676
screamer 28:0e774865873d 2677 /******************* Bit definition for CAN_TSR register ********************/
screamer 28:0e774865873d 2678 #define CAN_TSR_RQCP0_Pos (0U)
screamer 28:0e774865873d 2679 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2680 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
screamer 28:0e774865873d 2681 #define CAN_TSR_TXOK0_Pos (1U)
screamer 28:0e774865873d 2682 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2683 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
screamer 28:0e774865873d 2684 #define CAN_TSR_ALST0_Pos (2U)
screamer 28:0e774865873d 2685 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2686 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
screamer 28:0e774865873d 2687 #define CAN_TSR_TERR0_Pos (3U)
screamer 28:0e774865873d 2688 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2689 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
screamer 28:0e774865873d 2690 #define CAN_TSR_ABRQ0_Pos (7U)
screamer 28:0e774865873d 2691 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 2692 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
screamer 28:0e774865873d 2693 #define CAN_TSR_RQCP1_Pos (8U)
screamer 28:0e774865873d 2694 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2695 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
screamer 28:0e774865873d 2696 #define CAN_TSR_TXOK1_Pos (9U)
screamer 28:0e774865873d 2697 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2698 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
screamer 28:0e774865873d 2699 #define CAN_TSR_ALST1_Pos (10U)
screamer 28:0e774865873d 2700 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2701 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
screamer 28:0e774865873d 2702 #define CAN_TSR_TERR1_Pos (11U)
screamer 28:0e774865873d 2703 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2704 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
screamer 28:0e774865873d 2705 #define CAN_TSR_ABRQ1_Pos (15U)
screamer 28:0e774865873d 2706 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2707 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
screamer 28:0e774865873d 2708 #define CAN_TSR_RQCP2_Pos (16U)
screamer 28:0e774865873d 2709 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2710 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
screamer 28:0e774865873d 2711 #define CAN_TSR_TXOK2_Pos (17U)
screamer 28:0e774865873d 2712 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2713 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
screamer 28:0e774865873d 2714 #define CAN_TSR_ALST2_Pos (18U)
screamer 28:0e774865873d 2715 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2716 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
screamer 28:0e774865873d 2717 #define CAN_TSR_TERR2_Pos (19U)
screamer 28:0e774865873d 2718 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2719 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
screamer 28:0e774865873d 2720 #define CAN_TSR_ABRQ2_Pos (23U)
screamer 28:0e774865873d 2721 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 2722 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
screamer 28:0e774865873d 2723 #define CAN_TSR_CODE_Pos (24U)
screamer 28:0e774865873d 2724 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 2725 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
screamer 28:0e774865873d 2726
screamer 28:0e774865873d 2727 #define CAN_TSR_TME_Pos (26U)
screamer 28:0e774865873d 2728 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
screamer 28:0e774865873d 2729 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
screamer 28:0e774865873d 2730 #define CAN_TSR_TME0_Pos (26U)
screamer 28:0e774865873d 2731 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 2732 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
screamer 28:0e774865873d 2733 #define CAN_TSR_TME1_Pos (27U)
screamer 28:0e774865873d 2734 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 2735 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
screamer 28:0e774865873d 2736 #define CAN_TSR_TME2_Pos (28U)
screamer 28:0e774865873d 2737 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 2738 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
screamer 28:0e774865873d 2739
screamer 28:0e774865873d 2740 #define CAN_TSR_LOW_Pos (29U)
screamer 28:0e774865873d 2741 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
screamer 28:0e774865873d 2742 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
screamer 28:0e774865873d 2743 #define CAN_TSR_LOW0_Pos (29U)
screamer 28:0e774865873d 2744 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 2745 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
screamer 28:0e774865873d 2746 #define CAN_TSR_LOW1_Pos (30U)
screamer 28:0e774865873d 2747 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2748 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
screamer 28:0e774865873d 2749 #define CAN_TSR_LOW2_Pos (31U)
screamer 28:0e774865873d 2750 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2751 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
screamer 28:0e774865873d 2752
screamer 28:0e774865873d 2753 /******************* Bit definition for CAN_RF0R register *******************/
screamer 28:0e774865873d 2754 #define CAN_RF0R_FMP0_Pos (0U)
screamer 28:0e774865873d 2755 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 2756 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
screamer 28:0e774865873d 2757 #define CAN_RF0R_FULL0_Pos (3U)
screamer 28:0e774865873d 2758 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2759 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
screamer 28:0e774865873d 2760 #define CAN_RF0R_FOVR0_Pos (4U)
screamer 28:0e774865873d 2761 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2762 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
screamer 28:0e774865873d 2763 #define CAN_RF0R_RFOM0_Pos (5U)
screamer 28:0e774865873d 2764 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2765 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
screamer 28:0e774865873d 2766
screamer 28:0e774865873d 2767 /******************* Bit definition for CAN_RF1R register *******************/
screamer 28:0e774865873d 2768 #define CAN_RF1R_FMP1_Pos (0U)
screamer 28:0e774865873d 2769 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 2770 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
screamer 28:0e774865873d 2771 #define CAN_RF1R_FULL1_Pos (3U)
screamer 28:0e774865873d 2772 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2773 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
screamer 28:0e774865873d 2774 #define CAN_RF1R_FOVR1_Pos (4U)
screamer 28:0e774865873d 2775 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2776 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
screamer 28:0e774865873d 2777 #define CAN_RF1R_RFOM1_Pos (5U)
screamer 28:0e774865873d 2778 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2779 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
screamer 28:0e774865873d 2780
screamer 28:0e774865873d 2781 /******************** Bit definition for CAN_IER register *******************/
screamer 28:0e774865873d 2782 #define CAN_IER_TMEIE_Pos (0U)
screamer 28:0e774865873d 2783 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2784 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
screamer 28:0e774865873d 2785 #define CAN_IER_FMPIE0_Pos (1U)
screamer 28:0e774865873d 2786 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2787 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
screamer 28:0e774865873d 2788 #define CAN_IER_FFIE0_Pos (2U)
screamer 28:0e774865873d 2789 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2790 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
screamer 28:0e774865873d 2791 #define CAN_IER_FOVIE0_Pos (3U)
screamer 28:0e774865873d 2792 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 2793 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
screamer 28:0e774865873d 2794 #define CAN_IER_FMPIE1_Pos (4U)
screamer 28:0e774865873d 2795 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2796 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
screamer 28:0e774865873d 2797 #define CAN_IER_FFIE1_Pos (5U)
screamer 28:0e774865873d 2798 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2799 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
screamer 28:0e774865873d 2800 #define CAN_IER_FOVIE1_Pos (6U)
screamer 28:0e774865873d 2801 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2802 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
screamer 28:0e774865873d 2803 #define CAN_IER_EWGIE_Pos (8U)
screamer 28:0e774865873d 2804 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2805 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
screamer 28:0e774865873d 2806 #define CAN_IER_EPVIE_Pos (9U)
screamer 28:0e774865873d 2807 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 2808 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
screamer 28:0e774865873d 2809 #define CAN_IER_BOFIE_Pos (10U)
screamer 28:0e774865873d 2810 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 2811 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
screamer 28:0e774865873d 2812 #define CAN_IER_LECIE_Pos (11U)
screamer 28:0e774865873d 2813 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 2814 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
screamer 28:0e774865873d 2815 #define CAN_IER_ERRIE_Pos (15U)
screamer 28:0e774865873d 2816 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 2817 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
screamer 28:0e774865873d 2818 #define CAN_IER_WKUIE_Pos (16U)
screamer 28:0e774865873d 2819 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2820 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
screamer 28:0e774865873d 2821 #define CAN_IER_SLKIE_Pos (17U)
screamer 28:0e774865873d 2822 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2823 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
screamer 28:0e774865873d 2824
screamer 28:0e774865873d 2825 /******************** Bit definition for CAN_ESR register *******************/
screamer 28:0e774865873d 2826 #define CAN_ESR_EWGF_Pos (0U)
screamer 28:0e774865873d 2827 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2828 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
screamer 28:0e774865873d 2829 #define CAN_ESR_EPVF_Pos (1U)
screamer 28:0e774865873d 2830 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2831 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
screamer 28:0e774865873d 2832 #define CAN_ESR_BOFF_Pos (2U)
screamer 28:0e774865873d 2833 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2834 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
screamer 28:0e774865873d 2835
screamer 28:0e774865873d 2836 #define CAN_ESR_LEC_Pos (4U)
screamer 28:0e774865873d 2837 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 2838 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
screamer 28:0e774865873d 2839 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 2840 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 2841 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 2842
screamer 28:0e774865873d 2843 #define CAN_ESR_TEC_Pos (16U)
screamer 28:0e774865873d 2844 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 2845 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
screamer 28:0e774865873d 2846 #define CAN_ESR_REC_Pos (24U)
screamer 28:0e774865873d 2847 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 2848 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
screamer 28:0e774865873d 2849
screamer 28:0e774865873d 2850 /******************* Bit definition for CAN_BTR register ********************/
screamer 28:0e774865873d 2851 #define CAN_BTR_BRP_Pos (0U)
screamer 28:0e774865873d 2852 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
screamer 28:0e774865873d 2853 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
screamer 28:0e774865873d 2854 #define CAN_BTR_TS1_Pos (16U)
screamer 28:0e774865873d 2855 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 2856 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
screamer 28:0e774865873d 2857 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 2858 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 2859 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 2860 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 2861 #define CAN_BTR_TS2_Pos (20U)
screamer 28:0e774865873d 2862 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
screamer 28:0e774865873d 2863 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
screamer 28:0e774865873d 2864 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 2865 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 2866 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 2867 #define CAN_BTR_SJW_Pos (24U)
screamer 28:0e774865873d 2868 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 2869 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
screamer 28:0e774865873d 2870 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 2871 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 2872 #define CAN_BTR_LBKM_Pos (30U)
screamer 28:0e774865873d 2873 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 2874 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
screamer 28:0e774865873d 2875 #define CAN_BTR_SILM_Pos (31U)
screamer 28:0e774865873d 2876 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 2877 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
screamer 28:0e774865873d 2878
screamer 28:0e774865873d 2879 /*!<Mailbox registers */
screamer 28:0e774865873d 2880 /****************** Bit definition for CAN_TI0R register ********************/
screamer 28:0e774865873d 2881 #define CAN_TI0R_TXRQ_Pos (0U)
screamer 28:0e774865873d 2882 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2883 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
screamer 28:0e774865873d 2884 #define CAN_TI0R_RTR_Pos (1U)
screamer 28:0e774865873d 2885 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2886 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
screamer 28:0e774865873d 2887 #define CAN_TI0R_IDE_Pos (2U)
screamer 28:0e774865873d 2888 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2889 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
screamer 28:0e774865873d 2890 #define CAN_TI0R_EXID_Pos (3U)
screamer 28:0e774865873d 2891 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
screamer 28:0e774865873d 2892 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
screamer 28:0e774865873d 2893 #define CAN_TI0R_STID_Pos (21U)
screamer 28:0e774865873d 2894 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
screamer 28:0e774865873d 2895 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
screamer 28:0e774865873d 2896
screamer 28:0e774865873d 2897 /****************** Bit definition for CAN_TDT0R register *******************/
screamer 28:0e774865873d 2898 #define CAN_TDT0R_DLC_Pos (0U)
screamer 28:0e774865873d 2899 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 2900 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
screamer 28:0e774865873d 2901 #define CAN_TDT0R_TGT_Pos (8U)
screamer 28:0e774865873d 2902 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2903 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
screamer 28:0e774865873d 2904 #define CAN_TDT0R_TIME_Pos (16U)
screamer 28:0e774865873d 2905 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 2906 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
screamer 28:0e774865873d 2907
screamer 28:0e774865873d 2908 /****************** Bit definition for CAN_TDL0R register *******************/
screamer 28:0e774865873d 2909 #define CAN_TDL0R_DATA0_Pos (0U)
screamer 28:0e774865873d 2910 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 2911 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
screamer 28:0e774865873d 2912 #define CAN_TDL0R_DATA1_Pos (8U)
screamer 28:0e774865873d 2913 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 2914 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
screamer 28:0e774865873d 2915 #define CAN_TDL0R_DATA2_Pos (16U)
screamer 28:0e774865873d 2916 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 2917 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
screamer 28:0e774865873d 2918 #define CAN_TDL0R_DATA3_Pos (24U)
screamer 28:0e774865873d 2919 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 2920 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
screamer 28:0e774865873d 2921
screamer 28:0e774865873d 2922 /****************** Bit definition for CAN_TDH0R register *******************/
screamer 28:0e774865873d 2923 #define CAN_TDH0R_DATA4_Pos (0U)
screamer 28:0e774865873d 2924 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 2925 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
screamer 28:0e774865873d 2926 #define CAN_TDH0R_DATA5_Pos (8U)
screamer 28:0e774865873d 2927 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 2928 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
screamer 28:0e774865873d 2929 #define CAN_TDH0R_DATA6_Pos (16U)
screamer 28:0e774865873d 2930 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 2931 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
screamer 28:0e774865873d 2932 #define CAN_TDH0R_DATA7_Pos (24U)
screamer 28:0e774865873d 2933 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 2934 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
screamer 28:0e774865873d 2935
screamer 28:0e774865873d 2936 /******************* Bit definition for CAN_TI1R register *******************/
screamer 28:0e774865873d 2937 #define CAN_TI1R_TXRQ_Pos (0U)
screamer 28:0e774865873d 2938 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2939 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
screamer 28:0e774865873d 2940 #define CAN_TI1R_RTR_Pos (1U)
screamer 28:0e774865873d 2941 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2942 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
screamer 28:0e774865873d 2943 #define CAN_TI1R_IDE_Pos (2U)
screamer 28:0e774865873d 2944 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 2945 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
screamer 28:0e774865873d 2946 #define CAN_TI1R_EXID_Pos (3U)
screamer 28:0e774865873d 2947 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
screamer 28:0e774865873d 2948 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
screamer 28:0e774865873d 2949 #define CAN_TI1R_STID_Pos (21U)
screamer 28:0e774865873d 2950 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
screamer 28:0e774865873d 2951 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
screamer 28:0e774865873d 2952
screamer 28:0e774865873d 2953 /******************* Bit definition for CAN_TDT1R register ******************/
screamer 28:0e774865873d 2954 #define CAN_TDT1R_DLC_Pos (0U)
screamer 28:0e774865873d 2955 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 2956 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
screamer 28:0e774865873d 2957 #define CAN_TDT1R_TGT_Pos (8U)
screamer 28:0e774865873d 2958 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 2959 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
screamer 28:0e774865873d 2960 #define CAN_TDT1R_TIME_Pos (16U)
screamer 28:0e774865873d 2961 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 2962 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
screamer 28:0e774865873d 2963
screamer 28:0e774865873d 2964 /******************* Bit definition for CAN_TDL1R register ******************/
screamer 28:0e774865873d 2965 #define CAN_TDL1R_DATA0_Pos (0U)
screamer 28:0e774865873d 2966 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 2967 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
screamer 28:0e774865873d 2968 #define CAN_TDL1R_DATA1_Pos (8U)
screamer 28:0e774865873d 2969 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 2970 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
screamer 28:0e774865873d 2971 #define CAN_TDL1R_DATA2_Pos (16U)
screamer 28:0e774865873d 2972 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 2973 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
screamer 28:0e774865873d 2974 #define CAN_TDL1R_DATA3_Pos (24U)
screamer 28:0e774865873d 2975 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 2976 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
screamer 28:0e774865873d 2977
screamer 28:0e774865873d 2978 /******************* Bit definition for CAN_TDH1R register ******************/
screamer 28:0e774865873d 2979 #define CAN_TDH1R_DATA4_Pos (0U)
screamer 28:0e774865873d 2980 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 2981 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
screamer 28:0e774865873d 2982 #define CAN_TDH1R_DATA5_Pos (8U)
screamer 28:0e774865873d 2983 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 2984 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
screamer 28:0e774865873d 2985 #define CAN_TDH1R_DATA6_Pos (16U)
screamer 28:0e774865873d 2986 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 2987 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
screamer 28:0e774865873d 2988 #define CAN_TDH1R_DATA7_Pos (24U)
screamer 28:0e774865873d 2989 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 2990 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
screamer 28:0e774865873d 2991
screamer 28:0e774865873d 2992 /******************* Bit definition for CAN_TI2R register *******************/
screamer 28:0e774865873d 2993 #define CAN_TI2R_TXRQ_Pos (0U)
screamer 28:0e774865873d 2994 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 2995 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
screamer 28:0e774865873d 2996 #define CAN_TI2R_RTR_Pos (1U)
screamer 28:0e774865873d 2997 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 2998 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
screamer 28:0e774865873d 2999 #define CAN_TI2R_IDE_Pos (2U)
screamer 28:0e774865873d 3000 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3001 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
screamer 28:0e774865873d 3002 #define CAN_TI2R_EXID_Pos (3U)
screamer 28:0e774865873d 3003 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
screamer 28:0e774865873d 3004 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
screamer 28:0e774865873d 3005 #define CAN_TI2R_STID_Pos (21U)
screamer 28:0e774865873d 3006 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
screamer 28:0e774865873d 3007 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
screamer 28:0e774865873d 3008
screamer 28:0e774865873d 3009 /******************* Bit definition for CAN_TDT2R register ******************/
screamer 28:0e774865873d 3010 #define CAN_TDT2R_DLC_Pos (0U)
screamer 28:0e774865873d 3011 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 3012 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
screamer 28:0e774865873d 3013 #define CAN_TDT2R_TGT_Pos (8U)
screamer 28:0e774865873d 3014 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3015 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
screamer 28:0e774865873d 3016 #define CAN_TDT2R_TIME_Pos (16U)
screamer 28:0e774865873d 3017 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 3018 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
screamer 28:0e774865873d 3019
screamer 28:0e774865873d 3020 /******************* Bit definition for CAN_TDL2R register ******************/
screamer 28:0e774865873d 3021 #define CAN_TDL2R_DATA0_Pos (0U)
screamer 28:0e774865873d 3022 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 3023 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
screamer 28:0e774865873d 3024 #define CAN_TDL2R_DATA1_Pos (8U)
screamer 28:0e774865873d 3025 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3026 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
screamer 28:0e774865873d 3027 #define CAN_TDL2R_DATA2_Pos (16U)
screamer 28:0e774865873d 3028 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 3029 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
screamer 28:0e774865873d 3030 #define CAN_TDL2R_DATA3_Pos (24U)
screamer 28:0e774865873d 3031 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 3032 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
screamer 28:0e774865873d 3033
screamer 28:0e774865873d 3034 /******************* Bit definition for CAN_TDH2R register ******************/
screamer 28:0e774865873d 3035 #define CAN_TDH2R_DATA4_Pos (0U)
screamer 28:0e774865873d 3036 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 3037 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
screamer 28:0e774865873d 3038 #define CAN_TDH2R_DATA5_Pos (8U)
screamer 28:0e774865873d 3039 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3040 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
screamer 28:0e774865873d 3041 #define CAN_TDH2R_DATA6_Pos (16U)
screamer 28:0e774865873d 3042 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 3043 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
screamer 28:0e774865873d 3044 #define CAN_TDH2R_DATA7_Pos (24U)
screamer 28:0e774865873d 3045 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 3046 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
screamer 28:0e774865873d 3047
screamer 28:0e774865873d 3048 /******************* Bit definition for CAN_RI0R register *******************/
screamer 28:0e774865873d 3049 #define CAN_RI0R_RTR_Pos (1U)
screamer 28:0e774865873d 3050 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3051 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
screamer 28:0e774865873d 3052 #define CAN_RI0R_IDE_Pos (2U)
screamer 28:0e774865873d 3053 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3054 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
screamer 28:0e774865873d 3055 #define CAN_RI0R_EXID_Pos (3U)
screamer 28:0e774865873d 3056 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
screamer 28:0e774865873d 3057 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
screamer 28:0e774865873d 3058 #define CAN_RI0R_STID_Pos (21U)
screamer 28:0e774865873d 3059 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
screamer 28:0e774865873d 3060 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
screamer 28:0e774865873d 3061
screamer 28:0e774865873d 3062 /******************* Bit definition for CAN_RDT0R register ******************/
screamer 28:0e774865873d 3063 #define CAN_RDT0R_DLC_Pos (0U)
screamer 28:0e774865873d 3064 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 3065 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
screamer 28:0e774865873d 3066 #define CAN_RDT0R_FMI_Pos (8U)
screamer 28:0e774865873d 3067 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3068 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
screamer 28:0e774865873d 3069 #define CAN_RDT0R_TIME_Pos (16U)
screamer 28:0e774865873d 3070 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 3071 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
screamer 28:0e774865873d 3072
screamer 28:0e774865873d 3073 /******************* Bit definition for CAN_RDL0R register ******************/
screamer 28:0e774865873d 3074 #define CAN_RDL0R_DATA0_Pos (0U)
screamer 28:0e774865873d 3075 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 3076 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
screamer 28:0e774865873d 3077 #define CAN_RDL0R_DATA1_Pos (8U)
screamer 28:0e774865873d 3078 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3079 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
screamer 28:0e774865873d 3080 #define CAN_RDL0R_DATA2_Pos (16U)
screamer 28:0e774865873d 3081 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 3082 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
screamer 28:0e774865873d 3083 #define CAN_RDL0R_DATA3_Pos (24U)
screamer 28:0e774865873d 3084 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 3085 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
screamer 28:0e774865873d 3086
screamer 28:0e774865873d 3087 /******************* Bit definition for CAN_RDH0R register ******************/
screamer 28:0e774865873d 3088 #define CAN_RDH0R_DATA4_Pos (0U)
screamer 28:0e774865873d 3089 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 3090 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
screamer 28:0e774865873d 3091 #define CAN_RDH0R_DATA5_Pos (8U)
screamer 28:0e774865873d 3092 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3093 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
screamer 28:0e774865873d 3094 #define CAN_RDH0R_DATA6_Pos (16U)
screamer 28:0e774865873d 3095 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 3096 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
screamer 28:0e774865873d 3097 #define CAN_RDH0R_DATA7_Pos (24U)
screamer 28:0e774865873d 3098 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 3099 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
screamer 28:0e774865873d 3100
screamer 28:0e774865873d 3101 /******************* Bit definition for CAN_RI1R register *******************/
screamer 28:0e774865873d 3102 #define CAN_RI1R_RTR_Pos (1U)
screamer 28:0e774865873d 3103 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3104 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
screamer 28:0e774865873d 3105 #define CAN_RI1R_IDE_Pos (2U)
screamer 28:0e774865873d 3106 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3107 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
screamer 28:0e774865873d 3108 #define CAN_RI1R_EXID_Pos (3U)
screamer 28:0e774865873d 3109 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
screamer 28:0e774865873d 3110 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
screamer 28:0e774865873d 3111 #define CAN_RI1R_STID_Pos (21U)
screamer 28:0e774865873d 3112 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
screamer 28:0e774865873d 3113 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
screamer 28:0e774865873d 3114
screamer 28:0e774865873d 3115 /******************* Bit definition for CAN_RDT1R register ******************/
screamer 28:0e774865873d 3116 #define CAN_RDT1R_DLC_Pos (0U)
screamer 28:0e774865873d 3117 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 3118 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
screamer 28:0e774865873d 3119 #define CAN_RDT1R_FMI_Pos (8U)
screamer 28:0e774865873d 3120 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3121 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
screamer 28:0e774865873d 3122 #define CAN_RDT1R_TIME_Pos (16U)
screamer 28:0e774865873d 3123 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 3124 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
screamer 28:0e774865873d 3125
screamer 28:0e774865873d 3126 /******************* Bit definition for CAN_RDL1R register ******************/
screamer 28:0e774865873d 3127 #define CAN_RDL1R_DATA0_Pos (0U)
screamer 28:0e774865873d 3128 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 3129 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
screamer 28:0e774865873d 3130 #define CAN_RDL1R_DATA1_Pos (8U)
screamer 28:0e774865873d 3131 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3132 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
screamer 28:0e774865873d 3133 #define CAN_RDL1R_DATA2_Pos (16U)
screamer 28:0e774865873d 3134 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 3135 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
screamer 28:0e774865873d 3136 #define CAN_RDL1R_DATA3_Pos (24U)
screamer 28:0e774865873d 3137 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 3138 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
screamer 28:0e774865873d 3139
screamer 28:0e774865873d 3140 /******************* Bit definition for CAN_RDH1R register ******************/
screamer 28:0e774865873d 3141 #define CAN_RDH1R_DATA4_Pos (0U)
screamer 28:0e774865873d 3142 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 3143 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
screamer 28:0e774865873d 3144 #define CAN_RDH1R_DATA5_Pos (8U)
screamer 28:0e774865873d 3145 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 3146 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
screamer 28:0e774865873d 3147 #define CAN_RDH1R_DATA6_Pos (16U)
screamer 28:0e774865873d 3148 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 3149 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
screamer 28:0e774865873d 3150 #define CAN_RDH1R_DATA7_Pos (24U)
screamer 28:0e774865873d 3151 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 3152 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
screamer 28:0e774865873d 3153
screamer 28:0e774865873d 3154 /*!<CAN filter registers */
screamer 28:0e774865873d 3155 /******************* Bit definition for CAN_FMR register ********************/
screamer 28:0e774865873d 3156 #define CAN_FMR_FINIT_Pos (0U)
screamer 28:0e774865873d 3157 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3158 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
screamer 28:0e774865873d 3159
screamer 28:0e774865873d 3160 /******************* Bit definition for CAN_FM1R register *******************/
screamer 28:0e774865873d 3161 #define CAN_FM1R_FBM_Pos (0U)
screamer 28:0e774865873d 3162 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
screamer 28:0e774865873d 3163 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
screamer 28:0e774865873d 3164 #define CAN_FM1R_FBM0_Pos (0U)
screamer 28:0e774865873d 3165 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3166 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
screamer 28:0e774865873d 3167 #define CAN_FM1R_FBM1_Pos (1U)
screamer 28:0e774865873d 3168 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3169 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
screamer 28:0e774865873d 3170 #define CAN_FM1R_FBM2_Pos (2U)
screamer 28:0e774865873d 3171 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3172 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
screamer 28:0e774865873d 3173 #define CAN_FM1R_FBM3_Pos (3U)
screamer 28:0e774865873d 3174 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3175 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
screamer 28:0e774865873d 3176 #define CAN_FM1R_FBM4_Pos (4U)
screamer 28:0e774865873d 3177 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3178 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
screamer 28:0e774865873d 3179 #define CAN_FM1R_FBM5_Pos (5U)
screamer 28:0e774865873d 3180 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3181 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
screamer 28:0e774865873d 3182 #define CAN_FM1R_FBM6_Pos (6U)
screamer 28:0e774865873d 3183 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3184 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
screamer 28:0e774865873d 3185 #define CAN_FM1R_FBM7_Pos (7U)
screamer 28:0e774865873d 3186 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3187 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
screamer 28:0e774865873d 3188 #define CAN_FM1R_FBM8_Pos (8U)
screamer 28:0e774865873d 3189 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3190 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
screamer 28:0e774865873d 3191 #define CAN_FM1R_FBM9_Pos (9U)
screamer 28:0e774865873d 3192 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3193 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
screamer 28:0e774865873d 3194 #define CAN_FM1R_FBM10_Pos (10U)
screamer 28:0e774865873d 3195 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3196 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
screamer 28:0e774865873d 3197 #define CAN_FM1R_FBM11_Pos (11U)
screamer 28:0e774865873d 3198 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3199 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
screamer 28:0e774865873d 3200 #define CAN_FM1R_FBM12_Pos (12U)
screamer 28:0e774865873d 3201 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3202 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
screamer 28:0e774865873d 3203 #define CAN_FM1R_FBM13_Pos (13U)
screamer 28:0e774865873d 3204 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3205 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
screamer 28:0e774865873d 3206
screamer 28:0e774865873d 3207 /******************* Bit definition for CAN_FS1R register *******************/
screamer 28:0e774865873d 3208 #define CAN_FS1R_FSC_Pos (0U)
screamer 28:0e774865873d 3209 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
screamer 28:0e774865873d 3210 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
screamer 28:0e774865873d 3211 #define CAN_FS1R_FSC0_Pos (0U)
screamer 28:0e774865873d 3212 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3213 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
screamer 28:0e774865873d 3214 #define CAN_FS1R_FSC1_Pos (1U)
screamer 28:0e774865873d 3215 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3216 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
screamer 28:0e774865873d 3217 #define CAN_FS1R_FSC2_Pos (2U)
screamer 28:0e774865873d 3218 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3219 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
screamer 28:0e774865873d 3220 #define CAN_FS1R_FSC3_Pos (3U)
screamer 28:0e774865873d 3221 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3222 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
screamer 28:0e774865873d 3223 #define CAN_FS1R_FSC4_Pos (4U)
screamer 28:0e774865873d 3224 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3225 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
screamer 28:0e774865873d 3226 #define CAN_FS1R_FSC5_Pos (5U)
screamer 28:0e774865873d 3227 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3228 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
screamer 28:0e774865873d 3229 #define CAN_FS1R_FSC6_Pos (6U)
screamer 28:0e774865873d 3230 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3231 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
screamer 28:0e774865873d 3232 #define CAN_FS1R_FSC7_Pos (7U)
screamer 28:0e774865873d 3233 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3234 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
screamer 28:0e774865873d 3235 #define CAN_FS1R_FSC8_Pos (8U)
screamer 28:0e774865873d 3236 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3237 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
screamer 28:0e774865873d 3238 #define CAN_FS1R_FSC9_Pos (9U)
screamer 28:0e774865873d 3239 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3240 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
screamer 28:0e774865873d 3241 #define CAN_FS1R_FSC10_Pos (10U)
screamer 28:0e774865873d 3242 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3243 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
screamer 28:0e774865873d 3244 #define CAN_FS1R_FSC11_Pos (11U)
screamer 28:0e774865873d 3245 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3246 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
screamer 28:0e774865873d 3247 #define CAN_FS1R_FSC12_Pos (12U)
screamer 28:0e774865873d 3248 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3249 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
screamer 28:0e774865873d 3250 #define CAN_FS1R_FSC13_Pos (13U)
screamer 28:0e774865873d 3251 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3252 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
screamer 28:0e774865873d 3253
screamer 28:0e774865873d 3254 /****************** Bit definition for CAN_FFA1R register *******************/
screamer 28:0e774865873d 3255 #define CAN_FFA1R_FFA_Pos (0U)
screamer 28:0e774865873d 3256 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
screamer 28:0e774865873d 3257 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
screamer 28:0e774865873d 3258 #define CAN_FFA1R_FFA0_Pos (0U)
screamer 28:0e774865873d 3259 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3260 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
screamer 28:0e774865873d 3261 #define CAN_FFA1R_FFA1_Pos (1U)
screamer 28:0e774865873d 3262 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3263 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
screamer 28:0e774865873d 3264 #define CAN_FFA1R_FFA2_Pos (2U)
screamer 28:0e774865873d 3265 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3266 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
screamer 28:0e774865873d 3267 #define CAN_FFA1R_FFA3_Pos (3U)
screamer 28:0e774865873d 3268 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3269 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
screamer 28:0e774865873d 3270 #define CAN_FFA1R_FFA4_Pos (4U)
screamer 28:0e774865873d 3271 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3272 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
screamer 28:0e774865873d 3273 #define CAN_FFA1R_FFA5_Pos (5U)
screamer 28:0e774865873d 3274 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3275 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
screamer 28:0e774865873d 3276 #define CAN_FFA1R_FFA6_Pos (6U)
screamer 28:0e774865873d 3277 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3278 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
screamer 28:0e774865873d 3279 #define CAN_FFA1R_FFA7_Pos (7U)
screamer 28:0e774865873d 3280 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3281 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
screamer 28:0e774865873d 3282 #define CAN_FFA1R_FFA8_Pos (8U)
screamer 28:0e774865873d 3283 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3284 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
screamer 28:0e774865873d 3285 #define CAN_FFA1R_FFA9_Pos (9U)
screamer 28:0e774865873d 3286 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3287 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
screamer 28:0e774865873d 3288 #define CAN_FFA1R_FFA10_Pos (10U)
screamer 28:0e774865873d 3289 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3290 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
screamer 28:0e774865873d 3291 #define CAN_FFA1R_FFA11_Pos (11U)
screamer 28:0e774865873d 3292 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3293 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
screamer 28:0e774865873d 3294 #define CAN_FFA1R_FFA12_Pos (12U)
screamer 28:0e774865873d 3295 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3296 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
screamer 28:0e774865873d 3297 #define CAN_FFA1R_FFA13_Pos (13U)
screamer 28:0e774865873d 3298 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3299 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
screamer 28:0e774865873d 3300
screamer 28:0e774865873d 3301 /******************* Bit definition for CAN_FA1R register *******************/
screamer 28:0e774865873d 3302 #define CAN_FA1R_FACT_Pos (0U)
screamer 28:0e774865873d 3303 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
screamer 28:0e774865873d 3304 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
screamer 28:0e774865873d 3305 #define CAN_FA1R_FACT0_Pos (0U)
screamer 28:0e774865873d 3306 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3307 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
screamer 28:0e774865873d 3308 #define CAN_FA1R_FACT1_Pos (1U)
screamer 28:0e774865873d 3309 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3310 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
screamer 28:0e774865873d 3311 #define CAN_FA1R_FACT2_Pos (2U)
screamer 28:0e774865873d 3312 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3313 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
screamer 28:0e774865873d 3314 #define CAN_FA1R_FACT3_Pos (3U)
screamer 28:0e774865873d 3315 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3316 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
screamer 28:0e774865873d 3317 #define CAN_FA1R_FACT4_Pos (4U)
screamer 28:0e774865873d 3318 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3319 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
screamer 28:0e774865873d 3320 #define CAN_FA1R_FACT5_Pos (5U)
screamer 28:0e774865873d 3321 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3322 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
screamer 28:0e774865873d 3323 #define CAN_FA1R_FACT6_Pos (6U)
screamer 28:0e774865873d 3324 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3325 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
screamer 28:0e774865873d 3326 #define CAN_FA1R_FACT7_Pos (7U)
screamer 28:0e774865873d 3327 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3328 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
screamer 28:0e774865873d 3329 #define CAN_FA1R_FACT8_Pos (8U)
screamer 28:0e774865873d 3330 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3331 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
screamer 28:0e774865873d 3332 #define CAN_FA1R_FACT9_Pos (9U)
screamer 28:0e774865873d 3333 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3334 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
screamer 28:0e774865873d 3335 #define CAN_FA1R_FACT10_Pos (10U)
screamer 28:0e774865873d 3336 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3337 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
screamer 28:0e774865873d 3338 #define CAN_FA1R_FACT11_Pos (11U)
screamer 28:0e774865873d 3339 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3340 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
screamer 28:0e774865873d 3341 #define CAN_FA1R_FACT12_Pos (12U)
screamer 28:0e774865873d 3342 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3343 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
screamer 28:0e774865873d 3344 #define CAN_FA1R_FACT13_Pos (13U)
screamer 28:0e774865873d 3345 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3346 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
screamer 28:0e774865873d 3347
screamer 28:0e774865873d 3348 /******************* Bit definition for CAN_F0R1 register *******************/
screamer 28:0e774865873d 3349 #define CAN_F0R1_FB0_Pos (0U)
screamer 28:0e774865873d 3350 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3351 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3352 #define CAN_F0R1_FB1_Pos (1U)
screamer 28:0e774865873d 3353 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3354 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3355 #define CAN_F0R1_FB2_Pos (2U)
screamer 28:0e774865873d 3356 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3357 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3358 #define CAN_F0R1_FB3_Pos (3U)
screamer 28:0e774865873d 3359 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3360 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3361 #define CAN_F0R1_FB4_Pos (4U)
screamer 28:0e774865873d 3362 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3363 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3364 #define CAN_F0R1_FB5_Pos (5U)
screamer 28:0e774865873d 3365 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3366 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3367 #define CAN_F0R1_FB6_Pos (6U)
screamer 28:0e774865873d 3368 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3369 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3370 #define CAN_F0R1_FB7_Pos (7U)
screamer 28:0e774865873d 3371 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3372 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3373 #define CAN_F0R1_FB8_Pos (8U)
screamer 28:0e774865873d 3374 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3375 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3376 #define CAN_F0R1_FB9_Pos (9U)
screamer 28:0e774865873d 3377 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3378 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3379 #define CAN_F0R1_FB10_Pos (10U)
screamer 28:0e774865873d 3380 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3381 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3382 #define CAN_F0R1_FB11_Pos (11U)
screamer 28:0e774865873d 3383 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3384 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3385 #define CAN_F0R1_FB12_Pos (12U)
screamer 28:0e774865873d 3386 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3387 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3388 #define CAN_F0R1_FB13_Pos (13U)
screamer 28:0e774865873d 3389 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3390 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3391 #define CAN_F0R1_FB14_Pos (14U)
screamer 28:0e774865873d 3392 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3393 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3394 #define CAN_F0R1_FB15_Pos (15U)
screamer 28:0e774865873d 3395 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3396 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3397 #define CAN_F0R1_FB16_Pos (16U)
screamer 28:0e774865873d 3398 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3399 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3400 #define CAN_F0R1_FB17_Pos (17U)
screamer 28:0e774865873d 3401 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3402 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3403 #define CAN_F0R1_FB18_Pos (18U)
screamer 28:0e774865873d 3404 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3405 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3406 #define CAN_F0R1_FB19_Pos (19U)
screamer 28:0e774865873d 3407 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3408 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3409 #define CAN_F0R1_FB20_Pos (20U)
screamer 28:0e774865873d 3410 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3411 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 3412 #define CAN_F0R1_FB21_Pos (21U)
screamer 28:0e774865873d 3413 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 3414 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 3415 #define CAN_F0R1_FB22_Pos (22U)
screamer 28:0e774865873d 3416 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 3417 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 3418 #define CAN_F0R1_FB23_Pos (23U)
screamer 28:0e774865873d 3419 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 3420 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 3421 #define CAN_F0R1_FB24_Pos (24U)
screamer 28:0e774865873d 3422 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 3423 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 3424 #define CAN_F0R1_FB25_Pos (25U)
screamer 28:0e774865873d 3425 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 3426 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 3427 #define CAN_F0R1_FB26_Pos (26U)
screamer 28:0e774865873d 3428 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 3429 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 3430 #define CAN_F0R1_FB27_Pos (27U)
screamer 28:0e774865873d 3431 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 3432 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 3433 #define CAN_F0R1_FB28_Pos (28U)
screamer 28:0e774865873d 3434 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 3435 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 3436 #define CAN_F0R1_FB29_Pos (29U)
screamer 28:0e774865873d 3437 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 3438 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 3439 #define CAN_F0R1_FB30_Pos (30U)
screamer 28:0e774865873d 3440 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 3441 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 3442 #define CAN_F0R1_FB31_Pos (31U)
screamer 28:0e774865873d 3443 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 3444 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 3445
screamer 28:0e774865873d 3446 /******************* Bit definition for CAN_F1R1 register *******************/
screamer 28:0e774865873d 3447 #define CAN_F1R1_FB0_Pos (0U)
screamer 28:0e774865873d 3448 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3449 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3450 #define CAN_F1R1_FB1_Pos (1U)
screamer 28:0e774865873d 3451 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3452 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3453 #define CAN_F1R1_FB2_Pos (2U)
screamer 28:0e774865873d 3454 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3455 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3456 #define CAN_F1R1_FB3_Pos (3U)
screamer 28:0e774865873d 3457 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3458 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3459 #define CAN_F1R1_FB4_Pos (4U)
screamer 28:0e774865873d 3460 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3461 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3462 #define CAN_F1R1_FB5_Pos (5U)
screamer 28:0e774865873d 3463 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3464 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3465 #define CAN_F1R1_FB6_Pos (6U)
screamer 28:0e774865873d 3466 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3467 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3468 #define CAN_F1R1_FB7_Pos (7U)
screamer 28:0e774865873d 3469 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3470 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3471 #define CAN_F1R1_FB8_Pos (8U)
screamer 28:0e774865873d 3472 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3473 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3474 #define CAN_F1R1_FB9_Pos (9U)
screamer 28:0e774865873d 3475 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3476 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3477 #define CAN_F1R1_FB10_Pos (10U)
screamer 28:0e774865873d 3478 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3479 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3480 #define CAN_F1R1_FB11_Pos (11U)
screamer 28:0e774865873d 3481 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3482 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3483 #define CAN_F1R1_FB12_Pos (12U)
screamer 28:0e774865873d 3484 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3485 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3486 #define CAN_F1R1_FB13_Pos (13U)
screamer 28:0e774865873d 3487 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3488 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3489 #define CAN_F1R1_FB14_Pos (14U)
screamer 28:0e774865873d 3490 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3491 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3492 #define CAN_F1R1_FB15_Pos (15U)
screamer 28:0e774865873d 3493 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3494 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3495 #define CAN_F1R1_FB16_Pos (16U)
screamer 28:0e774865873d 3496 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3497 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3498 #define CAN_F1R1_FB17_Pos (17U)
screamer 28:0e774865873d 3499 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3500 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3501 #define CAN_F1R1_FB18_Pos (18U)
screamer 28:0e774865873d 3502 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3503 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3504 #define CAN_F1R1_FB19_Pos (19U)
screamer 28:0e774865873d 3505 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3506 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3507 #define CAN_F1R1_FB20_Pos (20U)
screamer 28:0e774865873d 3508 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3509 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 3510 #define CAN_F1R1_FB21_Pos (21U)
screamer 28:0e774865873d 3511 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 3512 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 3513 #define CAN_F1R1_FB22_Pos (22U)
screamer 28:0e774865873d 3514 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 3515 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 3516 #define CAN_F1R1_FB23_Pos (23U)
screamer 28:0e774865873d 3517 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 3518 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 3519 #define CAN_F1R1_FB24_Pos (24U)
screamer 28:0e774865873d 3520 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 3521 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 3522 #define CAN_F1R1_FB25_Pos (25U)
screamer 28:0e774865873d 3523 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 3524 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 3525 #define CAN_F1R1_FB26_Pos (26U)
screamer 28:0e774865873d 3526 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 3527 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 3528 #define CAN_F1R1_FB27_Pos (27U)
screamer 28:0e774865873d 3529 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 3530 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 3531 #define CAN_F1R1_FB28_Pos (28U)
screamer 28:0e774865873d 3532 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 3533 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 3534 #define CAN_F1R1_FB29_Pos (29U)
screamer 28:0e774865873d 3535 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 3536 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 3537 #define CAN_F1R1_FB30_Pos (30U)
screamer 28:0e774865873d 3538 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 3539 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 3540 #define CAN_F1R1_FB31_Pos (31U)
screamer 28:0e774865873d 3541 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 3542 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 3543
screamer 28:0e774865873d 3544 /******************* Bit definition for CAN_F2R1 register *******************/
screamer 28:0e774865873d 3545 #define CAN_F2R1_FB0_Pos (0U)
screamer 28:0e774865873d 3546 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3547 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3548 #define CAN_F2R1_FB1_Pos (1U)
screamer 28:0e774865873d 3549 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3550 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3551 #define CAN_F2R1_FB2_Pos (2U)
screamer 28:0e774865873d 3552 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3553 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3554 #define CAN_F2R1_FB3_Pos (3U)
screamer 28:0e774865873d 3555 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3556 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3557 #define CAN_F2R1_FB4_Pos (4U)
screamer 28:0e774865873d 3558 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3559 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3560 #define CAN_F2R1_FB5_Pos (5U)
screamer 28:0e774865873d 3561 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3562 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3563 #define CAN_F2R1_FB6_Pos (6U)
screamer 28:0e774865873d 3564 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3565 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3566 #define CAN_F2R1_FB7_Pos (7U)
screamer 28:0e774865873d 3567 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3568 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3569 #define CAN_F2R1_FB8_Pos (8U)
screamer 28:0e774865873d 3570 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3571 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3572 #define CAN_F2R1_FB9_Pos (9U)
screamer 28:0e774865873d 3573 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3574 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3575 #define CAN_F2R1_FB10_Pos (10U)
screamer 28:0e774865873d 3576 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3577 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3578 #define CAN_F2R1_FB11_Pos (11U)
screamer 28:0e774865873d 3579 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3580 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3581 #define CAN_F2R1_FB12_Pos (12U)
screamer 28:0e774865873d 3582 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3583 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3584 #define CAN_F2R1_FB13_Pos (13U)
screamer 28:0e774865873d 3585 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3586 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3587 #define CAN_F2R1_FB14_Pos (14U)
screamer 28:0e774865873d 3588 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3589 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3590 #define CAN_F2R1_FB15_Pos (15U)
screamer 28:0e774865873d 3591 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3592 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3593 #define CAN_F2R1_FB16_Pos (16U)
screamer 28:0e774865873d 3594 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3595 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3596 #define CAN_F2R1_FB17_Pos (17U)
screamer 28:0e774865873d 3597 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3598 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3599 #define CAN_F2R1_FB18_Pos (18U)
screamer 28:0e774865873d 3600 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3601 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3602 #define CAN_F2R1_FB19_Pos (19U)
screamer 28:0e774865873d 3603 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3604 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3605 #define CAN_F2R1_FB20_Pos (20U)
screamer 28:0e774865873d 3606 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3607 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 3608 #define CAN_F2R1_FB21_Pos (21U)
screamer 28:0e774865873d 3609 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 3610 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 3611 #define CAN_F2R1_FB22_Pos (22U)
screamer 28:0e774865873d 3612 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 3613 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 3614 #define CAN_F2R1_FB23_Pos (23U)
screamer 28:0e774865873d 3615 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 3616 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 3617 #define CAN_F2R1_FB24_Pos (24U)
screamer 28:0e774865873d 3618 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 3619 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 3620 #define CAN_F2R1_FB25_Pos (25U)
screamer 28:0e774865873d 3621 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 3622 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 3623 #define CAN_F2R1_FB26_Pos (26U)
screamer 28:0e774865873d 3624 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 3625 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 3626 #define CAN_F2R1_FB27_Pos (27U)
screamer 28:0e774865873d 3627 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 3628 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 3629 #define CAN_F2R1_FB28_Pos (28U)
screamer 28:0e774865873d 3630 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 3631 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 3632 #define CAN_F2R1_FB29_Pos (29U)
screamer 28:0e774865873d 3633 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 3634 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 3635 #define CAN_F2R1_FB30_Pos (30U)
screamer 28:0e774865873d 3636 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 3637 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 3638 #define CAN_F2R1_FB31_Pos (31U)
screamer 28:0e774865873d 3639 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 3640 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 3641
screamer 28:0e774865873d 3642 /******************* Bit definition for CAN_F3R1 register *******************/
screamer 28:0e774865873d 3643 #define CAN_F3R1_FB0_Pos (0U)
screamer 28:0e774865873d 3644 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3645 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3646 #define CAN_F3R1_FB1_Pos (1U)
screamer 28:0e774865873d 3647 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3648 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3649 #define CAN_F3R1_FB2_Pos (2U)
screamer 28:0e774865873d 3650 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3651 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3652 #define CAN_F3R1_FB3_Pos (3U)
screamer 28:0e774865873d 3653 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3654 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3655 #define CAN_F3R1_FB4_Pos (4U)
screamer 28:0e774865873d 3656 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3657 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3658 #define CAN_F3R1_FB5_Pos (5U)
screamer 28:0e774865873d 3659 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3660 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3661 #define CAN_F3R1_FB6_Pos (6U)
screamer 28:0e774865873d 3662 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3663 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3664 #define CAN_F3R1_FB7_Pos (7U)
screamer 28:0e774865873d 3665 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3666 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3667 #define CAN_F3R1_FB8_Pos (8U)
screamer 28:0e774865873d 3668 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3669 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3670 #define CAN_F3R1_FB9_Pos (9U)
screamer 28:0e774865873d 3671 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3672 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3673 #define CAN_F3R1_FB10_Pos (10U)
screamer 28:0e774865873d 3674 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3675 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3676 #define CAN_F3R1_FB11_Pos (11U)
screamer 28:0e774865873d 3677 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3678 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3679 #define CAN_F3R1_FB12_Pos (12U)
screamer 28:0e774865873d 3680 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3681 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3682 #define CAN_F3R1_FB13_Pos (13U)
screamer 28:0e774865873d 3683 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3684 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3685 #define CAN_F3R1_FB14_Pos (14U)
screamer 28:0e774865873d 3686 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3687 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3688 #define CAN_F3R1_FB15_Pos (15U)
screamer 28:0e774865873d 3689 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3690 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3691 #define CAN_F3R1_FB16_Pos (16U)
screamer 28:0e774865873d 3692 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3693 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3694 #define CAN_F3R1_FB17_Pos (17U)
screamer 28:0e774865873d 3695 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3696 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3697 #define CAN_F3R1_FB18_Pos (18U)
screamer 28:0e774865873d 3698 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3699 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3700 #define CAN_F3R1_FB19_Pos (19U)
screamer 28:0e774865873d 3701 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3702 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3703 #define CAN_F3R1_FB20_Pos (20U)
screamer 28:0e774865873d 3704 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3705 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 3706 #define CAN_F3R1_FB21_Pos (21U)
screamer 28:0e774865873d 3707 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 3708 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 3709 #define CAN_F3R1_FB22_Pos (22U)
screamer 28:0e774865873d 3710 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 3711 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 3712 #define CAN_F3R1_FB23_Pos (23U)
screamer 28:0e774865873d 3713 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 3714 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 3715 #define CAN_F3R1_FB24_Pos (24U)
screamer 28:0e774865873d 3716 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 3717 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 3718 #define CAN_F3R1_FB25_Pos (25U)
screamer 28:0e774865873d 3719 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 3720 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 3721 #define CAN_F3R1_FB26_Pos (26U)
screamer 28:0e774865873d 3722 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 3723 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 3724 #define CAN_F3R1_FB27_Pos (27U)
screamer 28:0e774865873d 3725 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 3726 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 3727 #define CAN_F3R1_FB28_Pos (28U)
screamer 28:0e774865873d 3728 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 3729 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 3730 #define CAN_F3R1_FB29_Pos (29U)
screamer 28:0e774865873d 3731 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 3732 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 3733 #define CAN_F3R1_FB30_Pos (30U)
screamer 28:0e774865873d 3734 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 3735 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 3736 #define CAN_F3R1_FB31_Pos (31U)
screamer 28:0e774865873d 3737 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 3738 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 3739
screamer 28:0e774865873d 3740 /******************* Bit definition for CAN_F4R1 register *******************/
screamer 28:0e774865873d 3741 #define CAN_F4R1_FB0_Pos (0U)
screamer 28:0e774865873d 3742 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3743 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3744 #define CAN_F4R1_FB1_Pos (1U)
screamer 28:0e774865873d 3745 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3746 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3747 #define CAN_F4R1_FB2_Pos (2U)
screamer 28:0e774865873d 3748 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3749 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3750 #define CAN_F4R1_FB3_Pos (3U)
screamer 28:0e774865873d 3751 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3752 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3753 #define CAN_F4R1_FB4_Pos (4U)
screamer 28:0e774865873d 3754 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3755 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3756 #define CAN_F4R1_FB5_Pos (5U)
screamer 28:0e774865873d 3757 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3758 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3759 #define CAN_F4R1_FB6_Pos (6U)
screamer 28:0e774865873d 3760 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3761 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3762 #define CAN_F4R1_FB7_Pos (7U)
screamer 28:0e774865873d 3763 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3764 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3765 #define CAN_F4R1_FB8_Pos (8U)
screamer 28:0e774865873d 3766 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3767 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3768 #define CAN_F4R1_FB9_Pos (9U)
screamer 28:0e774865873d 3769 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3770 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3771 #define CAN_F4R1_FB10_Pos (10U)
screamer 28:0e774865873d 3772 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3773 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3774 #define CAN_F4R1_FB11_Pos (11U)
screamer 28:0e774865873d 3775 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3776 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3777 #define CAN_F4R1_FB12_Pos (12U)
screamer 28:0e774865873d 3778 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3779 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3780 #define CAN_F4R1_FB13_Pos (13U)
screamer 28:0e774865873d 3781 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3782 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3783 #define CAN_F4R1_FB14_Pos (14U)
screamer 28:0e774865873d 3784 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3785 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3786 #define CAN_F4R1_FB15_Pos (15U)
screamer 28:0e774865873d 3787 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3788 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3789 #define CAN_F4R1_FB16_Pos (16U)
screamer 28:0e774865873d 3790 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3791 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3792 #define CAN_F4R1_FB17_Pos (17U)
screamer 28:0e774865873d 3793 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3794 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3795 #define CAN_F4R1_FB18_Pos (18U)
screamer 28:0e774865873d 3796 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3797 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3798 #define CAN_F4R1_FB19_Pos (19U)
screamer 28:0e774865873d 3799 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3800 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3801 #define CAN_F4R1_FB20_Pos (20U)
screamer 28:0e774865873d 3802 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3803 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 3804 #define CAN_F4R1_FB21_Pos (21U)
screamer 28:0e774865873d 3805 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 3806 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 3807 #define CAN_F4R1_FB22_Pos (22U)
screamer 28:0e774865873d 3808 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 3809 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 3810 #define CAN_F4R1_FB23_Pos (23U)
screamer 28:0e774865873d 3811 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 3812 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 3813 #define CAN_F4R1_FB24_Pos (24U)
screamer 28:0e774865873d 3814 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 3815 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 3816 #define CAN_F4R1_FB25_Pos (25U)
screamer 28:0e774865873d 3817 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 3818 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 3819 #define CAN_F4R1_FB26_Pos (26U)
screamer 28:0e774865873d 3820 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 3821 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 3822 #define CAN_F4R1_FB27_Pos (27U)
screamer 28:0e774865873d 3823 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 3824 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 3825 #define CAN_F4R1_FB28_Pos (28U)
screamer 28:0e774865873d 3826 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 3827 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 3828 #define CAN_F4R1_FB29_Pos (29U)
screamer 28:0e774865873d 3829 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 3830 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 3831 #define CAN_F4R1_FB30_Pos (30U)
screamer 28:0e774865873d 3832 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 3833 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 3834 #define CAN_F4R1_FB31_Pos (31U)
screamer 28:0e774865873d 3835 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 3836 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 3837
screamer 28:0e774865873d 3838 /******************* Bit definition for CAN_F5R1 register *******************/
screamer 28:0e774865873d 3839 #define CAN_F5R1_FB0_Pos (0U)
screamer 28:0e774865873d 3840 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3841 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3842 #define CAN_F5R1_FB1_Pos (1U)
screamer 28:0e774865873d 3843 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3844 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3845 #define CAN_F5R1_FB2_Pos (2U)
screamer 28:0e774865873d 3846 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3847 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3848 #define CAN_F5R1_FB3_Pos (3U)
screamer 28:0e774865873d 3849 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3850 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3851 #define CAN_F5R1_FB4_Pos (4U)
screamer 28:0e774865873d 3852 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3853 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3854 #define CAN_F5R1_FB5_Pos (5U)
screamer 28:0e774865873d 3855 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3856 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3857 #define CAN_F5R1_FB6_Pos (6U)
screamer 28:0e774865873d 3858 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3859 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3860 #define CAN_F5R1_FB7_Pos (7U)
screamer 28:0e774865873d 3861 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3862 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3863 #define CAN_F5R1_FB8_Pos (8U)
screamer 28:0e774865873d 3864 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3865 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3866 #define CAN_F5R1_FB9_Pos (9U)
screamer 28:0e774865873d 3867 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3868 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3869 #define CAN_F5R1_FB10_Pos (10U)
screamer 28:0e774865873d 3870 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3871 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3872 #define CAN_F5R1_FB11_Pos (11U)
screamer 28:0e774865873d 3873 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3874 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3875 #define CAN_F5R1_FB12_Pos (12U)
screamer 28:0e774865873d 3876 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3877 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3878 #define CAN_F5R1_FB13_Pos (13U)
screamer 28:0e774865873d 3879 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3880 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3881 #define CAN_F5R1_FB14_Pos (14U)
screamer 28:0e774865873d 3882 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3883 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3884 #define CAN_F5R1_FB15_Pos (15U)
screamer 28:0e774865873d 3885 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3886 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3887 #define CAN_F5R1_FB16_Pos (16U)
screamer 28:0e774865873d 3888 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3889 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3890 #define CAN_F5R1_FB17_Pos (17U)
screamer 28:0e774865873d 3891 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3892 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3893 #define CAN_F5R1_FB18_Pos (18U)
screamer 28:0e774865873d 3894 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3895 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3896 #define CAN_F5R1_FB19_Pos (19U)
screamer 28:0e774865873d 3897 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3898 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3899 #define CAN_F5R1_FB20_Pos (20U)
screamer 28:0e774865873d 3900 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3901 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 3902 #define CAN_F5R1_FB21_Pos (21U)
screamer 28:0e774865873d 3903 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 3904 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 3905 #define CAN_F5R1_FB22_Pos (22U)
screamer 28:0e774865873d 3906 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 3907 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 3908 #define CAN_F5R1_FB23_Pos (23U)
screamer 28:0e774865873d 3909 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 3910 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 3911 #define CAN_F5R1_FB24_Pos (24U)
screamer 28:0e774865873d 3912 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 3913 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 3914 #define CAN_F5R1_FB25_Pos (25U)
screamer 28:0e774865873d 3915 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 3916 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 3917 #define CAN_F5R1_FB26_Pos (26U)
screamer 28:0e774865873d 3918 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 3919 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 3920 #define CAN_F5R1_FB27_Pos (27U)
screamer 28:0e774865873d 3921 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 3922 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 3923 #define CAN_F5R1_FB28_Pos (28U)
screamer 28:0e774865873d 3924 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 3925 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 3926 #define CAN_F5R1_FB29_Pos (29U)
screamer 28:0e774865873d 3927 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 3928 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 3929 #define CAN_F5R1_FB30_Pos (30U)
screamer 28:0e774865873d 3930 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 3931 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 3932 #define CAN_F5R1_FB31_Pos (31U)
screamer 28:0e774865873d 3933 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 3934 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 3935
screamer 28:0e774865873d 3936 /******************* Bit definition for CAN_F6R1 register *******************/
screamer 28:0e774865873d 3937 #define CAN_F6R1_FB0_Pos (0U)
screamer 28:0e774865873d 3938 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 3939 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 3940 #define CAN_F6R1_FB1_Pos (1U)
screamer 28:0e774865873d 3941 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 3942 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 3943 #define CAN_F6R1_FB2_Pos (2U)
screamer 28:0e774865873d 3944 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 3945 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 3946 #define CAN_F6R1_FB3_Pos (3U)
screamer 28:0e774865873d 3947 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 3948 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 3949 #define CAN_F6R1_FB4_Pos (4U)
screamer 28:0e774865873d 3950 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 3951 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 3952 #define CAN_F6R1_FB5_Pos (5U)
screamer 28:0e774865873d 3953 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 3954 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 3955 #define CAN_F6R1_FB6_Pos (6U)
screamer 28:0e774865873d 3956 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 3957 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 3958 #define CAN_F6R1_FB7_Pos (7U)
screamer 28:0e774865873d 3959 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 3960 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 3961 #define CAN_F6R1_FB8_Pos (8U)
screamer 28:0e774865873d 3962 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 3963 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 3964 #define CAN_F6R1_FB9_Pos (9U)
screamer 28:0e774865873d 3965 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 3966 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 3967 #define CAN_F6R1_FB10_Pos (10U)
screamer 28:0e774865873d 3968 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 3969 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 3970 #define CAN_F6R1_FB11_Pos (11U)
screamer 28:0e774865873d 3971 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 3972 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 3973 #define CAN_F6R1_FB12_Pos (12U)
screamer 28:0e774865873d 3974 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 3975 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 3976 #define CAN_F6R1_FB13_Pos (13U)
screamer 28:0e774865873d 3977 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 3978 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 3979 #define CAN_F6R1_FB14_Pos (14U)
screamer 28:0e774865873d 3980 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 3981 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 3982 #define CAN_F6R1_FB15_Pos (15U)
screamer 28:0e774865873d 3983 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 3984 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 3985 #define CAN_F6R1_FB16_Pos (16U)
screamer 28:0e774865873d 3986 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 3987 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 3988 #define CAN_F6R1_FB17_Pos (17U)
screamer 28:0e774865873d 3989 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 3990 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 3991 #define CAN_F6R1_FB18_Pos (18U)
screamer 28:0e774865873d 3992 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 3993 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 3994 #define CAN_F6R1_FB19_Pos (19U)
screamer 28:0e774865873d 3995 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 3996 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 3997 #define CAN_F6R1_FB20_Pos (20U)
screamer 28:0e774865873d 3998 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 3999 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4000 #define CAN_F6R1_FB21_Pos (21U)
screamer 28:0e774865873d 4001 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4002 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4003 #define CAN_F6R1_FB22_Pos (22U)
screamer 28:0e774865873d 4004 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4005 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4006 #define CAN_F6R1_FB23_Pos (23U)
screamer 28:0e774865873d 4007 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4008 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4009 #define CAN_F6R1_FB24_Pos (24U)
screamer 28:0e774865873d 4010 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4011 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4012 #define CAN_F6R1_FB25_Pos (25U)
screamer 28:0e774865873d 4013 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4014 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4015 #define CAN_F6R1_FB26_Pos (26U)
screamer 28:0e774865873d 4016 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4017 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4018 #define CAN_F6R1_FB27_Pos (27U)
screamer 28:0e774865873d 4019 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4020 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4021 #define CAN_F6R1_FB28_Pos (28U)
screamer 28:0e774865873d 4022 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4023 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4024 #define CAN_F6R1_FB29_Pos (29U)
screamer 28:0e774865873d 4025 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4026 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4027 #define CAN_F6R1_FB30_Pos (30U)
screamer 28:0e774865873d 4028 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4029 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4030 #define CAN_F6R1_FB31_Pos (31U)
screamer 28:0e774865873d 4031 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4032 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4033
screamer 28:0e774865873d 4034 /******************* Bit definition for CAN_F7R1 register *******************/
screamer 28:0e774865873d 4035 #define CAN_F7R1_FB0_Pos (0U)
screamer 28:0e774865873d 4036 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4037 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4038 #define CAN_F7R1_FB1_Pos (1U)
screamer 28:0e774865873d 4039 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4040 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4041 #define CAN_F7R1_FB2_Pos (2U)
screamer 28:0e774865873d 4042 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4043 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4044 #define CAN_F7R1_FB3_Pos (3U)
screamer 28:0e774865873d 4045 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4046 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4047 #define CAN_F7R1_FB4_Pos (4U)
screamer 28:0e774865873d 4048 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4049 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4050 #define CAN_F7R1_FB5_Pos (5U)
screamer 28:0e774865873d 4051 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4052 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4053 #define CAN_F7R1_FB6_Pos (6U)
screamer 28:0e774865873d 4054 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4055 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4056 #define CAN_F7R1_FB7_Pos (7U)
screamer 28:0e774865873d 4057 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4058 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4059 #define CAN_F7R1_FB8_Pos (8U)
screamer 28:0e774865873d 4060 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4061 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4062 #define CAN_F7R1_FB9_Pos (9U)
screamer 28:0e774865873d 4063 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4064 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4065 #define CAN_F7R1_FB10_Pos (10U)
screamer 28:0e774865873d 4066 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4067 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4068 #define CAN_F7R1_FB11_Pos (11U)
screamer 28:0e774865873d 4069 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4070 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4071 #define CAN_F7R1_FB12_Pos (12U)
screamer 28:0e774865873d 4072 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4073 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4074 #define CAN_F7R1_FB13_Pos (13U)
screamer 28:0e774865873d 4075 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4076 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4077 #define CAN_F7R1_FB14_Pos (14U)
screamer 28:0e774865873d 4078 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4079 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4080 #define CAN_F7R1_FB15_Pos (15U)
screamer 28:0e774865873d 4081 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4082 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4083 #define CAN_F7R1_FB16_Pos (16U)
screamer 28:0e774865873d 4084 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4085 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4086 #define CAN_F7R1_FB17_Pos (17U)
screamer 28:0e774865873d 4087 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4088 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4089 #define CAN_F7R1_FB18_Pos (18U)
screamer 28:0e774865873d 4090 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4091 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4092 #define CAN_F7R1_FB19_Pos (19U)
screamer 28:0e774865873d 4093 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4094 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4095 #define CAN_F7R1_FB20_Pos (20U)
screamer 28:0e774865873d 4096 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4097 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4098 #define CAN_F7R1_FB21_Pos (21U)
screamer 28:0e774865873d 4099 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4100 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4101 #define CAN_F7R1_FB22_Pos (22U)
screamer 28:0e774865873d 4102 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4103 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4104 #define CAN_F7R1_FB23_Pos (23U)
screamer 28:0e774865873d 4105 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4106 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4107 #define CAN_F7R1_FB24_Pos (24U)
screamer 28:0e774865873d 4108 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4109 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4110 #define CAN_F7R1_FB25_Pos (25U)
screamer 28:0e774865873d 4111 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4112 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4113 #define CAN_F7R1_FB26_Pos (26U)
screamer 28:0e774865873d 4114 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4115 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4116 #define CAN_F7R1_FB27_Pos (27U)
screamer 28:0e774865873d 4117 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4118 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4119 #define CAN_F7R1_FB28_Pos (28U)
screamer 28:0e774865873d 4120 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4121 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4122 #define CAN_F7R1_FB29_Pos (29U)
screamer 28:0e774865873d 4123 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4124 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4125 #define CAN_F7R1_FB30_Pos (30U)
screamer 28:0e774865873d 4126 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4127 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4128 #define CAN_F7R1_FB31_Pos (31U)
screamer 28:0e774865873d 4129 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4130 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4131
screamer 28:0e774865873d 4132 /******************* Bit definition for CAN_F8R1 register *******************/
screamer 28:0e774865873d 4133 #define CAN_F8R1_FB0_Pos (0U)
screamer 28:0e774865873d 4134 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4135 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4136 #define CAN_F8R1_FB1_Pos (1U)
screamer 28:0e774865873d 4137 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4138 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4139 #define CAN_F8R1_FB2_Pos (2U)
screamer 28:0e774865873d 4140 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4141 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4142 #define CAN_F8R1_FB3_Pos (3U)
screamer 28:0e774865873d 4143 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4144 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4145 #define CAN_F8R1_FB4_Pos (4U)
screamer 28:0e774865873d 4146 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4147 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4148 #define CAN_F8R1_FB5_Pos (5U)
screamer 28:0e774865873d 4149 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4150 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4151 #define CAN_F8R1_FB6_Pos (6U)
screamer 28:0e774865873d 4152 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4153 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4154 #define CAN_F8R1_FB7_Pos (7U)
screamer 28:0e774865873d 4155 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4156 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4157 #define CAN_F8R1_FB8_Pos (8U)
screamer 28:0e774865873d 4158 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4159 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4160 #define CAN_F8R1_FB9_Pos (9U)
screamer 28:0e774865873d 4161 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4162 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4163 #define CAN_F8R1_FB10_Pos (10U)
screamer 28:0e774865873d 4164 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4165 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4166 #define CAN_F8R1_FB11_Pos (11U)
screamer 28:0e774865873d 4167 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4168 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4169 #define CAN_F8R1_FB12_Pos (12U)
screamer 28:0e774865873d 4170 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4171 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4172 #define CAN_F8R1_FB13_Pos (13U)
screamer 28:0e774865873d 4173 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4174 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4175 #define CAN_F8R1_FB14_Pos (14U)
screamer 28:0e774865873d 4176 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4177 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4178 #define CAN_F8R1_FB15_Pos (15U)
screamer 28:0e774865873d 4179 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4180 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4181 #define CAN_F8R1_FB16_Pos (16U)
screamer 28:0e774865873d 4182 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4183 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4184 #define CAN_F8R1_FB17_Pos (17U)
screamer 28:0e774865873d 4185 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4186 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4187 #define CAN_F8R1_FB18_Pos (18U)
screamer 28:0e774865873d 4188 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4189 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4190 #define CAN_F8R1_FB19_Pos (19U)
screamer 28:0e774865873d 4191 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4192 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4193 #define CAN_F8R1_FB20_Pos (20U)
screamer 28:0e774865873d 4194 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4195 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4196 #define CAN_F8R1_FB21_Pos (21U)
screamer 28:0e774865873d 4197 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4198 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4199 #define CAN_F8R1_FB22_Pos (22U)
screamer 28:0e774865873d 4200 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4201 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4202 #define CAN_F8R1_FB23_Pos (23U)
screamer 28:0e774865873d 4203 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4204 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4205 #define CAN_F8R1_FB24_Pos (24U)
screamer 28:0e774865873d 4206 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4207 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4208 #define CAN_F8R1_FB25_Pos (25U)
screamer 28:0e774865873d 4209 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4210 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4211 #define CAN_F8R1_FB26_Pos (26U)
screamer 28:0e774865873d 4212 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4213 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4214 #define CAN_F8R1_FB27_Pos (27U)
screamer 28:0e774865873d 4215 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4216 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4217 #define CAN_F8R1_FB28_Pos (28U)
screamer 28:0e774865873d 4218 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4219 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4220 #define CAN_F8R1_FB29_Pos (29U)
screamer 28:0e774865873d 4221 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4222 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4223 #define CAN_F8R1_FB30_Pos (30U)
screamer 28:0e774865873d 4224 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4225 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4226 #define CAN_F8R1_FB31_Pos (31U)
screamer 28:0e774865873d 4227 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4228 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4229
screamer 28:0e774865873d 4230 /******************* Bit definition for CAN_F9R1 register *******************/
screamer 28:0e774865873d 4231 #define CAN_F9R1_FB0_Pos (0U)
screamer 28:0e774865873d 4232 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4233 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4234 #define CAN_F9R1_FB1_Pos (1U)
screamer 28:0e774865873d 4235 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4236 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4237 #define CAN_F9R1_FB2_Pos (2U)
screamer 28:0e774865873d 4238 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4239 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4240 #define CAN_F9R1_FB3_Pos (3U)
screamer 28:0e774865873d 4241 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4242 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4243 #define CAN_F9R1_FB4_Pos (4U)
screamer 28:0e774865873d 4244 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4245 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4246 #define CAN_F9R1_FB5_Pos (5U)
screamer 28:0e774865873d 4247 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4248 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4249 #define CAN_F9R1_FB6_Pos (6U)
screamer 28:0e774865873d 4250 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4251 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4252 #define CAN_F9R1_FB7_Pos (7U)
screamer 28:0e774865873d 4253 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4254 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4255 #define CAN_F9R1_FB8_Pos (8U)
screamer 28:0e774865873d 4256 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4257 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4258 #define CAN_F9R1_FB9_Pos (9U)
screamer 28:0e774865873d 4259 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4260 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4261 #define CAN_F9R1_FB10_Pos (10U)
screamer 28:0e774865873d 4262 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4263 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4264 #define CAN_F9R1_FB11_Pos (11U)
screamer 28:0e774865873d 4265 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4266 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4267 #define CAN_F9R1_FB12_Pos (12U)
screamer 28:0e774865873d 4268 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4269 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4270 #define CAN_F9R1_FB13_Pos (13U)
screamer 28:0e774865873d 4271 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4272 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4273 #define CAN_F9R1_FB14_Pos (14U)
screamer 28:0e774865873d 4274 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4275 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4276 #define CAN_F9R1_FB15_Pos (15U)
screamer 28:0e774865873d 4277 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4278 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4279 #define CAN_F9R1_FB16_Pos (16U)
screamer 28:0e774865873d 4280 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4281 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4282 #define CAN_F9R1_FB17_Pos (17U)
screamer 28:0e774865873d 4283 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4284 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4285 #define CAN_F9R1_FB18_Pos (18U)
screamer 28:0e774865873d 4286 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4287 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4288 #define CAN_F9R1_FB19_Pos (19U)
screamer 28:0e774865873d 4289 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4290 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4291 #define CAN_F9R1_FB20_Pos (20U)
screamer 28:0e774865873d 4292 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4293 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4294 #define CAN_F9R1_FB21_Pos (21U)
screamer 28:0e774865873d 4295 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4296 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4297 #define CAN_F9R1_FB22_Pos (22U)
screamer 28:0e774865873d 4298 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4299 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4300 #define CAN_F9R1_FB23_Pos (23U)
screamer 28:0e774865873d 4301 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4302 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4303 #define CAN_F9R1_FB24_Pos (24U)
screamer 28:0e774865873d 4304 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4305 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4306 #define CAN_F9R1_FB25_Pos (25U)
screamer 28:0e774865873d 4307 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4308 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4309 #define CAN_F9R1_FB26_Pos (26U)
screamer 28:0e774865873d 4310 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4311 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4312 #define CAN_F9R1_FB27_Pos (27U)
screamer 28:0e774865873d 4313 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4314 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4315 #define CAN_F9R1_FB28_Pos (28U)
screamer 28:0e774865873d 4316 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4317 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4318 #define CAN_F9R1_FB29_Pos (29U)
screamer 28:0e774865873d 4319 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4320 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4321 #define CAN_F9R1_FB30_Pos (30U)
screamer 28:0e774865873d 4322 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4323 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4324 #define CAN_F9R1_FB31_Pos (31U)
screamer 28:0e774865873d 4325 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4326 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4327
screamer 28:0e774865873d 4328 /******************* Bit definition for CAN_F10R1 register ******************/
screamer 28:0e774865873d 4329 #define CAN_F10R1_FB0_Pos (0U)
screamer 28:0e774865873d 4330 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4331 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4332 #define CAN_F10R1_FB1_Pos (1U)
screamer 28:0e774865873d 4333 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4334 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4335 #define CAN_F10R1_FB2_Pos (2U)
screamer 28:0e774865873d 4336 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4337 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4338 #define CAN_F10R1_FB3_Pos (3U)
screamer 28:0e774865873d 4339 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4340 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4341 #define CAN_F10R1_FB4_Pos (4U)
screamer 28:0e774865873d 4342 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4343 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4344 #define CAN_F10R1_FB5_Pos (5U)
screamer 28:0e774865873d 4345 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4346 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4347 #define CAN_F10R1_FB6_Pos (6U)
screamer 28:0e774865873d 4348 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4349 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4350 #define CAN_F10R1_FB7_Pos (7U)
screamer 28:0e774865873d 4351 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4352 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4353 #define CAN_F10R1_FB8_Pos (8U)
screamer 28:0e774865873d 4354 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4355 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4356 #define CAN_F10R1_FB9_Pos (9U)
screamer 28:0e774865873d 4357 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4358 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4359 #define CAN_F10R1_FB10_Pos (10U)
screamer 28:0e774865873d 4360 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4361 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4362 #define CAN_F10R1_FB11_Pos (11U)
screamer 28:0e774865873d 4363 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4364 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4365 #define CAN_F10R1_FB12_Pos (12U)
screamer 28:0e774865873d 4366 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4367 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4368 #define CAN_F10R1_FB13_Pos (13U)
screamer 28:0e774865873d 4369 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4370 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4371 #define CAN_F10R1_FB14_Pos (14U)
screamer 28:0e774865873d 4372 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4373 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4374 #define CAN_F10R1_FB15_Pos (15U)
screamer 28:0e774865873d 4375 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4376 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4377 #define CAN_F10R1_FB16_Pos (16U)
screamer 28:0e774865873d 4378 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4379 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4380 #define CAN_F10R1_FB17_Pos (17U)
screamer 28:0e774865873d 4381 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4382 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4383 #define CAN_F10R1_FB18_Pos (18U)
screamer 28:0e774865873d 4384 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4385 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4386 #define CAN_F10R1_FB19_Pos (19U)
screamer 28:0e774865873d 4387 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4388 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4389 #define CAN_F10R1_FB20_Pos (20U)
screamer 28:0e774865873d 4390 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4391 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4392 #define CAN_F10R1_FB21_Pos (21U)
screamer 28:0e774865873d 4393 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4394 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4395 #define CAN_F10R1_FB22_Pos (22U)
screamer 28:0e774865873d 4396 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4397 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4398 #define CAN_F10R1_FB23_Pos (23U)
screamer 28:0e774865873d 4399 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4400 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4401 #define CAN_F10R1_FB24_Pos (24U)
screamer 28:0e774865873d 4402 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4403 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4404 #define CAN_F10R1_FB25_Pos (25U)
screamer 28:0e774865873d 4405 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4406 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4407 #define CAN_F10R1_FB26_Pos (26U)
screamer 28:0e774865873d 4408 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4409 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4410 #define CAN_F10R1_FB27_Pos (27U)
screamer 28:0e774865873d 4411 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4412 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4413 #define CAN_F10R1_FB28_Pos (28U)
screamer 28:0e774865873d 4414 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4415 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4416 #define CAN_F10R1_FB29_Pos (29U)
screamer 28:0e774865873d 4417 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4418 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4419 #define CAN_F10R1_FB30_Pos (30U)
screamer 28:0e774865873d 4420 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4421 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4422 #define CAN_F10R1_FB31_Pos (31U)
screamer 28:0e774865873d 4423 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4424 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4425
screamer 28:0e774865873d 4426 /******************* Bit definition for CAN_F11R1 register ******************/
screamer 28:0e774865873d 4427 #define CAN_F11R1_FB0_Pos (0U)
screamer 28:0e774865873d 4428 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4429 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4430 #define CAN_F11R1_FB1_Pos (1U)
screamer 28:0e774865873d 4431 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4432 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4433 #define CAN_F11R1_FB2_Pos (2U)
screamer 28:0e774865873d 4434 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4435 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4436 #define CAN_F11R1_FB3_Pos (3U)
screamer 28:0e774865873d 4437 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4438 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4439 #define CAN_F11R1_FB4_Pos (4U)
screamer 28:0e774865873d 4440 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4441 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4442 #define CAN_F11R1_FB5_Pos (5U)
screamer 28:0e774865873d 4443 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4444 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4445 #define CAN_F11R1_FB6_Pos (6U)
screamer 28:0e774865873d 4446 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4447 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4448 #define CAN_F11R1_FB7_Pos (7U)
screamer 28:0e774865873d 4449 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4450 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4451 #define CAN_F11R1_FB8_Pos (8U)
screamer 28:0e774865873d 4452 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4453 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4454 #define CAN_F11R1_FB9_Pos (9U)
screamer 28:0e774865873d 4455 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4456 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4457 #define CAN_F11R1_FB10_Pos (10U)
screamer 28:0e774865873d 4458 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4459 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4460 #define CAN_F11R1_FB11_Pos (11U)
screamer 28:0e774865873d 4461 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4462 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4463 #define CAN_F11R1_FB12_Pos (12U)
screamer 28:0e774865873d 4464 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4465 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4466 #define CAN_F11R1_FB13_Pos (13U)
screamer 28:0e774865873d 4467 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4468 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4469 #define CAN_F11R1_FB14_Pos (14U)
screamer 28:0e774865873d 4470 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4471 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4472 #define CAN_F11R1_FB15_Pos (15U)
screamer 28:0e774865873d 4473 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4474 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4475 #define CAN_F11R1_FB16_Pos (16U)
screamer 28:0e774865873d 4476 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4477 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4478 #define CAN_F11R1_FB17_Pos (17U)
screamer 28:0e774865873d 4479 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4480 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4481 #define CAN_F11R1_FB18_Pos (18U)
screamer 28:0e774865873d 4482 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4483 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4484 #define CAN_F11R1_FB19_Pos (19U)
screamer 28:0e774865873d 4485 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4486 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4487 #define CAN_F11R1_FB20_Pos (20U)
screamer 28:0e774865873d 4488 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4489 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4490 #define CAN_F11R1_FB21_Pos (21U)
screamer 28:0e774865873d 4491 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4492 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4493 #define CAN_F11R1_FB22_Pos (22U)
screamer 28:0e774865873d 4494 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4495 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4496 #define CAN_F11R1_FB23_Pos (23U)
screamer 28:0e774865873d 4497 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4498 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4499 #define CAN_F11R1_FB24_Pos (24U)
screamer 28:0e774865873d 4500 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4501 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4502 #define CAN_F11R1_FB25_Pos (25U)
screamer 28:0e774865873d 4503 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4504 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4505 #define CAN_F11R1_FB26_Pos (26U)
screamer 28:0e774865873d 4506 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4507 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4508 #define CAN_F11R1_FB27_Pos (27U)
screamer 28:0e774865873d 4509 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4510 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4511 #define CAN_F11R1_FB28_Pos (28U)
screamer 28:0e774865873d 4512 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4513 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4514 #define CAN_F11R1_FB29_Pos (29U)
screamer 28:0e774865873d 4515 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4516 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4517 #define CAN_F11R1_FB30_Pos (30U)
screamer 28:0e774865873d 4518 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4519 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4520 #define CAN_F11R1_FB31_Pos (31U)
screamer 28:0e774865873d 4521 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4522 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4523
screamer 28:0e774865873d 4524 /******************* Bit definition for CAN_F12R1 register ******************/
screamer 28:0e774865873d 4525 #define CAN_F12R1_FB0_Pos (0U)
screamer 28:0e774865873d 4526 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4527 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4528 #define CAN_F12R1_FB1_Pos (1U)
screamer 28:0e774865873d 4529 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4530 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4531 #define CAN_F12R1_FB2_Pos (2U)
screamer 28:0e774865873d 4532 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4533 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4534 #define CAN_F12R1_FB3_Pos (3U)
screamer 28:0e774865873d 4535 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4536 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4537 #define CAN_F12R1_FB4_Pos (4U)
screamer 28:0e774865873d 4538 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4539 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4540 #define CAN_F12R1_FB5_Pos (5U)
screamer 28:0e774865873d 4541 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4542 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4543 #define CAN_F12R1_FB6_Pos (6U)
screamer 28:0e774865873d 4544 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4545 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4546 #define CAN_F12R1_FB7_Pos (7U)
screamer 28:0e774865873d 4547 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4548 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4549 #define CAN_F12R1_FB8_Pos (8U)
screamer 28:0e774865873d 4550 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4551 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4552 #define CAN_F12R1_FB9_Pos (9U)
screamer 28:0e774865873d 4553 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4554 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4555 #define CAN_F12R1_FB10_Pos (10U)
screamer 28:0e774865873d 4556 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4557 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4558 #define CAN_F12R1_FB11_Pos (11U)
screamer 28:0e774865873d 4559 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4560 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4561 #define CAN_F12R1_FB12_Pos (12U)
screamer 28:0e774865873d 4562 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4563 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4564 #define CAN_F12R1_FB13_Pos (13U)
screamer 28:0e774865873d 4565 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4566 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4567 #define CAN_F12R1_FB14_Pos (14U)
screamer 28:0e774865873d 4568 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4569 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4570 #define CAN_F12R1_FB15_Pos (15U)
screamer 28:0e774865873d 4571 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4572 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4573 #define CAN_F12R1_FB16_Pos (16U)
screamer 28:0e774865873d 4574 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4575 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4576 #define CAN_F12R1_FB17_Pos (17U)
screamer 28:0e774865873d 4577 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4578 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4579 #define CAN_F12R1_FB18_Pos (18U)
screamer 28:0e774865873d 4580 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4581 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4582 #define CAN_F12R1_FB19_Pos (19U)
screamer 28:0e774865873d 4583 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4584 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4585 #define CAN_F12R1_FB20_Pos (20U)
screamer 28:0e774865873d 4586 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4587 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4588 #define CAN_F12R1_FB21_Pos (21U)
screamer 28:0e774865873d 4589 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4590 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4591 #define CAN_F12R1_FB22_Pos (22U)
screamer 28:0e774865873d 4592 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4593 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4594 #define CAN_F12R1_FB23_Pos (23U)
screamer 28:0e774865873d 4595 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4596 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4597 #define CAN_F12R1_FB24_Pos (24U)
screamer 28:0e774865873d 4598 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4599 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4600 #define CAN_F12R1_FB25_Pos (25U)
screamer 28:0e774865873d 4601 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4602 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4603 #define CAN_F12R1_FB26_Pos (26U)
screamer 28:0e774865873d 4604 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4605 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4606 #define CAN_F12R1_FB27_Pos (27U)
screamer 28:0e774865873d 4607 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4608 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4609 #define CAN_F12R1_FB28_Pos (28U)
screamer 28:0e774865873d 4610 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4611 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4612 #define CAN_F12R1_FB29_Pos (29U)
screamer 28:0e774865873d 4613 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4614 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4615 #define CAN_F12R1_FB30_Pos (30U)
screamer 28:0e774865873d 4616 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4617 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4618 #define CAN_F12R1_FB31_Pos (31U)
screamer 28:0e774865873d 4619 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4620 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4621
screamer 28:0e774865873d 4622 /******************* Bit definition for CAN_F13R1 register ******************/
screamer 28:0e774865873d 4623 #define CAN_F13R1_FB0_Pos (0U)
screamer 28:0e774865873d 4624 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4625 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4626 #define CAN_F13R1_FB1_Pos (1U)
screamer 28:0e774865873d 4627 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4628 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4629 #define CAN_F13R1_FB2_Pos (2U)
screamer 28:0e774865873d 4630 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4631 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4632 #define CAN_F13R1_FB3_Pos (3U)
screamer 28:0e774865873d 4633 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4634 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4635 #define CAN_F13R1_FB4_Pos (4U)
screamer 28:0e774865873d 4636 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4637 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4638 #define CAN_F13R1_FB5_Pos (5U)
screamer 28:0e774865873d 4639 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4640 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4641 #define CAN_F13R1_FB6_Pos (6U)
screamer 28:0e774865873d 4642 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4643 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4644 #define CAN_F13R1_FB7_Pos (7U)
screamer 28:0e774865873d 4645 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4646 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4647 #define CAN_F13R1_FB8_Pos (8U)
screamer 28:0e774865873d 4648 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4649 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4650 #define CAN_F13R1_FB9_Pos (9U)
screamer 28:0e774865873d 4651 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4652 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4653 #define CAN_F13R1_FB10_Pos (10U)
screamer 28:0e774865873d 4654 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4655 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4656 #define CAN_F13R1_FB11_Pos (11U)
screamer 28:0e774865873d 4657 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4658 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4659 #define CAN_F13R1_FB12_Pos (12U)
screamer 28:0e774865873d 4660 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4661 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4662 #define CAN_F13R1_FB13_Pos (13U)
screamer 28:0e774865873d 4663 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4664 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4665 #define CAN_F13R1_FB14_Pos (14U)
screamer 28:0e774865873d 4666 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4667 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4668 #define CAN_F13R1_FB15_Pos (15U)
screamer 28:0e774865873d 4669 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4670 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4671 #define CAN_F13R1_FB16_Pos (16U)
screamer 28:0e774865873d 4672 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4673 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4674 #define CAN_F13R1_FB17_Pos (17U)
screamer 28:0e774865873d 4675 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4676 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4677 #define CAN_F13R1_FB18_Pos (18U)
screamer 28:0e774865873d 4678 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4679 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4680 #define CAN_F13R1_FB19_Pos (19U)
screamer 28:0e774865873d 4681 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4682 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4683 #define CAN_F13R1_FB20_Pos (20U)
screamer 28:0e774865873d 4684 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4685 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4686 #define CAN_F13R1_FB21_Pos (21U)
screamer 28:0e774865873d 4687 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4688 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4689 #define CAN_F13R1_FB22_Pos (22U)
screamer 28:0e774865873d 4690 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4691 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4692 #define CAN_F13R1_FB23_Pos (23U)
screamer 28:0e774865873d 4693 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4694 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4695 #define CAN_F13R1_FB24_Pos (24U)
screamer 28:0e774865873d 4696 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4697 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4698 #define CAN_F13R1_FB25_Pos (25U)
screamer 28:0e774865873d 4699 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4700 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4701 #define CAN_F13R1_FB26_Pos (26U)
screamer 28:0e774865873d 4702 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4703 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4704 #define CAN_F13R1_FB27_Pos (27U)
screamer 28:0e774865873d 4705 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4706 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4707 #define CAN_F13R1_FB28_Pos (28U)
screamer 28:0e774865873d 4708 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4709 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4710 #define CAN_F13R1_FB29_Pos (29U)
screamer 28:0e774865873d 4711 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4712 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4713 #define CAN_F13R1_FB30_Pos (30U)
screamer 28:0e774865873d 4714 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4715 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4716 #define CAN_F13R1_FB31_Pos (31U)
screamer 28:0e774865873d 4717 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4718 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4719
screamer 28:0e774865873d 4720 /******************* Bit definition for CAN_F0R2 register *******************/
screamer 28:0e774865873d 4721 #define CAN_F0R2_FB0_Pos (0U)
screamer 28:0e774865873d 4722 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4723 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4724 #define CAN_F0R2_FB1_Pos (1U)
screamer 28:0e774865873d 4725 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4726 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4727 #define CAN_F0R2_FB2_Pos (2U)
screamer 28:0e774865873d 4728 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4729 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4730 #define CAN_F0R2_FB3_Pos (3U)
screamer 28:0e774865873d 4731 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4732 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4733 #define CAN_F0R2_FB4_Pos (4U)
screamer 28:0e774865873d 4734 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4735 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4736 #define CAN_F0R2_FB5_Pos (5U)
screamer 28:0e774865873d 4737 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4738 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4739 #define CAN_F0R2_FB6_Pos (6U)
screamer 28:0e774865873d 4740 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4741 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4742 #define CAN_F0R2_FB7_Pos (7U)
screamer 28:0e774865873d 4743 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4744 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4745 #define CAN_F0R2_FB8_Pos (8U)
screamer 28:0e774865873d 4746 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4747 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4748 #define CAN_F0R2_FB9_Pos (9U)
screamer 28:0e774865873d 4749 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4750 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4751 #define CAN_F0R2_FB10_Pos (10U)
screamer 28:0e774865873d 4752 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4753 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4754 #define CAN_F0R2_FB11_Pos (11U)
screamer 28:0e774865873d 4755 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4756 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4757 #define CAN_F0R2_FB12_Pos (12U)
screamer 28:0e774865873d 4758 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4759 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4760 #define CAN_F0R2_FB13_Pos (13U)
screamer 28:0e774865873d 4761 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4762 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4763 #define CAN_F0R2_FB14_Pos (14U)
screamer 28:0e774865873d 4764 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4765 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4766 #define CAN_F0R2_FB15_Pos (15U)
screamer 28:0e774865873d 4767 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4768 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4769 #define CAN_F0R2_FB16_Pos (16U)
screamer 28:0e774865873d 4770 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4771 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4772 #define CAN_F0R2_FB17_Pos (17U)
screamer 28:0e774865873d 4773 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4774 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4775 #define CAN_F0R2_FB18_Pos (18U)
screamer 28:0e774865873d 4776 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4777 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4778 #define CAN_F0R2_FB19_Pos (19U)
screamer 28:0e774865873d 4779 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4780 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4781 #define CAN_F0R2_FB20_Pos (20U)
screamer 28:0e774865873d 4782 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4783 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4784 #define CAN_F0R2_FB21_Pos (21U)
screamer 28:0e774865873d 4785 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4786 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4787 #define CAN_F0R2_FB22_Pos (22U)
screamer 28:0e774865873d 4788 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4789 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4790 #define CAN_F0R2_FB23_Pos (23U)
screamer 28:0e774865873d 4791 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4792 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4793 #define CAN_F0R2_FB24_Pos (24U)
screamer 28:0e774865873d 4794 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4795 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4796 #define CAN_F0R2_FB25_Pos (25U)
screamer 28:0e774865873d 4797 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4798 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4799 #define CAN_F0R2_FB26_Pos (26U)
screamer 28:0e774865873d 4800 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4801 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4802 #define CAN_F0R2_FB27_Pos (27U)
screamer 28:0e774865873d 4803 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4804 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4805 #define CAN_F0R2_FB28_Pos (28U)
screamer 28:0e774865873d 4806 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4807 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4808 #define CAN_F0R2_FB29_Pos (29U)
screamer 28:0e774865873d 4809 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4810 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4811 #define CAN_F0R2_FB30_Pos (30U)
screamer 28:0e774865873d 4812 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4813 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4814 #define CAN_F0R2_FB31_Pos (31U)
screamer 28:0e774865873d 4815 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4816 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4817
screamer 28:0e774865873d 4818 /******************* Bit definition for CAN_F1R2 register *******************/
screamer 28:0e774865873d 4819 #define CAN_F1R2_FB0_Pos (0U)
screamer 28:0e774865873d 4820 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4821 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4822 #define CAN_F1R2_FB1_Pos (1U)
screamer 28:0e774865873d 4823 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4824 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4825 #define CAN_F1R2_FB2_Pos (2U)
screamer 28:0e774865873d 4826 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4827 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4828 #define CAN_F1R2_FB3_Pos (3U)
screamer 28:0e774865873d 4829 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4830 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4831 #define CAN_F1R2_FB4_Pos (4U)
screamer 28:0e774865873d 4832 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4833 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4834 #define CAN_F1R2_FB5_Pos (5U)
screamer 28:0e774865873d 4835 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4836 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4837 #define CAN_F1R2_FB6_Pos (6U)
screamer 28:0e774865873d 4838 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4839 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4840 #define CAN_F1R2_FB7_Pos (7U)
screamer 28:0e774865873d 4841 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4842 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4843 #define CAN_F1R2_FB8_Pos (8U)
screamer 28:0e774865873d 4844 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4845 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4846 #define CAN_F1R2_FB9_Pos (9U)
screamer 28:0e774865873d 4847 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4848 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4849 #define CAN_F1R2_FB10_Pos (10U)
screamer 28:0e774865873d 4850 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4851 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4852 #define CAN_F1R2_FB11_Pos (11U)
screamer 28:0e774865873d 4853 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4854 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4855 #define CAN_F1R2_FB12_Pos (12U)
screamer 28:0e774865873d 4856 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4857 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4858 #define CAN_F1R2_FB13_Pos (13U)
screamer 28:0e774865873d 4859 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4860 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4861 #define CAN_F1R2_FB14_Pos (14U)
screamer 28:0e774865873d 4862 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4863 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4864 #define CAN_F1R2_FB15_Pos (15U)
screamer 28:0e774865873d 4865 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4866 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4867 #define CAN_F1R2_FB16_Pos (16U)
screamer 28:0e774865873d 4868 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4869 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4870 #define CAN_F1R2_FB17_Pos (17U)
screamer 28:0e774865873d 4871 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4872 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4873 #define CAN_F1R2_FB18_Pos (18U)
screamer 28:0e774865873d 4874 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4875 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4876 #define CAN_F1R2_FB19_Pos (19U)
screamer 28:0e774865873d 4877 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4878 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4879 #define CAN_F1R2_FB20_Pos (20U)
screamer 28:0e774865873d 4880 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4881 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4882 #define CAN_F1R2_FB21_Pos (21U)
screamer 28:0e774865873d 4883 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4884 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4885 #define CAN_F1R2_FB22_Pos (22U)
screamer 28:0e774865873d 4886 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4887 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4888 #define CAN_F1R2_FB23_Pos (23U)
screamer 28:0e774865873d 4889 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4890 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4891 #define CAN_F1R2_FB24_Pos (24U)
screamer 28:0e774865873d 4892 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4893 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4894 #define CAN_F1R2_FB25_Pos (25U)
screamer 28:0e774865873d 4895 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4896 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4897 #define CAN_F1R2_FB26_Pos (26U)
screamer 28:0e774865873d 4898 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4899 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4900 #define CAN_F1R2_FB27_Pos (27U)
screamer 28:0e774865873d 4901 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 4902 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 4903 #define CAN_F1R2_FB28_Pos (28U)
screamer 28:0e774865873d 4904 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 4905 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 4906 #define CAN_F1R2_FB29_Pos (29U)
screamer 28:0e774865873d 4907 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 4908 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 4909 #define CAN_F1R2_FB30_Pos (30U)
screamer 28:0e774865873d 4910 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 4911 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 4912 #define CAN_F1R2_FB31_Pos (31U)
screamer 28:0e774865873d 4913 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 4914 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 4915
screamer 28:0e774865873d 4916 /******************* Bit definition for CAN_F2R2 register *******************/
screamer 28:0e774865873d 4917 #define CAN_F2R2_FB0_Pos (0U)
screamer 28:0e774865873d 4918 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 4919 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 4920 #define CAN_F2R2_FB1_Pos (1U)
screamer 28:0e774865873d 4921 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 4922 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 4923 #define CAN_F2R2_FB2_Pos (2U)
screamer 28:0e774865873d 4924 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 4925 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 4926 #define CAN_F2R2_FB3_Pos (3U)
screamer 28:0e774865873d 4927 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 4928 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 4929 #define CAN_F2R2_FB4_Pos (4U)
screamer 28:0e774865873d 4930 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 4931 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 4932 #define CAN_F2R2_FB5_Pos (5U)
screamer 28:0e774865873d 4933 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 4934 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 4935 #define CAN_F2R2_FB6_Pos (6U)
screamer 28:0e774865873d 4936 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 4937 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 4938 #define CAN_F2R2_FB7_Pos (7U)
screamer 28:0e774865873d 4939 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 4940 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 4941 #define CAN_F2R2_FB8_Pos (8U)
screamer 28:0e774865873d 4942 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 4943 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 4944 #define CAN_F2R2_FB9_Pos (9U)
screamer 28:0e774865873d 4945 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 4946 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 4947 #define CAN_F2R2_FB10_Pos (10U)
screamer 28:0e774865873d 4948 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 4949 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 4950 #define CAN_F2R2_FB11_Pos (11U)
screamer 28:0e774865873d 4951 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 4952 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 4953 #define CAN_F2R2_FB12_Pos (12U)
screamer 28:0e774865873d 4954 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 4955 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 4956 #define CAN_F2R2_FB13_Pos (13U)
screamer 28:0e774865873d 4957 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 4958 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 4959 #define CAN_F2R2_FB14_Pos (14U)
screamer 28:0e774865873d 4960 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 4961 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 4962 #define CAN_F2R2_FB15_Pos (15U)
screamer 28:0e774865873d 4963 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 4964 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 4965 #define CAN_F2R2_FB16_Pos (16U)
screamer 28:0e774865873d 4966 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 4967 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 4968 #define CAN_F2R2_FB17_Pos (17U)
screamer 28:0e774865873d 4969 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 4970 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 4971 #define CAN_F2R2_FB18_Pos (18U)
screamer 28:0e774865873d 4972 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 4973 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 4974 #define CAN_F2R2_FB19_Pos (19U)
screamer 28:0e774865873d 4975 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 4976 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 4977 #define CAN_F2R2_FB20_Pos (20U)
screamer 28:0e774865873d 4978 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 4979 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 4980 #define CAN_F2R2_FB21_Pos (21U)
screamer 28:0e774865873d 4981 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 4982 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 4983 #define CAN_F2R2_FB22_Pos (22U)
screamer 28:0e774865873d 4984 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 4985 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 4986 #define CAN_F2R2_FB23_Pos (23U)
screamer 28:0e774865873d 4987 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 4988 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 4989 #define CAN_F2R2_FB24_Pos (24U)
screamer 28:0e774865873d 4990 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 4991 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 4992 #define CAN_F2R2_FB25_Pos (25U)
screamer 28:0e774865873d 4993 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 4994 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 4995 #define CAN_F2R2_FB26_Pos (26U)
screamer 28:0e774865873d 4996 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 4997 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 4998 #define CAN_F2R2_FB27_Pos (27U)
screamer 28:0e774865873d 4999 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5000 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5001 #define CAN_F2R2_FB28_Pos (28U)
screamer 28:0e774865873d 5002 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5003 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5004 #define CAN_F2R2_FB29_Pos (29U)
screamer 28:0e774865873d 5005 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5006 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5007 #define CAN_F2R2_FB30_Pos (30U)
screamer 28:0e774865873d 5008 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5009 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5010 #define CAN_F2R2_FB31_Pos (31U)
screamer 28:0e774865873d 5011 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5012 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5013
screamer 28:0e774865873d 5014 /******************* Bit definition for CAN_F3R2 register *******************/
screamer 28:0e774865873d 5015 #define CAN_F3R2_FB0_Pos (0U)
screamer 28:0e774865873d 5016 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5017 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5018 #define CAN_F3R2_FB1_Pos (1U)
screamer 28:0e774865873d 5019 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5020 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5021 #define CAN_F3R2_FB2_Pos (2U)
screamer 28:0e774865873d 5022 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5023 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5024 #define CAN_F3R2_FB3_Pos (3U)
screamer 28:0e774865873d 5025 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5026 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5027 #define CAN_F3R2_FB4_Pos (4U)
screamer 28:0e774865873d 5028 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5029 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5030 #define CAN_F3R2_FB5_Pos (5U)
screamer 28:0e774865873d 5031 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5032 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5033 #define CAN_F3R2_FB6_Pos (6U)
screamer 28:0e774865873d 5034 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5035 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5036 #define CAN_F3R2_FB7_Pos (7U)
screamer 28:0e774865873d 5037 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5038 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5039 #define CAN_F3R2_FB8_Pos (8U)
screamer 28:0e774865873d 5040 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5041 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5042 #define CAN_F3R2_FB9_Pos (9U)
screamer 28:0e774865873d 5043 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5044 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5045 #define CAN_F3R2_FB10_Pos (10U)
screamer 28:0e774865873d 5046 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5047 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5048 #define CAN_F3R2_FB11_Pos (11U)
screamer 28:0e774865873d 5049 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5050 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5051 #define CAN_F3R2_FB12_Pos (12U)
screamer 28:0e774865873d 5052 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5053 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5054 #define CAN_F3R2_FB13_Pos (13U)
screamer 28:0e774865873d 5055 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5056 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5057 #define CAN_F3R2_FB14_Pos (14U)
screamer 28:0e774865873d 5058 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5059 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5060 #define CAN_F3R2_FB15_Pos (15U)
screamer 28:0e774865873d 5061 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5062 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5063 #define CAN_F3R2_FB16_Pos (16U)
screamer 28:0e774865873d 5064 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5065 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5066 #define CAN_F3R2_FB17_Pos (17U)
screamer 28:0e774865873d 5067 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5068 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5069 #define CAN_F3R2_FB18_Pos (18U)
screamer 28:0e774865873d 5070 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5071 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5072 #define CAN_F3R2_FB19_Pos (19U)
screamer 28:0e774865873d 5073 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5074 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5075 #define CAN_F3R2_FB20_Pos (20U)
screamer 28:0e774865873d 5076 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5077 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5078 #define CAN_F3R2_FB21_Pos (21U)
screamer 28:0e774865873d 5079 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5080 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5081 #define CAN_F3R2_FB22_Pos (22U)
screamer 28:0e774865873d 5082 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5083 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5084 #define CAN_F3R2_FB23_Pos (23U)
screamer 28:0e774865873d 5085 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5086 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5087 #define CAN_F3R2_FB24_Pos (24U)
screamer 28:0e774865873d 5088 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5089 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5090 #define CAN_F3R2_FB25_Pos (25U)
screamer 28:0e774865873d 5091 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5092 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5093 #define CAN_F3R2_FB26_Pos (26U)
screamer 28:0e774865873d 5094 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5095 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5096 #define CAN_F3R2_FB27_Pos (27U)
screamer 28:0e774865873d 5097 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5098 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5099 #define CAN_F3R2_FB28_Pos (28U)
screamer 28:0e774865873d 5100 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5101 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5102 #define CAN_F3R2_FB29_Pos (29U)
screamer 28:0e774865873d 5103 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5104 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5105 #define CAN_F3R2_FB30_Pos (30U)
screamer 28:0e774865873d 5106 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5107 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5108 #define CAN_F3R2_FB31_Pos (31U)
screamer 28:0e774865873d 5109 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5110 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5111
screamer 28:0e774865873d 5112 /******************* Bit definition for CAN_F4R2 register *******************/
screamer 28:0e774865873d 5113 #define CAN_F4R2_FB0_Pos (0U)
screamer 28:0e774865873d 5114 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5115 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5116 #define CAN_F4R2_FB1_Pos (1U)
screamer 28:0e774865873d 5117 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5118 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5119 #define CAN_F4R2_FB2_Pos (2U)
screamer 28:0e774865873d 5120 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5121 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5122 #define CAN_F4R2_FB3_Pos (3U)
screamer 28:0e774865873d 5123 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5124 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5125 #define CAN_F4R2_FB4_Pos (4U)
screamer 28:0e774865873d 5126 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5127 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5128 #define CAN_F4R2_FB5_Pos (5U)
screamer 28:0e774865873d 5129 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5130 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5131 #define CAN_F4R2_FB6_Pos (6U)
screamer 28:0e774865873d 5132 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5133 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5134 #define CAN_F4R2_FB7_Pos (7U)
screamer 28:0e774865873d 5135 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5136 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5137 #define CAN_F4R2_FB8_Pos (8U)
screamer 28:0e774865873d 5138 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5139 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5140 #define CAN_F4R2_FB9_Pos (9U)
screamer 28:0e774865873d 5141 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5142 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5143 #define CAN_F4R2_FB10_Pos (10U)
screamer 28:0e774865873d 5144 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5145 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5146 #define CAN_F4R2_FB11_Pos (11U)
screamer 28:0e774865873d 5147 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5148 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5149 #define CAN_F4R2_FB12_Pos (12U)
screamer 28:0e774865873d 5150 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5151 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5152 #define CAN_F4R2_FB13_Pos (13U)
screamer 28:0e774865873d 5153 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5154 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5155 #define CAN_F4R2_FB14_Pos (14U)
screamer 28:0e774865873d 5156 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5157 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5158 #define CAN_F4R2_FB15_Pos (15U)
screamer 28:0e774865873d 5159 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5160 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5161 #define CAN_F4R2_FB16_Pos (16U)
screamer 28:0e774865873d 5162 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5163 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5164 #define CAN_F4R2_FB17_Pos (17U)
screamer 28:0e774865873d 5165 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5166 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5167 #define CAN_F4R2_FB18_Pos (18U)
screamer 28:0e774865873d 5168 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5169 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5170 #define CAN_F4R2_FB19_Pos (19U)
screamer 28:0e774865873d 5171 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5172 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5173 #define CAN_F4R2_FB20_Pos (20U)
screamer 28:0e774865873d 5174 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5175 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5176 #define CAN_F4R2_FB21_Pos (21U)
screamer 28:0e774865873d 5177 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5178 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5179 #define CAN_F4R2_FB22_Pos (22U)
screamer 28:0e774865873d 5180 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5181 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5182 #define CAN_F4R2_FB23_Pos (23U)
screamer 28:0e774865873d 5183 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5184 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5185 #define CAN_F4R2_FB24_Pos (24U)
screamer 28:0e774865873d 5186 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5187 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5188 #define CAN_F4R2_FB25_Pos (25U)
screamer 28:0e774865873d 5189 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5190 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5191 #define CAN_F4R2_FB26_Pos (26U)
screamer 28:0e774865873d 5192 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5193 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5194 #define CAN_F4R2_FB27_Pos (27U)
screamer 28:0e774865873d 5195 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5196 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5197 #define CAN_F4R2_FB28_Pos (28U)
screamer 28:0e774865873d 5198 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5199 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5200 #define CAN_F4R2_FB29_Pos (29U)
screamer 28:0e774865873d 5201 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5202 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5203 #define CAN_F4R2_FB30_Pos (30U)
screamer 28:0e774865873d 5204 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5205 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5206 #define CAN_F4R2_FB31_Pos (31U)
screamer 28:0e774865873d 5207 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5208 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5209
screamer 28:0e774865873d 5210 /******************* Bit definition for CAN_F5R2 register *******************/
screamer 28:0e774865873d 5211 #define CAN_F5R2_FB0_Pos (0U)
screamer 28:0e774865873d 5212 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5213 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5214 #define CAN_F5R2_FB1_Pos (1U)
screamer 28:0e774865873d 5215 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5216 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5217 #define CAN_F5R2_FB2_Pos (2U)
screamer 28:0e774865873d 5218 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5219 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5220 #define CAN_F5R2_FB3_Pos (3U)
screamer 28:0e774865873d 5221 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5222 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5223 #define CAN_F5R2_FB4_Pos (4U)
screamer 28:0e774865873d 5224 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5225 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5226 #define CAN_F5R2_FB5_Pos (5U)
screamer 28:0e774865873d 5227 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5228 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5229 #define CAN_F5R2_FB6_Pos (6U)
screamer 28:0e774865873d 5230 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5231 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5232 #define CAN_F5R2_FB7_Pos (7U)
screamer 28:0e774865873d 5233 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5234 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5235 #define CAN_F5R2_FB8_Pos (8U)
screamer 28:0e774865873d 5236 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5237 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5238 #define CAN_F5R2_FB9_Pos (9U)
screamer 28:0e774865873d 5239 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5240 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5241 #define CAN_F5R2_FB10_Pos (10U)
screamer 28:0e774865873d 5242 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5243 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5244 #define CAN_F5R2_FB11_Pos (11U)
screamer 28:0e774865873d 5245 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5246 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5247 #define CAN_F5R2_FB12_Pos (12U)
screamer 28:0e774865873d 5248 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5249 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5250 #define CAN_F5R2_FB13_Pos (13U)
screamer 28:0e774865873d 5251 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5252 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5253 #define CAN_F5R2_FB14_Pos (14U)
screamer 28:0e774865873d 5254 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5255 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5256 #define CAN_F5R2_FB15_Pos (15U)
screamer 28:0e774865873d 5257 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5258 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5259 #define CAN_F5R2_FB16_Pos (16U)
screamer 28:0e774865873d 5260 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5261 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5262 #define CAN_F5R2_FB17_Pos (17U)
screamer 28:0e774865873d 5263 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5264 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5265 #define CAN_F5R2_FB18_Pos (18U)
screamer 28:0e774865873d 5266 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5267 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5268 #define CAN_F5R2_FB19_Pos (19U)
screamer 28:0e774865873d 5269 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5270 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5271 #define CAN_F5R2_FB20_Pos (20U)
screamer 28:0e774865873d 5272 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5273 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5274 #define CAN_F5R2_FB21_Pos (21U)
screamer 28:0e774865873d 5275 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5276 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5277 #define CAN_F5R2_FB22_Pos (22U)
screamer 28:0e774865873d 5278 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5279 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5280 #define CAN_F5R2_FB23_Pos (23U)
screamer 28:0e774865873d 5281 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5282 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5283 #define CAN_F5R2_FB24_Pos (24U)
screamer 28:0e774865873d 5284 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5285 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5286 #define CAN_F5R2_FB25_Pos (25U)
screamer 28:0e774865873d 5287 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5288 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5289 #define CAN_F5R2_FB26_Pos (26U)
screamer 28:0e774865873d 5290 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5291 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5292 #define CAN_F5R2_FB27_Pos (27U)
screamer 28:0e774865873d 5293 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5294 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5295 #define CAN_F5R2_FB28_Pos (28U)
screamer 28:0e774865873d 5296 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5297 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5298 #define CAN_F5R2_FB29_Pos (29U)
screamer 28:0e774865873d 5299 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5300 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5301 #define CAN_F5R2_FB30_Pos (30U)
screamer 28:0e774865873d 5302 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5303 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5304 #define CAN_F5R2_FB31_Pos (31U)
screamer 28:0e774865873d 5305 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5306 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5307
screamer 28:0e774865873d 5308 /******************* Bit definition for CAN_F6R2 register *******************/
screamer 28:0e774865873d 5309 #define CAN_F6R2_FB0_Pos (0U)
screamer 28:0e774865873d 5310 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5311 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5312 #define CAN_F6R2_FB1_Pos (1U)
screamer 28:0e774865873d 5313 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5314 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5315 #define CAN_F6R2_FB2_Pos (2U)
screamer 28:0e774865873d 5316 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5317 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5318 #define CAN_F6R2_FB3_Pos (3U)
screamer 28:0e774865873d 5319 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5320 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5321 #define CAN_F6R2_FB4_Pos (4U)
screamer 28:0e774865873d 5322 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5323 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5324 #define CAN_F6R2_FB5_Pos (5U)
screamer 28:0e774865873d 5325 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5326 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5327 #define CAN_F6R2_FB6_Pos (6U)
screamer 28:0e774865873d 5328 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5329 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5330 #define CAN_F6R2_FB7_Pos (7U)
screamer 28:0e774865873d 5331 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5332 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5333 #define CAN_F6R2_FB8_Pos (8U)
screamer 28:0e774865873d 5334 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5335 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5336 #define CAN_F6R2_FB9_Pos (9U)
screamer 28:0e774865873d 5337 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5338 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5339 #define CAN_F6R2_FB10_Pos (10U)
screamer 28:0e774865873d 5340 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5341 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5342 #define CAN_F6R2_FB11_Pos (11U)
screamer 28:0e774865873d 5343 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5344 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5345 #define CAN_F6R2_FB12_Pos (12U)
screamer 28:0e774865873d 5346 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5347 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5348 #define CAN_F6R2_FB13_Pos (13U)
screamer 28:0e774865873d 5349 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5350 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5351 #define CAN_F6R2_FB14_Pos (14U)
screamer 28:0e774865873d 5352 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5353 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5354 #define CAN_F6R2_FB15_Pos (15U)
screamer 28:0e774865873d 5355 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5356 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5357 #define CAN_F6R2_FB16_Pos (16U)
screamer 28:0e774865873d 5358 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5359 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5360 #define CAN_F6R2_FB17_Pos (17U)
screamer 28:0e774865873d 5361 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5362 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5363 #define CAN_F6R2_FB18_Pos (18U)
screamer 28:0e774865873d 5364 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5365 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5366 #define CAN_F6R2_FB19_Pos (19U)
screamer 28:0e774865873d 5367 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5368 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5369 #define CAN_F6R2_FB20_Pos (20U)
screamer 28:0e774865873d 5370 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5371 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5372 #define CAN_F6R2_FB21_Pos (21U)
screamer 28:0e774865873d 5373 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5374 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5375 #define CAN_F6R2_FB22_Pos (22U)
screamer 28:0e774865873d 5376 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5377 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5378 #define CAN_F6R2_FB23_Pos (23U)
screamer 28:0e774865873d 5379 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5380 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5381 #define CAN_F6R2_FB24_Pos (24U)
screamer 28:0e774865873d 5382 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5383 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5384 #define CAN_F6R2_FB25_Pos (25U)
screamer 28:0e774865873d 5385 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5386 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5387 #define CAN_F6R2_FB26_Pos (26U)
screamer 28:0e774865873d 5388 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5389 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5390 #define CAN_F6R2_FB27_Pos (27U)
screamer 28:0e774865873d 5391 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5392 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5393 #define CAN_F6R2_FB28_Pos (28U)
screamer 28:0e774865873d 5394 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5395 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5396 #define CAN_F6R2_FB29_Pos (29U)
screamer 28:0e774865873d 5397 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5398 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5399 #define CAN_F6R2_FB30_Pos (30U)
screamer 28:0e774865873d 5400 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5401 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5402 #define CAN_F6R2_FB31_Pos (31U)
screamer 28:0e774865873d 5403 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5404 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5405
screamer 28:0e774865873d 5406 /******************* Bit definition for CAN_F7R2 register *******************/
screamer 28:0e774865873d 5407 #define CAN_F7R2_FB0_Pos (0U)
screamer 28:0e774865873d 5408 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5409 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5410 #define CAN_F7R2_FB1_Pos (1U)
screamer 28:0e774865873d 5411 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5412 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5413 #define CAN_F7R2_FB2_Pos (2U)
screamer 28:0e774865873d 5414 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5415 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5416 #define CAN_F7R2_FB3_Pos (3U)
screamer 28:0e774865873d 5417 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5418 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5419 #define CAN_F7R2_FB4_Pos (4U)
screamer 28:0e774865873d 5420 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5421 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5422 #define CAN_F7R2_FB5_Pos (5U)
screamer 28:0e774865873d 5423 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5424 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5425 #define CAN_F7R2_FB6_Pos (6U)
screamer 28:0e774865873d 5426 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5427 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5428 #define CAN_F7R2_FB7_Pos (7U)
screamer 28:0e774865873d 5429 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5430 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5431 #define CAN_F7R2_FB8_Pos (8U)
screamer 28:0e774865873d 5432 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5433 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5434 #define CAN_F7R2_FB9_Pos (9U)
screamer 28:0e774865873d 5435 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5436 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5437 #define CAN_F7R2_FB10_Pos (10U)
screamer 28:0e774865873d 5438 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5439 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5440 #define CAN_F7R2_FB11_Pos (11U)
screamer 28:0e774865873d 5441 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5442 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5443 #define CAN_F7R2_FB12_Pos (12U)
screamer 28:0e774865873d 5444 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5445 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5446 #define CAN_F7R2_FB13_Pos (13U)
screamer 28:0e774865873d 5447 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5448 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5449 #define CAN_F7R2_FB14_Pos (14U)
screamer 28:0e774865873d 5450 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5451 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5452 #define CAN_F7R2_FB15_Pos (15U)
screamer 28:0e774865873d 5453 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5454 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5455 #define CAN_F7R2_FB16_Pos (16U)
screamer 28:0e774865873d 5456 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5457 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5458 #define CAN_F7R2_FB17_Pos (17U)
screamer 28:0e774865873d 5459 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5460 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5461 #define CAN_F7R2_FB18_Pos (18U)
screamer 28:0e774865873d 5462 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5463 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5464 #define CAN_F7R2_FB19_Pos (19U)
screamer 28:0e774865873d 5465 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5466 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5467 #define CAN_F7R2_FB20_Pos (20U)
screamer 28:0e774865873d 5468 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5469 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5470 #define CAN_F7R2_FB21_Pos (21U)
screamer 28:0e774865873d 5471 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5472 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5473 #define CAN_F7R2_FB22_Pos (22U)
screamer 28:0e774865873d 5474 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5475 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5476 #define CAN_F7R2_FB23_Pos (23U)
screamer 28:0e774865873d 5477 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5478 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5479 #define CAN_F7R2_FB24_Pos (24U)
screamer 28:0e774865873d 5480 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5481 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5482 #define CAN_F7R2_FB25_Pos (25U)
screamer 28:0e774865873d 5483 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5484 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5485 #define CAN_F7R2_FB26_Pos (26U)
screamer 28:0e774865873d 5486 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5487 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5488 #define CAN_F7R2_FB27_Pos (27U)
screamer 28:0e774865873d 5489 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5490 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5491 #define CAN_F7R2_FB28_Pos (28U)
screamer 28:0e774865873d 5492 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5493 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5494 #define CAN_F7R2_FB29_Pos (29U)
screamer 28:0e774865873d 5495 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5496 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5497 #define CAN_F7R2_FB30_Pos (30U)
screamer 28:0e774865873d 5498 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5499 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5500 #define CAN_F7R2_FB31_Pos (31U)
screamer 28:0e774865873d 5501 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5502 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5503
screamer 28:0e774865873d 5504 /******************* Bit definition for CAN_F8R2 register *******************/
screamer 28:0e774865873d 5505 #define CAN_F8R2_FB0_Pos (0U)
screamer 28:0e774865873d 5506 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5507 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5508 #define CAN_F8R2_FB1_Pos (1U)
screamer 28:0e774865873d 5509 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5510 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5511 #define CAN_F8R2_FB2_Pos (2U)
screamer 28:0e774865873d 5512 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5513 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5514 #define CAN_F8R2_FB3_Pos (3U)
screamer 28:0e774865873d 5515 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5516 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5517 #define CAN_F8R2_FB4_Pos (4U)
screamer 28:0e774865873d 5518 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5519 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5520 #define CAN_F8R2_FB5_Pos (5U)
screamer 28:0e774865873d 5521 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5522 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5523 #define CAN_F8R2_FB6_Pos (6U)
screamer 28:0e774865873d 5524 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5525 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5526 #define CAN_F8R2_FB7_Pos (7U)
screamer 28:0e774865873d 5527 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5528 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5529 #define CAN_F8R2_FB8_Pos (8U)
screamer 28:0e774865873d 5530 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5531 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5532 #define CAN_F8R2_FB9_Pos (9U)
screamer 28:0e774865873d 5533 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5534 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5535 #define CAN_F8R2_FB10_Pos (10U)
screamer 28:0e774865873d 5536 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5537 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5538 #define CAN_F8R2_FB11_Pos (11U)
screamer 28:0e774865873d 5539 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5540 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5541 #define CAN_F8R2_FB12_Pos (12U)
screamer 28:0e774865873d 5542 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5543 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5544 #define CAN_F8R2_FB13_Pos (13U)
screamer 28:0e774865873d 5545 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5546 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5547 #define CAN_F8R2_FB14_Pos (14U)
screamer 28:0e774865873d 5548 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5549 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5550 #define CAN_F8R2_FB15_Pos (15U)
screamer 28:0e774865873d 5551 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5552 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5553 #define CAN_F8R2_FB16_Pos (16U)
screamer 28:0e774865873d 5554 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5555 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5556 #define CAN_F8R2_FB17_Pos (17U)
screamer 28:0e774865873d 5557 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5558 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5559 #define CAN_F8R2_FB18_Pos (18U)
screamer 28:0e774865873d 5560 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5561 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5562 #define CAN_F8R2_FB19_Pos (19U)
screamer 28:0e774865873d 5563 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5564 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5565 #define CAN_F8R2_FB20_Pos (20U)
screamer 28:0e774865873d 5566 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5567 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5568 #define CAN_F8R2_FB21_Pos (21U)
screamer 28:0e774865873d 5569 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5570 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5571 #define CAN_F8R2_FB22_Pos (22U)
screamer 28:0e774865873d 5572 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5573 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5574 #define CAN_F8R2_FB23_Pos (23U)
screamer 28:0e774865873d 5575 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5576 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5577 #define CAN_F8R2_FB24_Pos (24U)
screamer 28:0e774865873d 5578 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5579 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5580 #define CAN_F8R2_FB25_Pos (25U)
screamer 28:0e774865873d 5581 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5582 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5583 #define CAN_F8R2_FB26_Pos (26U)
screamer 28:0e774865873d 5584 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5585 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5586 #define CAN_F8R2_FB27_Pos (27U)
screamer 28:0e774865873d 5587 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5588 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5589 #define CAN_F8R2_FB28_Pos (28U)
screamer 28:0e774865873d 5590 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5591 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5592 #define CAN_F8R2_FB29_Pos (29U)
screamer 28:0e774865873d 5593 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5594 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5595 #define CAN_F8R2_FB30_Pos (30U)
screamer 28:0e774865873d 5596 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5597 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5598 #define CAN_F8R2_FB31_Pos (31U)
screamer 28:0e774865873d 5599 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5600 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5601
screamer 28:0e774865873d 5602 /******************* Bit definition for CAN_F9R2 register *******************/
screamer 28:0e774865873d 5603 #define CAN_F9R2_FB0_Pos (0U)
screamer 28:0e774865873d 5604 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5605 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5606 #define CAN_F9R2_FB1_Pos (1U)
screamer 28:0e774865873d 5607 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5608 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5609 #define CAN_F9R2_FB2_Pos (2U)
screamer 28:0e774865873d 5610 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5611 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5612 #define CAN_F9R2_FB3_Pos (3U)
screamer 28:0e774865873d 5613 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5614 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5615 #define CAN_F9R2_FB4_Pos (4U)
screamer 28:0e774865873d 5616 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5617 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5618 #define CAN_F9R2_FB5_Pos (5U)
screamer 28:0e774865873d 5619 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5620 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5621 #define CAN_F9R2_FB6_Pos (6U)
screamer 28:0e774865873d 5622 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5623 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5624 #define CAN_F9R2_FB7_Pos (7U)
screamer 28:0e774865873d 5625 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5626 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5627 #define CAN_F9R2_FB8_Pos (8U)
screamer 28:0e774865873d 5628 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5629 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5630 #define CAN_F9R2_FB9_Pos (9U)
screamer 28:0e774865873d 5631 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5632 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5633 #define CAN_F9R2_FB10_Pos (10U)
screamer 28:0e774865873d 5634 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5635 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5636 #define CAN_F9R2_FB11_Pos (11U)
screamer 28:0e774865873d 5637 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5638 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5639 #define CAN_F9R2_FB12_Pos (12U)
screamer 28:0e774865873d 5640 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5641 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5642 #define CAN_F9R2_FB13_Pos (13U)
screamer 28:0e774865873d 5643 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5644 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5645 #define CAN_F9R2_FB14_Pos (14U)
screamer 28:0e774865873d 5646 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5647 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5648 #define CAN_F9R2_FB15_Pos (15U)
screamer 28:0e774865873d 5649 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5650 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5651 #define CAN_F9R2_FB16_Pos (16U)
screamer 28:0e774865873d 5652 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5653 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5654 #define CAN_F9R2_FB17_Pos (17U)
screamer 28:0e774865873d 5655 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5656 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5657 #define CAN_F9R2_FB18_Pos (18U)
screamer 28:0e774865873d 5658 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5659 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5660 #define CAN_F9R2_FB19_Pos (19U)
screamer 28:0e774865873d 5661 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5662 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5663 #define CAN_F9R2_FB20_Pos (20U)
screamer 28:0e774865873d 5664 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5665 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5666 #define CAN_F9R2_FB21_Pos (21U)
screamer 28:0e774865873d 5667 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5668 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5669 #define CAN_F9R2_FB22_Pos (22U)
screamer 28:0e774865873d 5670 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5671 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5672 #define CAN_F9R2_FB23_Pos (23U)
screamer 28:0e774865873d 5673 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5674 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5675 #define CAN_F9R2_FB24_Pos (24U)
screamer 28:0e774865873d 5676 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5677 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5678 #define CAN_F9R2_FB25_Pos (25U)
screamer 28:0e774865873d 5679 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5680 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5681 #define CAN_F9R2_FB26_Pos (26U)
screamer 28:0e774865873d 5682 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5683 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5684 #define CAN_F9R2_FB27_Pos (27U)
screamer 28:0e774865873d 5685 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5686 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5687 #define CAN_F9R2_FB28_Pos (28U)
screamer 28:0e774865873d 5688 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5689 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5690 #define CAN_F9R2_FB29_Pos (29U)
screamer 28:0e774865873d 5691 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5692 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5693 #define CAN_F9R2_FB30_Pos (30U)
screamer 28:0e774865873d 5694 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5695 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5696 #define CAN_F9R2_FB31_Pos (31U)
screamer 28:0e774865873d 5697 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5698 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5699
screamer 28:0e774865873d 5700 /******************* Bit definition for CAN_F10R2 register ******************/
screamer 28:0e774865873d 5701 #define CAN_F10R2_FB0_Pos (0U)
screamer 28:0e774865873d 5702 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5703 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5704 #define CAN_F10R2_FB1_Pos (1U)
screamer 28:0e774865873d 5705 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5706 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5707 #define CAN_F10R2_FB2_Pos (2U)
screamer 28:0e774865873d 5708 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5709 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5710 #define CAN_F10R2_FB3_Pos (3U)
screamer 28:0e774865873d 5711 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5712 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5713 #define CAN_F10R2_FB4_Pos (4U)
screamer 28:0e774865873d 5714 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5715 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5716 #define CAN_F10R2_FB5_Pos (5U)
screamer 28:0e774865873d 5717 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5718 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5719 #define CAN_F10R2_FB6_Pos (6U)
screamer 28:0e774865873d 5720 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5721 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5722 #define CAN_F10R2_FB7_Pos (7U)
screamer 28:0e774865873d 5723 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5724 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5725 #define CAN_F10R2_FB8_Pos (8U)
screamer 28:0e774865873d 5726 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5727 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5728 #define CAN_F10R2_FB9_Pos (9U)
screamer 28:0e774865873d 5729 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5730 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5731 #define CAN_F10R2_FB10_Pos (10U)
screamer 28:0e774865873d 5732 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5733 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5734 #define CAN_F10R2_FB11_Pos (11U)
screamer 28:0e774865873d 5735 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5736 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5737 #define CAN_F10R2_FB12_Pos (12U)
screamer 28:0e774865873d 5738 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5739 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5740 #define CAN_F10R2_FB13_Pos (13U)
screamer 28:0e774865873d 5741 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5742 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5743 #define CAN_F10R2_FB14_Pos (14U)
screamer 28:0e774865873d 5744 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5745 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5746 #define CAN_F10R2_FB15_Pos (15U)
screamer 28:0e774865873d 5747 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5748 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5749 #define CAN_F10R2_FB16_Pos (16U)
screamer 28:0e774865873d 5750 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5751 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5752 #define CAN_F10R2_FB17_Pos (17U)
screamer 28:0e774865873d 5753 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5754 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5755 #define CAN_F10R2_FB18_Pos (18U)
screamer 28:0e774865873d 5756 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5757 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5758 #define CAN_F10R2_FB19_Pos (19U)
screamer 28:0e774865873d 5759 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5760 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5761 #define CAN_F10R2_FB20_Pos (20U)
screamer 28:0e774865873d 5762 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5763 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5764 #define CAN_F10R2_FB21_Pos (21U)
screamer 28:0e774865873d 5765 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5766 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5767 #define CAN_F10R2_FB22_Pos (22U)
screamer 28:0e774865873d 5768 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5769 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5770 #define CAN_F10R2_FB23_Pos (23U)
screamer 28:0e774865873d 5771 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5772 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5773 #define CAN_F10R2_FB24_Pos (24U)
screamer 28:0e774865873d 5774 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5775 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5776 #define CAN_F10R2_FB25_Pos (25U)
screamer 28:0e774865873d 5777 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5778 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5779 #define CAN_F10R2_FB26_Pos (26U)
screamer 28:0e774865873d 5780 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5781 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5782 #define CAN_F10R2_FB27_Pos (27U)
screamer 28:0e774865873d 5783 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5784 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5785 #define CAN_F10R2_FB28_Pos (28U)
screamer 28:0e774865873d 5786 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5787 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5788 #define CAN_F10R2_FB29_Pos (29U)
screamer 28:0e774865873d 5789 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5790 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5791 #define CAN_F10R2_FB30_Pos (30U)
screamer 28:0e774865873d 5792 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5793 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5794 #define CAN_F10R2_FB31_Pos (31U)
screamer 28:0e774865873d 5795 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5796 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5797
screamer 28:0e774865873d 5798 /******************* Bit definition for CAN_F11R2 register ******************/
screamer 28:0e774865873d 5799 #define CAN_F11R2_FB0_Pos (0U)
screamer 28:0e774865873d 5800 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5801 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5802 #define CAN_F11R2_FB1_Pos (1U)
screamer 28:0e774865873d 5803 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5804 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5805 #define CAN_F11R2_FB2_Pos (2U)
screamer 28:0e774865873d 5806 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5807 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5808 #define CAN_F11R2_FB3_Pos (3U)
screamer 28:0e774865873d 5809 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5810 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5811 #define CAN_F11R2_FB4_Pos (4U)
screamer 28:0e774865873d 5812 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5813 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5814 #define CAN_F11R2_FB5_Pos (5U)
screamer 28:0e774865873d 5815 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5816 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5817 #define CAN_F11R2_FB6_Pos (6U)
screamer 28:0e774865873d 5818 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5819 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5820 #define CAN_F11R2_FB7_Pos (7U)
screamer 28:0e774865873d 5821 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5822 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5823 #define CAN_F11R2_FB8_Pos (8U)
screamer 28:0e774865873d 5824 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5825 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5826 #define CAN_F11R2_FB9_Pos (9U)
screamer 28:0e774865873d 5827 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5828 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5829 #define CAN_F11R2_FB10_Pos (10U)
screamer 28:0e774865873d 5830 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5831 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5832 #define CAN_F11R2_FB11_Pos (11U)
screamer 28:0e774865873d 5833 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5834 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5835 #define CAN_F11R2_FB12_Pos (12U)
screamer 28:0e774865873d 5836 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5837 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5838 #define CAN_F11R2_FB13_Pos (13U)
screamer 28:0e774865873d 5839 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5840 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5841 #define CAN_F11R2_FB14_Pos (14U)
screamer 28:0e774865873d 5842 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5843 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5844 #define CAN_F11R2_FB15_Pos (15U)
screamer 28:0e774865873d 5845 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5846 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5847 #define CAN_F11R2_FB16_Pos (16U)
screamer 28:0e774865873d 5848 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5849 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5850 #define CAN_F11R2_FB17_Pos (17U)
screamer 28:0e774865873d 5851 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5852 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5853 #define CAN_F11R2_FB18_Pos (18U)
screamer 28:0e774865873d 5854 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5855 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5856 #define CAN_F11R2_FB19_Pos (19U)
screamer 28:0e774865873d 5857 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5858 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5859 #define CAN_F11R2_FB20_Pos (20U)
screamer 28:0e774865873d 5860 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5861 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5862 #define CAN_F11R2_FB21_Pos (21U)
screamer 28:0e774865873d 5863 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5864 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5865 #define CAN_F11R2_FB22_Pos (22U)
screamer 28:0e774865873d 5866 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5867 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5868 #define CAN_F11R2_FB23_Pos (23U)
screamer 28:0e774865873d 5869 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5870 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5871 #define CAN_F11R2_FB24_Pos (24U)
screamer 28:0e774865873d 5872 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5873 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5874 #define CAN_F11R2_FB25_Pos (25U)
screamer 28:0e774865873d 5875 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5876 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5877 #define CAN_F11R2_FB26_Pos (26U)
screamer 28:0e774865873d 5878 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5879 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5880 #define CAN_F11R2_FB27_Pos (27U)
screamer 28:0e774865873d 5881 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5882 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5883 #define CAN_F11R2_FB28_Pos (28U)
screamer 28:0e774865873d 5884 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5885 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5886 #define CAN_F11R2_FB29_Pos (29U)
screamer 28:0e774865873d 5887 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5888 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5889 #define CAN_F11R2_FB30_Pos (30U)
screamer 28:0e774865873d 5890 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5891 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5892 #define CAN_F11R2_FB31_Pos (31U)
screamer 28:0e774865873d 5893 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5894 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5895
screamer 28:0e774865873d 5896 /******************* Bit definition for CAN_F12R2 register ******************/
screamer 28:0e774865873d 5897 #define CAN_F12R2_FB0_Pos (0U)
screamer 28:0e774865873d 5898 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5899 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5900 #define CAN_F12R2_FB1_Pos (1U)
screamer 28:0e774865873d 5901 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 5902 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 5903 #define CAN_F12R2_FB2_Pos (2U)
screamer 28:0e774865873d 5904 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 5905 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 5906 #define CAN_F12R2_FB3_Pos (3U)
screamer 28:0e774865873d 5907 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 5908 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 5909 #define CAN_F12R2_FB4_Pos (4U)
screamer 28:0e774865873d 5910 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 5911 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 5912 #define CAN_F12R2_FB5_Pos (5U)
screamer 28:0e774865873d 5913 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 5914 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 5915 #define CAN_F12R2_FB6_Pos (6U)
screamer 28:0e774865873d 5916 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 5917 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 5918 #define CAN_F12R2_FB7_Pos (7U)
screamer 28:0e774865873d 5919 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 5920 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 5921 #define CAN_F12R2_FB8_Pos (8U)
screamer 28:0e774865873d 5922 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 5923 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 5924 #define CAN_F12R2_FB9_Pos (9U)
screamer 28:0e774865873d 5925 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 5926 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 5927 #define CAN_F12R2_FB10_Pos (10U)
screamer 28:0e774865873d 5928 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 5929 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 5930 #define CAN_F12R2_FB11_Pos (11U)
screamer 28:0e774865873d 5931 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 5932 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 5933 #define CAN_F12R2_FB12_Pos (12U)
screamer 28:0e774865873d 5934 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 5935 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 5936 #define CAN_F12R2_FB13_Pos (13U)
screamer 28:0e774865873d 5937 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 5938 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 5939 #define CAN_F12R2_FB14_Pos (14U)
screamer 28:0e774865873d 5940 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 5941 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 5942 #define CAN_F12R2_FB15_Pos (15U)
screamer 28:0e774865873d 5943 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 5944 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 5945 #define CAN_F12R2_FB16_Pos (16U)
screamer 28:0e774865873d 5946 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 5947 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 5948 #define CAN_F12R2_FB17_Pos (17U)
screamer 28:0e774865873d 5949 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 5950 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 5951 #define CAN_F12R2_FB18_Pos (18U)
screamer 28:0e774865873d 5952 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 5953 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 5954 #define CAN_F12R2_FB19_Pos (19U)
screamer 28:0e774865873d 5955 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 5956 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 5957 #define CAN_F12R2_FB20_Pos (20U)
screamer 28:0e774865873d 5958 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 5959 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 5960 #define CAN_F12R2_FB21_Pos (21U)
screamer 28:0e774865873d 5961 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 5962 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 5963 #define CAN_F12R2_FB22_Pos (22U)
screamer 28:0e774865873d 5964 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 5965 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 5966 #define CAN_F12R2_FB23_Pos (23U)
screamer 28:0e774865873d 5967 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 5968 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 5969 #define CAN_F12R2_FB24_Pos (24U)
screamer 28:0e774865873d 5970 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 5971 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 5972 #define CAN_F12R2_FB25_Pos (25U)
screamer 28:0e774865873d 5973 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 5974 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 5975 #define CAN_F12R2_FB26_Pos (26U)
screamer 28:0e774865873d 5976 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 5977 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 5978 #define CAN_F12R2_FB27_Pos (27U)
screamer 28:0e774865873d 5979 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 5980 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 5981 #define CAN_F12R2_FB28_Pos (28U)
screamer 28:0e774865873d 5982 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 5983 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 5984 #define CAN_F12R2_FB29_Pos (29U)
screamer 28:0e774865873d 5985 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 5986 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 5987 #define CAN_F12R2_FB30_Pos (30U)
screamer 28:0e774865873d 5988 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 5989 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 5990 #define CAN_F12R2_FB31_Pos (31U)
screamer 28:0e774865873d 5991 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 5992 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 5993
screamer 28:0e774865873d 5994 /******************* Bit definition for CAN_F13R2 register ******************/
screamer 28:0e774865873d 5995 #define CAN_F13R2_FB0_Pos (0U)
screamer 28:0e774865873d 5996 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 5997 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
screamer 28:0e774865873d 5998 #define CAN_F13R2_FB1_Pos (1U)
screamer 28:0e774865873d 5999 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6000 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
screamer 28:0e774865873d 6001 #define CAN_F13R2_FB2_Pos (2U)
screamer 28:0e774865873d 6002 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6003 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
screamer 28:0e774865873d 6004 #define CAN_F13R2_FB3_Pos (3U)
screamer 28:0e774865873d 6005 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6006 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
screamer 28:0e774865873d 6007 #define CAN_F13R2_FB4_Pos (4U)
screamer 28:0e774865873d 6008 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6009 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
screamer 28:0e774865873d 6010 #define CAN_F13R2_FB5_Pos (5U)
screamer 28:0e774865873d 6011 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6012 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
screamer 28:0e774865873d 6013 #define CAN_F13R2_FB6_Pos (6U)
screamer 28:0e774865873d 6014 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6015 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
screamer 28:0e774865873d 6016 #define CAN_F13R2_FB7_Pos (7U)
screamer 28:0e774865873d 6017 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6018 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
screamer 28:0e774865873d 6019 #define CAN_F13R2_FB8_Pos (8U)
screamer 28:0e774865873d 6020 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6021 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
screamer 28:0e774865873d 6022 #define CAN_F13R2_FB9_Pos (9U)
screamer 28:0e774865873d 6023 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6024 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
screamer 28:0e774865873d 6025 #define CAN_F13R2_FB10_Pos (10U)
screamer 28:0e774865873d 6026 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6027 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
screamer 28:0e774865873d 6028 #define CAN_F13R2_FB11_Pos (11U)
screamer 28:0e774865873d 6029 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 6030 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
screamer 28:0e774865873d 6031 #define CAN_F13R2_FB12_Pos (12U)
screamer 28:0e774865873d 6032 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6033 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
screamer 28:0e774865873d 6034 #define CAN_F13R2_FB13_Pos (13U)
screamer 28:0e774865873d 6035 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6036 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
screamer 28:0e774865873d 6037 #define CAN_F13R2_FB14_Pos (14U)
screamer 28:0e774865873d 6038 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6039 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
screamer 28:0e774865873d 6040 #define CAN_F13R2_FB15_Pos (15U)
screamer 28:0e774865873d 6041 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 6042 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
screamer 28:0e774865873d 6043 #define CAN_F13R2_FB16_Pos (16U)
screamer 28:0e774865873d 6044 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 6045 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
screamer 28:0e774865873d 6046 #define CAN_F13R2_FB17_Pos (17U)
screamer 28:0e774865873d 6047 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 6048 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
screamer 28:0e774865873d 6049 #define CAN_F13R2_FB18_Pos (18U)
screamer 28:0e774865873d 6050 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6051 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
screamer 28:0e774865873d 6052 #define CAN_F13R2_FB19_Pos (19U)
screamer 28:0e774865873d 6053 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 6054 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
screamer 28:0e774865873d 6055 #define CAN_F13R2_FB20_Pos (20U)
screamer 28:0e774865873d 6056 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 6057 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
screamer 28:0e774865873d 6058 #define CAN_F13R2_FB21_Pos (21U)
screamer 28:0e774865873d 6059 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 6060 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
screamer 28:0e774865873d 6061 #define CAN_F13R2_FB22_Pos (22U)
screamer 28:0e774865873d 6062 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 6063 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
screamer 28:0e774865873d 6064 #define CAN_F13R2_FB23_Pos (23U)
screamer 28:0e774865873d 6065 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 6066 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
screamer 28:0e774865873d 6067 #define CAN_F13R2_FB24_Pos (24U)
screamer 28:0e774865873d 6068 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 6069 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
screamer 28:0e774865873d 6070 #define CAN_F13R2_FB25_Pos (25U)
screamer 28:0e774865873d 6071 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 6072 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
screamer 28:0e774865873d 6073 #define CAN_F13R2_FB26_Pos (26U)
screamer 28:0e774865873d 6074 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 6075 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
screamer 28:0e774865873d 6076 #define CAN_F13R2_FB27_Pos (27U)
screamer 28:0e774865873d 6077 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 6078 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
screamer 28:0e774865873d 6079 #define CAN_F13R2_FB28_Pos (28U)
screamer 28:0e774865873d 6080 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 6081 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
screamer 28:0e774865873d 6082 #define CAN_F13R2_FB29_Pos (29U)
screamer 28:0e774865873d 6083 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 6084 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
screamer 28:0e774865873d 6085 #define CAN_F13R2_FB30_Pos (30U)
screamer 28:0e774865873d 6086 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 6087 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
screamer 28:0e774865873d 6088 #define CAN_F13R2_FB31_Pos (31U)
screamer 28:0e774865873d 6089 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 6090 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
screamer 28:0e774865873d 6091
screamer 28:0e774865873d 6092 /******************************************************************************/
screamer 28:0e774865873d 6093 /* */
screamer 28:0e774865873d 6094 /* CRC calculation unit */
screamer 28:0e774865873d 6095 /* */
screamer 28:0e774865873d 6096 /******************************************************************************/
screamer 28:0e774865873d 6097 /******************* Bit definition for CRC_DR register *********************/
screamer 28:0e774865873d 6098 #define CRC_DR_DR_Pos (0U)
screamer 28:0e774865873d 6099 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 6100 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
screamer 28:0e774865873d 6101
screamer 28:0e774865873d 6102 /******************* Bit definition for CRC_IDR register ********************/
screamer 28:0e774865873d 6103 #define CRC_IDR_IDR_Pos (0U)
screamer 28:0e774865873d 6104 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6105 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
screamer 28:0e774865873d 6106
screamer 28:0e774865873d 6107 /******************** Bit definition for CRC_CR register ********************/
screamer 28:0e774865873d 6108 #define CRC_CR_RESET_Pos (0U)
screamer 28:0e774865873d 6109 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6110 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
screamer 28:0e774865873d 6111 #define CRC_CR_POLYSIZE_Pos (3U)
screamer 28:0e774865873d 6112 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
screamer 28:0e774865873d 6113 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
screamer 28:0e774865873d 6114 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6115 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6116 #define CRC_CR_REV_IN_Pos (5U)
screamer 28:0e774865873d 6117 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
screamer 28:0e774865873d 6118 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
screamer 28:0e774865873d 6119 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6120 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6121 #define CRC_CR_REV_OUT_Pos (7U)
screamer 28:0e774865873d 6122 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6123 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
screamer 28:0e774865873d 6124
screamer 28:0e774865873d 6125 /******************* Bit definition for CRC_INIT register *******************/
screamer 28:0e774865873d 6126 #define CRC_INIT_INIT_Pos (0U)
screamer 28:0e774865873d 6127 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 6128 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
screamer 28:0e774865873d 6129
screamer 28:0e774865873d 6130 /******************* Bit definition for CRC_POL register ********************/
screamer 28:0e774865873d 6131 #define CRC_POL_POL_Pos (0U)
screamer 28:0e774865873d 6132 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 6133 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
screamer 28:0e774865873d 6134
screamer 28:0e774865873d 6135 /******************************************************************************/
screamer 28:0e774865873d 6136 /* */
screamer 28:0e774865873d 6137 /* Digital to Analog Converter */
screamer 28:0e774865873d 6138 /* */
screamer 28:0e774865873d 6139 /******************************************************************************/
screamer 28:0e774865873d 6140 /*
screamer 28:0e774865873d 6141 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
screamer 28:0e774865873d 6142 */
screamer 28:0e774865873d 6143 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
screamer 28:0e774865873d 6144
screamer 28:0e774865873d 6145 /******************** Bit definition for DAC_CR register ********************/
screamer 28:0e774865873d 6146 #define DAC_CR_EN1_Pos (0U)
screamer 28:0e774865873d 6147 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6148 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
screamer 28:0e774865873d 6149 #define DAC_CR_TEN1_Pos (2U)
screamer 28:0e774865873d 6150 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6151 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
screamer 28:0e774865873d 6152
screamer 28:0e774865873d 6153 #define DAC_CR_TSEL1_Pos (3U)
screamer 28:0e774865873d 6154 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
screamer 28:0e774865873d 6155 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
screamer 28:0e774865873d 6156 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6157 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6158 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6159
screamer 28:0e774865873d 6160 #define DAC_CR_WAVE1_Pos (6U)
screamer 28:0e774865873d 6161 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 6162 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
screamer 28:0e774865873d 6163 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6164 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6165
screamer 28:0e774865873d 6166 #define DAC_CR_MAMP1_Pos (8U)
screamer 28:0e774865873d 6167 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 6168 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
screamer 28:0e774865873d 6169 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6170 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6171 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6172 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 6173
screamer 28:0e774865873d 6174 #define DAC_CR_DMAEN1_Pos (12U)
screamer 28:0e774865873d 6175 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6176 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
screamer 28:0e774865873d 6177 #define DAC_CR_DMAUDRIE1_Pos (13U)
screamer 28:0e774865873d 6178 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6179 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
screamer 28:0e774865873d 6180 #define DAC_CR_CEN1_Pos (14U)
screamer 28:0e774865873d 6181 #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6182 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
screamer 28:0e774865873d 6183
screamer 28:0e774865873d 6184 #define DAC_CR_EN2_Pos (16U)
screamer 28:0e774865873d 6185 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 6186 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
screamer 28:0e774865873d 6187 #define DAC_CR_TEN2_Pos (18U)
screamer 28:0e774865873d 6188 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6189 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
screamer 28:0e774865873d 6190
screamer 28:0e774865873d 6191 #define DAC_CR_TSEL2_Pos (19U)
screamer 28:0e774865873d 6192 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
screamer 28:0e774865873d 6193 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
screamer 28:0e774865873d 6194 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 6195 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 6196 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 6197
screamer 28:0e774865873d 6198 #define DAC_CR_WAVE2_Pos (22U)
screamer 28:0e774865873d 6199 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
screamer 28:0e774865873d 6200 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
screamer 28:0e774865873d 6201 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 6202 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 6203
screamer 28:0e774865873d 6204 #define DAC_CR_MAMP2_Pos (24U)
screamer 28:0e774865873d 6205 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 6206 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
screamer 28:0e774865873d 6207 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 6208 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 6209 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 6210 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 6211
screamer 28:0e774865873d 6212 #define DAC_CR_DMAEN2_Pos (28U)
screamer 28:0e774865873d 6213 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 6214 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
screamer 28:0e774865873d 6215 #define DAC_CR_DMAUDRIE2_Pos (29U)
screamer 28:0e774865873d 6216 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 6217 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
screamer 28:0e774865873d 6218 #define DAC_CR_CEN2_Pos (30U)
screamer 28:0e774865873d 6219 #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 6220 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
screamer 28:0e774865873d 6221
screamer 28:0e774865873d 6222 /***************** Bit definition for DAC_SWTRIGR register ******************/
screamer 28:0e774865873d 6223 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
screamer 28:0e774865873d 6224 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6225 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
screamer 28:0e774865873d 6226 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
screamer 28:0e774865873d 6227 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6228 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
screamer 28:0e774865873d 6229
screamer 28:0e774865873d 6230 /***************** Bit definition for DAC_DHR12R1 register ******************/
screamer 28:0e774865873d 6231 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
screamer 28:0e774865873d 6232 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 6233 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
screamer 28:0e774865873d 6234
screamer 28:0e774865873d 6235 /***************** Bit definition for DAC_DHR12L1 register ******************/
screamer 28:0e774865873d 6236 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
screamer 28:0e774865873d 6237 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
screamer 28:0e774865873d 6238 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
screamer 28:0e774865873d 6239
screamer 28:0e774865873d 6240 /****************** Bit definition for DAC_DHR8R1 register ******************/
screamer 28:0e774865873d 6241 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
screamer 28:0e774865873d 6242 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6243 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
screamer 28:0e774865873d 6244
screamer 28:0e774865873d 6245 /***************** Bit definition for DAC_DHR12R2 register ******************/
screamer 28:0e774865873d 6246 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
screamer 28:0e774865873d 6247 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 6248 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
screamer 28:0e774865873d 6249
screamer 28:0e774865873d 6250 /***************** Bit definition for DAC_DHR12L2 register ******************/
screamer 28:0e774865873d 6251 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
screamer 28:0e774865873d 6252 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
screamer 28:0e774865873d 6253 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
screamer 28:0e774865873d 6254
screamer 28:0e774865873d 6255 /****************** Bit definition for DAC_DHR8R2 register ******************/
screamer 28:0e774865873d 6256 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
screamer 28:0e774865873d 6257 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6258 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
screamer 28:0e774865873d 6259
screamer 28:0e774865873d 6260 /***************** Bit definition for DAC_DHR12RD register ******************/
screamer 28:0e774865873d 6261 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
screamer 28:0e774865873d 6262 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 6263 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
screamer 28:0e774865873d 6264 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
screamer 28:0e774865873d 6265 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
screamer 28:0e774865873d 6266 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
screamer 28:0e774865873d 6267
screamer 28:0e774865873d 6268 /***************** Bit definition for DAC_DHR12LD register ******************/
screamer 28:0e774865873d 6269 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
screamer 28:0e774865873d 6270 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
screamer 28:0e774865873d 6271 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
screamer 28:0e774865873d 6272 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
screamer 28:0e774865873d 6273 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
screamer 28:0e774865873d 6274 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
screamer 28:0e774865873d 6275
screamer 28:0e774865873d 6276 /****************** Bit definition for DAC_DHR8RD register ******************/
screamer 28:0e774865873d 6277 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
screamer 28:0e774865873d 6278 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6279 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
screamer 28:0e774865873d 6280 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
screamer 28:0e774865873d 6281 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 6282 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
screamer 28:0e774865873d 6283
screamer 28:0e774865873d 6284 /******************* Bit definition for DAC_DOR1 register *******************/
screamer 28:0e774865873d 6285 #define DAC_DOR1_DACC1DOR_Pos (0U)
screamer 28:0e774865873d 6286 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 6287 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
screamer 28:0e774865873d 6288
screamer 28:0e774865873d 6289 /******************* Bit definition for DAC_DOR2 register *******************/
screamer 28:0e774865873d 6290 #define DAC_DOR2_DACC2DOR_Pos (0U)
screamer 28:0e774865873d 6291 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 6292 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
screamer 28:0e774865873d 6293
screamer 28:0e774865873d 6294 /******************** Bit definition for DAC_SR register ********************/
screamer 28:0e774865873d 6295 #define DAC_SR_DMAUDR1_Pos (13U)
screamer 28:0e774865873d 6296 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6297 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
screamer 28:0e774865873d 6298 #define DAC_SR_CAL_FLAG1_Pos (14U)
screamer 28:0e774865873d 6299 #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6300 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
screamer 28:0e774865873d 6301 #define DAC_SR_BWST1_Pos (15U)
screamer 28:0e774865873d 6302 #define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 6303 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
screamer 28:0e774865873d 6304
screamer 28:0e774865873d 6305 #define DAC_SR_DMAUDR2_Pos (29U)
screamer 28:0e774865873d 6306 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 6307 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
screamer 28:0e774865873d 6308 #define DAC_SR_CAL_FLAG2_Pos (30U)
screamer 28:0e774865873d 6309 #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 6310 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
screamer 28:0e774865873d 6311 #define DAC_SR_BWST2_Pos (31U)
screamer 28:0e774865873d 6312 #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 6313 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
screamer 28:0e774865873d 6314
screamer 28:0e774865873d 6315 /******************* Bit definition for DAC_CCR register ********************/
screamer 28:0e774865873d 6316 #define DAC_CCR_OTRIM1_Pos (0U)
screamer 28:0e774865873d 6317 #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 6318 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
screamer 28:0e774865873d 6319 #define DAC_CCR_OTRIM2_Pos (16U)
screamer 28:0e774865873d 6320 #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
screamer 28:0e774865873d 6321 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
screamer 28:0e774865873d 6322
screamer 28:0e774865873d 6323 /******************* Bit definition for DAC_MCR register *******************/
screamer 28:0e774865873d 6324 #define DAC_MCR_MODE1_Pos (0U)
screamer 28:0e774865873d 6325 #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 6326 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
screamer 28:0e774865873d 6327 #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6328 #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6329 #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6330
screamer 28:0e774865873d 6331 #define DAC_MCR_MODE2_Pos (16U)
screamer 28:0e774865873d 6332 #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
screamer 28:0e774865873d 6333 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
screamer 28:0e774865873d 6334 #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 6335 #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 6336 #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6337
screamer 28:0e774865873d 6338 /****************** Bit definition for DAC_SHSR1 register ******************/
screamer 28:0e774865873d 6339 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
screamer 28:0e774865873d 6340 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
screamer 28:0e774865873d 6341 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
screamer 28:0e774865873d 6342
screamer 28:0e774865873d 6343 /****************** Bit definition for DAC_SHSR2 register ******************/
screamer 28:0e774865873d 6344 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
screamer 28:0e774865873d 6345 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
screamer 28:0e774865873d 6346 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
screamer 28:0e774865873d 6347
screamer 28:0e774865873d 6348 /****************** Bit definition for DAC_SHHR register ******************/
screamer 28:0e774865873d 6349 #define DAC_SHHR_THOLD1_Pos (0U)
screamer 28:0e774865873d 6350 #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
screamer 28:0e774865873d 6351 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
screamer 28:0e774865873d 6352 #define DAC_SHHR_THOLD2_Pos (16U)
screamer 28:0e774865873d 6353 #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
screamer 28:0e774865873d 6354 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
screamer 28:0e774865873d 6355
screamer 28:0e774865873d 6356 /****************** Bit definition for DAC_SHRR register ******************/
screamer 28:0e774865873d 6357 #define DAC_SHRR_TREFRESH1_Pos (0U)
screamer 28:0e774865873d 6358 #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6359 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
screamer 28:0e774865873d 6360 #define DAC_SHRR_TREFRESH2_Pos (16U)
screamer 28:0e774865873d 6361 #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 6362 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
screamer 28:0e774865873d 6363
screamer 28:0e774865873d 6364 /******************************************************************************/
screamer 28:0e774865873d 6365 /* */
screamer 28:0e774865873d 6366 /* Digital Filter for Sigma Delta Modulators */
screamer 28:0e774865873d 6367 /* */
screamer 28:0e774865873d 6368 /******************************************************************************/
screamer 28:0e774865873d 6369
screamer 28:0e774865873d 6370 /**************** DFSDM channel configuration registers ********************/
screamer 28:0e774865873d 6371
screamer 28:0e774865873d 6372 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
screamer 28:0e774865873d 6373 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
screamer 28:0e774865873d 6374 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 6375 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
screamer 28:0e774865873d 6376 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
screamer 28:0e774865873d 6377 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 6378 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
screamer 28:0e774865873d 6379 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
screamer 28:0e774865873d 6380 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 6381 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
screamer 28:0e774865873d 6382 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
screamer 28:0e774865873d 6383 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 6384 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
screamer 28:0e774865873d 6385 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 6386 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6387 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
screamer 28:0e774865873d 6388 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 6389 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
screamer 28:0e774865873d 6390 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6391 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6392 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
screamer 28:0e774865873d 6393 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6394 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
screamer 28:0e774865873d 6395 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
screamer 28:0e774865873d 6396 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6397 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
screamer 28:0e774865873d 6398 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
screamer 28:0e774865873d 6399 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6400 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
screamer 28:0e774865873d 6401 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
screamer 28:0e774865873d 6402 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6403 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
screamer 28:0e774865873d 6404 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
screamer 28:0e774865873d 6405 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 6406 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
screamer 28:0e774865873d 6407 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6408 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6409 #define DFSDM_CHCFGR1_SITP_Pos (0U)
screamer 28:0e774865873d 6410 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 6411 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
screamer 28:0e774865873d 6412 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6413 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6414
screamer 28:0e774865873d 6415 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
screamer 28:0e774865873d 6416 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
screamer 28:0e774865873d 6417 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6418 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
screamer 28:0e774865873d 6419 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
screamer 28:0e774865873d 6420 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
screamer 28:0e774865873d 6421 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
screamer 28:0e774865873d 6422
screamer 28:0e774865873d 6423 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
screamer 28:0e774865873d 6424 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
screamer 28:0e774865873d 6425 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
screamer 28:0e774865873d 6426 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
screamer 28:0e774865873d 6427 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 6428 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 6429 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
screamer 28:0e774865873d 6430 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
screamer 28:0e774865873d 6431 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
screamer 28:0e774865873d 6432 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
screamer 28:0e774865873d 6433 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
screamer 28:0e774865873d 6434 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
screamer 28:0e774865873d 6435 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
screamer 28:0e774865873d 6436 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6437 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
screamer 28:0e774865873d 6438
screamer 28:0e774865873d 6439 /**************** Bit definition for DFSDM_CHWDATR register *******************/
screamer 28:0e774865873d 6440 #define DFSDM_CHWDATR_WDATA_Pos (0U)
screamer 28:0e774865873d 6441 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 6442 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
screamer 28:0e774865873d 6443
screamer 28:0e774865873d 6444 /**************** Bit definition for DFSDM_CHDATINR register *****************/
screamer 28:0e774865873d 6445 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
screamer 28:0e774865873d 6446 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 6447 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
screamer 28:0e774865873d 6448 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
screamer 28:0e774865873d 6449 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 6450 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
screamer 28:0e774865873d 6451
screamer 28:0e774865873d 6452 /************************ DFSDM module registers ****************************/
screamer 28:0e774865873d 6453
screamer 28:0e774865873d 6454 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
screamer 28:0e774865873d 6455 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
screamer 28:0e774865873d 6456 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 6457 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
screamer 28:0e774865873d 6458 #define DFSDM_FLTCR1_FAST_Pos (29U)
screamer 28:0e774865873d 6459 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 6460 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
screamer 28:0e774865873d 6461 #define DFSDM_FLTCR1_RCH_Pos (24U)
screamer 28:0e774865873d 6462 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
screamer 28:0e774865873d 6463 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
screamer 28:0e774865873d 6464 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
screamer 28:0e774865873d 6465 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 6466 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
screamer 28:0e774865873d 6467 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
screamer 28:0e774865873d 6468 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 6469 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
screamer 28:0e774865873d 6470 #define DFSDM_FLTCR1_RCONT_Pos (18U)
screamer 28:0e774865873d 6471 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6472 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
screamer 28:0e774865873d 6473 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
screamer 28:0e774865873d 6474 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 6475 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
screamer 28:0e774865873d 6476 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
screamer 28:0e774865873d 6477 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
screamer 28:0e774865873d 6478 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
screamer 28:0e774865873d 6479 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6480 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6481 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
screamer 28:0e774865873d 6482 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 6483 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
screamer 28:0e774865873d 6484 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6485 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6486 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6487 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
screamer 28:0e774865873d 6488 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6489 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
screamer 28:0e774865873d 6490 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
screamer 28:0e774865873d 6491 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6492 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
screamer 28:0e774865873d 6493 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
screamer 28:0e774865873d 6494 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6495 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
screamer 28:0e774865873d 6496 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
screamer 28:0e774865873d 6497 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6498 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
screamer 28:0e774865873d 6499 #define DFSDM_FLTCR1_DFEN_Pos (0U)
screamer 28:0e774865873d 6500 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6501 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
screamer 28:0e774865873d 6502
screamer 28:0e774865873d 6503 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
screamer 28:0e774865873d 6504 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
screamer 28:0e774865873d 6505 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 6506 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
screamer 28:0e774865873d 6507 #define DFSDM_FLTCR2_EXCH_Pos (8U)
screamer 28:0e774865873d 6508 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 6509 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
screamer 28:0e774865873d 6510 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
screamer 28:0e774865873d 6511 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6512 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
screamer 28:0e774865873d 6513 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
screamer 28:0e774865873d 6514 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6515 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
screamer 28:0e774865873d 6516 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
screamer 28:0e774865873d 6517 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6518 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
screamer 28:0e774865873d 6519 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
screamer 28:0e774865873d 6520 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6521 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
screamer 28:0e774865873d 6522 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
screamer 28:0e774865873d 6523 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6524 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
screamer 28:0e774865873d 6525 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
screamer 28:0e774865873d 6526 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6527 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
screamer 28:0e774865873d 6528 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
screamer 28:0e774865873d 6529 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6530 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
screamer 28:0e774865873d 6531
screamer 28:0e774865873d 6532 /***************** Bit definition for DFSDM_FLTISR register *******************/
screamer 28:0e774865873d 6533 #define DFSDM_FLTISR_SCDF_Pos (24U)
screamer 28:0e774865873d 6534 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 6535 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
screamer 28:0e774865873d 6536 #define DFSDM_FLTISR_CKABF_Pos (16U)
screamer 28:0e774865873d 6537 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 6538 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
screamer 28:0e774865873d 6539 #define DFSDM_FLTISR_RCIP_Pos (14U)
screamer 28:0e774865873d 6540 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6541 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
screamer 28:0e774865873d 6542 #define DFSDM_FLTISR_JCIP_Pos (13U)
screamer 28:0e774865873d 6543 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6544 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
screamer 28:0e774865873d 6545 #define DFSDM_FLTISR_AWDF_Pos (4U)
screamer 28:0e774865873d 6546 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6547 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
screamer 28:0e774865873d 6548 #define DFSDM_FLTISR_ROVRF_Pos (3U)
screamer 28:0e774865873d 6549 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6550 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
screamer 28:0e774865873d 6551 #define DFSDM_FLTISR_JOVRF_Pos (2U)
screamer 28:0e774865873d 6552 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6553 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
screamer 28:0e774865873d 6554 #define DFSDM_FLTISR_REOCF_Pos (1U)
screamer 28:0e774865873d 6555 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6556 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
screamer 28:0e774865873d 6557 #define DFSDM_FLTISR_JEOCF_Pos (0U)
screamer 28:0e774865873d 6558 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6559 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
screamer 28:0e774865873d 6560
screamer 28:0e774865873d 6561 /***************** Bit definition for DFSDM_FLTICR register *******************/
screamer 28:0e774865873d 6562 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
screamer 28:0e774865873d 6563 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 6564 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
screamer 28:0e774865873d 6565 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
screamer 28:0e774865873d 6566 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 6567 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
screamer 28:0e774865873d 6568 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
screamer 28:0e774865873d 6569 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6570 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
screamer 28:0e774865873d 6571 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
screamer 28:0e774865873d 6572 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6573 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
screamer 28:0e774865873d 6574
screamer 28:0e774865873d 6575 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
screamer 28:0e774865873d 6576 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
screamer 28:0e774865873d 6577 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6578 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
screamer 28:0e774865873d 6579
screamer 28:0e774865873d 6580 /***************** Bit definition for DFSDM_FLTFCR register *******************/
screamer 28:0e774865873d 6581 #define DFSDM_FLTFCR_FORD_Pos (29U)
screamer 28:0e774865873d 6582 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
screamer 28:0e774865873d 6583 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
screamer 28:0e774865873d 6584 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 6585 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 6586 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 6587 #define DFSDM_FLTFCR_FOSR_Pos (16U)
screamer 28:0e774865873d 6588 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
screamer 28:0e774865873d 6589 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
screamer 28:0e774865873d 6590 #define DFSDM_FLTFCR_IOSR_Pos (0U)
screamer 28:0e774865873d 6591 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6592 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
screamer 28:0e774865873d 6593
screamer 28:0e774865873d 6594 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
screamer 28:0e774865873d 6595 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
screamer 28:0e774865873d 6596 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6597 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
screamer 28:0e774865873d 6598 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
screamer 28:0e774865873d 6599 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 6600 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
screamer 28:0e774865873d 6601
screamer 28:0e774865873d 6602 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
screamer 28:0e774865873d 6603 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
screamer 28:0e774865873d 6604 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6605 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
screamer 28:0e774865873d 6606 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
screamer 28:0e774865873d 6607 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6608 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
screamer 28:0e774865873d 6609 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
screamer 28:0e774865873d 6610 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 6611 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
screamer 28:0e774865873d 6612
screamer 28:0e774865873d 6613 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
screamer 28:0e774865873d 6614 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
screamer 28:0e774865873d 6615 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6616 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
screamer 28:0e774865873d 6617 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
screamer 28:0e774865873d 6618 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 6619 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
screamer 28:0e774865873d 6620
screamer 28:0e774865873d 6621 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
screamer 28:0e774865873d 6622 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
screamer 28:0e774865873d 6623 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6624 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
screamer 28:0e774865873d 6625 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
screamer 28:0e774865873d 6626 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 6627 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
screamer 28:0e774865873d 6628
screamer 28:0e774865873d 6629 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
screamer 28:0e774865873d 6630 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
screamer 28:0e774865873d 6631 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 6632 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
screamer 28:0e774865873d 6633 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
screamer 28:0e774865873d 6634 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6635 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
screamer 28:0e774865873d 6636
screamer 28:0e774865873d 6637 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
screamer 28:0e774865873d 6638 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
screamer 28:0e774865873d 6639 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 6640 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
screamer 28:0e774865873d 6641 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
screamer 28:0e774865873d 6642 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 6643 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
screamer 28:0e774865873d 6644
screamer 28:0e774865873d 6645 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
screamer 28:0e774865873d 6646 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
screamer 28:0e774865873d 6647 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6648 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
screamer 28:0e774865873d 6649 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
screamer 28:0e774865873d 6650 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 6651 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
screamer 28:0e774865873d 6652
screamer 28:0e774865873d 6653 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
screamer 28:0e774865873d 6654 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
screamer 28:0e774865873d 6655 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
screamer 28:0e774865873d 6656 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
screamer 28:0e774865873d 6657 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
screamer 28:0e774865873d 6658 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 6659 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
screamer 28:0e774865873d 6660
screamer 28:0e774865873d 6661 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
screamer 28:0e774865873d 6662 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
screamer 28:0e774865873d 6663 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
screamer 28:0e774865873d 6664 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
screamer 28:0e774865873d 6665
screamer 28:0e774865873d 6666 /******************************************************************************/
screamer 28:0e774865873d 6667 /* */
screamer 28:0e774865873d 6668 /* DMA Controller (DMA) */
screamer 28:0e774865873d 6669 /* */
screamer 28:0e774865873d 6670 /******************************************************************************/
screamer 28:0e774865873d 6671
screamer 28:0e774865873d 6672 /******************* Bit definition for DMA_ISR register ********************/
screamer 28:0e774865873d 6673 #define DMA_ISR_GIF1_Pos (0U)
screamer 28:0e774865873d 6674 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6675 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
screamer 28:0e774865873d 6676 #define DMA_ISR_TCIF1_Pos (1U)
screamer 28:0e774865873d 6677 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6678 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
screamer 28:0e774865873d 6679 #define DMA_ISR_HTIF1_Pos (2U)
screamer 28:0e774865873d 6680 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6681 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
screamer 28:0e774865873d 6682 #define DMA_ISR_TEIF1_Pos (3U)
screamer 28:0e774865873d 6683 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6684 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
screamer 28:0e774865873d 6685 #define DMA_ISR_GIF2_Pos (4U)
screamer 28:0e774865873d 6686 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6687 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
screamer 28:0e774865873d 6688 #define DMA_ISR_TCIF2_Pos (5U)
screamer 28:0e774865873d 6689 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6690 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
screamer 28:0e774865873d 6691 #define DMA_ISR_HTIF2_Pos (6U)
screamer 28:0e774865873d 6692 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6693 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
screamer 28:0e774865873d 6694 #define DMA_ISR_TEIF2_Pos (7U)
screamer 28:0e774865873d 6695 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6696 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
screamer 28:0e774865873d 6697 #define DMA_ISR_GIF3_Pos (8U)
screamer 28:0e774865873d 6698 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6699 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
screamer 28:0e774865873d 6700 #define DMA_ISR_TCIF3_Pos (9U)
screamer 28:0e774865873d 6701 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6702 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
screamer 28:0e774865873d 6703 #define DMA_ISR_HTIF3_Pos (10U)
screamer 28:0e774865873d 6704 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6705 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
screamer 28:0e774865873d 6706 #define DMA_ISR_TEIF3_Pos (11U)
screamer 28:0e774865873d 6707 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 6708 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
screamer 28:0e774865873d 6709 #define DMA_ISR_GIF4_Pos (12U)
screamer 28:0e774865873d 6710 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6711 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
screamer 28:0e774865873d 6712 #define DMA_ISR_TCIF4_Pos (13U)
screamer 28:0e774865873d 6713 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6714 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
screamer 28:0e774865873d 6715 #define DMA_ISR_HTIF4_Pos (14U)
screamer 28:0e774865873d 6716 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6717 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
screamer 28:0e774865873d 6718 #define DMA_ISR_TEIF4_Pos (15U)
screamer 28:0e774865873d 6719 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 6720 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
screamer 28:0e774865873d 6721 #define DMA_ISR_GIF5_Pos (16U)
screamer 28:0e774865873d 6722 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 6723 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
screamer 28:0e774865873d 6724 #define DMA_ISR_TCIF5_Pos (17U)
screamer 28:0e774865873d 6725 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 6726 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
screamer 28:0e774865873d 6727 #define DMA_ISR_HTIF5_Pos (18U)
screamer 28:0e774865873d 6728 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6729 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
screamer 28:0e774865873d 6730 #define DMA_ISR_TEIF5_Pos (19U)
screamer 28:0e774865873d 6731 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 6732 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
screamer 28:0e774865873d 6733 #define DMA_ISR_GIF6_Pos (20U)
screamer 28:0e774865873d 6734 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 6735 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
screamer 28:0e774865873d 6736 #define DMA_ISR_TCIF6_Pos (21U)
screamer 28:0e774865873d 6737 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 6738 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
screamer 28:0e774865873d 6739 #define DMA_ISR_HTIF6_Pos (22U)
screamer 28:0e774865873d 6740 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 6741 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
screamer 28:0e774865873d 6742 #define DMA_ISR_TEIF6_Pos (23U)
screamer 28:0e774865873d 6743 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 6744 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
screamer 28:0e774865873d 6745 #define DMA_ISR_GIF7_Pos (24U)
screamer 28:0e774865873d 6746 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 6747 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
screamer 28:0e774865873d 6748 #define DMA_ISR_TCIF7_Pos (25U)
screamer 28:0e774865873d 6749 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 6750 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
screamer 28:0e774865873d 6751 #define DMA_ISR_HTIF7_Pos (26U)
screamer 28:0e774865873d 6752 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 6753 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
screamer 28:0e774865873d 6754 #define DMA_ISR_TEIF7_Pos (27U)
screamer 28:0e774865873d 6755 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 6756 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
screamer 28:0e774865873d 6757
screamer 28:0e774865873d 6758 /******************* Bit definition for DMA_IFCR register *******************/
screamer 28:0e774865873d 6759 #define DMA_IFCR_CGIF1_Pos (0U)
screamer 28:0e774865873d 6760 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6761 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
screamer 28:0e774865873d 6762 #define DMA_IFCR_CTCIF1_Pos (1U)
screamer 28:0e774865873d 6763 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6764 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
screamer 28:0e774865873d 6765 #define DMA_IFCR_CHTIF1_Pos (2U)
screamer 28:0e774865873d 6766 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6767 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
screamer 28:0e774865873d 6768 #define DMA_IFCR_CTEIF1_Pos (3U)
screamer 28:0e774865873d 6769 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6770 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
screamer 28:0e774865873d 6771 #define DMA_IFCR_CGIF2_Pos (4U)
screamer 28:0e774865873d 6772 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6773 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
screamer 28:0e774865873d 6774 #define DMA_IFCR_CTCIF2_Pos (5U)
screamer 28:0e774865873d 6775 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6776 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
screamer 28:0e774865873d 6777 #define DMA_IFCR_CHTIF2_Pos (6U)
screamer 28:0e774865873d 6778 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6779 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
screamer 28:0e774865873d 6780 #define DMA_IFCR_CTEIF2_Pos (7U)
screamer 28:0e774865873d 6781 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6782 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
screamer 28:0e774865873d 6783 #define DMA_IFCR_CGIF3_Pos (8U)
screamer 28:0e774865873d 6784 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6785 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
screamer 28:0e774865873d 6786 #define DMA_IFCR_CTCIF3_Pos (9U)
screamer 28:0e774865873d 6787 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6788 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
screamer 28:0e774865873d 6789 #define DMA_IFCR_CHTIF3_Pos (10U)
screamer 28:0e774865873d 6790 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6791 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
screamer 28:0e774865873d 6792 #define DMA_IFCR_CTEIF3_Pos (11U)
screamer 28:0e774865873d 6793 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 6794 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
screamer 28:0e774865873d 6795 #define DMA_IFCR_CGIF4_Pos (12U)
screamer 28:0e774865873d 6796 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6797 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
screamer 28:0e774865873d 6798 #define DMA_IFCR_CTCIF4_Pos (13U)
screamer 28:0e774865873d 6799 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6800 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
screamer 28:0e774865873d 6801 #define DMA_IFCR_CHTIF4_Pos (14U)
screamer 28:0e774865873d 6802 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6803 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
screamer 28:0e774865873d 6804 #define DMA_IFCR_CTEIF4_Pos (15U)
screamer 28:0e774865873d 6805 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 6806 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
screamer 28:0e774865873d 6807 #define DMA_IFCR_CGIF5_Pos (16U)
screamer 28:0e774865873d 6808 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 6809 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
screamer 28:0e774865873d 6810 #define DMA_IFCR_CTCIF5_Pos (17U)
screamer 28:0e774865873d 6811 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 6812 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
screamer 28:0e774865873d 6813 #define DMA_IFCR_CHTIF5_Pos (18U)
screamer 28:0e774865873d 6814 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6815 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
screamer 28:0e774865873d 6816 #define DMA_IFCR_CTEIF5_Pos (19U)
screamer 28:0e774865873d 6817 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 6818 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
screamer 28:0e774865873d 6819 #define DMA_IFCR_CGIF6_Pos (20U)
screamer 28:0e774865873d 6820 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 6821 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
screamer 28:0e774865873d 6822 #define DMA_IFCR_CTCIF6_Pos (21U)
screamer 28:0e774865873d 6823 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 6824 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
screamer 28:0e774865873d 6825 #define DMA_IFCR_CHTIF6_Pos (22U)
screamer 28:0e774865873d 6826 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 6827 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
screamer 28:0e774865873d 6828 #define DMA_IFCR_CTEIF6_Pos (23U)
screamer 28:0e774865873d 6829 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 6830 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
screamer 28:0e774865873d 6831 #define DMA_IFCR_CGIF7_Pos (24U)
screamer 28:0e774865873d 6832 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 6833 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
screamer 28:0e774865873d 6834 #define DMA_IFCR_CTCIF7_Pos (25U)
screamer 28:0e774865873d 6835 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 6836 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
screamer 28:0e774865873d 6837 #define DMA_IFCR_CHTIF7_Pos (26U)
screamer 28:0e774865873d 6838 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 6839 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
screamer 28:0e774865873d 6840 #define DMA_IFCR_CTEIF7_Pos (27U)
screamer 28:0e774865873d 6841 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 6842 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
screamer 28:0e774865873d 6843
screamer 28:0e774865873d 6844 /******************* Bit definition for DMA_CCR register ********************/
screamer 28:0e774865873d 6845 #define DMA_CCR_EN_Pos (0U)
screamer 28:0e774865873d 6846 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6847 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
screamer 28:0e774865873d 6848 #define DMA_CCR_TCIE_Pos (1U)
screamer 28:0e774865873d 6849 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6850 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
screamer 28:0e774865873d 6851 #define DMA_CCR_HTIE_Pos (2U)
screamer 28:0e774865873d 6852 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6853 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
screamer 28:0e774865873d 6854 #define DMA_CCR_TEIE_Pos (3U)
screamer 28:0e774865873d 6855 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6856 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
screamer 28:0e774865873d 6857 #define DMA_CCR_DIR_Pos (4U)
screamer 28:0e774865873d 6858 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6859 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
screamer 28:0e774865873d 6860 #define DMA_CCR_CIRC_Pos (5U)
screamer 28:0e774865873d 6861 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6862 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
screamer 28:0e774865873d 6863 #define DMA_CCR_PINC_Pos (6U)
screamer 28:0e774865873d 6864 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6865 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
screamer 28:0e774865873d 6866 #define DMA_CCR_MINC_Pos (7U)
screamer 28:0e774865873d 6867 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6868 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
screamer 28:0e774865873d 6869
screamer 28:0e774865873d 6870 #define DMA_CCR_PSIZE_Pos (8U)
screamer 28:0e774865873d 6871 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 6872 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
screamer 28:0e774865873d 6873 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6874 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6875
screamer 28:0e774865873d 6876 #define DMA_CCR_MSIZE_Pos (10U)
screamer 28:0e774865873d 6877 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 6878 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
screamer 28:0e774865873d 6879 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6880 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 6881
screamer 28:0e774865873d 6882 #define DMA_CCR_PL_Pos (12U)
screamer 28:0e774865873d 6883 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 6884 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
screamer 28:0e774865873d 6885 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6886 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6887
screamer 28:0e774865873d 6888 #define DMA_CCR_MEM2MEM_Pos (14U)
screamer 28:0e774865873d 6889 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6890 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
screamer 28:0e774865873d 6891
screamer 28:0e774865873d 6892 /****************** Bit definition for DMA_CNDTR register *******************/
screamer 28:0e774865873d 6893 #define DMA_CNDTR_NDT_Pos (0U)
screamer 28:0e774865873d 6894 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 6895 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
screamer 28:0e774865873d 6896
screamer 28:0e774865873d 6897 /****************** Bit definition for DMA_CPAR register ********************/
screamer 28:0e774865873d 6898 #define DMA_CPAR_PA_Pos (0U)
screamer 28:0e774865873d 6899 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 6900 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
screamer 28:0e774865873d 6901
screamer 28:0e774865873d 6902 /****************** Bit definition for DMA_CMAR register ********************/
screamer 28:0e774865873d 6903 #define DMA_CMAR_MA_Pos (0U)
screamer 28:0e774865873d 6904 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 6905 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
screamer 28:0e774865873d 6906
screamer 28:0e774865873d 6907
screamer 28:0e774865873d 6908 /******************* Bit definition for DMA_CSELR register *******************/
screamer 28:0e774865873d 6909 #define DMA_CSELR_C1S_Pos (0U)
screamer 28:0e774865873d 6910 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 6911 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
screamer 28:0e774865873d 6912 #define DMA_CSELR_C2S_Pos (4U)
screamer 28:0e774865873d 6913 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 6914 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
screamer 28:0e774865873d 6915 #define DMA_CSELR_C3S_Pos (8U)
screamer 28:0e774865873d 6916 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 6917 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
screamer 28:0e774865873d 6918 #define DMA_CSELR_C4S_Pos (12U)
screamer 28:0e774865873d 6919 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
screamer 28:0e774865873d 6920 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
screamer 28:0e774865873d 6921 #define DMA_CSELR_C5S_Pos (16U)
screamer 28:0e774865873d 6922 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 6923 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
screamer 28:0e774865873d 6924 #define DMA_CSELR_C6S_Pos (20U)
screamer 28:0e774865873d 6925 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 6926 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
screamer 28:0e774865873d 6927 #define DMA_CSELR_C7S_Pos (24U)
screamer 28:0e774865873d 6928 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 6929 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
screamer 28:0e774865873d 6930
screamer 28:0e774865873d 6931 /******************************************************************************/
screamer 28:0e774865873d 6932 /* */
screamer 28:0e774865873d 6933 /* External Interrupt/Event Controller */
screamer 28:0e774865873d 6934 /* */
screamer 28:0e774865873d 6935 /******************************************************************************/
screamer 28:0e774865873d 6936 /******************* Bit definition for EXTI_IMR1 register ******************/
screamer 28:0e774865873d 6937 #define EXTI_IMR1_IM0_Pos (0U)
screamer 28:0e774865873d 6938 #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 6939 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
screamer 28:0e774865873d 6940 #define EXTI_IMR1_IM1_Pos (1U)
screamer 28:0e774865873d 6941 #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 6942 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
screamer 28:0e774865873d 6943 #define EXTI_IMR1_IM2_Pos (2U)
screamer 28:0e774865873d 6944 #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 6945 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
screamer 28:0e774865873d 6946 #define EXTI_IMR1_IM3_Pos (3U)
screamer 28:0e774865873d 6947 #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 6948 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
screamer 28:0e774865873d 6949 #define EXTI_IMR1_IM4_Pos (4U)
screamer 28:0e774865873d 6950 #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 6951 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
screamer 28:0e774865873d 6952 #define EXTI_IMR1_IM5_Pos (5U)
screamer 28:0e774865873d 6953 #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 6954 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
screamer 28:0e774865873d 6955 #define EXTI_IMR1_IM6_Pos (6U)
screamer 28:0e774865873d 6956 #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 6957 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
screamer 28:0e774865873d 6958 #define EXTI_IMR1_IM7_Pos (7U)
screamer 28:0e774865873d 6959 #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 6960 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
screamer 28:0e774865873d 6961 #define EXTI_IMR1_IM8_Pos (8U)
screamer 28:0e774865873d 6962 #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 6963 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
screamer 28:0e774865873d 6964 #define EXTI_IMR1_IM9_Pos (9U)
screamer 28:0e774865873d 6965 #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 6966 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
screamer 28:0e774865873d 6967 #define EXTI_IMR1_IM10_Pos (10U)
screamer 28:0e774865873d 6968 #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 6969 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
screamer 28:0e774865873d 6970 #define EXTI_IMR1_IM11_Pos (11U)
screamer 28:0e774865873d 6971 #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 6972 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
screamer 28:0e774865873d 6973 #define EXTI_IMR1_IM12_Pos (12U)
screamer 28:0e774865873d 6974 #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 6975 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
screamer 28:0e774865873d 6976 #define EXTI_IMR1_IM13_Pos (13U)
screamer 28:0e774865873d 6977 #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 6978 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
screamer 28:0e774865873d 6979 #define EXTI_IMR1_IM14_Pos (14U)
screamer 28:0e774865873d 6980 #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 6981 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
screamer 28:0e774865873d 6982 #define EXTI_IMR1_IM15_Pos (15U)
screamer 28:0e774865873d 6983 #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 6984 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
screamer 28:0e774865873d 6985 #define EXTI_IMR1_IM16_Pos (16U)
screamer 28:0e774865873d 6986 #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 6987 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
screamer 28:0e774865873d 6988 #define EXTI_IMR1_IM17_Pos (17U)
screamer 28:0e774865873d 6989 #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 6990 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
screamer 28:0e774865873d 6991 #define EXTI_IMR1_IM18_Pos (18U)
screamer 28:0e774865873d 6992 #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 6993 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
screamer 28:0e774865873d 6994 #define EXTI_IMR1_IM19_Pos (19U)
screamer 28:0e774865873d 6995 #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 6996 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
screamer 28:0e774865873d 6997 #define EXTI_IMR1_IM20_Pos (20U)
screamer 28:0e774865873d 6998 #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 6999 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
screamer 28:0e774865873d 7000 #define EXTI_IMR1_IM21_Pos (21U)
screamer 28:0e774865873d 7001 #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7002 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
screamer 28:0e774865873d 7003 #define EXTI_IMR1_IM22_Pos (22U)
screamer 28:0e774865873d 7004 #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7005 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
screamer 28:0e774865873d 7006 #define EXTI_IMR1_IM23_Pos (23U)
screamer 28:0e774865873d 7007 #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 7008 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
screamer 28:0e774865873d 7009 #define EXTI_IMR1_IM24_Pos (24U)
screamer 28:0e774865873d 7010 #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 7011 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
screamer 28:0e774865873d 7012 #define EXTI_IMR1_IM25_Pos (25U)
screamer 28:0e774865873d 7013 #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 7014 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
screamer 28:0e774865873d 7015 #define EXTI_IMR1_IM26_Pos (26U)
screamer 28:0e774865873d 7016 #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 7017 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
screamer 28:0e774865873d 7018 #define EXTI_IMR1_IM27_Pos (27U)
screamer 28:0e774865873d 7019 #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 7020 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
screamer 28:0e774865873d 7021 #define EXTI_IMR1_IM28_Pos (28U)
screamer 28:0e774865873d 7022 #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 7023 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
screamer 28:0e774865873d 7024 #define EXTI_IMR1_IM29_Pos (29U)
screamer 28:0e774865873d 7025 #define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 7026 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
screamer 28:0e774865873d 7027 #define EXTI_IMR1_IM30_Pos (30U)
screamer 28:0e774865873d 7028 #define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 7029 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
screamer 28:0e774865873d 7030 #define EXTI_IMR1_IM31_Pos (31U)
screamer 28:0e774865873d 7031 #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 7032 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
screamer 28:0e774865873d 7033 #define EXTI_IMR1_IM_Pos (0U)
screamer 28:0e774865873d 7034 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 7035 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
screamer 28:0e774865873d 7036
screamer 28:0e774865873d 7037 /******************* Bit definition for EXTI_EMR1 register ******************/
screamer 28:0e774865873d 7038 #define EXTI_EMR1_EM0_Pos (0U)
screamer 28:0e774865873d 7039 #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7040 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
screamer 28:0e774865873d 7041 #define EXTI_EMR1_EM1_Pos (1U)
screamer 28:0e774865873d 7042 #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7043 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
screamer 28:0e774865873d 7044 #define EXTI_EMR1_EM2_Pos (2U)
screamer 28:0e774865873d 7045 #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7046 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
screamer 28:0e774865873d 7047 #define EXTI_EMR1_EM3_Pos (3U)
screamer 28:0e774865873d 7048 #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7049 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
screamer 28:0e774865873d 7050 #define EXTI_EMR1_EM4_Pos (4U)
screamer 28:0e774865873d 7051 #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7052 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
screamer 28:0e774865873d 7053 #define EXTI_EMR1_EM5_Pos (5U)
screamer 28:0e774865873d 7054 #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7055 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
screamer 28:0e774865873d 7056 #define EXTI_EMR1_EM6_Pos (6U)
screamer 28:0e774865873d 7057 #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7058 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
screamer 28:0e774865873d 7059 #define EXTI_EMR1_EM7_Pos (7U)
screamer 28:0e774865873d 7060 #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7061 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
screamer 28:0e774865873d 7062 #define EXTI_EMR1_EM8_Pos (8U)
screamer 28:0e774865873d 7063 #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7064 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
screamer 28:0e774865873d 7065 #define EXTI_EMR1_EM9_Pos (9U)
screamer 28:0e774865873d 7066 #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7067 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
screamer 28:0e774865873d 7068 #define EXTI_EMR1_EM10_Pos (10U)
screamer 28:0e774865873d 7069 #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7070 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
screamer 28:0e774865873d 7071 #define EXTI_EMR1_EM11_Pos (11U)
screamer 28:0e774865873d 7072 #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7073 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
screamer 28:0e774865873d 7074 #define EXTI_EMR1_EM12_Pos (12U)
screamer 28:0e774865873d 7075 #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7076 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
screamer 28:0e774865873d 7077 #define EXTI_EMR1_EM13_Pos (13U)
screamer 28:0e774865873d 7078 #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7079 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
screamer 28:0e774865873d 7080 #define EXTI_EMR1_EM14_Pos (14U)
screamer 28:0e774865873d 7081 #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7082 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
screamer 28:0e774865873d 7083 #define EXTI_EMR1_EM15_Pos (15U)
screamer 28:0e774865873d 7084 #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7085 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
screamer 28:0e774865873d 7086 #define EXTI_EMR1_EM16_Pos (16U)
screamer 28:0e774865873d 7087 #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7088 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
screamer 28:0e774865873d 7089 #define EXTI_EMR1_EM17_Pos (17U)
screamer 28:0e774865873d 7090 #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7091 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
screamer 28:0e774865873d 7092 #define EXTI_EMR1_EM18_Pos (18U)
screamer 28:0e774865873d 7093 #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7094 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
screamer 28:0e774865873d 7095 #define EXTI_EMR1_EM19_Pos (19U)
screamer 28:0e774865873d 7096 #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7097 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
screamer 28:0e774865873d 7098 #define EXTI_EMR1_EM20_Pos (20U)
screamer 28:0e774865873d 7099 #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7100 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
screamer 28:0e774865873d 7101 #define EXTI_EMR1_EM21_Pos (21U)
screamer 28:0e774865873d 7102 #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7103 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
screamer 28:0e774865873d 7104 #define EXTI_EMR1_EM22_Pos (22U)
screamer 28:0e774865873d 7105 #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7106 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
screamer 28:0e774865873d 7107 #define EXTI_EMR1_EM23_Pos (23U)
screamer 28:0e774865873d 7108 #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 7109 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
screamer 28:0e774865873d 7110 #define EXTI_EMR1_EM24_Pos (24U)
screamer 28:0e774865873d 7111 #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 7112 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
screamer 28:0e774865873d 7113 #define EXTI_EMR1_EM25_Pos (25U)
screamer 28:0e774865873d 7114 #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 7115 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
screamer 28:0e774865873d 7116 #define EXTI_EMR1_EM26_Pos (26U)
screamer 28:0e774865873d 7117 #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 7118 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
screamer 28:0e774865873d 7119 #define EXTI_EMR1_EM27_Pos (27U)
screamer 28:0e774865873d 7120 #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 7121 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
screamer 28:0e774865873d 7122 #define EXTI_EMR1_EM28_Pos (28U)
screamer 28:0e774865873d 7123 #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 7124 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
screamer 28:0e774865873d 7125 #define EXTI_EMR1_EM29_Pos (29U)
screamer 28:0e774865873d 7126 #define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 7127 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
screamer 28:0e774865873d 7128 #define EXTI_EMR1_EM30_Pos (30U)
screamer 28:0e774865873d 7129 #define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 7130 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
screamer 28:0e774865873d 7131 #define EXTI_EMR1_EM31_Pos (31U)
screamer 28:0e774865873d 7132 #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 7133 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
screamer 28:0e774865873d 7134
screamer 28:0e774865873d 7135 /****************** Bit definition for EXTI_RTSR1 register ******************/
screamer 28:0e774865873d 7136 #define EXTI_RTSR1_RT0_Pos (0U)
screamer 28:0e774865873d 7137 #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7138 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
screamer 28:0e774865873d 7139 #define EXTI_RTSR1_RT1_Pos (1U)
screamer 28:0e774865873d 7140 #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7141 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
screamer 28:0e774865873d 7142 #define EXTI_RTSR1_RT2_Pos (2U)
screamer 28:0e774865873d 7143 #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7144 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
screamer 28:0e774865873d 7145 #define EXTI_RTSR1_RT3_Pos (3U)
screamer 28:0e774865873d 7146 #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7147 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
screamer 28:0e774865873d 7148 #define EXTI_RTSR1_RT4_Pos (4U)
screamer 28:0e774865873d 7149 #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7150 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
screamer 28:0e774865873d 7151 #define EXTI_RTSR1_RT5_Pos (5U)
screamer 28:0e774865873d 7152 #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7153 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
screamer 28:0e774865873d 7154 #define EXTI_RTSR1_RT6_Pos (6U)
screamer 28:0e774865873d 7155 #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7156 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
screamer 28:0e774865873d 7157 #define EXTI_RTSR1_RT7_Pos (7U)
screamer 28:0e774865873d 7158 #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7159 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
screamer 28:0e774865873d 7160 #define EXTI_RTSR1_RT8_Pos (8U)
screamer 28:0e774865873d 7161 #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7162 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
screamer 28:0e774865873d 7163 #define EXTI_RTSR1_RT9_Pos (9U)
screamer 28:0e774865873d 7164 #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7165 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
screamer 28:0e774865873d 7166 #define EXTI_RTSR1_RT10_Pos (10U)
screamer 28:0e774865873d 7167 #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7168 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
screamer 28:0e774865873d 7169 #define EXTI_RTSR1_RT11_Pos (11U)
screamer 28:0e774865873d 7170 #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7171 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
screamer 28:0e774865873d 7172 #define EXTI_RTSR1_RT12_Pos (12U)
screamer 28:0e774865873d 7173 #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7174 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
screamer 28:0e774865873d 7175 #define EXTI_RTSR1_RT13_Pos (13U)
screamer 28:0e774865873d 7176 #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7177 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
screamer 28:0e774865873d 7178 #define EXTI_RTSR1_RT14_Pos (14U)
screamer 28:0e774865873d 7179 #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7180 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
screamer 28:0e774865873d 7181 #define EXTI_RTSR1_RT15_Pos (15U)
screamer 28:0e774865873d 7182 #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7183 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
screamer 28:0e774865873d 7184 #define EXTI_RTSR1_RT16_Pos (16U)
screamer 28:0e774865873d 7185 #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7186 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
screamer 28:0e774865873d 7187 #define EXTI_RTSR1_RT18_Pos (18U)
screamer 28:0e774865873d 7188 #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7189 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
screamer 28:0e774865873d 7190 #define EXTI_RTSR1_RT19_Pos (19U)
screamer 28:0e774865873d 7191 #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7192 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
screamer 28:0e774865873d 7193 #define EXTI_RTSR1_RT20_Pos (20U)
screamer 28:0e774865873d 7194 #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7195 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
screamer 28:0e774865873d 7196 #define EXTI_RTSR1_RT21_Pos (21U)
screamer 28:0e774865873d 7197 #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7198 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
screamer 28:0e774865873d 7199 #define EXTI_RTSR1_RT22_Pos (22U)
screamer 28:0e774865873d 7200 #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7201 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
screamer 28:0e774865873d 7202
screamer 28:0e774865873d 7203 /****************** Bit definition for EXTI_FTSR1 register ******************/
screamer 28:0e774865873d 7204 #define EXTI_FTSR1_FT0_Pos (0U)
screamer 28:0e774865873d 7205 #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7206 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
screamer 28:0e774865873d 7207 #define EXTI_FTSR1_FT1_Pos (1U)
screamer 28:0e774865873d 7208 #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7209 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
screamer 28:0e774865873d 7210 #define EXTI_FTSR1_FT2_Pos (2U)
screamer 28:0e774865873d 7211 #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7212 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
screamer 28:0e774865873d 7213 #define EXTI_FTSR1_FT3_Pos (3U)
screamer 28:0e774865873d 7214 #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7215 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
screamer 28:0e774865873d 7216 #define EXTI_FTSR1_FT4_Pos (4U)
screamer 28:0e774865873d 7217 #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7218 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
screamer 28:0e774865873d 7219 #define EXTI_FTSR1_FT5_Pos (5U)
screamer 28:0e774865873d 7220 #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7221 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
screamer 28:0e774865873d 7222 #define EXTI_FTSR1_FT6_Pos (6U)
screamer 28:0e774865873d 7223 #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7224 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
screamer 28:0e774865873d 7225 #define EXTI_FTSR1_FT7_Pos (7U)
screamer 28:0e774865873d 7226 #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7227 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
screamer 28:0e774865873d 7228 #define EXTI_FTSR1_FT8_Pos (8U)
screamer 28:0e774865873d 7229 #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7230 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
screamer 28:0e774865873d 7231 #define EXTI_FTSR1_FT9_Pos (9U)
screamer 28:0e774865873d 7232 #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7233 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
screamer 28:0e774865873d 7234 #define EXTI_FTSR1_FT10_Pos (10U)
screamer 28:0e774865873d 7235 #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7236 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
screamer 28:0e774865873d 7237 #define EXTI_FTSR1_FT11_Pos (11U)
screamer 28:0e774865873d 7238 #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7239 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
screamer 28:0e774865873d 7240 #define EXTI_FTSR1_FT12_Pos (12U)
screamer 28:0e774865873d 7241 #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7242 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
screamer 28:0e774865873d 7243 #define EXTI_FTSR1_FT13_Pos (13U)
screamer 28:0e774865873d 7244 #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7245 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
screamer 28:0e774865873d 7246 #define EXTI_FTSR1_FT14_Pos (14U)
screamer 28:0e774865873d 7247 #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7248 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
screamer 28:0e774865873d 7249 #define EXTI_FTSR1_FT15_Pos (15U)
screamer 28:0e774865873d 7250 #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7251 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
screamer 28:0e774865873d 7252 #define EXTI_FTSR1_FT16_Pos (16U)
screamer 28:0e774865873d 7253 #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7254 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
screamer 28:0e774865873d 7255 #define EXTI_FTSR1_FT18_Pos (18U)
screamer 28:0e774865873d 7256 #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7257 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
screamer 28:0e774865873d 7258 #define EXTI_FTSR1_FT19_Pos (19U)
screamer 28:0e774865873d 7259 #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7260 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
screamer 28:0e774865873d 7261 #define EXTI_FTSR1_FT20_Pos (20U)
screamer 28:0e774865873d 7262 #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7263 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
screamer 28:0e774865873d 7264 #define EXTI_FTSR1_FT21_Pos (21U)
screamer 28:0e774865873d 7265 #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7266 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
screamer 28:0e774865873d 7267 #define EXTI_FTSR1_FT22_Pos (22U)
screamer 28:0e774865873d 7268 #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7269 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
screamer 28:0e774865873d 7270
screamer 28:0e774865873d 7271 /****************** Bit definition for EXTI_SWIER1 register *****************/
screamer 28:0e774865873d 7272 #define EXTI_SWIER1_SWI0_Pos (0U)
screamer 28:0e774865873d 7273 #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7274 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
screamer 28:0e774865873d 7275 #define EXTI_SWIER1_SWI1_Pos (1U)
screamer 28:0e774865873d 7276 #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7277 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
screamer 28:0e774865873d 7278 #define EXTI_SWIER1_SWI2_Pos (2U)
screamer 28:0e774865873d 7279 #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7280 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
screamer 28:0e774865873d 7281 #define EXTI_SWIER1_SWI3_Pos (3U)
screamer 28:0e774865873d 7282 #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7283 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
screamer 28:0e774865873d 7284 #define EXTI_SWIER1_SWI4_Pos (4U)
screamer 28:0e774865873d 7285 #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7286 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
screamer 28:0e774865873d 7287 #define EXTI_SWIER1_SWI5_Pos (5U)
screamer 28:0e774865873d 7288 #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7289 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
screamer 28:0e774865873d 7290 #define EXTI_SWIER1_SWI6_Pos (6U)
screamer 28:0e774865873d 7291 #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7292 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
screamer 28:0e774865873d 7293 #define EXTI_SWIER1_SWI7_Pos (7U)
screamer 28:0e774865873d 7294 #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7295 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
screamer 28:0e774865873d 7296 #define EXTI_SWIER1_SWI8_Pos (8U)
screamer 28:0e774865873d 7297 #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7298 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
screamer 28:0e774865873d 7299 #define EXTI_SWIER1_SWI9_Pos (9U)
screamer 28:0e774865873d 7300 #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7301 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
screamer 28:0e774865873d 7302 #define EXTI_SWIER1_SWI10_Pos (10U)
screamer 28:0e774865873d 7303 #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7304 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
screamer 28:0e774865873d 7305 #define EXTI_SWIER1_SWI11_Pos (11U)
screamer 28:0e774865873d 7306 #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7307 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
screamer 28:0e774865873d 7308 #define EXTI_SWIER1_SWI12_Pos (12U)
screamer 28:0e774865873d 7309 #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7310 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
screamer 28:0e774865873d 7311 #define EXTI_SWIER1_SWI13_Pos (13U)
screamer 28:0e774865873d 7312 #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7313 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
screamer 28:0e774865873d 7314 #define EXTI_SWIER1_SWI14_Pos (14U)
screamer 28:0e774865873d 7315 #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7316 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
screamer 28:0e774865873d 7317 #define EXTI_SWIER1_SWI15_Pos (15U)
screamer 28:0e774865873d 7318 #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7319 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
screamer 28:0e774865873d 7320 #define EXTI_SWIER1_SWI16_Pos (16U)
screamer 28:0e774865873d 7321 #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7322 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
screamer 28:0e774865873d 7323 #define EXTI_SWIER1_SWI18_Pos (18U)
screamer 28:0e774865873d 7324 #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7325 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
screamer 28:0e774865873d 7326 #define EXTI_SWIER1_SWI19_Pos (19U)
screamer 28:0e774865873d 7327 #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7328 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
screamer 28:0e774865873d 7329 #define EXTI_SWIER1_SWI20_Pos (20U)
screamer 28:0e774865873d 7330 #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7331 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
screamer 28:0e774865873d 7332 #define EXTI_SWIER1_SWI21_Pos (21U)
screamer 28:0e774865873d 7333 #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7334 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
screamer 28:0e774865873d 7335 #define EXTI_SWIER1_SWI22_Pos (22U)
screamer 28:0e774865873d 7336 #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7337 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
screamer 28:0e774865873d 7338
screamer 28:0e774865873d 7339 /******************* Bit definition for EXTI_PR1 register *******************/
screamer 28:0e774865873d 7340 #define EXTI_PR1_PIF0_Pos (0U)
screamer 28:0e774865873d 7341 #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7342 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
screamer 28:0e774865873d 7343 #define EXTI_PR1_PIF1_Pos (1U)
screamer 28:0e774865873d 7344 #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7345 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
screamer 28:0e774865873d 7346 #define EXTI_PR1_PIF2_Pos (2U)
screamer 28:0e774865873d 7347 #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7348 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
screamer 28:0e774865873d 7349 #define EXTI_PR1_PIF3_Pos (3U)
screamer 28:0e774865873d 7350 #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7351 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
screamer 28:0e774865873d 7352 #define EXTI_PR1_PIF4_Pos (4U)
screamer 28:0e774865873d 7353 #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7354 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
screamer 28:0e774865873d 7355 #define EXTI_PR1_PIF5_Pos (5U)
screamer 28:0e774865873d 7356 #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7357 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
screamer 28:0e774865873d 7358 #define EXTI_PR1_PIF6_Pos (6U)
screamer 28:0e774865873d 7359 #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7360 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
screamer 28:0e774865873d 7361 #define EXTI_PR1_PIF7_Pos (7U)
screamer 28:0e774865873d 7362 #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7363 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
screamer 28:0e774865873d 7364 #define EXTI_PR1_PIF8_Pos (8U)
screamer 28:0e774865873d 7365 #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7366 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
screamer 28:0e774865873d 7367 #define EXTI_PR1_PIF9_Pos (9U)
screamer 28:0e774865873d 7368 #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7369 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
screamer 28:0e774865873d 7370 #define EXTI_PR1_PIF10_Pos (10U)
screamer 28:0e774865873d 7371 #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7372 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
screamer 28:0e774865873d 7373 #define EXTI_PR1_PIF11_Pos (11U)
screamer 28:0e774865873d 7374 #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7375 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
screamer 28:0e774865873d 7376 #define EXTI_PR1_PIF12_Pos (12U)
screamer 28:0e774865873d 7377 #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7378 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
screamer 28:0e774865873d 7379 #define EXTI_PR1_PIF13_Pos (13U)
screamer 28:0e774865873d 7380 #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7381 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
screamer 28:0e774865873d 7382 #define EXTI_PR1_PIF14_Pos (14U)
screamer 28:0e774865873d 7383 #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7384 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
screamer 28:0e774865873d 7385 #define EXTI_PR1_PIF15_Pos (15U)
screamer 28:0e774865873d 7386 #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7387 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
screamer 28:0e774865873d 7388 #define EXTI_PR1_PIF16_Pos (16U)
screamer 28:0e774865873d 7389 #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7390 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
screamer 28:0e774865873d 7391 #define EXTI_PR1_PIF18_Pos (18U)
screamer 28:0e774865873d 7392 #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7393 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
screamer 28:0e774865873d 7394 #define EXTI_PR1_PIF19_Pos (19U)
screamer 28:0e774865873d 7395 #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7396 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
screamer 28:0e774865873d 7397 #define EXTI_PR1_PIF20_Pos (20U)
screamer 28:0e774865873d 7398 #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7399 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
screamer 28:0e774865873d 7400 #define EXTI_PR1_PIF21_Pos (21U)
screamer 28:0e774865873d 7401 #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7402 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
screamer 28:0e774865873d 7403 #define EXTI_PR1_PIF22_Pos (22U)
screamer 28:0e774865873d 7404 #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7405 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
screamer 28:0e774865873d 7406
screamer 28:0e774865873d 7407 /******************* Bit definition for EXTI_IMR2 register ******************/
screamer 28:0e774865873d 7408 #define EXTI_IMR2_IM32_Pos (0U)
screamer 28:0e774865873d 7409 #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7410 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
screamer 28:0e774865873d 7411 #define EXTI_IMR2_IM33_Pos (1U)
screamer 28:0e774865873d 7412 #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7413 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
screamer 28:0e774865873d 7414 #define EXTI_IMR2_IM34_Pos (2U)
screamer 28:0e774865873d 7415 #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7416 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
screamer 28:0e774865873d 7417 #define EXTI_IMR2_IM35_Pos (3U)
screamer 28:0e774865873d 7418 #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7419 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
screamer 28:0e774865873d 7420 #define EXTI_IMR2_IM36_Pos (4U)
screamer 28:0e774865873d 7421 #define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7422 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
screamer 28:0e774865873d 7423 #define EXTI_IMR2_IM37_Pos (5U)
screamer 28:0e774865873d 7424 #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7425 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
screamer 28:0e774865873d 7426 #define EXTI_IMR2_IM38_Pos (6U)
screamer 28:0e774865873d 7427 #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7428 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
screamer 28:0e774865873d 7429 #define EXTI_IMR2_IM_Pos (0U)
screamer 28:0e774865873d 7430 #define EXTI_IMR2_IM_Msk (0x7FU << EXTI_IMR2_IM_Pos) /*!< 0x0000007F */
screamer 28:0e774865873d 7431 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
screamer 28:0e774865873d 7432
screamer 28:0e774865873d 7433 /******************* Bit definition for EXTI_EMR2 register ******************/
screamer 28:0e774865873d 7434 #define EXTI_EMR2_EM32_Pos (0U)
screamer 28:0e774865873d 7435 #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7436 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
screamer 28:0e774865873d 7437 #define EXTI_EMR2_EM33_Pos (1U)
screamer 28:0e774865873d 7438 #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7439 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
screamer 28:0e774865873d 7440 #define EXTI_EMR2_EM34_Pos (2U)
screamer 28:0e774865873d 7441 #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7442 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
screamer 28:0e774865873d 7443 #define EXTI_EMR2_EM35_Pos (3U)
screamer 28:0e774865873d 7444 #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7445 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
screamer 28:0e774865873d 7446 #define EXTI_EMR2_EM36_Pos (4U)
screamer 28:0e774865873d 7447 #define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7448 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
screamer 28:0e774865873d 7449 #define EXTI_EMR2_EM37_Pos (5U)
screamer 28:0e774865873d 7450 #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7451 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
screamer 28:0e774865873d 7452 #define EXTI_EMR2_EM38_Pos (6U)
screamer 28:0e774865873d 7453 #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7454 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
screamer 28:0e774865873d 7455 #define EXTI_EMR2_EM_Pos (0U)
screamer 28:0e774865873d 7456 #define EXTI_EMR2_EM_Msk (0x7FU << EXTI_EMR2_EM_Pos) /*!< 0x0000007F */
screamer 28:0e774865873d 7457 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
screamer 28:0e774865873d 7458
screamer 28:0e774865873d 7459 /****************** Bit definition for EXTI_RTSR2 register ******************/
screamer 28:0e774865873d 7460 #define EXTI_RTSR2_RT35_Pos (3U)
screamer 28:0e774865873d 7461 #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7462 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
screamer 28:0e774865873d 7463 #define EXTI_RTSR2_RT36_Pos (4U)
screamer 28:0e774865873d 7464 #define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7465 #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
screamer 28:0e774865873d 7466 #define EXTI_RTSR2_RT37_Pos (5U)
screamer 28:0e774865873d 7467 #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7468 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
screamer 28:0e774865873d 7469 #define EXTI_RTSR2_RT38_Pos (6U)
screamer 28:0e774865873d 7470 #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7471 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
screamer 28:0e774865873d 7472
screamer 28:0e774865873d 7473 /****************** Bit definition for EXTI_FTSR2 register ******************/
screamer 28:0e774865873d 7474 #define EXTI_FTSR2_FT35_Pos (3U)
screamer 28:0e774865873d 7475 #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7476 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
screamer 28:0e774865873d 7477 #define EXTI_FTSR2_FT36_Pos (4U)
screamer 28:0e774865873d 7478 #define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7479 #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
screamer 28:0e774865873d 7480 #define EXTI_FTSR2_FT37_Pos (5U)
screamer 28:0e774865873d 7481 #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7482 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
screamer 28:0e774865873d 7483 #define EXTI_FTSR2_FT38_Pos (6U)
screamer 28:0e774865873d 7484 #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7485 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
screamer 28:0e774865873d 7486
screamer 28:0e774865873d 7487 /****************** Bit definition for EXTI_SWIER2 register *****************/
screamer 28:0e774865873d 7488 #define EXTI_SWIER2_SWI35_Pos (3U)
screamer 28:0e774865873d 7489 #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7490 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
screamer 28:0e774865873d 7491 #define EXTI_SWIER2_SWI36_Pos (4U)
screamer 28:0e774865873d 7492 #define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7493 #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
screamer 28:0e774865873d 7494 #define EXTI_SWIER2_SWI37_Pos (5U)
screamer 28:0e774865873d 7495 #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7496 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
screamer 28:0e774865873d 7497 #define EXTI_SWIER2_SWI38_Pos (6U)
screamer 28:0e774865873d 7498 #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7499 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
screamer 28:0e774865873d 7500
screamer 28:0e774865873d 7501 /******************* Bit definition for EXTI_PR2 register *******************/
screamer 28:0e774865873d 7502 #define EXTI_PR2_PIF35_Pos (3U)
screamer 28:0e774865873d 7503 #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7504 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
screamer 28:0e774865873d 7505 #define EXTI_PR2_PIF36_Pos (4U)
screamer 28:0e774865873d 7506 #define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7507 #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
screamer 28:0e774865873d 7508 #define EXTI_PR2_PIF37_Pos (5U)
screamer 28:0e774865873d 7509 #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7510 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
screamer 28:0e774865873d 7511 #define EXTI_PR2_PIF38_Pos (6U)
screamer 28:0e774865873d 7512 #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7513 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
screamer 28:0e774865873d 7514
screamer 28:0e774865873d 7515
screamer 28:0e774865873d 7516 /******************************************************************************/
screamer 28:0e774865873d 7517 /* */
screamer 28:0e774865873d 7518 /* FLASH */
screamer 28:0e774865873d 7519 /* */
screamer 28:0e774865873d 7520 /******************************************************************************/
screamer 28:0e774865873d 7521 /******************* Bits definition for FLASH_ACR register *****************/
screamer 28:0e774865873d 7522 #define FLASH_ACR_LATENCY_Pos (0U)
screamer 28:0e774865873d 7523 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 7524 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
screamer 28:0e774865873d 7525 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
screamer 28:0e774865873d 7526 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
screamer 28:0e774865873d 7527 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
screamer 28:0e774865873d 7528 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
screamer 28:0e774865873d 7529 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
screamer 28:0e774865873d 7530 #define FLASH_ACR_PRFTEN_Pos (8U)
screamer 28:0e774865873d 7531 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7532 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
screamer 28:0e774865873d 7533 #define FLASH_ACR_ICEN_Pos (9U)
screamer 28:0e774865873d 7534 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7535 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
screamer 28:0e774865873d 7536 #define FLASH_ACR_DCEN_Pos (10U)
screamer 28:0e774865873d 7537 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7538 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
screamer 28:0e774865873d 7539 #define FLASH_ACR_ICRST_Pos (11U)
screamer 28:0e774865873d 7540 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7541 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
screamer 28:0e774865873d 7542 #define FLASH_ACR_DCRST_Pos (12U)
screamer 28:0e774865873d 7543 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7544 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
screamer 28:0e774865873d 7545 #define FLASH_ACR_RUN_PD_Pos (13U)
screamer 28:0e774865873d 7546 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7547 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
screamer 28:0e774865873d 7548 #define FLASH_ACR_SLEEP_PD_Pos (14U)
screamer 28:0e774865873d 7549 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7550 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
screamer 28:0e774865873d 7551
screamer 28:0e774865873d 7552 /******************* Bits definition for FLASH_SR register ******************/
screamer 28:0e774865873d 7553 #define FLASH_SR_EOP_Pos (0U)
screamer 28:0e774865873d 7554 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7555 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
screamer 28:0e774865873d 7556 #define FLASH_SR_OPERR_Pos (1U)
screamer 28:0e774865873d 7557 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7558 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
screamer 28:0e774865873d 7559 #define FLASH_SR_PROGERR_Pos (3U)
screamer 28:0e774865873d 7560 #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7561 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
screamer 28:0e774865873d 7562 #define FLASH_SR_WRPERR_Pos (4U)
screamer 28:0e774865873d 7563 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7564 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
screamer 28:0e774865873d 7565 #define FLASH_SR_PGAERR_Pos (5U)
screamer 28:0e774865873d 7566 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7567 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
screamer 28:0e774865873d 7568 #define FLASH_SR_SIZERR_Pos (6U)
screamer 28:0e774865873d 7569 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7570 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
screamer 28:0e774865873d 7571 #define FLASH_SR_PGSERR_Pos (7U)
screamer 28:0e774865873d 7572 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7573 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
screamer 28:0e774865873d 7574 #define FLASH_SR_MISERR_Pos (8U)
screamer 28:0e774865873d 7575 #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7576 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
screamer 28:0e774865873d 7577 #define FLASH_SR_FASTERR_Pos (9U)
screamer 28:0e774865873d 7578 #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7579 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
screamer 28:0e774865873d 7580 #define FLASH_SR_RDERR_Pos (14U)
screamer 28:0e774865873d 7581 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7582 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
screamer 28:0e774865873d 7583 #define FLASH_SR_OPTVERR_Pos (15U)
screamer 28:0e774865873d 7584 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7585 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
screamer 28:0e774865873d 7586 #define FLASH_SR_BSY_Pos (16U)
screamer 28:0e774865873d 7587 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7588 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
screamer 28:0e774865873d 7589
screamer 28:0e774865873d 7590 /******************* Bits definition for FLASH_CR register ******************/
screamer 28:0e774865873d 7591 #define FLASH_CR_PG_Pos (0U)
screamer 28:0e774865873d 7592 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7593 #define FLASH_CR_PG FLASH_CR_PG_Msk
screamer 28:0e774865873d 7594 #define FLASH_CR_PER_Pos (1U)
screamer 28:0e774865873d 7595 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7596 #define FLASH_CR_PER FLASH_CR_PER_Msk
screamer 28:0e774865873d 7597 #define FLASH_CR_MER1_Pos (2U)
screamer 28:0e774865873d 7598 #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7599 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
screamer 28:0e774865873d 7600 #define FLASH_CR_PNB_Pos (3U)
screamer 28:0e774865873d 7601 #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
screamer 28:0e774865873d 7602 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
screamer 28:0e774865873d 7603 #define FLASH_CR_BKER_Pos (11U)
screamer 28:0e774865873d 7604 #define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7605 #define FLASH_CR_BKER FLASH_CR_BKER_Msk
screamer 28:0e774865873d 7606 #define FLASH_CR_MER2_Pos (15U)
screamer 28:0e774865873d 7607 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7608 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
screamer 28:0e774865873d 7609 #define FLASH_CR_STRT_Pos (16U)
screamer 28:0e774865873d 7610 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7611 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
screamer 28:0e774865873d 7612 #define FLASH_CR_OPTSTRT_Pos (17U)
screamer 28:0e774865873d 7613 #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7614 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
screamer 28:0e774865873d 7615 #define FLASH_CR_FSTPG_Pos (18U)
screamer 28:0e774865873d 7616 #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7617 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
screamer 28:0e774865873d 7618 #define FLASH_CR_EOPIE_Pos (24U)
screamer 28:0e774865873d 7619 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 7620 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
screamer 28:0e774865873d 7621 #define FLASH_CR_ERRIE_Pos (25U)
screamer 28:0e774865873d 7622 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 7623 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
screamer 28:0e774865873d 7624 #define FLASH_CR_RDERRIE_Pos (26U)
screamer 28:0e774865873d 7625 #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 7626 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
screamer 28:0e774865873d 7627 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
screamer 28:0e774865873d 7628 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 7629 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
screamer 28:0e774865873d 7630 #define FLASH_CR_OPTLOCK_Pos (30U)
screamer 28:0e774865873d 7631 #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 7632 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
screamer 28:0e774865873d 7633 #define FLASH_CR_LOCK_Pos (31U)
screamer 28:0e774865873d 7634 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 7635 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
screamer 28:0e774865873d 7636
screamer 28:0e774865873d 7637 /******************* Bits definition for FLASH_ECCR register ***************/
screamer 28:0e774865873d 7638 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
screamer 28:0e774865873d 7639 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 7640 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
screamer 28:0e774865873d 7641 #define FLASH_ECCR_BK_ECC_Pos (19U)
screamer 28:0e774865873d 7642 #define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7643 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
screamer 28:0e774865873d 7644 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
screamer 28:0e774865873d 7645 #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7646 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
screamer 28:0e774865873d 7647 #define FLASH_ECCR_ECCIE_Pos (24U)
screamer 28:0e774865873d 7648 #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 7649 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
screamer 28:0e774865873d 7650 #define FLASH_ECCR_ECCC_Pos (30U)
screamer 28:0e774865873d 7651 #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 7652 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
screamer 28:0e774865873d 7653 #define FLASH_ECCR_ECCD_Pos (31U)
screamer 28:0e774865873d 7654 #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 7655 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
screamer 28:0e774865873d 7656
screamer 28:0e774865873d 7657 /******************* Bits definition for FLASH_OPTR register ***************/
screamer 28:0e774865873d 7658 #define FLASH_OPTR_RDP_Pos (0U)
screamer 28:0e774865873d 7659 #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 7660 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
screamer 28:0e774865873d 7661 #define FLASH_OPTR_BOR_LEV_Pos (8U)
screamer 28:0e774865873d 7662 #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 7663 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
screamer 28:0e774865873d 7664 #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
screamer 28:0e774865873d 7665 #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7666 #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7667 #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 7668 #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7669 #define FLASH_OPTR_nRST_STOP_Pos (12U)
screamer 28:0e774865873d 7670 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7671 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
screamer 28:0e774865873d 7672 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
screamer 28:0e774865873d 7673 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7674 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
screamer 28:0e774865873d 7675 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
screamer 28:0e774865873d 7676 #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7677 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
screamer 28:0e774865873d 7678 #define FLASH_OPTR_IWDG_SW_Pos (16U)
screamer 28:0e774865873d 7679 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7680 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
screamer 28:0e774865873d 7681 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
screamer 28:0e774865873d 7682 #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7683 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
screamer 28:0e774865873d 7684 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
screamer 28:0e774865873d 7685 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7686 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
screamer 28:0e774865873d 7687 #define FLASH_OPTR_WWDG_SW_Pos (19U)
screamer 28:0e774865873d 7688 #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7689 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
screamer 28:0e774865873d 7690 #define FLASH_OPTR_BFB2_Pos (20U)
screamer 28:0e774865873d 7691 #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7692 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
screamer 28:0e774865873d 7693 #define FLASH_OPTR_DUALBANK_Pos (21U)
screamer 28:0e774865873d 7694 #define FLASH_OPTR_DUALBANK_Msk (0x1U << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7695 #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
screamer 28:0e774865873d 7696 #define FLASH_OPTR_nBOOT1_Pos (23U)
screamer 28:0e774865873d 7697 #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 7698 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
screamer 28:0e774865873d 7699 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
screamer 28:0e774865873d 7700 #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 7701 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
screamer 28:0e774865873d 7702 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
screamer 28:0e774865873d 7703 #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 7704 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
screamer 28:0e774865873d 7705
screamer 28:0e774865873d 7706 /****************** Bits definition for FLASH_PCROP1SR register **********/
screamer 28:0e774865873d 7707 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
screamer 28:0e774865873d 7708 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 7709 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
screamer 28:0e774865873d 7710
screamer 28:0e774865873d 7711 /****************** Bits definition for FLASH_PCROP1ER register ***********/
screamer 28:0e774865873d 7712 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
screamer 28:0e774865873d 7713 #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 7714 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
screamer 28:0e774865873d 7715 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
screamer 28:0e774865873d 7716 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 7717 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
screamer 28:0e774865873d 7718
screamer 28:0e774865873d 7719 /****************** Bits definition for FLASH_WRP1AR register ***************/
screamer 28:0e774865873d 7720 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
screamer 28:0e774865873d 7721 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 7722 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
screamer 28:0e774865873d 7723 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
screamer 28:0e774865873d 7724 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 7725 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
screamer 28:0e774865873d 7726
screamer 28:0e774865873d 7727 /****************** Bits definition for FLASH_WRPB1R register ***************/
screamer 28:0e774865873d 7728 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
screamer 28:0e774865873d 7729 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 7730 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
screamer 28:0e774865873d 7731 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
screamer 28:0e774865873d 7732 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 7733 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
screamer 28:0e774865873d 7734
screamer 28:0e774865873d 7735 /****************** Bits definition for FLASH_PCROP2SR register **********/
screamer 28:0e774865873d 7736 #define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
screamer 28:0e774865873d 7737 #define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 7738 #define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
screamer 28:0e774865873d 7739
screamer 28:0e774865873d 7740 /****************** Bits definition for FLASH_PCROP2ER register ***********/
screamer 28:0e774865873d 7741 #define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
screamer 28:0e774865873d 7742 #define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 7743 #define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
screamer 28:0e774865873d 7744
screamer 28:0e774865873d 7745 /****************** Bits definition for FLASH_WRP2AR register ***************/
screamer 28:0e774865873d 7746 #define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
screamer 28:0e774865873d 7747 #define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 7748 #define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
screamer 28:0e774865873d 7749 #define FLASH_WRP2AR_WRP2A_END_Pos (16U)
screamer 28:0e774865873d 7750 #define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 7751 #define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
screamer 28:0e774865873d 7752
screamer 28:0e774865873d 7753 /****************** Bits definition for FLASH_WRP2BR register ***************/
screamer 28:0e774865873d 7754 #define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
screamer 28:0e774865873d 7755 #define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 7756 #define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
screamer 28:0e774865873d 7757 #define FLASH_WRP2BR_WRP2B_END_Pos (16U)
screamer 28:0e774865873d 7758 #define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 7759 #define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
screamer 28:0e774865873d 7760
screamer 28:0e774865873d 7761
screamer 28:0e774865873d 7762 /******************************************************************************/
screamer 28:0e774865873d 7763 /* */
screamer 28:0e774865873d 7764 /* Flexible Memory Controller */
screamer 28:0e774865873d 7765 /* */
screamer 28:0e774865873d 7766 /******************************************************************************/
screamer 28:0e774865873d 7767 /****************** Bit definition for FMC_BCR1 register *******************/
screamer 28:0e774865873d 7768 #define FMC_BCR1_CCLKEN_Pos (20U)
screamer 28:0e774865873d 7769 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7770 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
screamer 28:0e774865873d 7771
screamer 28:0e774865873d 7772 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
screamer 28:0e774865873d 7773 #define FMC_BCRx_MBKEN_Pos (0U)
screamer 28:0e774865873d 7774 #define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7775 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
screamer 28:0e774865873d 7776 #define FMC_BCRx_MUXEN_Pos (1U)
screamer 28:0e774865873d 7777 #define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7778 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
screamer 28:0e774865873d 7779
screamer 28:0e774865873d 7780 #define FMC_BCRx_MTYP_Pos (2U)
screamer 28:0e774865873d 7781 #define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 7782 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
screamer 28:0e774865873d 7783 #define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7784 #define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7785
screamer 28:0e774865873d 7786 #define FMC_BCRx_MWID_Pos (4U)
screamer 28:0e774865873d 7787 #define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 7788 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
screamer 28:0e774865873d 7789 #define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7790 #define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7791
screamer 28:0e774865873d 7792 #define FMC_BCRx_FACCEN_Pos (6U)
screamer 28:0e774865873d 7793 #define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7794 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
screamer 28:0e774865873d 7795 #define FMC_BCRx_BURSTEN_Pos (8U)
screamer 28:0e774865873d 7796 #define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7797 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
screamer 28:0e774865873d 7798 #define FMC_BCRx_WAITPOL_Pos (9U)
screamer 28:0e774865873d 7799 #define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7800 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
screamer 28:0e774865873d 7801 #define FMC_BCRx_WAITCFG_Pos (11U)
screamer 28:0e774865873d 7802 #define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7803 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
screamer 28:0e774865873d 7804 #define FMC_BCRx_WREN_Pos (12U)
screamer 28:0e774865873d 7805 #define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7806 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
screamer 28:0e774865873d 7807 #define FMC_BCRx_WAITEN_Pos (13U)
screamer 28:0e774865873d 7808 #define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7809 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
screamer 28:0e774865873d 7810 #define FMC_BCRx_EXTMOD_Pos (14U)
screamer 28:0e774865873d 7811 #define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7812 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
screamer 28:0e774865873d 7813 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
screamer 28:0e774865873d 7814 #define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7815 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
screamer 28:0e774865873d 7816
screamer 28:0e774865873d 7817 #define FMC_BCRx_CPSIZE_Pos (16U)
screamer 28:0e774865873d 7818 #define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
screamer 28:0e774865873d 7819 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
screamer 28:0e774865873d 7820 #define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7821 #define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7822 #define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7823
screamer 28:0e774865873d 7824 #define FMC_BCRx_CBURSTRW_Pos (19U)
screamer 28:0e774865873d 7825 #define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7826 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
screamer 28:0e774865873d 7827
screamer 28:0e774865873d 7828 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
screamer 28:0e774865873d 7829 #define FMC_BTRx_ADDSET_Pos (0U)
screamer 28:0e774865873d 7830 #define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 7831 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
screamer 28:0e774865873d 7832 #define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7833 #define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7834 #define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7835 #define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7836
screamer 28:0e774865873d 7837 #define FMC_BTRx_ADDHLD_Pos (4U)
screamer 28:0e774865873d 7838 #define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 7839 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
screamer 28:0e774865873d 7840 #define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7841 #define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7842 #define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7843 #define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7844
screamer 28:0e774865873d 7845 #define FMC_BTRx_DATAST_Pos (8U)
screamer 28:0e774865873d 7846 #define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 7847 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
screamer 28:0e774865873d 7848 #define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7849 #define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7850 #define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7851 #define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7852 #define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7853 #define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7854 #define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7855 #define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7856
screamer 28:0e774865873d 7857 #define FMC_BTRx_BUSTURN_Pos (16U)
screamer 28:0e774865873d 7858 #define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 7859 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
screamer 28:0e774865873d 7860 #define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7861 #define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7862 #define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7863 #define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7864
screamer 28:0e774865873d 7865 #define FMC_BTRx_CLKDIV_Pos (20U)
screamer 28:0e774865873d 7866 #define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 7867 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
screamer 28:0e774865873d 7868 #define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 7869 #define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 7870 #define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 7871 #define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 7872
screamer 28:0e774865873d 7873 #define FMC_BTRx_DATLAT_Pos (24U)
screamer 28:0e774865873d 7874 #define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 7875 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
screamer 28:0e774865873d 7876 #define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 7877 #define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 7878 #define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 7879 #define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 7880
screamer 28:0e774865873d 7881 #define FMC_BTRx_ACCMOD_Pos (28U)
screamer 28:0e774865873d 7882 #define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 7883 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
screamer 28:0e774865873d 7884 #define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 7885 #define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 7886
screamer 28:0e774865873d 7887 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
screamer 28:0e774865873d 7888 #define FMC_BWTRx_ADDSET_Pos (0U)
screamer 28:0e774865873d 7889 #define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 7890 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
screamer 28:0e774865873d 7891 #define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7892 #define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7893 #define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7894 #define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7895
screamer 28:0e774865873d 7896 #define FMC_BWTRx_ADDHLD_Pos (4U)
screamer 28:0e774865873d 7897 #define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 7898 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
screamer 28:0e774865873d 7899 #define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7900 #define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7901 #define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7902 #define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 7903
screamer 28:0e774865873d 7904 #define FMC_BWTRx_DATAST_Pos (8U)
screamer 28:0e774865873d 7905 #define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 7906 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
screamer 28:0e774865873d 7907 #define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 7908 #define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7909 #define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7910 #define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7911 #define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7912 #define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7913 #define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7914 #define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7915
screamer 28:0e774865873d 7916 #define FMC_BWTRx_BUSTURN_Pos (16U)
screamer 28:0e774865873d 7917 #define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 7918 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
screamer 28:0e774865873d 7919 #define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7920 #define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7921 #define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7922 #define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7923
screamer 28:0e774865873d 7924 #define FMC_BWTRx_ACCMOD_Pos (28U)
screamer 28:0e774865873d 7925 #define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 7926 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
screamer 28:0e774865873d 7927 #define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 7928 #define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 7929
screamer 28:0e774865873d 7930 /****************** Bit definition for FMC_PCR register ********************/
screamer 28:0e774865873d 7931 #define FMC_PCR_PWAITEN_Pos (1U)
screamer 28:0e774865873d 7932 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7933 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
screamer 28:0e774865873d 7934 #define FMC_PCR_PBKEN_Pos (2U)
screamer 28:0e774865873d 7935 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7936 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
screamer 28:0e774865873d 7937 #define FMC_PCR_PTYP_Pos (3U)
screamer 28:0e774865873d 7938 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7939 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
screamer 28:0e774865873d 7940
screamer 28:0e774865873d 7941 #define FMC_PCR_PWID_Pos (4U)
screamer 28:0e774865873d 7942 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 7943 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
screamer 28:0e774865873d 7944 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7945 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7946
screamer 28:0e774865873d 7947 #define FMC_PCR_ECCEN_Pos (6U)
screamer 28:0e774865873d 7948 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7949 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
screamer 28:0e774865873d 7950
screamer 28:0e774865873d 7951 #define FMC_PCR_TCLR_Pos (9U)
screamer 28:0e774865873d 7952 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
screamer 28:0e774865873d 7953 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
screamer 28:0e774865873d 7954 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 7955 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 7956 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 7957 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 7958
screamer 28:0e774865873d 7959 #define FMC_PCR_TAR_Pos (13U)
screamer 28:0e774865873d 7960 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
screamer 28:0e774865873d 7961 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
screamer 28:0e774865873d 7962 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 7963 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 7964 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 7965 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 7966
screamer 28:0e774865873d 7967 #define FMC_PCR_ECCPS_Pos (17U)
screamer 28:0e774865873d 7968 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
screamer 28:0e774865873d 7969 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
screamer 28:0e774865873d 7970 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 7971 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 7972 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 7973
screamer 28:0e774865873d 7974 /******************* Bit definition for FMC_SR register ********************/
screamer 28:0e774865873d 7975 #define FMC_SR_IRS_Pos (0U)
screamer 28:0e774865873d 7976 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 7977 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
screamer 28:0e774865873d 7978 #define FMC_SR_ILS_Pos (1U)
screamer 28:0e774865873d 7979 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 7980 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
screamer 28:0e774865873d 7981 #define FMC_SR_IFS_Pos (2U)
screamer 28:0e774865873d 7982 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 7983 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
screamer 28:0e774865873d 7984 #define FMC_SR_IREN_Pos (3U)
screamer 28:0e774865873d 7985 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 7986 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
screamer 28:0e774865873d 7987 #define FMC_SR_ILEN_Pos (4U)
screamer 28:0e774865873d 7988 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 7989 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
screamer 28:0e774865873d 7990 #define FMC_SR_IFEN_Pos (5U)
screamer 28:0e774865873d 7991 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 7992 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
screamer 28:0e774865873d 7993 #define FMC_SR_FEMPT_Pos (6U)
screamer 28:0e774865873d 7994 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 7995 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
screamer 28:0e774865873d 7996
screamer 28:0e774865873d 7997 /****************** Bit definition for FMC_PMEM register ******************/
screamer 28:0e774865873d 7998 #define FMC_PMEM_MEMSET_Pos (0U)
screamer 28:0e774865873d 7999 #define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 8000 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
screamer 28:0e774865873d 8001 #define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8002 #define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8003 #define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8004 #define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8005 #define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8006 #define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8007 #define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8008 #define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8009
screamer 28:0e774865873d 8010 #define FMC_PMEM_MEMWAIT_Pos (8U)
screamer 28:0e774865873d 8011 #define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 8012 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
screamer 28:0e774865873d 8013 #define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8014 #define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8015 #define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8016 #define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8017 #define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8018 #define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8019 #define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8020 #define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8021
screamer 28:0e774865873d 8022 #define FMC_PMEM_MEMHOLD_Pos (16U)
screamer 28:0e774865873d 8023 #define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 8024 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
screamer 28:0e774865873d 8025 #define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8026 #define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8027 #define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8028 #define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8029 #define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8030 #define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8031 #define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8032 #define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8033
screamer 28:0e774865873d 8034 #define FMC_PMEM_MEMHIZ_Pos (24U)
screamer 28:0e774865873d 8035 #define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 8036 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
screamer 28:0e774865873d 8037 #define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8038 #define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8039 #define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8040 #define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8041 #define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8042 #define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8043 #define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8044 #define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8045
screamer 28:0e774865873d 8046 /****************** Bit definition for FMC_PATT register *******************/
screamer 28:0e774865873d 8047 #define FMC_PATT_ATTSET_Pos (0U)
screamer 28:0e774865873d 8048 #define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 8049 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
screamer 28:0e774865873d 8050 #define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8051 #define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8052 #define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8053 #define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8054 #define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8055 #define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8056 #define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8057 #define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8058
screamer 28:0e774865873d 8059 #define FMC_PATT_ATTWAIT_Pos (8U)
screamer 28:0e774865873d 8060 #define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 8061 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
screamer 28:0e774865873d 8062 #define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8063 #define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8064 #define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8065 #define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8066 #define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8067 #define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8068 #define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8069 #define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8070
screamer 28:0e774865873d 8071 #define FMC_PATT_ATTHOLD_Pos (16U)
screamer 28:0e774865873d 8072 #define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 8073 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
screamer 28:0e774865873d 8074 #define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8075 #define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8076 #define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8077 #define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8078 #define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8079 #define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8080 #define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8081 #define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8082
screamer 28:0e774865873d 8083 #define FMC_PATT_ATTHIZ_Pos (24U)
screamer 28:0e774865873d 8084 #define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 8085 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
screamer 28:0e774865873d 8086 #define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8087 #define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8088 #define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8089 #define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8090 #define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8091 #define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8092 #define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8093 #define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8094
screamer 28:0e774865873d 8095 /****************** Bit definition for FMC_ECCR register *******************/
screamer 28:0e774865873d 8096 #define FMC_ECCR_ECC_Pos (0U)
screamer 28:0e774865873d 8097 #define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 8098 #define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
screamer 28:0e774865873d 8099
screamer 28:0e774865873d 8100 /******************************************************************************/
screamer 28:0e774865873d 8101 /* */
screamer 28:0e774865873d 8102 /* General Purpose IOs (GPIO) */
screamer 28:0e774865873d 8103 /* */
screamer 28:0e774865873d 8104 /******************************************************************************/
screamer 28:0e774865873d 8105 /****************** Bits definition for GPIO_MODER register *****************/
screamer 28:0e774865873d 8106 #define GPIO_MODER_MODE0_Pos (0U)
screamer 28:0e774865873d 8107 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 8108 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
screamer 28:0e774865873d 8109 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8110 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8111 #define GPIO_MODER_MODE1_Pos (2U)
screamer 28:0e774865873d 8112 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 8113 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
screamer 28:0e774865873d 8114 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8115 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8116 #define GPIO_MODER_MODE2_Pos (4U)
screamer 28:0e774865873d 8117 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 8118 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
screamer 28:0e774865873d 8119 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8120 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8121 #define GPIO_MODER_MODE3_Pos (6U)
screamer 28:0e774865873d 8122 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 8123 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
screamer 28:0e774865873d 8124 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8125 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8126 #define GPIO_MODER_MODE4_Pos (8U)
screamer 28:0e774865873d 8127 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 8128 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
screamer 28:0e774865873d 8129 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8130 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8131 #define GPIO_MODER_MODE5_Pos (10U)
screamer 28:0e774865873d 8132 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 8133 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
screamer 28:0e774865873d 8134 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8135 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8136 #define GPIO_MODER_MODE6_Pos (12U)
screamer 28:0e774865873d 8137 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 8138 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
screamer 28:0e774865873d 8139 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8140 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8141 #define GPIO_MODER_MODE7_Pos (14U)
screamer 28:0e774865873d 8142 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 8143 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
screamer 28:0e774865873d 8144 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8145 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8146 #define GPIO_MODER_MODE8_Pos (16U)
screamer 28:0e774865873d 8147 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 8148 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
screamer 28:0e774865873d 8149 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8150 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8151 #define GPIO_MODER_MODE9_Pos (18U)
screamer 28:0e774865873d 8152 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 8153 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
screamer 28:0e774865873d 8154 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8155 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8156 #define GPIO_MODER_MODE10_Pos (20U)
screamer 28:0e774865873d 8157 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 8158 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
screamer 28:0e774865873d 8159 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8160 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8161 #define GPIO_MODER_MODE11_Pos (22U)
screamer 28:0e774865873d 8162 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
screamer 28:0e774865873d 8163 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
screamer 28:0e774865873d 8164 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8165 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8166 #define GPIO_MODER_MODE12_Pos (24U)
screamer 28:0e774865873d 8167 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 8168 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
screamer 28:0e774865873d 8169 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8170 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8171 #define GPIO_MODER_MODE13_Pos (26U)
screamer 28:0e774865873d 8172 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
screamer 28:0e774865873d 8173 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
screamer 28:0e774865873d 8174 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8175 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8176 #define GPIO_MODER_MODE14_Pos (28U)
screamer 28:0e774865873d 8177 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 8178 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
screamer 28:0e774865873d 8179 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8180 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8181 #define GPIO_MODER_MODE15_Pos (30U)
screamer 28:0e774865873d 8182 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
screamer 28:0e774865873d 8183 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
screamer 28:0e774865873d 8184 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8185 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8186
screamer 28:0e774865873d 8187 /* Legacy defines */
screamer 28:0e774865873d 8188 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
screamer 28:0e774865873d 8189 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
screamer 28:0e774865873d 8190 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
screamer 28:0e774865873d 8191 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
screamer 28:0e774865873d 8192 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
screamer 28:0e774865873d 8193 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
screamer 28:0e774865873d 8194 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
screamer 28:0e774865873d 8195 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
screamer 28:0e774865873d 8196 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
screamer 28:0e774865873d 8197 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
screamer 28:0e774865873d 8198 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
screamer 28:0e774865873d 8199 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
screamer 28:0e774865873d 8200 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
screamer 28:0e774865873d 8201 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
screamer 28:0e774865873d 8202 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
screamer 28:0e774865873d 8203 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
screamer 28:0e774865873d 8204 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
screamer 28:0e774865873d 8205 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
screamer 28:0e774865873d 8206 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
screamer 28:0e774865873d 8207 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
screamer 28:0e774865873d 8208 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
screamer 28:0e774865873d 8209 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
screamer 28:0e774865873d 8210 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
screamer 28:0e774865873d 8211 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
screamer 28:0e774865873d 8212 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
screamer 28:0e774865873d 8213 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
screamer 28:0e774865873d 8214 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
screamer 28:0e774865873d 8215 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
screamer 28:0e774865873d 8216 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
screamer 28:0e774865873d 8217 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
screamer 28:0e774865873d 8218 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
screamer 28:0e774865873d 8219 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
screamer 28:0e774865873d 8220 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
screamer 28:0e774865873d 8221 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
screamer 28:0e774865873d 8222 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
screamer 28:0e774865873d 8223 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
screamer 28:0e774865873d 8224 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
screamer 28:0e774865873d 8225 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
screamer 28:0e774865873d 8226 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
screamer 28:0e774865873d 8227 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
screamer 28:0e774865873d 8228 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
screamer 28:0e774865873d 8229 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
screamer 28:0e774865873d 8230 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
screamer 28:0e774865873d 8231 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
screamer 28:0e774865873d 8232 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
screamer 28:0e774865873d 8233 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
screamer 28:0e774865873d 8234 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
screamer 28:0e774865873d 8235 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
screamer 28:0e774865873d 8236
screamer 28:0e774865873d 8237 /****************** Bits definition for GPIO_OTYPER register ****************/
screamer 28:0e774865873d 8238 #define GPIO_OTYPER_OT0_Pos (0U)
screamer 28:0e774865873d 8239 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8240 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
screamer 28:0e774865873d 8241 #define GPIO_OTYPER_OT1_Pos (1U)
screamer 28:0e774865873d 8242 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8243 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
screamer 28:0e774865873d 8244 #define GPIO_OTYPER_OT2_Pos (2U)
screamer 28:0e774865873d 8245 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8246 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
screamer 28:0e774865873d 8247 #define GPIO_OTYPER_OT3_Pos (3U)
screamer 28:0e774865873d 8248 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8249 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
screamer 28:0e774865873d 8250 #define GPIO_OTYPER_OT4_Pos (4U)
screamer 28:0e774865873d 8251 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8252 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
screamer 28:0e774865873d 8253 #define GPIO_OTYPER_OT5_Pos (5U)
screamer 28:0e774865873d 8254 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8255 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
screamer 28:0e774865873d 8256 #define GPIO_OTYPER_OT6_Pos (6U)
screamer 28:0e774865873d 8257 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8258 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
screamer 28:0e774865873d 8259 #define GPIO_OTYPER_OT7_Pos (7U)
screamer 28:0e774865873d 8260 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8261 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
screamer 28:0e774865873d 8262 #define GPIO_OTYPER_OT8_Pos (8U)
screamer 28:0e774865873d 8263 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8264 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
screamer 28:0e774865873d 8265 #define GPIO_OTYPER_OT9_Pos (9U)
screamer 28:0e774865873d 8266 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8267 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
screamer 28:0e774865873d 8268 #define GPIO_OTYPER_OT10_Pos (10U)
screamer 28:0e774865873d 8269 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8270 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
screamer 28:0e774865873d 8271 #define GPIO_OTYPER_OT11_Pos (11U)
screamer 28:0e774865873d 8272 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8273 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
screamer 28:0e774865873d 8274 #define GPIO_OTYPER_OT12_Pos (12U)
screamer 28:0e774865873d 8275 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8276 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
screamer 28:0e774865873d 8277 #define GPIO_OTYPER_OT13_Pos (13U)
screamer 28:0e774865873d 8278 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8279 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
screamer 28:0e774865873d 8280 #define GPIO_OTYPER_OT14_Pos (14U)
screamer 28:0e774865873d 8281 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8282 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
screamer 28:0e774865873d 8283 #define GPIO_OTYPER_OT15_Pos (15U)
screamer 28:0e774865873d 8284 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8285 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
screamer 28:0e774865873d 8286
screamer 28:0e774865873d 8287 /* Legacy defines */
screamer 28:0e774865873d 8288 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
screamer 28:0e774865873d 8289 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
screamer 28:0e774865873d 8290 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
screamer 28:0e774865873d 8291 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
screamer 28:0e774865873d 8292 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
screamer 28:0e774865873d 8293 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
screamer 28:0e774865873d 8294 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
screamer 28:0e774865873d 8295 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
screamer 28:0e774865873d 8296 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
screamer 28:0e774865873d 8297 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
screamer 28:0e774865873d 8298 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
screamer 28:0e774865873d 8299 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
screamer 28:0e774865873d 8300 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
screamer 28:0e774865873d 8301 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
screamer 28:0e774865873d 8302 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
screamer 28:0e774865873d 8303 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
screamer 28:0e774865873d 8304
screamer 28:0e774865873d 8305 /****************** Bits definition for GPIO_OSPEEDR register ***************/
screamer 28:0e774865873d 8306 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
screamer 28:0e774865873d 8307 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 8308 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
screamer 28:0e774865873d 8309 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8310 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8311 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
screamer 28:0e774865873d 8312 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 8313 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
screamer 28:0e774865873d 8314 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8315 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8316 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
screamer 28:0e774865873d 8317 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 8318 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
screamer 28:0e774865873d 8319 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8320 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8321 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
screamer 28:0e774865873d 8322 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 8323 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
screamer 28:0e774865873d 8324 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8325 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8326 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
screamer 28:0e774865873d 8327 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 8328 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
screamer 28:0e774865873d 8329 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8330 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8331 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
screamer 28:0e774865873d 8332 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 8333 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
screamer 28:0e774865873d 8334 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8335 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8336 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
screamer 28:0e774865873d 8337 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 8338 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
screamer 28:0e774865873d 8339 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8340 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8341 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
screamer 28:0e774865873d 8342 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 8343 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
screamer 28:0e774865873d 8344 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8345 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8346 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
screamer 28:0e774865873d 8347 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 8348 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
screamer 28:0e774865873d 8349 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8350 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8351 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
screamer 28:0e774865873d 8352 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 8353 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
screamer 28:0e774865873d 8354 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8355 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8356 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
screamer 28:0e774865873d 8357 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 8358 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
screamer 28:0e774865873d 8359 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8360 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8361 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
screamer 28:0e774865873d 8362 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
screamer 28:0e774865873d 8363 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
screamer 28:0e774865873d 8364 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8365 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8366 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
screamer 28:0e774865873d 8367 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 8368 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
screamer 28:0e774865873d 8369 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8370 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8371 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
screamer 28:0e774865873d 8372 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
screamer 28:0e774865873d 8373 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
screamer 28:0e774865873d 8374 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8375 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8376 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
screamer 28:0e774865873d 8377 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 8378 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
screamer 28:0e774865873d 8379 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8380 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8381 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
screamer 28:0e774865873d 8382 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
screamer 28:0e774865873d 8383 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
screamer 28:0e774865873d 8384 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8385 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8386
screamer 28:0e774865873d 8387 /* Legacy defines */
screamer 28:0e774865873d 8388 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
screamer 28:0e774865873d 8389 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
screamer 28:0e774865873d 8390 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
screamer 28:0e774865873d 8391 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
screamer 28:0e774865873d 8392 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
screamer 28:0e774865873d 8393 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
screamer 28:0e774865873d 8394 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
screamer 28:0e774865873d 8395 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
screamer 28:0e774865873d 8396 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
screamer 28:0e774865873d 8397 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
screamer 28:0e774865873d 8398 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
screamer 28:0e774865873d 8399 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
screamer 28:0e774865873d 8400 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
screamer 28:0e774865873d 8401 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
screamer 28:0e774865873d 8402 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
screamer 28:0e774865873d 8403 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
screamer 28:0e774865873d 8404 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
screamer 28:0e774865873d 8405 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
screamer 28:0e774865873d 8406 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
screamer 28:0e774865873d 8407 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
screamer 28:0e774865873d 8408 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
screamer 28:0e774865873d 8409 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
screamer 28:0e774865873d 8410 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
screamer 28:0e774865873d 8411 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
screamer 28:0e774865873d 8412 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
screamer 28:0e774865873d 8413 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
screamer 28:0e774865873d 8414 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
screamer 28:0e774865873d 8415 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
screamer 28:0e774865873d 8416 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
screamer 28:0e774865873d 8417 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
screamer 28:0e774865873d 8418 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
screamer 28:0e774865873d 8419 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
screamer 28:0e774865873d 8420 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
screamer 28:0e774865873d 8421 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
screamer 28:0e774865873d 8422 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
screamer 28:0e774865873d 8423 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
screamer 28:0e774865873d 8424 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
screamer 28:0e774865873d 8425 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
screamer 28:0e774865873d 8426 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
screamer 28:0e774865873d 8427 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
screamer 28:0e774865873d 8428 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
screamer 28:0e774865873d 8429 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
screamer 28:0e774865873d 8430 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
screamer 28:0e774865873d 8431 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
screamer 28:0e774865873d 8432 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
screamer 28:0e774865873d 8433 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
screamer 28:0e774865873d 8434 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
screamer 28:0e774865873d 8435 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
screamer 28:0e774865873d 8436
screamer 28:0e774865873d 8437 /****************** Bits definition for GPIO_PUPDR register *****************/
screamer 28:0e774865873d 8438 #define GPIO_PUPDR_PUPD0_Pos (0U)
screamer 28:0e774865873d 8439 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 8440 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
screamer 28:0e774865873d 8441 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8442 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8443 #define GPIO_PUPDR_PUPD1_Pos (2U)
screamer 28:0e774865873d 8444 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 8445 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
screamer 28:0e774865873d 8446 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8447 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8448 #define GPIO_PUPDR_PUPD2_Pos (4U)
screamer 28:0e774865873d 8449 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 8450 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
screamer 28:0e774865873d 8451 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8452 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8453 #define GPIO_PUPDR_PUPD3_Pos (6U)
screamer 28:0e774865873d 8454 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 8455 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
screamer 28:0e774865873d 8456 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8457 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8458 #define GPIO_PUPDR_PUPD4_Pos (8U)
screamer 28:0e774865873d 8459 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 8460 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
screamer 28:0e774865873d 8461 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8462 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8463 #define GPIO_PUPDR_PUPD5_Pos (10U)
screamer 28:0e774865873d 8464 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 8465 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
screamer 28:0e774865873d 8466 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8467 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8468 #define GPIO_PUPDR_PUPD6_Pos (12U)
screamer 28:0e774865873d 8469 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 8470 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
screamer 28:0e774865873d 8471 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8472 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8473 #define GPIO_PUPDR_PUPD7_Pos (14U)
screamer 28:0e774865873d 8474 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 8475 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
screamer 28:0e774865873d 8476 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8477 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8478 #define GPIO_PUPDR_PUPD8_Pos (16U)
screamer 28:0e774865873d 8479 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 8480 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
screamer 28:0e774865873d 8481 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8482 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8483 #define GPIO_PUPDR_PUPD9_Pos (18U)
screamer 28:0e774865873d 8484 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 8485 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
screamer 28:0e774865873d 8486 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8487 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8488 #define GPIO_PUPDR_PUPD10_Pos (20U)
screamer 28:0e774865873d 8489 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 8490 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
screamer 28:0e774865873d 8491 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8492 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8493 #define GPIO_PUPDR_PUPD11_Pos (22U)
screamer 28:0e774865873d 8494 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
screamer 28:0e774865873d 8495 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
screamer 28:0e774865873d 8496 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8497 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8498 #define GPIO_PUPDR_PUPD12_Pos (24U)
screamer 28:0e774865873d 8499 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 8500 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
screamer 28:0e774865873d 8501 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8502 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8503 #define GPIO_PUPDR_PUPD13_Pos (26U)
screamer 28:0e774865873d 8504 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
screamer 28:0e774865873d 8505 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
screamer 28:0e774865873d 8506 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8507 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8508 #define GPIO_PUPDR_PUPD14_Pos (28U)
screamer 28:0e774865873d 8509 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 8510 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
screamer 28:0e774865873d 8511 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8512 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8513 #define GPIO_PUPDR_PUPD15_Pos (30U)
screamer 28:0e774865873d 8514 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
screamer 28:0e774865873d 8515 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
screamer 28:0e774865873d 8516 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8517 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8518
screamer 28:0e774865873d 8519 /* Legacy defines */
screamer 28:0e774865873d 8520 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
screamer 28:0e774865873d 8521 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
screamer 28:0e774865873d 8522 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
screamer 28:0e774865873d 8523 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
screamer 28:0e774865873d 8524 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
screamer 28:0e774865873d 8525 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
screamer 28:0e774865873d 8526 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
screamer 28:0e774865873d 8527 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
screamer 28:0e774865873d 8528 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
screamer 28:0e774865873d 8529 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
screamer 28:0e774865873d 8530 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
screamer 28:0e774865873d 8531 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
screamer 28:0e774865873d 8532 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
screamer 28:0e774865873d 8533 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
screamer 28:0e774865873d 8534 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
screamer 28:0e774865873d 8535 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
screamer 28:0e774865873d 8536 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
screamer 28:0e774865873d 8537 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
screamer 28:0e774865873d 8538 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
screamer 28:0e774865873d 8539 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
screamer 28:0e774865873d 8540 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
screamer 28:0e774865873d 8541 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
screamer 28:0e774865873d 8542 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
screamer 28:0e774865873d 8543 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
screamer 28:0e774865873d 8544 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
screamer 28:0e774865873d 8545 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
screamer 28:0e774865873d 8546 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
screamer 28:0e774865873d 8547 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
screamer 28:0e774865873d 8548 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
screamer 28:0e774865873d 8549 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
screamer 28:0e774865873d 8550 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
screamer 28:0e774865873d 8551 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
screamer 28:0e774865873d 8552 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
screamer 28:0e774865873d 8553 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
screamer 28:0e774865873d 8554 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
screamer 28:0e774865873d 8555 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
screamer 28:0e774865873d 8556 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
screamer 28:0e774865873d 8557 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
screamer 28:0e774865873d 8558 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
screamer 28:0e774865873d 8559 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
screamer 28:0e774865873d 8560 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
screamer 28:0e774865873d 8561 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
screamer 28:0e774865873d 8562 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
screamer 28:0e774865873d 8563 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
screamer 28:0e774865873d 8564 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
screamer 28:0e774865873d 8565 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
screamer 28:0e774865873d 8566 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
screamer 28:0e774865873d 8567 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
screamer 28:0e774865873d 8568
screamer 28:0e774865873d 8569 /****************** Bits definition for GPIO_IDR register *******************/
screamer 28:0e774865873d 8570 #define GPIO_IDR_ID0_Pos (0U)
screamer 28:0e774865873d 8571 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8572 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
screamer 28:0e774865873d 8573 #define GPIO_IDR_ID1_Pos (1U)
screamer 28:0e774865873d 8574 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8575 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
screamer 28:0e774865873d 8576 #define GPIO_IDR_ID2_Pos (2U)
screamer 28:0e774865873d 8577 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8578 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
screamer 28:0e774865873d 8579 #define GPIO_IDR_ID3_Pos (3U)
screamer 28:0e774865873d 8580 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8581 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
screamer 28:0e774865873d 8582 #define GPIO_IDR_ID4_Pos (4U)
screamer 28:0e774865873d 8583 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8584 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
screamer 28:0e774865873d 8585 #define GPIO_IDR_ID5_Pos (5U)
screamer 28:0e774865873d 8586 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8587 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
screamer 28:0e774865873d 8588 #define GPIO_IDR_ID6_Pos (6U)
screamer 28:0e774865873d 8589 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8590 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
screamer 28:0e774865873d 8591 #define GPIO_IDR_ID7_Pos (7U)
screamer 28:0e774865873d 8592 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8593 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
screamer 28:0e774865873d 8594 #define GPIO_IDR_ID8_Pos (8U)
screamer 28:0e774865873d 8595 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8596 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
screamer 28:0e774865873d 8597 #define GPIO_IDR_ID9_Pos (9U)
screamer 28:0e774865873d 8598 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8599 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
screamer 28:0e774865873d 8600 #define GPIO_IDR_ID10_Pos (10U)
screamer 28:0e774865873d 8601 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8602 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
screamer 28:0e774865873d 8603 #define GPIO_IDR_ID11_Pos (11U)
screamer 28:0e774865873d 8604 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8605 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
screamer 28:0e774865873d 8606 #define GPIO_IDR_ID12_Pos (12U)
screamer 28:0e774865873d 8607 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8608 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
screamer 28:0e774865873d 8609 #define GPIO_IDR_ID13_Pos (13U)
screamer 28:0e774865873d 8610 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8611 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
screamer 28:0e774865873d 8612 #define GPIO_IDR_ID14_Pos (14U)
screamer 28:0e774865873d 8613 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8614 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
screamer 28:0e774865873d 8615 #define GPIO_IDR_ID15_Pos (15U)
screamer 28:0e774865873d 8616 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8617 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
screamer 28:0e774865873d 8618
screamer 28:0e774865873d 8619 /* Legacy defines */
screamer 28:0e774865873d 8620 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
screamer 28:0e774865873d 8621 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
screamer 28:0e774865873d 8622 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
screamer 28:0e774865873d 8623 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
screamer 28:0e774865873d 8624 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
screamer 28:0e774865873d 8625 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
screamer 28:0e774865873d 8626 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
screamer 28:0e774865873d 8627 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
screamer 28:0e774865873d 8628 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
screamer 28:0e774865873d 8629 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
screamer 28:0e774865873d 8630 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
screamer 28:0e774865873d 8631 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
screamer 28:0e774865873d 8632 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
screamer 28:0e774865873d 8633 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
screamer 28:0e774865873d 8634 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
screamer 28:0e774865873d 8635 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
screamer 28:0e774865873d 8636
screamer 28:0e774865873d 8637 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
screamer 28:0e774865873d 8638 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
screamer 28:0e774865873d 8639 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
screamer 28:0e774865873d 8640 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
screamer 28:0e774865873d 8641 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
screamer 28:0e774865873d 8642 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
screamer 28:0e774865873d 8643 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
screamer 28:0e774865873d 8644 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
screamer 28:0e774865873d 8645 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
screamer 28:0e774865873d 8646 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
screamer 28:0e774865873d 8647 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
screamer 28:0e774865873d 8648 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
screamer 28:0e774865873d 8649 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
screamer 28:0e774865873d 8650 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
screamer 28:0e774865873d 8651 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
screamer 28:0e774865873d 8652 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
screamer 28:0e774865873d 8653 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
screamer 28:0e774865873d 8654
screamer 28:0e774865873d 8655 /****************** Bits definition for GPIO_ODR register *******************/
screamer 28:0e774865873d 8656 #define GPIO_ODR_OD0_Pos (0U)
screamer 28:0e774865873d 8657 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8658 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
screamer 28:0e774865873d 8659 #define GPIO_ODR_OD1_Pos (1U)
screamer 28:0e774865873d 8660 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8661 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
screamer 28:0e774865873d 8662 #define GPIO_ODR_OD2_Pos (2U)
screamer 28:0e774865873d 8663 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8664 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
screamer 28:0e774865873d 8665 #define GPIO_ODR_OD3_Pos (3U)
screamer 28:0e774865873d 8666 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8667 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
screamer 28:0e774865873d 8668 #define GPIO_ODR_OD4_Pos (4U)
screamer 28:0e774865873d 8669 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8670 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
screamer 28:0e774865873d 8671 #define GPIO_ODR_OD5_Pos (5U)
screamer 28:0e774865873d 8672 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8673 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
screamer 28:0e774865873d 8674 #define GPIO_ODR_OD6_Pos (6U)
screamer 28:0e774865873d 8675 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8676 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
screamer 28:0e774865873d 8677 #define GPIO_ODR_OD7_Pos (7U)
screamer 28:0e774865873d 8678 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8679 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
screamer 28:0e774865873d 8680 #define GPIO_ODR_OD8_Pos (8U)
screamer 28:0e774865873d 8681 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8682 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
screamer 28:0e774865873d 8683 #define GPIO_ODR_OD9_Pos (9U)
screamer 28:0e774865873d 8684 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8685 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
screamer 28:0e774865873d 8686 #define GPIO_ODR_OD10_Pos (10U)
screamer 28:0e774865873d 8687 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8688 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
screamer 28:0e774865873d 8689 #define GPIO_ODR_OD11_Pos (11U)
screamer 28:0e774865873d 8690 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8691 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
screamer 28:0e774865873d 8692 #define GPIO_ODR_OD12_Pos (12U)
screamer 28:0e774865873d 8693 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8694 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
screamer 28:0e774865873d 8695 #define GPIO_ODR_OD13_Pos (13U)
screamer 28:0e774865873d 8696 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8697 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
screamer 28:0e774865873d 8698 #define GPIO_ODR_OD14_Pos (14U)
screamer 28:0e774865873d 8699 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8700 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
screamer 28:0e774865873d 8701 #define GPIO_ODR_OD15_Pos (15U)
screamer 28:0e774865873d 8702 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8703 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
screamer 28:0e774865873d 8704
screamer 28:0e774865873d 8705 /* Legacy defines */
screamer 28:0e774865873d 8706 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
screamer 28:0e774865873d 8707 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
screamer 28:0e774865873d 8708 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
screamer 28:0e774865873d 8709 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
screamer 28:0e774865873d 8710 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
screamer 28:0e774865873d 8711 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
screamer 28:0e774865873d 8712 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
screamer 28:0e774865873d 8713 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
screamer 28:0e774865873d 8714 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
screamer 28:0e774865873d 8715 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
screamer 28:0e774865873d 8716 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
screamer 28:0e774865873d 8717 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
screamer 28:0e774865873d 8718 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
screamer 28:0e774865873d 8719 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
screamer 28:0e774865873d 8720 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
screamer 28:0e774865873d 8721 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
screamer 28:0e774865873d 8722
screamer 28:0e774865873d 8723 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
screamer 28:0e774865873d 8724 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
screamer 28:0e774865873d 8725 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
screamer 28:0e774865873d 8726 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
screamer 28:0e774865873d 8727 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
screamer 28:0e774865873d 8728 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
screamer 28:0e774865873d 8729 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
screamer 28:0e774865873d 8730 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
screamer 28:0e774865873d 8731 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
screamer 28:0e774865873d 8732 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
screamer 28:0e774865873d 8733 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
screamer 28:0e774865873d 8734 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
screamer 28:0e774865873d 8735 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
screamer 28:0e774865873d 8736 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
screamer 28:0e774865873d 8737 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
screamer 28:0e774865873d 8738 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
screamer 28:0e774865873d 8739 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
screamer 28:0e774865873d 8740
screamer 28:0e774865873d 8741 /****************** Bits definition for GPIO_BSRR register ******************/
screamer 28:0e774865873d 8742 #define GPIO_BSRR_BS0_Pos (0U)
screamer 28:0e774865873d 8743 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8744 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
screamer 28:0e774865873d 8745 #define GPIO_BSRR_BS1_Pos (1U)
screamer 28:0e774865873d 8746 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8747 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
screamer 28:0e774865873d 8748 #define GPIO_BSRR_BS2_Pos (2U)
screamer 28:0e774865873d 8749 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8750 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
screamer 28:0e774865873d 8751 #define GPIO_BSRR_BS3_Pos (3U)
screamer 28:0e774865873d 8752 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8753 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
screamer 28:0e774865873d 8754 #define GPIO_BSRR_BS4_Pos (4U)
screamer 28:0e774865873d 8755 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8756 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
screamer 28:0e774865873d 8757 #define GPIO_BSRR_BS5_Pos (5U)
screamer 28:0e774865873d 8758 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8759 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
screamer 28:0e774865873d 8760 #define GPIO_BSRR_BS6_Pos (6U)
screamer 28:0e774865873d 8761 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8762 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
screamer 28:0e774865873d 8763 #define GPIO_BSRR_BS7_Pos (7U)
screamer 28:0e774865873d 8764 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8765 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
screamer 28:0e774865873d 8766 #define GPIO_BSRR_BS8_Pos (8U)
screamer 28:0e774865873d 8767 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8768 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
screamer 28:0e774865873d 8769 #define GPIO_BSRR_BS9_Pos (9U)
screamer 28:0e774865873d 8770 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8771 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
screamer 28:0e774865873d 8772 #define GPIO_BSRR_BS10_Pos (10U)
screamer 28:0e774865873d 8773 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8774 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
screamer 28:0e774865873d 8775 #define GPIO_BSRR_BS11_Pos (11U)
screamer 28:0e774865873d 8776 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8777 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
screamer 28:0e774865873d 8778 #define GPIO_BSRR_BS12_Pos (12U)
screamer 28:0e774865873d 8779 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8780 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
screamer 28:0e774865873d 8781 #define GPIO_BSRR_BS13_Pos (13U)
screamer 28:0e774865873d 8782 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8783 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
screamer 28:0e774865873d 8784 #define GPIO_BSRR_BS14_Pos (14U)
screamer 28:0e774865873d 8785 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8786 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
screamer 28:0e774865873d 8787 #define GPIO_BSRR_BS15_Pos (15U)
screamer 28:0e774865873d 8788 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8789 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
screamer 28:0e774865873d 8790 #define GPIO_BSRR_BR0_Pos (16U)
screamer 28:0e774865873d 8791 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8792 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
screamer 28:0e774865873d 8793 #define GPIO_BSRR_BR1_Pos (17U)
screamer 28:0e774865873d 8794 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8795 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
screamer 28:0e774865873d 8796 #define GPIO_BSRR_BR2_Pos (18U)
screamer 28:0e774865873d 8797 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8798 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
screamer 28:0e774865873d 8799 #define GPIO_BSRR_BR3_Pos (19U)
screamer 28:0e774865873d 8800 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8801 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
screamer 28:0e774865873d 8802 #define GPIO_BSRR_BR4_Pos (20U)
screamer 28:0e774865873d 8803 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8804 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
screamer 28:0e774865873d 8805 #define GPIO_BSRR_BR5_Pos (21U)
screamer 28:0e774865873d 8806 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8807 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
screamer 28:0e774865873d 8808 #define GPIO_BSRR_BR6_Pos (22U)
screamer 28:0e774865873d 8809 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8810 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
screamer 28:0e774865873d 8811 #define GPIO_BSRR_BR7_Pos (23U)
screamer 28:0e774865873d 8812 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8813 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
screamer 28:0e774865873d 8814 #define GPIO_BSRR_BR8_Pos (24U)
screamer 28:0e774865873d 8815 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8816 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
screamer 28:0e774865873d 8817 #define GPIO_BSRR_BR9_Pos (25U)
screamer 28:0e774865873d 8818 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8819 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
screamer 28:0e774865873d 8820 #define GPIO_BSRR_BR10_Pos (26U)
screamer 28:0e774865873d 8821 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8822 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
screamer 28:0e774865873d 8823 #define GPIO_BSRR_BR11_Pos (27U)
screamer 28:0e774865873d 8824 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8825 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
screamer 28:0e774865873d 8826 #define GPIO_BSRR_BR12_Pos (28U)
screamer 28:0e774865873d 8827 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8828 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
screamer 28:0e774865873d 8829 #define GPIO_BSRR_BR13_Pos (29U)
screamer 28:0e774865873d 8830 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8831 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
screamer 28:0e774865873d 8832 #define GPIO_BSRR_BR14_Pos (30U)
screamer 28:0e774865873d 8833 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8834 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
screamer 28:0e774865873d 8835 #define GPIO_BSRR_BR15_Pos (31U)
screamer 28:0e774865873d 8836 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8837 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
screamer 28:0e774865873d 8838
screamer 28:0e774865873d 8839 /* Legacy defines */
screamer 28:0e774865873d 8840 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
screamer 28:0e774865873d 8841 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
screamer 28:0e774865873d 8842 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
screamer 28:0e774865873d 8843 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
screamer 28:0e774865873d 8844 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
screamer 28:0e774865873d 8845 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
screamer 28:0e774865873d 8846 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
screamer 28:0e774865873d 8847 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
screamer 28:0e774865873d 8848 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
screamer 28:0e774865873d 8849 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
screamer 28:0e774865873d 8850 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
screamer 28:0e774865873d 8851 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
screamer 28:0e774865873d 8852 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
screamer 28:0e774865873d 8853 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
screamer 28:0e774865873d 8854 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
screamer 28:0e774865873d 8855 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
screamer 28:0e774865873d 8856 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
screamer 28:0e774865873d 8857 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
screamer 28:0e774865873d 8858 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
screamer 28:0e774865873d 8859 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
screamer 28:0e774865873d 8860 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
screamer 28:0e774865873d 8861 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
screamer 28:0e774865873d 8862 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
screamer 28:0e774865873d 8863 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
screamer 28:0e774865873d 8864 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
screamer 28:0e774865873d 8865 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
screamer 28:0e774865873d 8866 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
screamer 28:0e774865873d 8867 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
screamer 28:0e774865873d 8868 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
screamer 28:0e774865873d 8869 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
screamer 28:0e774865873d 8870 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
screamer 28:0e774865873d 8871 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
screamer 28:0e774865873d 8872
screamer 28:0e774865873d 8873 /****************** Bit definition for GPIO_LCKR register *********************/
screamer 28:0e774865873d 8874 #define GPIO_LCKR_LCK0_Pos (0U)
screamer 28:0e774865873d 8875 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8876 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
screamer 28:0e774865873d 8877 #define GPIO_LCKR_LCK1_Pos (1U)
screamer 28:0e774865873d 8878 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8879 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
screamer 28:0e774865873d 8880 #define GPIO_LCKR_LCK2_Pos (2U)
screamer 28:0e774865873d 8881 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8882 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
screamer 28:0e774865873d 8883 #define GPIO_LCKR_LCK3_Pos (3U)
screamer 28:0e774865873d 8884 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8885 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
screamer 28:0e774865873d 8886 #define GPIO_LCKR_LCK4_Pos (4U)
screamer 28:0e774865873d 8887 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8888 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
screamer 28:0e774865873d 8889 #define GPIO_LCKR_LCK5_Pos (5U)
screamer 28:0e774865873d 8890 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8891 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
screamer 28:0e774865873d 8892 #define GPIO_LCKR_LCK6_Pos (6U)
screamer 28:0e774865873d 8893 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8894 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
screamer 28:0e774865873d 8895 #define GPIO_LCKR_LCK7_Pos (7U)
screamer 28:0e774865873d 8896 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8897 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
screamer 28:0e774865873d 8898 #define GPIO_LCKR_LCK8_Pos (8U)
screamer 28:0e774865873d 8899 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8900 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
screamer 28:0e774865873d 8901 #define GPIO_LCKR_LCK9_Pos (9U)
screamer 28:0e774865873d 8902 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8903 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
screamer 28:0e774865873d 8904 #define GPIO_LCKR_LCK10_Pos (10U)
screamer 28:0e774865873d 8905 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8906 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
screamer 28:0e774865873d 8907 #define GPIO_LCKR_LCK11_Pos (11U)
screamer 28:0e774865873d 8908 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8909 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
screamer 28:0e774865873d 8910 #define GPIO_LCKR_LCK12_Pos (12U)
screamer 28:0e774865873d 8911 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8912 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
screamer 28:0e774865873d 8913 #define GPIO_LCKR_LCK13_Pos (13U)
screamer 28:0e774865873d 8914 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8915 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
screamer 28:0e774865873d 8916 #define GPIO_LCKR_LCK14_Pos (14U)
screamer 28:0e774865873d 8917 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8918 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
screamer 28:0e774865873d 8919 #define GPIO_LCKR_LCK15_Pos (15U)
screamer 28:0e774865873d 8920 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8921 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
screamer 28:0e774865873d 8922 #define GPIO_LCKR_LCKK_Pos (16U)
screamer 28:0e774865873d 8923 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8924 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
screamer 28:0e774865873d 8925
screamer 28:0e774865873d 8926 /****************** Bit definition for GPIO_AFRL register *********************/
screamer 28:0e774865873d 8927 #define GPIO_AFRL_AFSEL0_Pos (0U)
screamer 28:0e774865873d 8928 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 8929 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
screamer 28:0e774865873d 8930 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8931 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 8932 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 8933 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 8934 #define GPIO_AFRL_AFSEL1_Pos (4U)
screamer 28:0e774865873d 8935 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 8936 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
screamer 28:0e774865873d 8937 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 8938 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 8939 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 8940 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 8941 #define GPIO_AFRL_AFSEL2_Pos (8U)
screamer 28:0e774865873d 8942 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 8943 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
screamer 28:0e774865873d 8944 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 8945 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 8946 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 8947 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 8948 #define GPIO_AFRL_AFSEL3_Pos (12U)
screamer 28:0e774865873d 8949 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
screamer 28:0e774865873d 8950 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
screamer 28:0e774865873d 8951 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 8952 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 8953 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 8954 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 8955 #define GPIO_AFRL_AFSEL4_Pos (16U)
screamer 28:0e774865873d 8956 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 8957 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
screamer 28:0e774865873d 8958 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 8959 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 8960 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 8961 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 8962 #define GPIO_AFRL_AFSEL5_Pos (20U)
screamer 28:0e774865873d 8963 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 8964 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
screamer 28:0e774865873d 8965 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 8966 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 8967 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 8968 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 8969 #define GPIO_AFRL_AFSEL6_Pos (24U)
screamer 28:0e774865873d 8970 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 8971 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
screamer 28:0e774865873d 8972 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 8973 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 8974 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 8975 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 8976 #define GPIO_AFRL_AFSEL7_Pos (28U)
screamer 28:0e774865873d 8977 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
screamer 28:0e774865873d 8978 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
screamer 28:0e774865873d 8979 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 8980 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 8981 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 8982 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 8983
screamer 28:0e774865873d 8984 /* Legacy defines */
screamer 28:0e774865873d 8985 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
screamer 28:0e774865873d 8986 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
screamer 28:0e774865873d 8987 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
screamer 28:0e774865873d 8988 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
screamer 28:0e774865873d 8989 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
screamer 28:0e774865873d 8990 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
screamer 28:0e774865873d 8991 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
screamer 28:0e774865873d 8992 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
screamer 28:0e774865873d 8993
screamer 28:0e774865873d 8994 /****************** Bit definition for GPIO_AFRH register *********************/
screamer 28:0e774865873d 8995 #define GPIO_AFRH_AFSEL8_Pos (0U)
screamer 28:0e774865873d 8996 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 8997 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
screamer 28:0e774865873d 8998 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 8999 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9000 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9001 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9002 #define GPIO_AFRH_AFSEL9_Pos (4U)
screamer 28:0e774865873d 9003 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 9004 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
screamer 28:0e774865873d 9005 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9006 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9007 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9008 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9009 #define GPIO_AFRH_AFSEL10_Pos (8U)
screamer 28:0e774865873d 9010 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 9011 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
screamer 28:0e774865873d 9012 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9013 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9014 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9015 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9016 #define GPIO_AFRH_AFSEL11_Pos (12U)
screamer 28:0e774865873d 9017 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
screamer 28:0e774865873d 9018 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
screamer 28:0e774865873d 9019 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9020 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9021 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9022 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9023 #define GPIO_AFRH_AFSEL12_Pos (16U)
screamer 28:0e774865873d 9024 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 9025 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
screamer 28:0e774865873d 9026 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 9027 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 9028 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 9029 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 9030 #define GPIO_AFRH_AFSEL13_Pos (20U)
screamer 28:0e774865873d 9031 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 9032 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
screamer 28:0e774865873d 9033 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 9034 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 9035 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 9036 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 9037 #define GPIO_AFRH_AFSEL14_Pos (24U)
screamer 28:0e774865873d 9038 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 9039 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
screamer 28:0e774865873d 9040 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 9041 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 9042 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 9043 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 9044 #define GPIO_AFRH_AFSEL15_Pos (28U)
screamer 28:0e774865873d 9045 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
screamer 28:0e774865873d 9046 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
screamer 28:0e774865873d 9047 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 9048 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 9049 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 9050 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 9051
screamer 28:0e774865873d 9052 /* Legacy defines */
screamer 28:0e774865873d 9053 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
screamer 28:0e774865873d 9054 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
screamer 28:0e774865873d 9055 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
screamer 28:0e774865873d 9056 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
screamer 28:0e774865873d 9057 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
screamer 28:0e774865873d 9058 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
screamer 28:0e774865873d 9059 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
screamer 28:0e774865873d 9060 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
screamer 28:0e774865873d 9061
screamer 28:0e774865873d 9062 /****************** Bits definition for GPIO_BRR register ******************/
screamer 28:0e774865873d 9063 #define GPIO_BRR_BR0_Pos (0U)
screamer 28:0e774865873d 9064 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9065 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
screamer 28:0e774865873d 9066 #define GPIO_BRR_BR1_Pos (1U)
screamer 28:0e774865873d 9067 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9068 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
screamer 28:0e774865873d 9069 #define GPIO_BRR_BR2_Pos (2U)
screamer 28:0e774865873d 9070 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9071 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
screamer 28:0e774865873d 9072 #define GPIO_BRR_BR3_Pos (3U)
screamer 28:0e774865873d 9073 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9074 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
screamer 28:0e774865873d 9075 #define GPIO_BRR_BR4_Pos (4U)
screamer 28:0e774865873d 9076 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9077 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
screamer 28:0e774865873d 9078 #define GPIO_BRR_BR5_Pos (5U)
screamer 28:0e774865873d 9079 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9080 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
screamer 28:0e774865873d 9081 #define GPIO_BRR_BR6_Pos (6U)
screamer 28:0e774865873d 9082 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9083 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
screamer 28:0e774865873d 9084 #define GPIO_BRR_BR7_Pos (7U)
screamer 28:0e774865873d 9085 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9086 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
screamer 28:0e774865873d 9087 #define GPIO_BRR_BR8_Pos (8U)
screamer 28:0e774865873d 9088 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9089 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
screamer 28:0e774865873d 9090 #define GPIO_BRR_BR9_Pos (9U)
screamer 28:0e774865873d 9091 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9092 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
screamer 28:0e774865873d 9093 #define GPIO_BRR_BR10_Pos (10U)
screamer 28:0e774865873d 9094 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9095 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
screamer 28:0e774865873d 9096 #define GPIO_BRR_BR11_Pos (11U)
screamer 28:0e774865873d 9097 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9098 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
screamer 28:0e774865873d 9099 #define GPIO_BRR_BR12_Pos (12U)
screamer 28:0e774865873d 9100 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9101 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
screamer 28:0e774865873d 9102 #define GPIO_BRR_BR13_Pos (13U)
screamer 28:0e774865873d 9103 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9104 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
screamer 28:0e774865873d 9105 #define GPIO_BRR_BR14_Pos (14U)
screamer 28:0e774865873d 9106 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9107 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
screamer 28:0e774865873d 9108 #define GPIO_BRR_BR15_Pos (15U)
screamer 28:0e774865873d 9109 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9110 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
screamer 28:0e774865873d 9111
screamer 28:0e774865873d 9112 /* Legacy defines */
screamer 28:0e774865873d 9113 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
screamer 28:0e774865873d 9114 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
screamer 28:0e774865873d 9115 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
screamer 28:0e774865873d 9116 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
screamer 28:0e774865873d 9117 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
screamer 28:0e774865873d 9118 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
screamer 28:0e774865873d 9119 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
screamer 28:0e774865873d 9120 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
screamer 28:0e774865873d 9121 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
screamer 28:0e774865873d 9122 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
screamer 28:0e774865873d 9123 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
screamer 28:0e774865873d 9124 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
screamer 28:0e774865873d 9125 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
screamer 28:0e774865873d 9126 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
screamer 28:0e774865873d 9127 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
screamer 28:0e774865873d 9128 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
screamer 28:0e774865873d 9129
screamer 28:0e774865873d 9130
screamer 28:0e774865873d 9131 /****************** Bits definition for GPIO_ASCR register *******************/
screamer 28:0e774865873d 9132 #define GPIO_ASCR_ASC0_Pos (0U)
screamer 28:0e774865873d 9133 #define GPIO_ASCR_ASC0_Msk (0x1U << GPIO_ASCR_ASC0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9134 #define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
screamer 28:0e774865873d 9135 #define GPIO_ASCR_ASC1_Pos (1U)
screamer 28:0e774865873d 9136 #define GPIO_ASCR_ASC1_Msk (0x1U << GPIO_ASCR_ASC1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9137 #define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
screamer 28:0e774865873d 9138 #define GPIO_ASCR_ASC2_Pos (2U)
screamer 28:0e774865873d 9139 #define GPIO_ASCR_ASC2_Msk (0x1U << GPIO_ASCR_ASC2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9140 #define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
screamer 28:0e774865873d 9141 #define GPIO_ASCR_ASC3_Pos (3U)
screamer 28:0e774865873d 9142 #define GPIO_ASCR_ASC3_Msk (0x1U << GPIO_ASCR_ASC3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9143 #define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
screamer 28:0e774865873d 9144 #define GPIO_ASCR_ASC4_Pos (4U)
screamer 28:0e774865873d 9145 #define GPIO_ASCR_ASC4_Msk (0x1U << GPIO_ASCR_ASC4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9146 #define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
screamer 28:0e774865873d 9147 #define GPIO_ASCR_ASC5_Pos (5U)
screamer 28:0e774865873d 9148 #define GPIO_ASCR_ASC5_Msk (0x1U << GPIO_ASCR_ASC5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9149 #define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
screamer 28:0e774865873d 9150 #define GPIO_ASCR_ASC6_Pos (6U)
screamer 28:0e774865873d 9151 #define GPIO_ASCR_ASC6_Msk (0x1U << GPIO_ASCR_ASC6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9152 #define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
screamer 28:0e774865873d 9153 #define GPIO_ASCR_ASC7_Pos (7U)
screamer 28:0e774865873d 9154 #define GPIO_ASCR_ASC7_Msk (0x1U << GPIO_ASCR_ASC7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9155 #define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
screamer 28:0e774865873d 9156 #define GPIO_ASCR_ASC8_Pos (8U)
screamer 28:0e774865873d 9157 #define GPIO_ASCR_ASC8_Msk (0x1U << GPIO_ASCR_ASC8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9158 #define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
screamer 28:0e774865873d 9159 #define GPIO_ASCR_ASC9_Pos (9U)
screamer 28:0e774865873d 9160 #define GPIO_ASCR_ASC9_Msk (0x1U << GPIO_ASCR_ASC9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9161 #define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
screamer 28:0e774865873d 9162 #define GPIO_ASCR_ASC10_Pos (10U)
screamer 28:0e774865873d 9163 #define GPIO_ASCR_ASC10_Msk (0x1U << GPIO_ASCR_ASC10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9164 #define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
screamer 28:0e774865873d 9165 #define GPIO_ASCR_ASC11_Pos (11U)
screamer 28:0e774865873d 9166 #define GPIO_ASCR_ASC11_Msk (0x1U << GPIO_ASCR_ASC11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9167 #define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
screamer 28:0e774865873d 9168 #define GPIO_ASCR_ASC12_Pos (12U)
screamer 28:0e774865873d 9169 #define GPIO_ASCR_ASC12_Msk (0x1U << GPIO_ASCR_ASC12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9170 #define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
screamer 28:0e774865873d 9171 #define GPIO_ASCR_ASC13_Pos (13U)
screamer 28:0e774865873d 9172 #define GPIO_ASCR_ASC13_Msk (0x1U << GPIO_ASCR_ASC13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9173 #define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
screamer 28:0e774865873d 9174 #define GPIO_ASCR_ASC14_Pos (14U)
screamer 28:0e774865873d 9175 #define GPIO_ASCR_ASC14_Msk (0x1U << GPIO_ASCR_ASC14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9176 #define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
screamer 28:0e774865873d 9177 #define GPIO_ASCR_ASC15_Pos (15U)
screamer 28:0e774865873d 9178 #define GPIO_ASCR_ASC15_Msk (0x1U << GPIO_ASCR_ASC15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9179 #define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
screamer 28:0e774865873d 9180
screamer 28:0e774865873d 9181 /* Legacy defines */
screamer 28:0e774865873d 9182 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
screamer 28:0e774865873d 9183 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
screamer 28:0e774865873d 9184 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
screamer 28:0e774865873d 9185 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
screamer 28:0e774865873d 9186 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
screamer 28:0e774865873d 9187 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
screamer 28:0e774865873d 9188 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
screamer 28:0e774865873d 9189 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
screamer 28:0e774865873d 9190 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
screamer 28:0e774865873d 9191 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
screamer 28:0e774865873d 9192 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
screamer 28:0e774865873d 9193 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
screamer 28:0e774865873d 9194 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
screamer 28:0e774865873d 9195 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
screamer 28:0e774865873d 9196 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
screamer 28:0e774865873d 9197 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
screamer 28:0e774865873d 9198
screamer 28:0e774865873d 9199 /******************************************************************************/
screamer 28:0e774865873d 9200 /* */
screamer 28:0e774865873d 9201 /* Inter-integrated Circuit Interface (I2C) */
screamer 28:0e774865873d 9202 /* */
screamer 28:0e774865873d 9203 /******************************************************************************/
screamer 28:0e774865873d 9204 /******************* Bit definition for I2C_CR1 register *******************/
screamer 28:0e774865873d 9205 #define I2C_CR1_PE_Pos (0U)
screamer 28:0e774865873d 9206 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9207 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
screamer 28:0e774865873d 9208 #define I2C_CR1_TXIE_Pos (1U)
screamer 28:0e774865873d 9209 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9210 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
screamer 28:0e774865873d 9211 #define I2C_CR1_RXIE_Pos (2U)
screamer 28:0e774865873d 9212 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9213 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
screamer 28:0e774865873d 9214 #define I2C_CR1_ADDRIE_Pos (3U)
screamer 28:0e774865873d 9215 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9216 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
screamer 28:0e774865873d 9217 #define I2C_CR1_NACKIE_Pos (4U)
screamer 28:0e774865873d 9218 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9219 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
screamer 28:0e774865873d 9220 #define I2C_CR1_STOPIE_Pos (5U)
screamer 28:0e774865873d 9221 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9222 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
screamer 28:0e774865873d 9223 #define I2C_CR1_TCIE_Pos (6U)
screamer 28:0e774865873d 9224 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9225 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
screamer 28:0e774865873d 9226 #define I2C_CR1_ERRIE_Pos (7U)
screamer 28:0e774865873d 9227 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9228 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
screamer 28:0e774865873d 9229 #define I2C_CR1_DNF_Pos (8U)
screamer 28:0e774865873d 9230 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 9231 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
screamer 28:0e774865873d 9232 #define I2C_CR1_ANFOFF_Pos (12U)
screamer 28:0e774865873d 9233 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9234 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
screamer 28:0e774865873d 9235 #define I2C_CR1_SWRST_Pos (13U)
screamer 28:0e774865873d 9236 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9237 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
screamer 28:0e774865873d 9238 #define I2C_CR1_TXDMAEN_Pos (14U)
screamer 28:0e774865873d 9239 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9240 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
screamer 28:0e774865873d 9241 #define I2C_CR1_RXDMAEN_Pos (15U)
screamer 28:0e774865873d 9242 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9243 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
screamer 28:0e774865873d 9244 #define I2C_CR1_SBC_Pos (16U)
screamer 28:0e774865873d 9245 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 9246 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
screamer 28:0e774865873d 9247 #define I2C_CR1_NOSTRETCH_Pos (17U)
screamer 28:0e774865873d 9248 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 9249 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
screamer 28:0e774865873d 9250 #define I2C_CR1_WUPEN_Pos (18U)
screamer 28:0e774865873d 9251 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 9252 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
screamer 28:0e774865873d 9253 #define I2C_CR1_GCEN_Pos (19U)
screamer 28:0e774865873d 9254 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 9255 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
screamer 28:0e774865873d 9256 #define I2C_CR1_SMBHEN_Pos (20U)
screamer 28:0e774865873d 9257 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 9258 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
screamer 28:0e774865873d 9259 #define I2C_CR1_SMBDEN_Pos (21U)
screamer 28:0e774865873d 9260 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 9261 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
screamer 28:0e774865873d 9262 #define I2C_CR1_ALERTEN_Pos (22U)
screamer 28:0e774865873d 9263 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 9264 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
screamer 28:0e774865873d 9265 #define I2C_CR1_PECEN_Pos (23U)
screamer 28:0e774865873d 9266 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 9267 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
screamer 28:0e774865873d 9268
screamer 28:0e774865873d 9269 /****************** Bit definition for I2C_CR2 register ********************/
screamer 28:0e774865873d 9270 #define I2C_CR2_SADD_Pos (0U)
screamer 28:0e774865873d 9271 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
screamer 28:0e774865873d 9272 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
screamer 28:0e774865873d 9273 #define I2C_CR2_RD_WRN_Pos (10U)
screamer 28:0e774865873d 9274 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9275 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
screamer 28:0e774865873d 9276 #define I2C_CR2_ADD10_Pos (11U)
screamer 28:0e774865873d 9277 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9278 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
screamer 28:0e774865873d 9279 #define I2C_CR2_HEAD10R_Pos (12U)
screamer 28:0e774865873d 9280 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9281 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
screamer 28:0e774865873d 9282 #define I2C_CR2_START_Pos (13U)
screamer 28:0e774865873d 9283 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9284 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
screamer 28:0e774865873d 9285 #define I2C_CR2_STOP_Pos (14U)
screamer 28:0e774865873d 9286 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9287 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
screamer 28:0e774865873d 9288 #define I2C_CR2_NACK_Pos (15U)
screamer 28:0e774865873d 9289 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9290 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
screamer 28:0e774865873d 9291 #define I2C_CR2_NBYTES_Pos (16U)
screamer 28:0e774865873d 9292 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 9293 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
screamer 28:0e774865873d 9294 #define I2C_CR2_RELOAD_Pos (24U)
screamer 28:0e774865873d 9295 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 9296 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
screamer 28:0e774865873d 9297 #define I2C_CR2_AUTOEND_Pos (25U)
screamer 28:0e774865873d 9298 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 9299 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
screamer 28:0e774865873d 9300 #define I2C_CR2_PECBYTE_Pos (26U)
screamer 28:0e774865873d 9301 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 9302 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
screamer 28:0e774865873d 9303
screamer 28:0e774865873d 9304 /******************* Bit definition for I2C_OAR1 register ******************/
screamer 28:0e774865873d 9305 #define I2C_OAR1_OA1_Pos (0U)
screamer 28:0e774865873d 9306 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
screamer 28:0e774865873d 9307 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
screamer 28:0e774865873d 9308 #define I2C_OAR1_OA1MODE_Pos (10U)
screamer 28:0e774865873d 9309 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9310 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
screamer 28:0e774865873d 9311 #define I2C_OAR1_OA1EN_Pos (15U)
screamer 28:0e774865873d 9312 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9313 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
screamer 28:0e774865873d 9314
screamer 28:0e774865873d 9315 /******************* Bit definition for I2C_OAR2 register ******************/
screamer 28:0e774865873d 9316 #define I2C_OAR2_OA2_Pos (1U)
screamer 28:0e774865873d 9317 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
screamer 28:0e774865873d 9318 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
screamer 28:0e774865873d 9319 #define I2C_OAR2_OA2MSK_Pos (8U)
screamer 28:0e774865873d 9320 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 9321 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
screamer 28:0e774865873d 9322 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
screamer 28:0e774865873d 9323 #define I2C_OAR2_OA2MASK01_Pos (8U)
screamer 28:0e774865873d 9324 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9325 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
screamer 28:0e774865873d 9326 #define I2C_OAR2_OA2MASK02_Pos (9U)
screamer 28:0e774865873d 9327 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9328 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
screamer 28:0e774865873d 9329 #define I2C_OAR2_OA2MASK03_Pos (8U)
screamer 28:0e774865873d 9330 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 9331 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
screamer 28:0e774865873d 9332 #define I2C_OAR2_OA2MASK04_Pos (10U)
screamer 28:0e774865873d 9333 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9334 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
screamer 28:0e774865873d 9335 #define I2C_OAR2_OA2MASK05_Pos (8U)
screamer 28:0e774865873d 9336 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
screamer 28:0e774865873d 9337 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
screamer 28:0e774865873d 9338 #define I2C_OAR2_OA2MASK06_Pos (9U)
screamer 28:0e774865873d 9339 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
screamer 28:0e774865873d 9340 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
screamer 28:0e774865873d 9341 #define I2C_OAR2_OA2MASK07_Pos (8U)
screamer 28:0e774865873d 9342 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 9343 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
screamer 28:0e774865873d 9344 #define I2C_OAR2_OA2EN_Pos (15U)
screamer 28:0e774865873d 9345 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9346 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
screamer 28:0e774865873d 9347
screamer 28:0e774865873d 9348 /******************* Bit definition for I2C_TIMINGR register *******************/
screamer 28:0e774865873d 9349 #define I2C_TIMINGR_SCLL_Pos (0U)
screamer 28:0e774865873d 9350 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 9351 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
screamer 28:0e774865873d 9352 #define I2C_TIMINGR_SCLH_Pos (8U)
screamer 28:0e774865873d 9353 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 9354 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
screamer 28:0e774865873d 9355 #define I2C_TIMINGR_SDADEL_Pos (16U)
screamer 28:0e774865873d 9356 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 9357 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
screamer 28:0e774865873d 9358 #define I2C_TIMINGR_SCLDEL_Pos (20U)
screamer 28:0e774865873d 9359 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 9360 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
screamer 28:0e774865873d 9361 #define I2C_TIMINGR_PRESC_Pos (28U)
screamer 28:0e774865873d 9362 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
screamer 28:0e774865873d 9363 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
screamer 28:0e774865873d 9364
screamer 28:0e774865873d 9365 /******************* Bit definition for I2C_TIMEOUTR register *******************/
screamer 28:0e774865873d 9366 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
screamer 28:0e774865873d 9367 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 9368 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
screamer 28:0e774865873d 9369 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
screamer 28:0e774865873d 9370 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9371 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
screamer 28:0e774865873d 9372 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
screamer 28:0e774865873d 9373 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9374 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
screamer 28:0e774865873d 9375 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
screamer 28:0e774865873d 9376 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
screamer 28:0e774865873d 9377 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
screamer 28:0e774865873d 9378 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
screamer 28:0e774865873d 9379 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 9380 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
screamer 28:0e774865873d 9381
screamer 28:0e774865873d 9382 /****************** Bit definition for I2C_ISR register *********************/
screamer 28:0e774865873d 9383 #define I2C_ISR_TXE_Pos (0U)
screamer 28:0e774865873d 9384 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9385 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
screamer 28:0e774865873d 9386 #define I2C_ISR_TXIS_Pos (1U)
screamer 28:0e774865873d 9387 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9388 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
screamer 28:0e774865873d 9389 #define I2C_ISR_RXNE_Pos (2U)
screamer 28:0e774865873d 9390 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9391 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
screamer 28:0e774865873d 9392 #define I2C_ISR_ADDR_Pos (3U)
screamer 28:0e774865873d 9393 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9394 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
screamer 28:0e774865873d 9395 #define I2C_ISR_NACKF_Pos (4U)
screamer 28:0e774865873d 9396 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9397 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
screamer 28:0e774865873d 9398 #define I2C_ISR_STOPF_Pos (5U)
screamer 28:0e774865873d 9399 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9400 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
screamer 28:0e774865873d 9401 #define I2C_ISR_TC_Pos (6U)
screamer 28:0e774865873d 9402 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9403 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
screamer 28:0e774865873d 9404 #define I2C_ISR_TCR_Pos (7U)
screamer 28:0e774865873d 9405 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9406 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
screamer 28:0e774865873d 9407 #define I2C_ISR_BERR_Pos (8U)
screamer 28:0e774865873d 9408 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9409 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
screamer 28:0e774865873d 9410 #define I2C_ISR_ARLO_Pos (9U)
screamer 28:0e774865873d 9411 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9412 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
screamer 28:0e774865873d 9413 #define I2C_ISR_OVR_Pos (10U)
screamer 28:0e774865873d 9414 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9415 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
screamer 28:0e774865873d 9416 #define I2C_ISR_PECERR_Pos (11U)
screamer 28:0e774865873d 9417 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9418 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
screamer 28:0e774865873d 9419 #define I2C_ISR_TIMEOUT_Pos (12U)
screamer 28:0e774865873d 9420 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9421 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
screamer 28:0e774865873d 9422 #define I2C_ISR_ALERT_Pos (13U)
screamer 28:0e774865873d 9423 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9424 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
screamer 28:0e774865873d 9425 #define I2C_ISR_BUSY_Pos (15U)
screamer 28:0e774865873d 9426 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9427 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
screamer 28:0e774865873d 9428 #define I2C_ISR_DIR_Pos (16U)
screamer 28:0e774865873d 9429 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 9430 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
screamer 28:0e774865873d 9431 #define I2C_ISR_ADDCODE_Pos (17U)
screamer 28:0e774865873d 9432 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
screamer 28:0e774865873d 9433 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
screamer 28:0e774865873d 9434
screamer 28:0e774865873d 9435 /****************** Bit definition for I2C_ICR register *********************/
screamer 28:0e774865873d 9436 #define I2C_ICR_ADDRCF_Pos (3U)
screamer 28:0e774865873d 9437 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9438 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
screamer 28:0e774865873d 9439 #define I2C_ICR_NACKCF_Pos (4U)
screamer 28:0e774865873d 9440 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9441 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
screamer 28:0e774865873d 9442 #define I2C_ICR_STOPCF_Pos (5U)
screamer 28:0e774865873d 9443 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9444 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
screamer 28:0e774865873d 9445 #define I2C_ICR_BERRCF_Pos (8U)
screamer 28:0e774865873d 9446 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9447 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
screamer 28:0e774865873d 9448 #define I2C_ICR_ARLOCF_Pos (9U)
screamer 28:0e774865873d 9449 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9450 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
screamer 28:0e774865873d 9451 #define I2C_ICR_OVRCF_Pos (10U)
screamer 28:0e774865873d 9452 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9453 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
screamer 28:0e774865873d 9454 #define I2C_ICR_PECCF_Pos (11U)
screamer 28:0e774865873d 9455 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9456 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
screamer 28:0e774865873d 9457 #define I2C_ICR_TIMOUTCF_Pos (12U)
screamer 28:0e774865873d 9458 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9459 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
screamer 28:0e774865873d 9460 #define I2C_ICR_ALERTCF_Pos (13U)
screamer 28:0e774865873d 9461 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9462 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
screamer 28:0e774865873d 9463
screamer 28:0e774865873d 9464 /****************** Bit definition for I2C_PECR register *********************/
screamer 28:0e774865873d 9465 #define I2C_PECR_PEC_Pos (0U)
screamer 28:0e774865873d 9466 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 9467 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
screamer 28:0e774865873d 9468
screamer 28:0e774865873d 9469 /****************** Bit definition for I2C_RXDR register *********************/
screamer 28:0e774865873d 9470 #define I2C_RXDR_RXDATA_Pos (0U)
screamer 28:0e774865873d 9471 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 9472 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
screamer 28:0e774865873d 9473
screamer 28:0e774865873d 9474 /****************** Bit definition for I2C_TXDR register *********************/
screamer 28:0e774865873d 9475 #define I2C_TXDR_TXDATA_Pos (0U)
screamer 28:0e774865873d 9476 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 9477 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
screamer 28:0e774865873d 9478
screamer 28:0e774865873d 9479 /******************************************************************************/
screamer 28:0e774865873d 9480 /* */
screamer 28:0e774865873d 9481 /* Independent WATCHDOG */
screamer 28:0e774865873d 9482 /* */
screamer 28:0e774865873d 9483 /******************************************************************************/
screamer 28:0e774865873d 9484 /******************* Bit definition for IWDG_KR register ********************/
screamer 28:0e774865873d 9485 #define IWDG_KR_KEY_Pos (0U)
screamer 28:0e774865873d 9486 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 9487 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
screamer 28:0e774865873d 9488
screamer 28:0e774865873d 9489 /******************* Bit definition for IWDG_PR register ********************/
screamer 28:0e774865873d 9490 #define IWDG_PR_PR_Pos (0U)
screamer 28:0e774865873d 9491 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 9492 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
screamer 28:0e774865873d 9493 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9494 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9495 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9496
screamer 28:0e774865873d 9497 /******************* Bit definition for IWDG_RLR register *******************/
screamer 28:0e774865873d 9498 #define IWDG_RLR_RL_Pos (0U)
screamer 28:0e774865873d 9499 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 9500 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
screamer 28:0e774865873d 9501
screamer 28:0e774865873d 9502 /******************* Bit definition for IWDG_SR register ********************/
screamer 28:0e774865873d 9503 #define IWDG_SR_PVU_Pos (0U)
screamer 28:0e774865873d 9504 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9505 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
screamer 28:0e774865873d 9506 #define IWDG_SR_RVU_Pos (1U)
screamer 28:0e774865873d 9507 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9508 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
screamer 28:0e774865873d 9509 #define IWDG_SR_WVU_Pos (2U)
screamer 28:0e774865873d 9510 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9511 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
screamer 28:0e774865873d 9512
screamer 28:0e774865873d 9513 /******************* Bit definition for IWDG_KR register ********************/
screamer 28:0e774865873d 9514 #define IWDG_WINR_WIN_Pos (0U)
screamer 28:0e774865873d 9515 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 9516 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
screamer 28:0e774865873d 9517
screamer 28:0e774865873d 9518 /******************************************************************************/
screamer 28:0e774865873d 9519 /* */
screamer 28:0e774865873d 9520 /* Firewall */
screamer 28:0e774865873d 9521 /* */
screamer 28:0e774865873d 9522 /******************************************************************************/
screamer 28:0e774865873d 9523
screamer 28:0e774865873d 9524 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
screamer 28:0e774865873d 9525 #define FW_CSSA_ADD_Pos (8U)
screamer 28:0e774865873d 9526 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
screamer 28:0e774865873d 9527 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
screamer 28:0e774865873d 9528 #define FW_CSL_LENG_Pos (8U)
screamer 28:0e774865873d 9529 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
screamer 28:0e774865873d 9530 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
screamer 28:0e774865873d 9531 #define FW_NVDSSA_ADD_Pos (8U)
screamer 28:0e774865873d 9532 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
screamer 28:0e774865873d 9533 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
screamer 28:0e774865873d 9534 #define FW_NVDSL_LENG_Pos (8U)
screamer 28:0e774865873d 9535 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
screamer 28:0e774865873d 9536 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
screamer 28:0e774865873d 9537 #define FW_VDSSA_ADD_Pos (6U)
screamer 28:0e774865873d 9538 #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
screamer 28:0e774865873d 9539 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
screamer 28:0e774865873d 9540 #define FW_VDSL_LENG_Pos (6U)
screamer 28:0e774865873d 9541 #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
screamer 28:0e774865873d 9542 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
screamer 28:0e774865873d 9543
screamer 28:0e774865873d 9544 /**************************Bit definition for CR register *********************/
screamer 28:0e774865873d 9545 #define FW_CR_FPA_Pos (0U)
screamer 28:0e774865873d 9546 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9547 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
screamer 28:0e774865873d 9548 #define FW_CR_VDS_Pos (1U)
screamer 28:0e774865873d 9549 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9550 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
screamer 28:0e774865873d 9551 #define FW_CR_VDE_Pos (2U)
screamer 28:0e774865873d 9552 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9553 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
screamer 28:0e774865873d 9554
screamer 28:0e774865873d 9555 /******************************************************************************/
screamer 28:0e774865873d 9556 /* */
screamer 28:0e774865873d 9557 /* Power Control */
screamer 28:0e774865873d 9558 /* */
screamer 28:0e774865873d 9559 /******************************************************************************/
screamer 28:0e774865873d 9560
screamer 28:0e774865873d 9561 /******************** Bit definition for PWR_CR1 register ********************/
screamer 28:0e774865873d 9562
screamer 28:0e774865873d 9563 #define PWR_CR1_LPR_Pos (14U)
screamer 28:0e774865873d 9564 #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9565 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
screamer 28:0e774865873d 9566 #define PWR_CR1_VOS_Pos (9U)
screamer 28:0e774865873d 9567 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
screamer 28:0e774865873d 9568 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
screamer 28:0e774865873d 9569 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9570 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9571 #define PWR_CR1_DBP_Pos (8U)
screamer 28:0e774865873d 9572 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9573 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
screamer 28:0e774865873d 9574 #define PWR_CR1_LPMS_Pos (0U)
screamer 28:0e774865873d 9575 #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 9576 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
screamer 28:0e774865873d 9577 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
screamer 28:0e774865873d 9578 #define PWR_CR1_LPMS_STOP1_Pos (0U)
screamer 28:0e774865873d 9579 #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9580 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
screamer 28:0e774865873d 9581 #define PWR_CR1_LPMS_STOP2_Pos (1U)
screamer 28:0e774865873d 9582 #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9583 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
screamer 28:0e774865873d 9584 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
screamer 28:0e774865873d 9585 #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 9586 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
screamer 28:0e774865873d 9587 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
screamer 28:0e774865873d 9588 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9589 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
screamer 28:0e774865873d 9590
screamer 28:0e774865873d 9591
screamer 28:0e774865873d 9592 /******************** Bit definition for PWR_CR2 register ********************/
screamer 28:0e774865873d 9593 #define PWR_CR2_USV_Pos (10U)
screamer 28:0e774865873d 9594 #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9595 #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
screamer 28:0e774865873d 9596 #define PWR_CR2_IOSV_Pos (9U)
screamer 28:0e774865873d 9597 #define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9598 #define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
screamer 28:0e774865873d 9599 /*!< PVME Peripheral Voltage Monitor Enable */
screamer 28:0e774865873d 9600 #define PWR_CR2_PVME_Pos (4U)
screamer 28:0e774865873d 9601 #define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 9602 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
screamer 28:0e774865873d 9603 #define PWR_CR2_PVME4_Pos (7U)
screamer 28:0e774865873d 9604 #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9605 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
screamer 28:0e774865873d 9606 #define PWR_CR2_PVME3_Pos (6U)
screamer 28:0e774865873d 9607 #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9608 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
screamer 28:0e774865873d 9609 #define PWR_CR2_PVME2_Pos (5U)
screamer 28:0e774865873d 9610 #define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9611 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
screamer 28:0e774865873d 9612 #define PWR_CR2_PVME1_Pos (4U)
screamer 28:0e774865873d 9613 #define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9614 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
screamer 28:0e774865873d 9615 /*!< PVD level configuration */
screamer 28:0e774865873d 9616 #define PWR_CR2_PLS_Pos (1U)
screamer 28:0e774865873d 9617 #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
screamer 28:0e774865873d 9618 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
screamer 28:0e774865873d 9619 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
screamer 28:0e774865873d 9620 #define PWR_CR2_PLS_LEV1_Pos (1U)
screamer 28:0e774865873d 9621 #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9622 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
screamer 28:0e774865873d 9623 #define PWR_CR2_PLS_LEV2_Pos (2U)
screamer 28:0e774865873d 9624 #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9625 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
screamer 28:0e774865873d 9626 #define PWR_CR2_PLS_LEV3_Pos (1U)
screamer 28:0e774865873d 9627 #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
screamer 28:0e774865873d 9628 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
screamer 28:0e774865873d 9629 #define PWR_CR2_PLS_LEV4_Pos (3U)
screamer 28:0e774865873d 9630 #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9631 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
screamer 28:0e774865873d 9632 #define PWR_CR2_PLS_LEV5_Pos (1U)
screamer 28:0e774865873d 9633 #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
screamer 28:0e774865873d 9634 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
screamer 28:0e774865873d 9635 #define PWR_CR2_PLS_LEV6_Pos (2U)
screamer 28:0e774865873d 9636 #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 9637 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
screamer 28:0e774865873d 9638 #define PWR_CR2_PLS_LEV7_Pos (1U)
screamer 28:0e774865873d 9639 #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
screamer 28:0e774865873d 9640 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
screamer 28:0e774865873d 9641 #define PWR_CR2_PVDE_Pos (0U)
screamer 28:0e774865873d 9642 #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9643 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
screamer 28:0e774865873d 9644
screamer 28:0e774865873d 9645 /******************** Bit definition for PWR_CR3 register ********************/
screamer 28:0e774865873d 9646 #define PWR_CR3_EIWUL_Pos (15U)
screamer 28:0e774865873d 9647 #define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9648 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
screamer 28:0e774865873d 9649 #define PWR_CR3_APC_Pos (10U)
screamer 28:0e774865873d 9650 #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9651 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
screamer 28:0e774865873d 9652 #define PWR_CR3_RRS_Pos (8U)
screamer 28:0e774865873d 9653 #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9654 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
screamer 28:0e774865873d 9655 #define PWR_CR3_EWUP5_Pos (4U)
screamer 28:0e774865873d 9656 #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9657 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
screamer 28:0e774865873d 9658 #define PWR_CR3_EWUP4_Pos (3U)
screamer 28:0e774865873d 9659 #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9660 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
screamer 28:0e774865873d 9661 #define PWR_CR3_EWUP3_Pos (2U)
screamer 28:0e774865873d 9662 #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9663 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
screamer 28:0e774865873d 9664 #define PWR_CR3_EWUP2_Pos (1U)
screamer 28:0e774865873d 9665 #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9666 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
screamer 28:0e774865873d 9667 #define PWR_CR3_EWUP1_Pos (0U)
screamer 28:0e774865873d 9668 #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9669 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
screamer 28:0e774865873d 9670 #define PWR_CR3_EWUP_Pos (0U)
screamer 28:0e774865873d 9671 #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 9672 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
screamer 28:0e774865873d 9673
screamer 28:0e774865873d 9674 /* Legacy defines */
screamer 28:0e774865873d 9675 #define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
screamer 28:0e774865873d 9676 #define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
screamer 28:0e774865873d 9677 #define PWR_CR3_EIWF PWR_CR3_EIWUL
screamer 28:0e774865873d 9678
screamer 28:0e774865873d 9679
screamer 28:0e774865873d 9680 /******************** Bit definition for PWR_CR4 register ********************/
screamer 28:0e774865873d 9681 #define PWR_CR4_VBRS_Pos (9U)
screamer 28:0e774865873d 9682 #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9683 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
screamer 28:0e774865873d 9684 #define PWR_CR4_VBE_Pos (8U)
screamer 28:0e774865873d 9685 #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9686 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
screamer 28:0e774865873d 9687 #define PWR_CR4_WP5_Pos (4U)
screamer 28:0e774865873d 9688 #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9689 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
screamer 28:0e774865873d 9690 #define PWR_CR4_WP4_Pos (3U)
screamer 28:0e774865873d 9691 #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9692 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
screamer 28:0e774865873d 9693 #define PWR_CR4_WP3_Pos (2U)
screamer 28:0e774865873d 9694 #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9695 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
screamer 28:0e774865873d 9696 #define PWR_CR4_WP2_Pos (1U)
screamer 28:0e774865873d 9697 #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9698 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
screamer 28:0e774865873d 9699 #define PWR_CR4_WP1_Pos (0U)
screamer 28:0e774865873d 9700 #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9701 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
screamer 28:0e774865873d 9702
screamer 28:0e774865873d 9703 /******************** Bit definition for PWR_SR1 register ********************/
screamer 28:0e774865873d 9704 #define PWR_SR1_WUFI_Pos (15U)
screamer 28:0e774865873d 9705 #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9706 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
screamer 28:0e774865873d 9707 #define PWR_SR1_SBF_Pos (8U)
screamer 28:0e774865873d 9708 #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9709 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
screamer 28:0e774865873d 9710 #define PWR_SR1_WUF_Pos (0U)
screamer 28:0e774865873d 9711 #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 9712 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
screamer 28:0e774865873d 9713 #define PWR_SR1_WUF5_Pos (4U)
screamer 28:0e774865873d 9714 #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9715 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
screamer 28:0e774865873d 9716 #define PWR_SR1_WUF4_Pos (3U)
screamer 28:0e774865873d 9717 #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9718 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
screamer 28:0e774865873d 9719 #define PWR_SR1_WUF3_Pos (2U)
screamer 28:0e774865873d 9720 #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9721 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
screamer 28:0e774865873d 9722 #define PWR_SR1_WUF2_Pos (1U)
screamer 28:0e774865873d 9723 #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9724 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
screamer 28:0e774865873d 9725 #define PWR_SR1_WUF1_Pos (0U)
screamer 28:0e774865873d 9726 #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9727 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
screamer 28:0e774865873d 9728
screamer 28:0e774865873d 9729 /******************** Bit definition for PWR_SR2 register ********************/
screamer 28:0e774865873d 9730 #define PWR_SR2_PVMO4_Pos (15U)
screamer 28:0e774865873d 9731 #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9732 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
screamer 28:0e774865873d 9733 #define PWR_SR2_PVMO3_Pos (14U)
screamer 28:0e774865873d 9734 #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9735 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
screamer 28:0e774865873d 9736 #define PWR_SR2_PVMO2_Pos (13U)
screamer 28:0e774865873d 9737 #define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9738 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
screamer 28:0e774865873d 9739 #define PWR_SR2_PVMO1_Pos (12U)
screamer 28:0e774865873d 9740 #define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9741 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
screamer 28:0e774865873d 9742 #define PWR_SR2_PVDO_Pos (11U)
screamer 28:0e774865873d 9743 #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9744 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
screamer 28:0e774865873d 9745 #define PWR_SR2_VOSF_Pos (10U)
screamer 28:0e774865873d 9746 #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9747 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
screamer 28:0e774865873d 9748 #define PWR_SR2_REGLPF_Pos (9U)
screamer 28:0e774865873d 9749 #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9750 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
screamer 28:0e774865873d 9751 #define PWR_SR2_REGLPS_Pos (8U)
screamer 28:0e774865873d 9752 #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9753 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
screamer 28:0e774865873d 9754
screamer 28:0e774865873d 9755 /******************** Bit definition for PWR_SCR register ********************/
screamer 28:0e774865873d 9756 #define PWR_SCR_CSBF_Pos (8U)
screamer 28:0e774865873d 9757 #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9758 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
screamer 28:0e774865873d 9759 #define PWR_SCR_CWUF_Pos (0U)
screamer 28:0e774865873d 9760 #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 9761 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
screamer 28:0e774865873d 9762 #define PWR_SCR_CWUF5_Pos (4U)
screamer 28:0e774865873d 9763 #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9764 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
screamer 28:0e774865873d 9765 #define PWR_SCR_CWUF4_Pos (3U)
screamer 28:0e774865873d 9766 #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9767 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
screamer 28:0e774865873d 9768 #define PWR_SCR_CWUF3_Pos (2U)
screamer 28:0e774865873d 9769 #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9770 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
screamer 28:0e774865873d 9771 #define PWR_SCR_CWUF2_Pos (1U)
screamer 28:0e774865873d 9772 #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9773 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
screamer 28:0e774865873d 9774 #define PWR_SCR_CWUF1_Pos (0U)
screamer 28:0e774865873d 9775 #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9776 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
screamer 28:0e774865873d 9777
screamer 28:0e774865873d 9778 /******************** Bit definition for PWR_PUCRA register ********************/
screamer 28:0e774865873d 9779 #define PWR_PUCRA_PA15_Pos (15U)
screamer 28:0e774865873d 9780 #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9781 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
screamer 28:0e774865873d 9782 #define PWR_PUCRA_PA13_Pos (13U)
screamer 28:0e774865873d 9783 #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9784 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
screamer 28:0e774865873d 9785 #define PWR_PUCRA_PA12_Pos (12U)
screamer 28:0e774865873d 9786 #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9787 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
screamer 28:0e774865873d 9788 #define PWR_PUCRA_PA11_Pos (11U)
screamer 28:0e774865873d 9789 #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9790 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
screamer 28:0e774865873d 9791 #define PWR_PUCRA_PA10_Pos (10U)
screamer 28:0e774865873d 9792 #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9793 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
screamer 28:0e774865873d 9794 #define PWR_PUCRA_PA9_Pos (9U)
screamer 28:0e774865873d 9795 #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9796 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
screamer 28:0e774865873d 9797 #define PWR_PUCRA_PA8_Pos (8U)
screamer 28:0e774865873d 9798 #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9799 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
screamer 28:0e774865873d 9800 #define PWR_PUCRA_PA7_Pos (7U)
screamer 28:0e774865873d 9801 #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9802 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
screamer 28:0e774865873d 9803 #define PWR_PUCRA_PA6_Pos (6U)
screamer 28:0e774865873d 9804 #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9805 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
screamer 28:0e774865873d 9806 #define PWR_PUCRA_PA5_Pos (5U)
screamer 28:0e774865873d 9807 #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9808 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
screamer 28:0e774865873d 9809 #define PWR_PUCRA_PA4_Pos (4U)
screamer 28:0e774865873d 9810 #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9811 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
screamer 28:0e774865873d 9812 #define PWR_PUCRA_PA3_Pos (3U)
screamer 28:0e774865873d 9813 #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9814 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
screamer 28:0e774865873d 9815 #define PWR_PUCRA_PA2_Pos (2U)
screamer 28:0e774865873d 9816 #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9817 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
screamer 28:0e774865873d 9818 #define PWR_PUCRA_PA1_Pos (1U)
screamer 28:0e774865873d 9819 #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9820 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
screamer 28:0e774865873d 9821 #define PWR_PUCRA_PA0_Pos (0U)
screamer 28:0e774865873d 9822 #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9823 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
screamer 28:0e774865873d 9824
screamer 28:0e774865873d 9825 /******************** Bit definition for PWR_PDCRA register ********************/
screamer 28:0e774865873d 9826 #define PWR_PDCRA_PA14_Pos (14U)
screamer 28:0e774865873d 9827 #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9828 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
screamer 28:0e774865873d 9829 #define PWR_PDCRA_PA12_Pos (12U)
screamer 28:0e774865873d 9830 #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9831 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
screamer 28:0e774865873d 9832 #define PWR_PDCRA_PA11_Pos (11U)
screamer 28:0e774865873d 9833 #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9834 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
screamer 28:0e774865873d 9835 #define PWR_PDCRA_PA10_Pos (10U)
screamer 28:0e774865873d 9836 #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9837 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
screamer 28:0e774865873d 9838 #define PWR_PDCRA_PA9_Pos (9U)
screamer 28:0e774865873d 9839 #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9840 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
screamer 28:0e774865873d 9841 #define PWR_PDCRA_PA8_Pos (8U)
screamer 28:0e774865873d 9842 #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9843 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
screamer 28:0e774865873d 9844 #define PWR_PDCRA_PA7_Pos (7U)
screamer 28:0e774865873d 9845 #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9846 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
screamer 28:0e774865873d 9847 #define PWR_PDCRA_PA6_Pos (6U)
screamer 28:0e774865873d 9848 #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9849 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
screamer 28:0e774865873d 9850 #define PWR_PDCRA_PA5_Pos (5U)
screamer 28:0e774865873d 9851 #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9852 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
screamer 28:0e774865873d 9853 #define PWR_PDCRA_PA4_Pos (4U)
screamer 28:0e774865873d 9854 #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9855 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
screamer 28:0e774865873d 9856 #define PWR_PDCRA_PA3_Pos (3U)
screamer 28:0e774865873d 9857 #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9858 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
screamer 28:0e774865873d 9859 #define PWR_PDCRA_PA2_Pos (2U)
screamer 28:0e774865873d 9860 #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9861 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
screamer 28:0e774865873d 9862 #define PWR_PDCRA_PA1_Pos (1U)
screamer 28:0e774865873d 9863 #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9864 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
screamer 28:0e774865873d 9865 #define PWR_PDCRA_PA0_Pos (0U)
screamer 28:0e774865873d 9866 #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9867 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
screamer 28:0e774865873d 9868
screamer 28:0e774865873d 9869 /******************** Bit definition for PWR_PUCRB register ********************/
screamer 28:0e774865873d 9870 #define PWR_PUCRB_PB15_Pos (15U)
screamer 28:0e774865873d 9871 #define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9872 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
screamer 28:0e774865873d 9873 #define PWR_PUCRB_PB14_Pos (14U)
screamer 28:0e774865873d 9874 #define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9875 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
screamer 28:0e774865873d 9876 #define PWR_PUCRB_PB13_Pos (13U)
screamer 28:0e774865873d 9877 #define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9878 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
screamer 28:0e774865873d 9879 #define PWR_PUCRB_PB12_Pos (12U)
screamer 28:0e774865873d 9880 #define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9881 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
screamer 28:0e774865873d 9882 #define PWR_PUCRB_PB11_Pos (11U)
screamer 28:0e774865873d 9883 #define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9884 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
screamer 28:0e774865873d 9885 #define PWR_PUCRB_PB10_Pos (10U)
screamer 28:0e774865873d 9886 #define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9887 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
screamer 28:0e774865873d 9888 #define PWR_PUCRB_PB9_Pos (9U)
screamer 28:0e774865873d 9889 #define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9890 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
screamer 28:0e774865873d 9891 #define PWR_PUCRB_PB8_Pos (8U)
screamer 28:0e774865873d 9892 #define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9893 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
screamer 28:0e774865873d 9894 #define PWR_PUCRB_PB7_Pos (7U)
screamer 28:0e774865873d 9895 #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9896 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
screamer 28:0e774865873d 9897 #define PWR_PUCRB_PB6_Pos (6U)
screamer 28:0e774865873d 9898 #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9899 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
screamer 28:0e774865873d 9900 #define PWR_PUCRB_PB5_Pos (5U)
screamer 28:0e774865873d 9901 #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9902 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
screamer 28:0e774865873d 9903 #define PWR_PUCRB_PB4_Pos (4U)
screamer 28:0e774865873d 9904 #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 9905 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
screamer 28:0e774865873d 9906 #define PWR_PUCRB_PB3_Pos (3U)
screamer 28:0e774865873d 9907 #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9908 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
screamer 28:0e774865873d 9909 #define PWR_PUCRB_PB2_Pos (2U)
screamer 28:0e774865873d 9910 #define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9911 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
screamer 28:0e774865873d 9912 #define PWR_PUCRB_PB1_Pos (1U)
screamer 28:0e774865873d 9913 #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9914 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
screamer 28:0e774865873d 9915 #define PWR_PUCRB_PB0_Pos (0U)
screamer 28:0e774865873d 9916 #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9917 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
screamer 28:0e774865873d 9918
screamer 28:0e774865873d 9919 /******************** Bit definition for PWR_PDCRB register ********************/
screamer 28:0e774865873d 9920 #define PWR_PDCRB_PB15_Pos (15U)
screamer 28:0e774865873d 9921 #define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9922 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
screamer 28:0e774865873d 9923 #define PWR_PDCRB_PB14_Pos (14U)
screamer 28:0e774865873d 9924 #define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9925 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
screamer 28:0e774865873d 9926 #define PWR_PDCRB_PB13_Pos (13U)
screamer 28:0e774865873d 9927 #define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9928 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
screamer 28:0e774865873d 9929 #define PWR_PDCRB_PB12_Pos (12U)
screamer 28:0e774865873d 9930 #define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9931 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
screamer 28:0e774865873d 9932 #define PWR_PDCRB_PB11_Pos (11U)
screamer 28:0e774865873d 9933 #define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9934 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
screamer 28:0e774865873d 9935 #define PWR_PDCRB_PB10_Pos (10U)
screamer 28:0e774865873d 9936 #define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9937 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
screamer 28:0e774865873d 9938 #define PWR_PDCRB_PB9_Pos (9U)
screamer 28:0e774865873d 9939 #define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9940 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
screamer 28:0e774865873d 9941 #define PWR_PDCRB_PB8_Pos (8U)
screamer 28:0e774865873d 9942 #define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9943 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
screamer 28:0e774865873d 9944 #define PWR_PDCRB_PB7_Pos (7U)
screamer 28:0e774865873d 9945 #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9946 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
screamer 28:0e774865873d 9947 #define PWR_PDCRB_PB6_Pos (6U)
screamer 28:0e774865873d 9948 #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9949 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
screamer 28:0e774865873d 9950 #define PWR_PDCRB_PB5_Pos (5U)
screamer 28:0e774865873d 9951 #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9952 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
screamer 28:0e774865873d 9953 #define PWR_PDCRB_PB3_Pos (3U)
screamer 28:0e774865873d 9954 #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 9955 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
screamer 28:0e774865873d 9956 #define PWR_PDCRB_PB2_Pos (2U)
screamer 28:0e774865873d 9957 #define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 9958 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
screamer 28:0e774865873d 9959 #define PWR_PDCRB_PB1_Pos (1U)
screamer 28:0e774865873d 9960 #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 9961 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
screamer 28:0e774865873d 9962 #define PWR_PDCRB_PB0_Pos (0U)
screamer 28:0e774865873d 9963 #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 9964 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
screamer 28:0e774865873d 9965
screamer 28:0e774865873d 9966 /******************** Bit definition for PWR_PUCRC register ********************/
screamer 28:0e774865873d 9967 #define PWR_PUCRC_PC15_Pos (15U)
screamer 28:0e774865873d 9968 #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 9969 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
screamer 28:0e774865873d 9970 #define PWR_PUCRC_PC14_Pos (14U)
screamer 28:0e774865873d 9971 #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 9972 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
screamer 28:0e774865873d 9973 #define PWR_PUCRC_PC13_Pos (13U)
screamer 28:0e774865873d 9974 #define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 9975 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
screamer 28:0e774865873d 9976 #define PWR_PUCRC_PC12_Pos (12U)
screamer 28:0e774865873d 9977 #define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 9978 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
screamer 28:0e774865873d 9979 #define PWR_PUCRC_PC11_Pos (11U)
screamer 28:0e774865873d 9980 #define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 9981 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
screamer 28:0e774865873d 9982 #define PWR_PUCRC_PC10_Pos (10U)
screamer 28:0e774865873d 9983 #define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 9984 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
screamer 28:0e774865873d 9985 #define PWR_PUCRC_PC9_Pos (9U)
screamer 28:0e774865873d 9986 #define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 9987 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
screamer 28:0e774865873d 9988 #define PWR_PUCRC_PC8_Pos (8U)
screamer 28:0e774865873d 9989 #define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 9990 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
screamer 28:0e774865873d 9991 #define PWR_PUCRC_PC7_Pos (7U)
screamer 28:0e774865873d 9992 #define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 9993 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
screamer 28:0e774865873d 9994 #define PWR_PUCRC_PC6_Pos (6U)
screamer 28:0e774865873d 9995 #define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 9996 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
screamer 28:0e774865873d 9997 #define PWR_PUCRC_PC5_Pos (5U)
screamer 28:0e774865873d 9998 #define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 9999 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
screamer 28:0e774865873d 10000 #define PWR_PUCRC_PC4_Pos (4U)
screamer 28:0e774865873d 10001 #define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10002 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
screamer 28:0e774865873d 10003 #define PWR_PUCRC_PC3_Pos (3U)
screamer 28:0e774865873d 10004 #define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10005 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
screamer 28:0e774865873d 10006 #define PWR_PUCRC_PC2_Pos (2U)
screamer 28:0e774865873d 10007 #define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10008 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
screamer 28:0e774865873d 10009 #define PWR_PUCRC_PC1_Pos (1U)
screamer 28:0e774865873d 10010 #define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10011 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
screamer 28:0e774865873d 10012 #define PWR_PUCRC_PC0_Pos (0U)
screamer 28:0e774865873d 10013 #define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10014 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
screamer 28:0e774865873d 10015
screamer 28:0e774865873d 10016 /******************** Bit definition for PWR_PDCRC register ********************/
screamer 28:0e774865873d 10017 #define PWR_PDCRC_PC15_Pos (15U)
screamer 28:0e774865873d 10018 #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10019 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
screamer 28:0e774865873d 10020 #define PWR_PDCRC_PC14_Pos (14U)
screamer 28:0e774865873d 10021 #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10022 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
screamer 28:0e774865873d 10023 #define PWR_PDCRC_PC13_Pos (13U)
screamer 28:0e774865873d 10024 #define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10025 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
screamer 28:0e774865873d 10026 #define PWR_PDCRC_PC12_Pos (12U)
screamer 28:0e774865873d 10027 #define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10028 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
screamer 28:0e774865873d 10029 #define PWR_PDCRC_PC11_Pos (11U)
screamer 28:0e774865873d 10030 #define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10031 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
screamer 28:0e774865873d 10032 #define PWR_PDCRC_PC10_Pos (10U)
screamer 28:0e774865873d 10033 #define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10034 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
screamer 28:0e774865873d 10035 #define PWR_PDCRC_PC9_Pos (9U)
screamer 28:0e774865873d 10036 #define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10037 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
screamer 28:0e774865873d 10038 #define PWR_PDCRC_PC8_Pos (8U)
screamer 28:0e774865873d 10039 #define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10040 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
screamer 28:0e774865873d 10041 #define PWR_PDCRC_PC7_Pos (7U)
screamer 28:0e774865873d 10042 #define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10043 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
screamer 28:0e774865873d 10044 #define PWR_PDCRC_PC6_Pos (6U)
screamer 28:0e774865873d 10045 #define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10046 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
screamer 28:0e774865873d 10047 #define PWR_PDCRC_PC5_Pos (5U)
screamer 28:0e774865873d 10048 #define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10049 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
screamer 28:0e774865873d 10050 #define PWR_PDCRC_PC4_Pos (4U)
screamer 28:0e774865873d 10051 #define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10052 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
screamer 28:0e774865873d 10053 #define PWR_PDCRC_PC3_Pos (3U)
screamer 28:0e774865873d 10054 #define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10055 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
screamer 28:0e774865873d 10056 #define PWR_PDCRC_PC2_Pos (2U)
screamer 28:0e774865873d 10057 #define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10058 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
screamer 28:0e774865873d 10059 #define PWR_PDCRC_PC1_Pos (1U)
screamer 28:0e774865873d 10060 #define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10061 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
screamer 28:0e774865873d 10062 #define PWR_PDCRC_PC0_Pos (0U)
screamer 28:0e774865873d 10063 #define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10064 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
screamer 28:0e774865873d 10065
screamer 28:0e774865873d 10066 /******************** Bit definition for PWR_PUCRD register ********************/
screamer 28:0e774865873d 10067 #define PWR_PUCRD_PD15_Pos (15U)
screamer 28:0e774865873d 10068 #define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10069 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
screamer 28:0e774865873d 10070 #define PWR_PUCRD_PD14_Pos (14U)
screamer 28:0e774865873d 10071 #define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10072 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
screamer 28:0e774865873d 10073 #define PWR_PUCRD_PD13_Pos (13U)
screamer 28:0e774865873d 10074 #define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10075 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
screamer 28:0e774865873d 10076 #define PWR_PUCRD_PD12_Pos (12U)
screamer 28:0e774865873d 10077 #define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10078 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
screamer 28:0e774865873d 10079 #define PWR_PUCRD_PD11_Pos (11U)
screamer 28:0e774865873d 10080 #define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10081 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
screamer 28:0e774865873d 10082 #define PWR_PUCRD_PD10_Pos (10U)
screamer 28:0e774865873d 10083 #define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10084 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
screamer 28:0e774865873d 10085 #define PWR_PUCRD_PD9_Pos (9U)
screamer 28:0e774865873d 10086 #define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10087 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
screamer 28:0e774865873d 10088 #define PWR_PUCRD_PD8_Pos (8U)
screamer 28:0e774865873d 10089 #define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10090 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
screamer 28:0e774865873d 10091 #define PWR_PUCRD_PD7_Pos (7U)
screamer 28:0e774865873d 10092 #define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10093 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
screamer 28:0e774865873d 10094 #define PWR_PUCRD_PD6_Pos (6U)
screamer 28:0e774865873d 10095 #define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10096 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
screamer 28:0e774865873d 10097 #define PWR_PUCRD_PD5_Pos (5U)
screamer 28:0e774865873d 10098 #define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10099 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
screamer 28:0e774865873d 10100 #define PWR_PUCRD_PD4_Pos (4U)
screamer 28:0e774865873d 10101 #define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10102 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
screamer 28:0e774865873d 10103 #define PWR_PUCRD_PD3_Pos (3U)
screamer 28:0e774865873d 10104 #define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10105 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
screamer 28:0e774865873d 10106 #define PWR_PUCRD_PD2_Pos (2U)
screamer 28:0e774865873d 10107 #define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10108 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
screamer 28:0e774865873d 10109 #define PWR_PUCRD_PD1_Pos (1U)
screamer 28:0e774865873d 10110 #define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10111 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
screamer 28:0e774865873d 10112 #define PWR_PUCRD_PD0_Pos (0U)
screamer 28:0e774865873d 10113 #define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10114 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
screamer 28:0e774865873d 10115
screamer 28:0e774865873d 10116 /******************** Bit definition for PWR_PDCRD register ********************/
screamer 28:0e774865873d 10117 #define PWR_PDCRD_PD15_Pos (15U)
screamer 28:0e774865873d 10118 #define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10119 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
screamer 28:0e774865873d 10120 #define PWR_PDCRD_PD14_Pos (14U)
screamer 28:0e774865873d 10121 #define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10122 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
screamer 28:0e774865873d 10123 #define PWR_PDCRD_PD13_Pos (13U)
screamer 28:0e774865873d 10124 #define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10125 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
screamer 28:0e774865873d 10126 #define PWR_PDCRD_PD12_Pos (12U)
screamer 28:0e774865873d 10127 #define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10128 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
screamer 28:0e774865873d 10129 #define PWR_PDCRD_PD11_Pos (11U)
screamer 28:0e774865873d 10130 #define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10131 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
screamer 28:0e774865873d 10132 #define PWR_PDCRD_PD10_Pos (10U)
screamer 28:0e774865873d 10133 #define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10134 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
screamer 28:0e774865873d 10135 #define PWR_PDCRD_PD9_Pos (9U)
screamer 28:0e774865873d 10136 #define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10137 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
screamer 28:0e774865873d 10138 #define PWR_PDCRD_PD8_Pos (8U)
screamer 28:0e774865873d 10139 #define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10140 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
screamer 28:0e774865873d 10141 #define PWR_PDCRD_PD7_Pos (7U)
screamer 28:0e774865873d 10142 #define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10143 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
screamer 28:0e774865873d 10144 #define PWR_PDCRD_PD6_Pos (6U)
screamer 28:0e774865873d 10145 #define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10146 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
screamer 28:0e774865873d 10147 #define PWR_PDCRD_PD5_Pos (5U)
screamer 28:0e774865873d 10148 #define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10149 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
screamer 28:0e774865873d 10150 #define PWR_PDCRD_PD4_Pos (4U)
screamer 28:0e774865873d 10151 #define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10152 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
screamer 28:0e774865873d 10153 #define PWR_PDCRD_PD3_Pos (3U)
screamer 28:0e774865873d 10154 #define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10155 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
screamer 28:0e774865873d 10156 #define PWR_PDCRD_PD2_Pos (2U)
screamer 28:0e774865873d 10157 #define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10158 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
screamer 28:0e774865873d 10159 #define PWR_PDCRD_PD1_Pos (1U)
screamer 28:0e774865873d 10160 #define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10161 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
screamer 28:0e774865873d 10162 #define PWR_PDCRD_PD0_Pos (0U)
screamer 28:0e774865873d 10163 #define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10164 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
screamer 28:0e774865873d 10165
screamer 28:0e774865873d 10166 /******************** Bit definition for PWR_PUCRE register ********************/
screamer 28:0e774865873d 10167 #define PWR_PUCRE_PE15_Pos (15U)
screamer 28:0e774865873d 10168 #define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10169 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
screamer 28:0e774865873d 10170 #define PWR_PUCRE_PE14_Pos (14U)
screamer 28:0e774865873d 10171 #define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10172 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
screamer 28:0e774865873d 10173 #define PWR_PUCRE_PE13_Pos (13U)
screamer 28:0e774865873d 10174 #define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10175 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
screamer 28:0e774865873d 10176 #define PWR_PUCRE_PE12_Pos (12U)
screamer 28:0e774865873d 10177 #define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10178 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
screamer 28:0e774865873d 10179 #define PWR_PUCRE_PE11_Pos (11U)
screamer 28:0e774865873d 10180 #define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10181 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
screamer 28:0e774865873d 10182 #define PWR_PUCRE_PE10_Pos (10U)
screamer 28:0e774865873d 10183 #define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10184 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
screamer 28:0e774865873d 10185 #define PWR_PUCRE_PE9_Pos (9U)
screamer 28:0e774865873d 10186 #define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10187 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
screamer 28:0e774865873d 10188 #define PWR_PUCRE_PE8_Pos (8U)
screamer 28:0e774865873d 10189 #define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10190 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
screamer 28:0e774865873d 10191 #define PWR_PUCRE_PE7_Pos (7U)
screamer 28:0e774865873d 10192 #define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10193 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
screamer 28:0e774865873d 10194 #define PWR_PUCRE_PE6_Pos (6U)
screamer 28:0e774865873d 10195 #define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10196 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
screamer 28:0e774865873d 10197 #define PWR_PUCRE_PE5_Pos (5U)
screamer 28:0e774865873d 10198 #define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10199 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
screamer 28:0e774865873d 10200 #define PWR_PUCRE_PE4_Pos (4U)
screamer 28:0e774865873d 10201 #define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10202 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
screamer 28:0e774865873d 10203 #define PWR_PUCRE_PE3_Pos (3U)
screamer 28:0e774865873d 10204 #define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10205 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
screamer 28:0e774865873d 10206 #define PWR_PUCRE_PE2_Pos (2U)
screamer 28:0e774865873d 10207 #define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10208 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
screamer 28:0e774865873d 10209 #define PWR_PUCRE_PE1_Pos (1U)
screamer 28:0e774865873d 10210 #define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10211 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
screamer 28:0e774865873d 10212 #define PWR_PUCRE_PE0_Pos (0U)
screamer 28:0e774865873d 10213 #define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10214 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
screamer 28:0e774865873d 10215
screamer 28:0e774865873d 10216 /******************** Bit definition for PWR_PDCRE register ********************/
screamer 28:0e774865873d 10217 #define PWR_PDCRE_PE15_Pos (15U)
screamer 28:0e774865873d 10218 #define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10219 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
screamer 28:0e774865873d 10220 #define PWR_PDCRE_PE14_Pos (14U)
screamer 28:0e774865873d 10221 #define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10222 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
screamer 28:0e774865873d 10223 #define PWR_PDCRE_PE13_Pos (13U)
screamer 28:0e774865873d 10224 #define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10225 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
screamer 28:0e774865873d 10226 #define PWR_PDCRE_PE12_Pos (12U)
screamer 28:0e774865873d 10227 #define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10228 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
screamer 28:0e774865873d 10229 #define PWR_PDCRE_PE11_Pos (11U)
screamer 28:0e774865873d 10230 #define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10231 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
screamer 28:0e774865873d 10232 #define PWR_PDCRE_PE10_Pos (10U)
screamer 28:0e774865873d 10233 #define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10234 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
screamer 28:0e774865873d 10235 #define PWR_PDCRE_PE9_Pos (9U)
screamer 28:0e774865873d 10236 #define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10237 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
screamer 28:0e774865873d 10238 #define PWR_PDCRE_PE8_Pos (8U)
screamer 28:0e774865873d 10239 #define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10240 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
screamer 28:0e774865873d 10241 #define PWR_PDCRE_PE7_Pos (7U)
screamer 28:0e774865873d 10242 #define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10243 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
screamer 28:0e774865873d 10244 #define PWR_PDCRE_PE6_Pos (6U)
screamer 28:0e774865873d 10245 #define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10246 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
screamer 28:0e774865873d 10247 #define PWR_PDCRE_PE5_Pos (5U)
screamer 28:0e774865873d 10248 #define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10249 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
screamer 28:0e774865873d 10250 #define PWR_PDCRE_PE4_Pos (4U)
screamer 28:0e774865873d 10251 #define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10252 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
screamer 28:0e774865873d 10253 #define PWR_PDCRE_PE3_Pos (3U)
screamer 28:0e774865873d 10254 #define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10255 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
screamer 28:0e774865873d 10256 #define PWR_PDCRE_PE2_Pos (2U)
screamer 28:0e774865873d 10257 #define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10258 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
screamer 28:0e774865873d 10259 #define PWR_PDCRE_PE1_Pos (1U)
screamer 28:0e774865873d 10260 #define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10261 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
screamer 28:0e774865873d 10262 #define PWR_PDCRE_PE0_Pos (0U)
screamer 28:0e774865873d 10263 #define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10264 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
screamer 28:0e774865873d 10265
screamer 28:0e774865873d 10266 /******************** Bit definition for PWR_PUCRF register ********************/
screamer 28:0e774865873d 10267 #define PWR_PUCRF_PF15_Pos (15U)
screamer 28:0e774865873d 10268 #define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10269 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
screamer 28:0e774865873d 10270 #define PWR_PUCRF_PF14_Pos (14U)
screamer 28:0e774865873d 10271 #define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10272 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
screamer 28:0e774865873d 10273 #define PWR_PUCRF_PF13_Pos (13U)
screamer 28:0e774865873d 10274 #define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10275 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
screamer 28:0e774865873d 10276 #define PWR_PUCRF_PF12_Pos (12U)
screamer 28:0e774865873d 10277 #define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10278 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
screamer 28:0e774865873d 10279 #define PWR_PUCRF_PF11_Pos (11U)
screamer 28:0e774865873d 10280 #define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10281 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
screamer 28:0e774865873d 10282 #define PWR_PUCRF_PF10_Pos (10U)
screamer 28:0e774865873d 10283 #define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10284 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
screamer 28:0e774865873d 10285 #define PWR_PUCRF_PF9_Pos (9U)
screamer 28:0e774865873d 10286 #define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10287 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
screamer 28:0e774865873d 10288 #define PWR_PUCRF_PF8_Pos (8U)
screamer 28:0e774865873d 10289 #define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10290 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
screamer 28:0e774865873d 10291 #define PWR_PUCRF_PF7_Pos (7U)
screamer 28:0e774865873d 10292 #define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10293 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
screamer 28:0e774865873d 10294 #define PWR_PUCRF_PF6_Pos (6U)
screamer 28:0e774865873d 10295 #define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10296 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
screamer 28:0e774865873d 10297 #define PWR_PUCRF_PF5_Pos (5U)
screamer 28:0e774865873d 10298 #define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10299 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
screamer 28:0e774865873d 10300 #define PWR_PUCRF_PF4_Pos (4U)
screamer 28:0e774865873d 10301 #define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10302 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
screamer 28:0e774865873d 10303 #define PWR_PUCRF_PF3_Pos (3U)
screamer 28:0e774865873d 10304 #define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10305 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
screamer 28:0e774865873d 10306 #define PWR_PUCRF_PF2_Pos (2U)
screamer 28:0e774865873d 10307 #define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10308 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
screamer 28:0e774865873d 10309 #define PWR_PUCRF_PF1_Pos (1U)
screamer 28:0e774865873d 10310 #define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10311 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
screamer 28:0e774865873d 10312 #define PWR_PUCRF_PF0_Pos (0U)
screamer 28:0e774865873d 10313 #define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10314 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
screamer 28:0e774865873d 10315
screamer 28:0e774865873d 10316 /******************** Bit definition for PWR_PDCRF register ********************/
screamer 28:0e774865873d 10317 #define PWR_PDCRF_PF15_Pos (15U)
screamer 28:0e774865873d 10318 #define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10319 #define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
screamer 28:0e774865873d 10320 #define PWR_PDCRF_PF14_Pos (14U)
screamer 28:0e774865873d 10321 #define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10322 #define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
screamer 28:0e774865873d 10323 #define PWR_PDCRF_PF13_Pos (13U)
screamer 28:0e774865873d 10324 #define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10325 #define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
screamer 28:0e774865873d 10326 #define PWR_PDCRF_PF12_Pos (12U)
screamer 28:0e774865873d 10327 #define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10328 #define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
screamer 28:0e774865873d 10329 #define PWR_PDCRF_PF11_Pos (11U)
screamer 28:0e774865873d 10330 #define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10331 #define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
screamer 28:0e774865873d 10332 #define PWR_PDCRF_PF10_Pos (10U)
screamer 28:0e774865873d 10333 #define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10334 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
screamer 28:0e774865873d 10335 #define PWR_PDCRF_PF9_Pos (9U)
screamer 28:0e774865873d 10336 #define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10337 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
screamer 28:0e774865873d 10338 #define PWR_PDCRF_PF8_Pos (8U)
screamer 28:0e774865873d 10339 #define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10340 #define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
screamer 28:0e774865873d 10341 #define PWR_PDCRF_PF7_Pos (7U)
screamer 28:0e774865873d 10342 #define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10343 #define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
screamer 28:0e774865873d 10344 #define PWR_PDCRF_PF6_Pos (6U)
screamer 28:0e774865873d 10345 #define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10346 #define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
screamer 28:0e774865873d 10347 #define PWR_PDCRF_PF5_Pos (5U)
screamer 28:0e774865873d 10348 #define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10349 #define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
screamer 28:0e774865873d 10350 #define PWR_PDCRF_PF4_Pos (4U)
screamer 28:0e774865873d 10351 #define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10352 #define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
screamer 28:0e774865873d 10353 #define PWR_PDCRF_PF3_Pos (3U)
screamer 28:0e774865873d 10354 #define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10355 #define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
screamer 28:0e774865873d 10356 #define PWR_PDCRF_PF2_Pos (2U)
screamer 28:0e774865873d 10357 #define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10358 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
screamer 28:0e774865873d 10359 #define PWR_PDCRF_PF1_Pos (1U)
screamer 28:0e774865873d 10360 #define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10361 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
screamer 28:0e774865873d 10362 #define PWR_PDCRF_PF0_Pos (0U)
screamer 28:0e774865873d 10363 #define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10364 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
screamer 28:0e774865873d 10365
screamer 28:0e774865873d 10366 /******************** Bit definition for PWR_PUCRG register ********************/
screamer 28:0e774865873d 10367 #define PWR_PUCRG_PG15_Pos (15U)
screamer 28:0e774865873d 10368 #define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10369 #define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
screamer 28:0e774865873d 10370 #define PWR_PUCRG_PG14_Pos (14U)
screamer 28:0e774865873d 10371 #define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10372 #define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
screamer 28:0e774865873d 10373 #define PWR_PUCRG_PG13_Pos (13U)
screamer 28:0e774865873d 10374 #define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10375 #define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
screamer 28:0e774865873d 10376 #define PWR_PUCRG_PG12_Pos (12U)
screamer 28:0e774865873d 10377 #define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10378 #define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
screamer 28:0e774865873d 10379 #define PWR_PUCRG_PG11_Pos (11U)
screamer 28:0e774865873d 10380 #define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10381 #define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
screamer 28:0e774865873d 10382 #define PWR_PUCRG_PG10_Pos (10U)
screamer 28:0e774865873d 10383 #define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10384 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
screamer 28:0e774865873d 10385 #define PWR_PUCRG_PG9_Pos (9U)
screamer 28:0e774865873d 10386 #define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10387 #define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
screamer 28:0e774865873d 10388 #define PWR_PUCRG_PG8_Pos (8U)
screamer 28:0e774865873d 10389 #define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10390 #define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
screamer 28:0e774865873d 10391 #define PWR_PUCRG_PG7_Pos (7U)
screamer 28:0e774865873d 10392 #define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10393 #define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
screamer 28:0e774865873d 10394 #define PWR_PUCRG_PG6_Pos (6U)
screamer 28:0e774865873d 10395 #define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10396 #define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
screamer 28:0e774865873d 10397 #define PWR_PUCRG_PG5_Pos (5U)
screamer 28:0e774865873d 10398 #define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10399 #define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
screamer 28:0e774865873d 10400 #define PWR_PUCRG_PG4_Pos (4U)
screamer 28:0e774865873d 10401 #define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10402 #define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
screamer 28:0e774865873d 10403 #define PWR_PUCRG_PG3_Pos (3U)
screamer 28:0e774865873d 10404 #define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10405 #define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
screamer 28:0e774865873d 10406 #define PWR_PUCRG_PG2_Pos (2U)
screamer 28:0e774865873d 10407 #define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10408 #define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
screamer 28:0e774865873d 10409 #define PWR_PUCRG_PG1_Pos (1U)
screamer 28:0e774865873d 10410 #define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10411 #define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
screamer 28:0e774865873d 10412 #define PWR_PUCRG_PG0_Pos (0U)
screamer 28:0e774865873d 10413 #define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10414 #define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
screamer 28:0e774865873d 10415
screamer 28:0e774865873d 10416 /******************** Bit definition for PWR_PDCRG register ********************/
screamer 28:0e774865873d 10417 #define PWR_PDCRG_PG15_Pos (15U)
screamer 28:0e774865873d 10418 #define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10419 #define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
screamer 28:0e774865873d 10420 #define PWR_PDCRG_PG14_Pos (14U)
screamer 28:0e774865873d 10421 #define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10422 #define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
screamer 28:0e774865873d 10423 #define PWR_PDCRG_PG13_Pos (13U)
screamer 28:0e774865873d 10424 #define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10425 #define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
screamer 28:0e774865873d 10426 #define PWR_PDCRG_PG12_Pos (12U)
screamer 28:0e774865873d 10427 #define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10428 #define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
screamer 28:0e774865873d 10429 #define PWR_PDCRG_PG11_Pos (11U)
screamer 28:0e774865873d 10430 #define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10431 #define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
screamer 28:0e774865873d 10432 #define PWR_PDCRG_PG10_Pos (10U)
screamer 28:0e774865873d 10433 #define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10434 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
screamer 28:0e774865873d 10435 #define PWR_PDCRG_PG9_Pos (9U)
screamer 28:0e774865873d 10436 #define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10437 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
screamer 28:0e774865873d 10438 #define PWR_PDCRG_PG8_Pos (8U)
screamer 28:0e774865873d 10439 #define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10440 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
screamer 28:0e774865873d 10441 #define PWR_PDCRG_PG7_Pos (7U)
screamer 28:0e774865873d 10442 #define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10443 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
screamer 28:0e774865873d 10444 #define PWR_PDCRG_PG6_Pos (6U)
screamer 28:0e774865873d 10445 #define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10446 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
screamer 28:0e774865873d 10447 #define PWR_PDCRG_PG5_Pos (5U)
screamer 28:0e774865873d 10448 #define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10449 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
screamer 28:0e774865873d 10450 #define PWR_PDCRG_PG4_Pos (4U)
screamer 28:0e774865873d 10451 #define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10452 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
screamer 28:0e774865873d 10453 #define PWR_PDCRG_PG3_Pos (3U)
screamer 28:0e774865873d 10454 #define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10455 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
screamer 28:0e774865873d 10456 #define PWR_PDCRG_PG2_Pos (2U)
screamer 28:0e774865873d 10457 #define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10458 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
screamer 28:0e774865873d 10459 #define PWR_PDCRG_PG1_Pos (1U)
screamer 28:0e774865873d 10460 #define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10461 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
screamer 28:0e774865873d 10462 #define PWR_PDCRG_PG0_Pos (0U)
screamer 28:0e774865873d 10463 #define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10464 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
screamer 28:0e774865873d 10465
screamer 28:0e774865873d 10466 /******************** Bit definition for PWR_PUCRH register ********************/
screamer 28:0e774865873d 10467 #define PWR_PUCRH_PH1_Pos (1U)
screamer 28:0e774865873d 10468 #define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10469 #define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
screamer 28:0e774865873d 10470 #define PWR_PUCRH_PH0_Pos (0U)
screamer 28:0e774865873d 10471 #define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10472 #define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
screamer 28:0e774865873d 10473
screamer 28:0e774865873d 10474 /******************** Bit definition for PWR_PDCRH register ********************/
screamer 28:0e774865873d 10475 #define PWR_PDCRH_PH1_Pos (1U)
screamer 28:0e774865873d 10476 #define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10477 #define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
screamer 28:0e774865873d 10478 #define PWR_PDCRH_PH0_Pos (0U)
screamer 28:0e774865873d 10479 #define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10480 #define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
screamer 28:0e774865873d 10481
screamer 28:0e774865873d 10482
screamer 28:0e774865873d 10483 /******************************************************************************/
screamer 28:0e774865873d 10484 /* */
screamer 28:0e774865873d 10485 /* Reset and Clock Control */
screamer 28:0e774865873d 10486 /* */
screamer 28:0e774865873d 10487 /******************************************************************************/
screamer 28:0e774865873d 10488 /*
screamer 28:0e774865873d 10489 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
screamer 28:0e774865873d 10490 */
screamer 28:0e774865873d 10491 #define RCC_PLLSAI2_SUPPORT
screamer 28:0e774865873d 10492
screamer 28:0e774865873d 10493 /******************** Bit definition for RCC_CR register ********************/
screamer 28:0e774865873d 10494 #define RCC_CR_MSION_Pos (0U)
screamer 28:0e774865873d 10495 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10496 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
screamer 28:0e774865873d 10497 #define RCC_CR_MSIRDY_Pos (1U)
screamer 28:0e774865873d 10498 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10499 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
screamer 28:0e774865873d 10500 #define RCC_CR_MSIPLLEN_Pos (2U)
screamer 28:0e774865873d 10501 #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10502 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
screamer 28:0e774865873d 10503 #define RCC_CR_MSIRGSEL_Pos (3U)
screamer 28:0e774865873d 10504 #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10505 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
screamer 28:0e774865873d 10506
screamer 28:0e774865873d 10507 /*!< MSIRANGE configuration : 12 frequency ranges available */
screamer 28:0e774865873d 10508 #define RCC_CR_MSIRANGE_Pos (4U)
screamer 28:0e774865873d 10509 #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 10510 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
screamer 28:0e774865873d 10511 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
screamer 28:0e774865873d 10512 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10513 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10514 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 10515 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10516 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
screamer 28:0e774865873d 10517 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
screamer 28:0e774865873d 10518 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 10519 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10520 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
screamer 28:0e774865873d 10521 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
screamer 28:0e774865873d 10522 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
screamer 28:0e774865873d 10523
screamer 28:0e774865873d 10524 #define RCC_CR_HSION_Pos (8U)
screamer 28:0e774865873d 10525 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10526 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
screamer 28:0e774865873d 10527 #define RCC_CR_HSIKERON_Pos (9U)
screamer 28:0e774865873d 10528 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10529 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
screamer 28:0e774865873d 10530 #define RCC_CR_HSIRDY_Pos (10U)
screamer 28:0e774865873d 10531 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10532 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
screamer 28:0e774865873d 10533 #define RCC_CR_HSIASFS_Pos (11U)
screamer 28:0e774865873d 10534 #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10535 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
screamer 28:0e774865873d 10536
screamer 28:0e774865873d 10537 #define RCC_CR_HSEON_Pos (16U)
screamer 28:0e774865873d 10538 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 10539 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
screamer 28:0e774865873d 10540 #define RCC_CR_HSERDY_Pos (17U)
screamer 28:0e774865873d 10541 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 10542 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
screamer 28:0e774865873d 10543 #define RCC_CR_HSEBYP_Pos (18U)
screamer 28:0e774865873d 10544 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 10545 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
screamer 28:0e774865873d 10546 #define RCC_CR_CSSON_Pos (19U)
screamer 28:0e774865873d 10547 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 10548 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
screamer 28:0e774865873d 10549
screamer 28:0e774865873d 10550 #define RCC_CR_PLLON_Pos (24U)
screamer 28:0e774865873d 10551 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 10552 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
screamer 28:0e774865873d 10553 #define RCC_CR_PLLRDY_Pos (25U)
screamer 28:0e774865873d 10554 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 10555 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
screamer 28:0e774865873d 10556 #define RCC_CR_PLLSAI1ON_Pos (26U)
screamer 28:0e774865873d 10557 #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 10558 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
screamer 28:0e774865873d 10559 #define RCC_CR_PLLSAI1RDY_Pos (27U)
screamer 28:0e774865873d 10560 #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 10561 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
screamer 28:0e774865873d 10562 #define RCC_CR_PLLSAI2ON_Pos (28U)
screamer 28:0e774865873d 10563 #define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 10564 #define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
screamer 28:0e774865873d 10565 #define RCC_CR_PLLSAI2RDY_Pos (29U)
screamer 28:0e774865873d 10566 #define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 10567 #define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
screamer 28:0e774865873d 10568
screamer 28:0e774865873d 10569 /******************** Bit definition for RCC_ICSCR register ***************/
screamer 28:0e774865873d 10570 /*!< MSICAL configuration */
screamer 28:0e774865873d 10571 #define RCC_ICSCR_MSICAL_Pos (0U)
screamer 28:0e774865873d 10572 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 10573 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
screamer 28:0e774865873d 10574 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10575 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10576 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10577 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10578 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10579 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10580 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10581 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10582
screamer 28:0e774865873d 10583 /*!< MSITRIM configuration */
screamer 28:0e774865873d 10584 #define RCC_ICSCR_MSITRIM_Pos (8U)
screamer 28:0e774865873d 10585 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 10586 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
screamer 28:0e774865873d 10587 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10588 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10589 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10590 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10591 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10592 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10593 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10594 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10595
screamer 28:0e774865873d 10596 /*!< HSICAL configuration */
screamer 28:0e774865873d 10597 #define RCC_ICSCR_HSICAL_Pos (16U)
screamer 28:0e774865873d 10598 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 10599 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
screamer 28:0e774865873d 10600 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 10601 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 10602 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 10603 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 10604 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 10605 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 10606 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 10607 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 10608
screamer 28:0e774865873d 10609 /*!< HSITRIM configuration */
screamer 28:0e774865873d 10610 #define RCC_ICSCR_HSITRIM_Pos (24U)
screamer 28:0e774865873d 10611 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
screamer 28:0e774865873d 10612 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
screamer 28:0e774865873d 10613 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 10614 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 10615 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 10616 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 10617 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 10618
screamer 28:0e774865873d 10619 /******************** Bit definition for RCC_CFGR register ******************/
screamer 28:0e774865873d 10620 /*!< SW configuration */
screamer 28:0e774865873d 10621 #define RCC_CFGR_SW_Pos (0U)
screamer 28:0e774865873d 10622 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 10623 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
screamer 28:0e774865873d 10624 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10625 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10626
screamer 28:0e774865873d 10627 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
screamer 28:0e774865873d 10628 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
screamer 28:0e774865873d 10629 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
screamer 28:0e774865873d 10630 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
screamer 28:0e774865873d 10631
screamer 28:0e774865873d 10632 /*!< SWS configuration */
screamer 28:0e774865873d 10633 #define RCC_CFGR_SWS_Pos (2U)
screamer 28:0e774865873d 10634 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 10635 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
screamer 28:0e774865873d 10636 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10637 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10638
screamer 28:0e774865873d 10639 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
screamer 28:0e774865873d 10640 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
screamer 28:0e774865873d 10641 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
screamer 28:0e774865873d 10642 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
screamer 28:0e774865873d 10643
screamer 28:0e774865873d 10644 /*!< HPRE configuration */
screamer 28:0e774865873d 10645 #define RCC_CFGR_HPRE_Pos (4U)
screamer 28:0e774865873d 10646 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 10647 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
screamer 28:0e774865873d 10648 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10649 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10650 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10651 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10652
screamer 28:0e774865873d 10653 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
screamer 28:0e774865873d 10654 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
screamer 28:0e774865873d 10655 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
screamer 28:0e774865873d 10656 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
screamer 28:0e774865873d 10657 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
screamer 28:0e774865873d 10658 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
screamer 28:0e774865873d 10659 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
screamer 28:0e774865873d 10660 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
screamer 28:0e774865873d 10661 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
screamer 28:0e774865873d 10662
screamer 28:0e774865873d 10663 /*!< PPRE1 configuration */
screamer 28:0e774865873d 10664 #define RCC_CFGR_PPRE1_Pos (8U)
screamer 28:0e774865873d 10665 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 10666 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
screamer 28:0e774865873d 10667 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10668 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10669 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10670
screamer 28:0e774865873d 10671 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
screamer 28:0e774865873d 10672 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
screamer 28:0e774865873d 10673 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
screamer 28:0e774865873d 10674 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
screamer 28:0e774865873d 10675 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
screamer 28:0e774865873d 10676
screamer 28:0e774865873d 10677 /*!< PPRE2 configuration */
screamer 28:0e774865873d 10678 #define RCC_CFGR_PPRE2_Pos (11U)
screamer 28:0e774865873d 10679 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
screamer 28:0e774865873d 10680 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
screamer 28:0e774865873d 10681 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10682 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10683 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10684
screamer 28:0e774865873d 10685 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
screamer 28:0e774865873d 10686 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
screamer 28:0e774865873d 10687 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
screamer 28:0e774865873d 10688 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
screamer 28:0e774865873d 10689 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
screamer 28:0e774865873d 10690
screamer 28:0e774865873d 10691 #define RCC_CFGR_STOPWUCK_Pos (15U)
screamer 28:0e774865873d 10692 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 10693 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
screamer 28:0e774865873d 10694
screamer 28:0e774865873d 10695 /*!< MCOSEL configuration */
screamer 28:0e774865873d 10696 #define RCC_CFGR_MCOSEL_Pos (24U)
screamer 28:0e774865873d 10697 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
screamer 28:0e774865873d 10698 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
screamer 28:0e774865873d 10699 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 10700 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 10701 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 10702
screamer 28:0e774865873d 10703 #define RCC_CFGR_MCOPRE_Pos (28U)
screamer 28:0e774865873d 10704 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
screamer 28:0e774865873d 10705 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
screamer 28:0e774865873d 10706 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 10707 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 10708 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 10709
screamer 28:0e774865873d 10710 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
screamer 28:0e774865873d 10711 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
screamer 28:0e774865873d 10712 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
screamer 28:0e774865873d 10713 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
screamer 28:0e774865873d 10714 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
screamer 28:0e774865873d 10715
screamer 28:0e774865873d 10716 /* Legacy aliases */
screamer 28:0e774865873d 10717 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
screamer 28:0e774865873d 10718 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
screamer 28:0e774865873d 10719 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
screamer 28:0e774865873d 10720 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
screamer 28:0e774865873d 10721 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
screamer 28:0e774865873d 10722 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
screamer 28:0e774865873d 10723
screamer 28:0e774865873d 10724 /******************** Bit definition for RCC_PLLCFGR register ***************/
screamer 28:0e774865873d 10725 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
screamer 28:0e774865873d 10726 #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 10727 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
screamer 28:0e774865873d 10728
screamer 28:0e774865873d 10729 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
screamer 28:0e774865873d 10730 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10731 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
screamer 28:0e774865873d 10732 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
screamer 28:0e774865873d 10733 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10734 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
screamer 28:0e774865873d 10735 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
screamer 28:0e774865873d 10736 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 10737 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
screamer 28:0e774865873d 10738
screamer 28:0e774865873d 10739 #define RCC_PLLCFGR_PLLM_Pos (4U)
screamer 28:0e774865873d 10740 #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 10741 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
screamer 28:0e774865873d 10742 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10743 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10744 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10745
screamer 28:0e774865873d 10746 #define RCC_PLLCFGR_PLLN_Pos (8U)
screamer 28:0e774865873d 10747 #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
screamer 28:0e774865873d 10748 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
screamer 28:0e774865873d 10749 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10750 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10751 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10752 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10753 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10754 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10755 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10756
screamer 28:0e774865873d 10757 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
screamer 28:0e774865873d 10758 #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 10759 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
screamer 28:0e774865873d 10760 #define RCC_PLLCFGR_PLLP_Pos (17U)
screamer 28:0e774865873d 10761 #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 10762 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
screamer 28:0e774865873d 10763 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
screamer 28:0e774865873d 10764 #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 10765 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
screamer 28:0e774865873d 10766
screamer 28:0e774865873d 10767 #define RCC_PLLCFGR_PLLQ_Pos (21U)
screamer 28:0e774865873d 10768 #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
screamer 28:0e774865873d 10769 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
screamer 28:0e774865873d 10770 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 10771 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 10772
screamer 28:0e774865873d 10773 #define RCC_PLLCFGR_PLLREN_Pos (24U)
screamer 28:0e774865873d 10774 #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 10775 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
screamer 28:0e774865873d 10776 #define RCC_PLLCFGR_PLLR_Pos (25U)
screamer 28:0e774865873d 10777 #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
screamer 28:0e774865873d 10778 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
screamer 28:0e774865873d 10779 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 10780 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 10781
screamer 28:0e774865873d 10782 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
screamer 28:0e774865873d 10783 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
screamer 28:0e774865873d 10784 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
screamer 28:0e774865873d 10785 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
screamer 28:0e774865873d 10786 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10787 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10788 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10789 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10790 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10791 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10792 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10793
screamer 28:0e774865873d 10794 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
screamer 28:0e774865873d 10795 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 10796 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
screamer 28:0e774865873d 10797 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
screamer 28:0e774865873d 10798 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 10799 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
screamer 28:0e774865873d 10800
screamer 28:0e774865873d 10801 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
screamer 28:0e774865873d 10802 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 10803 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
screamer 28:0e774865873d 10804 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
screamer 28:0e774865873d 10805 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
screamer 28:0e774865873d 10806 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
screamer 28:0e774865873d 10807 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 10808 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 10809
screamer 28:0e774865873d 10810 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
screamer 28:0e774865873d 10811 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 10812 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
screamer 28:0e774865873d 10813 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
screamer 28:0e774865873d 10814 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
screamer 28:0e774865873d 10815 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
screamer 28:0e774865873d 10816 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 10817 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 10818
screamer 28:0e774865873d 10819 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
screamer 28:0e774865873d 10820 #define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
screamer 28:0e774865873d 10821 #define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
screamer 28:0e774865873d 10822 #define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
screamer 28:0e774865873d 10823 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10824 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10825 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 10826 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 10827 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10828 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10829 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 10830
screamer 28:0e774865873d 10831 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
screamer 28:0e774865873d 10832 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 10833 #define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
screamer 28:0e774865873d 10834 #define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
screamer 28:0e774865873d 10835 #define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 10836 #define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
screamer 28:0e774865873d 10837
screamer 28:0e774865873d 10838 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
screamer 28:0e774865873d 10839 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 10840 #define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
screamer 28:0e774865873d 10841 #define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
screamer 28:0e774865873d 10842 #define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
screamer 28:0e774865873d 10843 #define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
screamer 28:0e774865873d 10844 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 10845 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 10846
screamer 28:0e774865873d 10847 /******************** Bit definition for RCC_CIER register ******************/
screamer 28:0e774865873d 10848 #define RCC_CIER_LSIRDYIE_Pos (0U)
screamer 28:0e774865873d 10849 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10850 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
screamer 28:0e774865873d 10851 #define RCC_CIER_LSERDYIE_Pos (1U)
screamer 28:0e774865873d 10852 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10853 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
screamer 28:0e774865873d 10854 #define RCC_CIER_MSIRDYIE_Pos (2U)
screamer 28:0e774865873d 10855 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10856 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
screamer 28:0e774865873d 10857 #define RCC_CIER_HSIRDYIE_Pos (3U)
screamer 28:0e774865873d 10858 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10859 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
screamer 28:0e774865873d 10860 #define RCC_CIER_HSERDYIE_Pos (4U)
screamer 28:0e774865873d 10861 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10862 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
screamer 28:0e774865873d 10863 #define RCC_CIER_PLLRDYIE_Pos (5U)
screamer 28:0e774865873d 10864 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10865 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
screamer 28:0e774865873d 10866 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
screamer 28:0e774865873d 10867 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10868 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
screamer 28:0e774865873d 10869 #define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
screamer 28:0e774865873d 10870 #define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10871 #define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
screamer 28:0e774865873d 10872 #define RCC_CIER_LSECSSIE_Pos (9U)
screamer 28:0e774865873d 10873 #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10874 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
screamer 28:0e774865873d 10875
screamer 28:0e774865873d 10876 /******************** Bit definition for RCC_CIFR register ******************/
screamer 28:0e774865873d 10877 #define RCC_CIFR_LSIRDYF_Pos (0U)
screamer 28:0e774865873d 10878 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10879 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
screamer 28:0e774865873d 10880 #define RCC_CIFR_LSERDYF_Pos (1U)
screamer 28:0e774865873d 10881 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10882 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
screamer 28:0e774865873d 10883 #define RCC_CIFR_MSIRDYF_Pos (2U)
screamer 28:0e774865873d 10884 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10885 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
screamer 28:0e774865873d 10886 #define RCC_CIFR_HSIRDYF_Pos (3U)
screamer 28:0e774865873d 10887 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10888 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
screamer 28:0e774865873d 10889 #define RCC_CIFR_HSERDYF_Pos (4U)
screamer 28:0e774865873d 10890 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10891 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
screamer 28:0e774865873d 10892 #define RCC_CIFR_PLLRDYF_Pos (5U)
screamer 28:0e774865873d 10893 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10894 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
screamer 28:0e774865873d 10895 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
screamer 28:0e774865873d 10896 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10897 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
screamer 28:0e774865873d 10898 #define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
screamer 28:0e774865873d 10899 #define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10900 #define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
screamer 28:0e774865873d 10901 #define RCC_CIFR_CSSF_Pos (8U)
screamer 28:0e774865873d 10902 #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10903 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
screamer 28:0e774865873d 10904 #define RCC_CIFR_LSECSSF_Pos (9U)
screamer 28:0e774865873d 10905 #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10906 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
screamer 28:0e774865873d 10907
screamer 28:0e774865873d 10908 /******************** Bit definition for RCC_CICR register ******************/
screamer 28:0e774865873d 10909 #define RCC_CICR_LSIRDYC_Pos (0U)
screamer 28:0e774865873d 10910 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10911 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
screamer 28:0e774865873d 10912 #define RCC_CICR_LSERDYC_Pos (1U)
screamer 28:0e774865873d 10913 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10914 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
screamer 28:0e774865873d 10915 #define RCC_CICR_MSIRDYC_Pos (2U)
screamer 28:0e774865873d 10916 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10917 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
screamer 28:0e774865873d 10918 #define RCC_CICR_HSIRDYC_Pos (3U)
screamer 28:0e774865873d 10919 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10920 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
screamer 28:0e774865873d 10921 #define RCC_CICR_HSERDYC_Pos (4U)
screamer 28:0e774865873d 10922 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10923 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
screamer 28:0e774865873d 10924 #define RCC_CICR_PLLRDYC_Pos (5U)
screamer 28:0e774865873d 10925 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10926 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
screamer 28:0e774865873d 10927 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
screamer 28:0e774865873d 10928 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10929 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
screamer 28:0e774865873d 10930 #define RCC_CICR_PLLSAI2RDYC_Pos (7U)
screamer 28:0e774865873d 10931 #define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10932 #define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
screamer 28:0e774865873d 10933 #define RCC_CICR_CSSC_Pos (8U)
screamer 28:0e774865873d 10934 #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10935 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
screamer 28:0e774865873d 10936 #define RCC_CICR_LSECSSC_Pos (9U)
screamer 28:0e774865873d 10937 #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 10938 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
screamer 28:0e774865873d 10939
screamer 28:0e774865873d 10940 /******************** Bit definition for RCC_AHB1RSTR register **************/
screamer 28:0e774865873d 10941 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
screamer 28:0e774865873d 10942 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10943 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
screamer 28:0e774865873d 10944 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
screamer 28:0e774865873d 10945 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10946 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
screamer 28:0e774865873d 10947 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
screamer 28:0e774865873d 10948 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10949 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
screamer 28:0e774865873d 10950 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
screamer 28:0e774865873d 10951 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10952 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
screamer 28:0e774865873d 10953 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
screamer 28:0e774865873d 10954 #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 10955 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
screamer 28:0e774865873d 10956
screamer 28:0e774865873d 10957 /******************** Bit definition for RCC_AHB2RSTR register **************/
screamer 28:0e774865873d 10958 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
screamer 28:0e774865873d 10959 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10960 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
screamer 28:0e774865873d 10961 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
screamer 28:0e774865873d 10962 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 10963 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
screamer 28:0e774865873d 10964 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
screamer 28:0e774865873d 10965 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 10966 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
screamer 28:0e774865873d 10967 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
screamer 28:0e774865873d 10968 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 10969 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
screamer 28:0e774865873d 10970 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
screamer 28:0e774865873d 10971 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 10972 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
screamer 28:0e774865873d 10973 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
screamer 28:0e774865873d 10974 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 10975 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
screamer 28:0e774865873d 10976 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
screamer 28:0e774865873d 10977 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 10978 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
screamer 28:0e774865873d 10979 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
screamer 28:0e774865873d 10980 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 10981 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
screamer 28:0e774865873d 10982 #define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
screamer 28:0e774865873d 10983 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 10984 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
screamer 28:0e774865873d 10985 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
screamer 28:0e774865873d 10986 #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 10987 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
screamer 28:0e774865873d 10988 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
screamer 28:0e774865873d 10989 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 10990 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
screamer 28:0e774865873d 10991
screamer 28:0e774865873d 10992 /******************** Bit definition for RCC_AHB3RSTR register **************/
screamer 28:0e774865873d 10993 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
screamer 28:0e774865873d 10994 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 10995 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
screamer 28:0e774865873d 10996 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
screamer 28:0e774865873d 10997 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 10998 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
screamer 28:0e774865873d 10999
screamer 28:0e774865873d 11000 /******************** Bit definition for RCC_APB1RSTR1 register **************/
screamer 28:0e774865873d 11001 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
screamer 28:0e774865873d 11002 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11003 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
screamer 28:0e774865873d 11004 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
screamer 28:0e774865873d 11005 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11006 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
screamer 28:0e774865873d 11007 #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
screamer 28:0e774865873d 11008 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11009 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
screamer 28:0e774865873d 11010 #define RCC_APB1RSTR1_TIM5RST_Pos (3U)
screamer 28:0e774865873d 11011 #define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11012 #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
screamer 28:0e774865873d 11013 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
screamer 28:0e774865873d 11014 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11015 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
screamer 28:0e774865873d 11016 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
screamer 28:0e774865873d 11017 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11018 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
screamer 28:0e774865873d 11019 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
screamer 28:0e774865873d 11020 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11021 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
screamer 28:0e774865873d 11022 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
screamer 28:0e774865873d 11023 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11024 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
screamer 28:0e774865873d 11025 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
screamer 28:0e774865873d 11026 #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11027 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
screamer 28:0e774865873d 11028 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
screamer 28:0e774865873d 11029 #define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11030 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
screamer 28:0e774865873d 11031 #define RCC_APB1RSTR1_UART4RST_Pos (19U)
screamer 28:0e774865873d 11032 #define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11033 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
screamer 28:0e774865873d 11034 #define RCC_APB1RSTR1_UART5RST_Pos (20U)
screamer 28:0e774865873d 11035 #define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11036 #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
screamer 28:0e774865873d 11037 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
screamer 28:0e774865873d 11038 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11039 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
screamer 28:0e774865873d 11040 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
screamer 28:0e774865873d 11041 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11042 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
screamer 28:0e774865873d 11043 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
screamer 28:0e774865873d 11044 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11045 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
screamer 28:0e774865873d 11046 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
screamer 28:0e774865873d 11047 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11048 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
screamer 28:0e774865873d 11049 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
screamer 28:0e774865873d 11050 #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 11051 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
screamer 28:0e774865873d 11052 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
screamer 28:0e774865873d 11053 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 11054 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
screamer 28:0e774865873d 11055 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
screamer 28:0e774865873d 11056 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 11057 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
screamer 28:0e774865873d 11058 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
screamer 28:0e774865873d 11059 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 11060 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
screamer 28:0e774865873d 11061
screamer 28:0e774865873d 11062 /******************** Bit definition for RCC_APB1RSTR2 register **************/
screamer 28:0e774865873d 11063 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
screamer 28:0e774865873d 11064 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11065 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
screamer 28:0e774865873d 11066 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
screamer 28:0e774865873d 11067 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11068 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
screamer 28:0e774865873d 11069 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
screamer 28:0e774865873d 11070 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11071 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
screamer 28:0e774865873d 11072
screamer 28:0e774865873d 11073 /******************** Bit definition for RCC_APB2RSTR register **************/
screamer 28:0e774865873d 11074 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
screamer 28:0e774865873d 11075 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11076 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
screamer 28:0e774865873d 11077 #define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
screamer 28:0e774865873d 11078 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11079 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
screamer 28:0e774865873d 11080 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
screamer 28:0e774865873d 11081 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11082 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
screamer 28:0e774865873d 11083 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
screamer 28:0e774865873d 11084 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11085 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
screamer 28:0e774865873d 11086 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
screamer 28:0e774865873d 11087 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11088 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
screamer 28:0e774865873d 11089 #define RCC_APB2RSTR_USART1RST_Pos (14U)
screamer 28:0e774865873d 11090 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11091 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
screamer 28:0e774865873d 11092 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
screamer 28:0e774865873d 11093 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11094 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
screamer 28:0e774865873d 11095 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
screamer 28:0e774865873d 11096 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11097 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
screamer 28:0e774865873d 11098 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
screamer 28:0e774865873d 11099 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11100 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
screamer 28:0e774865873d 11101 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
screamer 28:0e774865873d 11102 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11103 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
screamer 28:0e774865873d 11104 #define RCC_APB2RSTR_SAI2RST_Pos (22U)
screamer 28:0e774865873d 11105 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11106 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
screamer 28:0e774865873d 11107 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
screamer 28:0e774865873d 11108 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11109 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
screamer 28:0e774865873d 11110
screamer 28:0e774865873d 11111 /******************** Bit definition for RCC_AHB1ENR register ***************/
screamer 28:0e774865873d 11112 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
screamer 28:0e774865873d 11113 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11114 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
screamer 28:0e774865873d 11115 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
screamer 28:0e774865873d 11116 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11117 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
screamer 28:0e774865873d 11118 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
screamer 28:0e774865873d 11119 #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11120 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
screamer 28:0e774865873d 11121 #define RCC_AHB1ENR_CRCEN_Pos (12U)
screamer 28:0e774865873d 11122 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11123 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
screamer 28:0e774865873d 11124 #define RCC_AHB1ENR_TSCEN_Pos (16U)
screamer 28:0e774865873d 11125 #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11126 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
screamer 28:0e774865873d 11127
screamer 28:0e774865873d 11128 /******************** Bit definition for RCC_AHB2ENR register ***************/
screamer 28:0e774865873d 11129 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
screamer 28:0e774865873d 11130 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11131 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
screamer 28:0e774865873d 11132 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
screamer 28:0e774865873d 11133 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11134 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
screamer 28:0e774865873d 11135 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
screamer 28:0e774865873d 11136 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11137 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
screamer 28:0e774865873d 11138 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
screamer 28:0e774865873d 11139 #define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11140 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
screamer 28:0e774865873d 11141 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
screamer 28:0e774865873d 11142 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11143 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
screamer 28:0e774865873d 11144 #define RCC_AHB2ENR_GPIOFEN_Pos (5U)
screamer 28:0e774865873d 11145 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11146 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
screamer 28:0e774865873d 11147 #define RCC_AHB2ENR_GPIOGEN_Pos (6U)
screamer 28:0e774865873d 11148 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11149 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
screamer 28:0e774865873d 11150 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
screamer 28:0e774865873d 11151 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 11152 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
screamer 28:0e774865873d 11153 #define RCC_AHB2ENR_OTGFSEN_Pos (12U)
screamer 28:0e774865873d 11154 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11155 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
screamer 28:0e774865873d 11156 #define RCC_AHB2ENR_ADCEN_Pos (13U)
screamer 28:0e774865873d 11157 #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11158 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
screamer 28:0e774865873d 11159 #define RCC_AHB2ENR_RNGEN_Pos (18U)
screamer 28:0e774865873d 11160 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11161 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
screamer 28:0e774865873d 11162
screamer 28:0e774865873d 11163 /******************** Bit definition for RCC_AHB3ENR register ***************/
screamer 28:0e774865873d 11164 #define RCC_AHB3ENR_FMCEN_Pos (0U)
screamer 28:0e774865873d 11165 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11166 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
screamer 28:0e774865873d 11167 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
screamer 28:0e774865873d 11168 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11169 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
screamer 28:0e774865873d 11170
screamer 28:0e774865873d 11171 /******************** Bit definition for RCC_APB1ENR1 register ***************/
screamer 28:0e774865873d 11172 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
screamer 28:0e774865873d 11173 #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11174 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
screamer 28:0e774865873d 11175 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
screamer 28:0e774865873d 11176 #define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11177 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
screamer 28:0e774865873d 11178 #define RCC_APB1ENR1_TIM4EN_Pos (2U)
screamer 28:0e774865873d 11179 #define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11180 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
screamer 28:0e774865873d 11181 #define RCC_APB1ENR1_TIM5EN_Pos (3U)
screamer 28:0e774865873d 11182 #define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11183 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
screamer 28:0e774865873d 11184 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
screamer 28:0e774865873d 11185 #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11186 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
screamer 28:0e774865873d 11187 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
screamer 28:0e774865873d 11188 #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11189 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
screamer 28:0e774865873d 11190 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
screamer 28:0e774865873d 11191 #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11192 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
screamer 28:0e774865873d 11193 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
screamer 28:0e774865873d 11194 #define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11195 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
screamer 28:0e774865873d 11196 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
screamer 28:0e774865873d 11197 #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11198 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
screamer 28:0e774865873d 11199 #define RCC_APB1ENR1_USART2EN_Pos (17U)
screamer 28:0e774865873d 11200 #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11201 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
screamer 28:0e774865873d 11202 #define RCC_APB1ENR1_USART3EN_Pos (18U)
screamer 28:0e774865873d 11203 #define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11204 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
screamer 28:0e774865873d 11205 #define RCC_APB1ENR1_UART4EN_Pos (19U)
screamer 28:0e774865873d 11206 #define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11207 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
screamer 28:0e774865873d 11208 #define RCC_APB1ENR1_UART5EN_Pos (20U)
screamer 28:0e774865873d 11209 #define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11210 #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
screamer 28:0e774865873d 11211 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
screamer 28:0e774865873d 11212 #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11213 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
screamer 28:0e774865873d 11214 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
screamer 28:0e774865873d 11215 #define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11216 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
screamer 28:0e774865873d 11217 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
screamer 28:0e774865873d 11218 #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11219 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
screamer 28:0e774865873d 11220 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
screamer 28:0e774865873d 11221 #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11222 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
screamer 28:0e774865873d 11223 #define RCC_APB1ENR1_PWREN_Pos (28U)
screamer 28:0e774865873d 11224 #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 11225 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
screamer 28:0e774865873d 11226 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
screamer 28:0e774865873d 11227 #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 11228 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
screamer 28:0e774865873d 11229 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
screamer 28:0e774865873d 11230 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 11231 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
screamer 28:0e774865873d 11232 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
screamer 28:0e774865873d 11233 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 11234 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
screamer 28:0e774865873d 11235
screamer 28:0e774865873d 11236 /******************** Bit definition for RCC_APB1RSTR2 register **************/
screamer 28:0e774865873d 11237 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
screamer 28:0e774865873d 11238 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11239 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
screamer 28:0e774865873d 11240 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
screamer 28:0e774865873d 11241 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11242 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
screamer 28:0e774865873d 11243 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
screamer 28:0e774865873d 11244 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11245 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
screamer 28:0e774865873d 11246
screamer 28:0e774865873d 11247 /******************** Bit definition for RCC_APB2ENR register ***************/
screamer 28:0e774865873d 11248 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
screamer 28:0e774865873d 11249 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11250 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
screamer 28:0e774865873d 11251 #define RCC_APB2ENR_FWEN_Pos (7U)
screamer 28:0e774865873d 11252 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 11253 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
screamer 28:0e774865873d 11254 #define RCC_APB2ENR_SDMMC1EN_Pos (10U)
screamer 28:0e774865873d 11255 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11256 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
screamer 28:0e774865873d 11257 #define RCC_APB2ENR_TIM1EN_Pos (11U)
screamer 28:0e774865873d 11258 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11259 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
screamer 28:0e774865873d 11260 #define RCC_APB2ENR_SPI1EN_Pos (12U)
screamer 28:0e774865873d 11261 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11262 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
screamer 28:0e774865873d 11263 #define RCC_APB2ENR_TIM8EN_Pos (13U)
screamer 28:0e774865873d 11264 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11265 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
screamer 28:0e774865873d 11266 #define RCC_APB2ENR_USART1EN_Pos (14U)
screamer 28:0e774865873d 11267 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11268 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
screamer 28:0e774865873d 11269 #define RCC_APB2ENR_TIM15EN_Pos (16U)
screamer 28:0e774865873d 11270 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11271 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
screamer 28:0e774865873d 11272 #define RCC_APB2ENR_TIM16EN_Pos (17U)
screamer 28:0e774865873d 11273 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11274 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
screamer 28:0e774865873d 11275 #define RCC_APB2ENR_TIM17EN_Pos (18U)
screamer 28:0e774865873d 11276 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11277 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
screamer 28:0e774865873d 11278 #define RCC_APB2ENR_SAI1EN_Pos (21U)
screamer 28:0e774865873d 11279 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11280 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
screamer 28:0e774865873d 11281 #define RCC_APB2ENR_SAI2EN_Pos (22U)
screamer 28:0e774865873d 11282 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11283 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
screamer 28:0e774865873d 11284 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
screamer 28:0e774865873d 11285 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11286 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
screamer 28:0e774865873d 11287
screamer 28:0e774865873d 11288 /******************** Bit definition for RCC_AHB1SMENR register ***************/
screamer 28:0e774865873d 11289 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
screamer 28:0e774865873d 11290 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11291 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
screamer 28:0e774865873d 11292 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
screamer 28:0e774865873d 11293 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11294 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
screamer 28:0e774865873d 11295 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
screamer 28:0e774865873d 11296 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11297 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
screamer 28:0e774865873d 11298 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
screamer 28:0e774865873d 11299 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11300 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
screamer 28:0e774865873d 11301 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
screamer 28:0e774865873d 11302 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11303 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
screamer 28:0e774865873d 11304 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
screamer 28:0e774865873d 11305 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11306 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
screamer 28:0e774865873d 11307
screamer 28:0e774865873d 11308 /******************** Bit definition for RCC_AHB2SMENR register *************/
screamer 28:0e774865873d 11309 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
screamer 28:0e774865873d 11310 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11311 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
screamer 28:0e774865873d 11312 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
screamer 28:0e774865873d 11313 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11314 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
screamer 28:0e774865873d 11315 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
screamer 28:0e774865873d 11316 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11317 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
screamer 28:0e774865873d 11318 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
screamer 28:0e774865873d 11319 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11320 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
screamer 28:0e774865873d 11321 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
screamer 28:0e774865873d 11322 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11323 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
screamer 28:0e774865873d 11324 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
screamer 28:0e774865873d 11325 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11326 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
screamer 28:0e774865873d 11327 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
screamer 28:0e774865873d 11328 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11329 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
screamer 28:0e774865873d 11330 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
screamer 28:0e774865873d 11331 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 11332 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
screamer 28:0e774865873d 11333 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
screamer 28:0e774865873d 11334 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11335 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
screamer 28:0e774865873d 11336 #define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
screamer 28:0e774865873d 11337 #define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11338 #define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
screamer 28:0e774865873d 11339 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
screamer 28:0e774865873d 11340 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11341 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
screamer 28:0e774865873d 11342 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
screamer 28:0e774865873d 11343 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11344 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
screamer 28:0e774865873d 11345
screamer 28:0e774865873d 11346 /******************** Bit definition for RCC_AHB3SMENR register *************/
screamer 28:0e774865873d 11347 #define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
screamer 28:0e774865873d 11348 #define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11349 #define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
screamer 28:0e774865873d 11350 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
screamer 28:0e774865873d 11351 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11352 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
screamer 28:0e774865873d 11353
screamer 28:0e774865873d 11354 /******************** Bit definition for RCC_APB1SMENR1 register *************/
screamer 28:0e774865873d 11355 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
screamer 28:0e774865873d 11356 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11357 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
screamer 28:0e774865873d 11358 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
screamer 28:0e774865873d 11359 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11360 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
screamer 28:0e774865873d 11361 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
screamer 28:0e774865873d 11362 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11363 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
screamer 28:0e774865873d 11364 #define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
screamer 28:0e774865873d 11365 #define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11366 #define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
screamer 28:0e774865873d 11367 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
screamer 28:0e774865873d 11368 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11369 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
screamer 28:0e774865873d 11370 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
screamer 28:0e774865873d 11371 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11372 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
screamer 28:0e774865873d 11373 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
screamer 28:0e774865873d 11374 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11375 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
screamer 28:0e774865873d 11376 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
screamer 28:0e774865873d 11377 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11378 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
screamer 28:0e774865873d 11379 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
screamer 28:0e774865873d 11380 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11381 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
screamer 28:0e774865873d 11382 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
screamer 28:0e774865873d 11383 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11384 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
screamer 28:0e774865873d 11385 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
screamer 28:0e774865873d 11386 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11387 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
screamer 28:0e774865873d 11388 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
screamer 28:0e774865873d 11389 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11390 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
screamer 28:0e774865873d 11391 #define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
screamer 28:0e774865873d 11392 #define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11393 #define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
screamer 28:0e774865873d 11394 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
screamer 28:0e774865873d 11395 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11396 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
screamer 28:0e774865873d 11397 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
screamer 28:0e774865873d 11398 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11399 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
screamer 28:0e774865873d 11400 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
screamer 28:0e774865873d 11401 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11402 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
screamer 28:0e774865873d 11403 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
screamer 28:0e774865873d 11404 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11405 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
screamer 28:0e774865873d 11406 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
screamer 28:0e774865873d 11407 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 11408 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
screamer 28:0e774865873d 11409 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
screamer 28:0e774865873d 11410 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 11411 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
screamer 28:0e774865873d 11412 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
screamer 28:0e774865873d 11413 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 11414 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
screamer 28:0e774865873d 11415 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
screamer 28:0e774865873d 11416 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 11417 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
screamer 28:0e774865873d 11418
screamer 28:0e774865873d 11419 /******************** Bit definition for RCC_APB1SMENR2 register *************/
screamer 28:0e774865873d 11420 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
screamer 28:0e774865873d 11421 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11422 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
screamer 28:0e774865873d 11423 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
screamer 28:0e774865873d 11424 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11425 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
screamer 28:0e774865873d 11426 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
screamer 28:0e774865873d 11427 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11428 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
screamer 28:0e774865873d 11429
screamer 28:0e774865873d 11430 /******************** Bit definition for RCC_APB2SMENR register *************/
screamer 28:0e774865873d 11431 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
screamer 28:0e774865873d 11432 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11433 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
screamer 28:0e774865873d 11434 #define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
screamer 28:0e774865873d 11435 #define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11436 #define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
screamer 28:0e774865873d 11437 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
screamer 28:0e774865873d 11438 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11439 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
screamer 28:0e774865873d 11440 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
screamer 28:0e774865873d 11441 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11442 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
screamer 28:0e774865873d 11443 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
screamer 28:0e774865873d 11444 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11445 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
screamer 28:0e774865873d 11446 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
screamer 28:0e774865873d 11447 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11448 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
screamer 28:0e774865873d 11449 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
screamer 28:0e774865873d 11450 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11451 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
screamer 28:0e774865873d 11452 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
screamer 28:0e774865873d 11453 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11454 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
screamer 28:0e774865873d 11455 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
screamer 28:0e774865873d 11456 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11457 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
screamer 28:0e774865873d 11458 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
screamer 28:0e774865873d 11459 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11460 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
screamer 28:0e774865873d 11461 #define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
screamer 28:0e774865873d 11462 #define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11463 #define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
screamer 28:0e774865873d 11464 #define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
screamer 28:0e774865873d 11465 #define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11466 #define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
screamer 28:0e774865873d 11467
screamer 28:0e774865873d 11468 /******************** Bit definition for RCC_CCIPR register ******************/
screamer 28:0e774865873d 11469 #define RCC_CCIPR_USART1SEL_Pos (0U)
screamer 28:0e774865873d 11470 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 11471 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
screamer 28:0e774865873d 11472 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11473 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11474
screamer 28:0e774865873d 11475 #define RCC_CCIPR_USART2SEL_Pos (2U)
screamer 28:0e774865873d 11476 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 11477 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
screamer 28:0e774865873d 11478 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11479 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11480
screamer 28:0e774865873d 11481 #define RCC_CCIPR_USART3SEL_Pos (4U)
screamer 28:0e774865873d 11482 #define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 11483 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
screamer 28:0e774865873d 11484 #define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11485 #define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11486
screamer 28:0e774865873d 11487 #define RCC_CCIPR_UART4SEL_Pos (6U)
screamer 28:0e774865873d 11488 #define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 11489 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
screamer 28:0e774865873d 11490 #define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11491 #define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 11492
screamer 28:0e774865873d 11493 #define RCC_CCIPR_UART5SEL_Pos (8U)
screamer 28:0e774865873d 11494 #define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 11495 #define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
screamer 28:0e774865873d 11496 #define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11497 #define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11498
screamer 28:0e774865873d 11499 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
screamer 28:0e774865873d 11500 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 11501 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
screamer 28:0e774865873d 11502 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11503 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11504
screamer 28:0e774865873d 11505 #define RCC_CCIPR_I2C1SEL_Pos (12U)
screamer 28:0e774865873d 11506 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 11507 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
screamer 28:0e774865873d 11508 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11509 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11510
screamer 28:0e774865873d 11511 #define RCC_CCIPR_I2C2SEL_Pos (14U)
screamer 28:0e774865873d 11512 #define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 11513 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
screamer 28:0e774865873d 11514 #define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11515 #define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11516
screamer 28:0e774865873d 11517 #define RCC_CCIPR_I2C3SEL_Pos (16U)
screamer 28:0e774865873d 11518 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 11519 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
screamer 28:0e774865873d 11520 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11521 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11522
screamer 28:0e774865873d 11523 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
screamer 28:0e774865873d 11524 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 11525 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
screamer 28:0e774865873d 11526 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11527 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11528
screamer 28:0e774865873d 11529 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
screamer 28:0e774865873d 11530 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 11531 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
screamer 28:0e774865873d 11532 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11533 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11534
screamer 28:0e774865873d 11535 #define RCC_CCIPR_SAI1SEL_Pos (22U)
screamer 28:0e774865873d 11536 #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
screamer 28:0e774865873d 11537 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
screamer 28:0e774865873d 11538 #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11539 #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11540
screamer 28:0e774865873d 11541 #define RCC_CCIPR_SAI2SEL_Pos (24U)
screamer 28:0e774865873d 11542 #define RCC_CCIPR_SAI2SEL_Msk (0x3U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 11543 #define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
screamer 28:0e774865873d 11544 #define RCC_CCIPR_SAI2SEL_0 (0x1U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11545 #define RCC_CCIPR_SAI2SEL_1 (0x2U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11546
screamer 28:0e774865873d 11547 #define RCC_CCIPR_CLK48SEL_Pos (26U)
screamer 28:0e774865873d 11548 #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
screamer 28:0e774865873d 11549 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
screamer 28:0e774865873d 11550 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 11551 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 11552
screamer 28:0e774865873d 11553 #define RCC_CCIPR_ADCSEL_Pos (28U)
screamer 28:0e774865873d 11554 #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 11555 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
screamer 28:0e774865873d 11556 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 11557 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 11558
screamer 28:0e774865873d 11559 #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
screamer 28:0e774865873d 11560 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 11561 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
screamer 28:0e774865873d 11562
screamer 28:0e774865873d 11563 #define RCC_CCIPR_DFSDM1SEL_Pos (31U)
screamer 28:0e774865873d 11564 #define RCC_CCIPR_DFSDM1SEL_Msk (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 11565 #define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
screamer 28:0e774865873d 11566
screamer 28:0e774865873d 11567 /******************** Bit definition for RCC_BDCR register ******************/
screamer 28:0e774865873d 11568 #define RCC_BDCR_LSEON_Pos (0U)
screamer 28:0e774865873d 11569 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11570 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
screamer 28:0e774865873d 11571 #define RCC_BDCR_LSERDY_Pos (1U)
screamer 28:0e774865873d 11572 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11573 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
screamer 28:0e774865873d 11574 #define RCC_BDCR_LSEBYP_Pos (2U)
screamer 28:0e774865873d 11575 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11576 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
screamer 28:0e774865873d 11577
screamer 28:0e774865873d 11578 #define RCC_BDCR_LSEDRV_Pos (3U)
screamer 28:0e774865873d 11579 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
screamer 28:0e774865873d 11580 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
screamer 28:0e774865873d 11581 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11582 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11583
screamer 28:0e774865873d 11584 #define RCC_BDCR_LSECSSON_Pos (5U)
screamer 28:0e774865873d 11585 #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11586 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
screamer 28:0e774865873d 11587 #define RCC_BDCR_LSECSSD_Pos (6U)
screamer 28:0e774865873d 11588 #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11589 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
screamer 28:0e774865873d 11590
screamer 28:0e774865873d 11591 #define RCC_BDCR_RTCSEL_Pos (8U)
screamer 28:0e774865873d 11592 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 11593 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
screamer 28:0e774865873d 11594 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11595 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11596
screamer 28:0e774865873d 11597 #define RCC_BDCR_RTCEN_Pos (15U)
screamer 28:0e774865873d 11598 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11599 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
screamer 28:0e774865873d 11600 #define RCC_BDCR_BDRST_Pos (16U)
screamer 28:0e774865873d 11601 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11602 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
screamer 28:0e774865873d 11603 #define RCC_BDCR_LSCOEN_Pos (24U)
screamer 28:0e774865873d 11604 #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11605 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
screamer 28:0e774865873d 11606 #define RCC_BDCR_LSCOSEL_Pos (25U)
screamer 28:0e774865873d 11607 #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11608 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
screamer 28:0e774865873d 11609
screamer 28:0e774865873d 11610 /******************** Bit definition for RCC_CSR register *******************/
screamer 28:0e774865873d 11611 #define RCC_CSR_LSION_Pos (0U)
screamer 28:0e774865873d 11612 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11613 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
screamer 28:0e774865873d 11614 #define RCC_CSR_LSIRDY_Pos (1U)
screamer 28:0e774865873d 11615 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11616 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
screamer 28:0e774865873d 11617
screamer 28:0e774865873d 11618 #define RCC_CSR_MSISRANGE_Pos (8U)
screamer 28:0e774865873d 11619 #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 11620 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
screamer 28:0e774865873d 11621 #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11622 #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
screamer 28:0e774865873d 11623 #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
screamer 28:0e774865873d 11624 #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 11625
screamer 28:0e774865873d 11626 #define RCC_CSR_RMVF_Pos (23U)
screamer 28:0e774865873d 11627 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11628 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
screamer 28:0e774865873d 11629 #define RCC_CSR_FWRSTF_Pos (24U)
screamer 28:0e774865873d 11630 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11631 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
screamer 28:0e774865873d 11632 #define RCC_CSR_OBLRSTF_Pos (25U)
screamer 28:0e774865873d 11633 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11634 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
screamer 28:0e774865873d 11635 #define RCC_CSR_PINRSTF_Pos (26U)
screamer 28:0e774865873d 11636 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 11637 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
screamer 28:0e774865873d 11638 #define RCC_CSR_BORRSTF_Pos (27U)
screamer 28:0e774865873d 11639 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 11640 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
screamer 28:0e774865873d 11641 #define RCC_CSR_SFTRSTF_Pos (28U)
screamer 28:0e774865873d 11642 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 11643 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
screamer 28:0e774865873d 11644 #define RCC_CSR_IWDGRSTF_Pos (29U)
screamer 28:0e774865873d 11645 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 11646 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
screamer 28:0e774865873d 11647 #define RCC_CSR_WWDGRSTF_Pos (30U)
screamer 28:0e774865873d 11648 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 11649 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
screamer 28:0e774865873d 11650 #define RCC_CSR_LPWRRSTF_Pos (31U)
screamer 28:0e774865873d 11651 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 11652 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
screamer 28:0e774865873d 11653
screamer 28:0e774865873d 11654 /******************************************************************************/
screamer 28:0e774865873d 11655 /* */
screamer 28:0e774865873d 11656 /* RNG */
screamer 28:0e774865873d 11657 /* */
screamer 28:0e774865873d 11658 /******************************************************************************/
screamer 28:0e774865873d 11659 /******************** Bits definition for RNG_CR register *******************/
screamer 28:0e774865873d 11660 #define RNG_CR_RNGEN_Pos (2U)
screamer 28:0e774865873d 11661 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11662 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
screamer 28:0e774865873d 11663 #define RNG_CR_IE_Pos (3U)
screamer 28:0e774865873d 11664 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11665 #define RNG_CR_IE RNG_CR_IE_Msk
screamer 28:0e774865873d 11666
screamer 28:0e774865873d 11667 /******************** Bits definition for RNG_SR register *******************/
screamer 28:0e774865873d 11668 #define RNG_SR_DRDY_Pos (0U)
screamer 28:0e774865873d 11669 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11670 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
screamer 28:0e774865873d 11671 #define RNG_SR_CECS_Pos (1U)
screamer 28:0e774865873d 11672 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11673 #define RNG_SR_CECS RNG_SR_CECS_Msk
screamer 28:0e774865873d 11674 #define RNG_SR_SECS_Pos (2U)
screamer 28:0e774865873d 11675 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11676 #define RNG_SR_SECS RNG_SR_SECS_Msk
screamer 28:0e774865873d 11677 #define RNG_SR_CEIS_Pos (5U)
screamer 28:0e774865873d 11678 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11679 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
screamer 28:0e774865873d 11680 #define RNG_SR_SEIS_Pos (6U)
screamer 28:0e774865873d 11681 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11682 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
screamer 28:0e774865873d 11683
screamer 28:0e774865873d 11684 /******************************************************************************/
screamer 28:0e774865873d 11685 /* */
screamer 28:0e774865873d 11686 /* Real-Time Clock (RTC) */
screamer 28:0e774865873d 11687 /* */
screamer 28:0e774865873d 11688 /******************************************************************************/
screamer 28:0e774865873d 11689 /*
screamer 28:0e774865873d 11690 * @brief Specific device feature definitions
screamer 28:0e774865873d 11691 */
screamer 28:0e774865873d 11692 #define RTC_TAMPER1_SUPPORT
screamer 28:0e774865873d 11693 #define RTC_TAMPER2_SUPPORT
screamer 28:0e774865873d 11694 #define RTC_TAMPER3_SUPPORT
screamer 28:0e774865873d 11695 #define RTC_WAKEUP_SUPPORT
screamer 28:0e774865873d 11696 #define RTC_BACKUP_SUPPORT
screamer 28:0e774865873d 11697
screamer 28:0e774865873d 11698 /******************** Bits definition for RTC_TR register *******************/
screamer 28:0e774865873d 11699 #define RTC_TR_PM_Pos (22U)
screamer 28:0e774865873d 11700 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11701 #define RTC_TR_PM RTC_TR_PM_Msk
screamer 28:0e774865873d 11702 #define RTC_TR_HT_Pos (20U)
screamer 28:0e774865873d 11703 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 11704 #define RTC_TR_HT RTC_TR_HT_Msk
screamer 28:0e774865873d 11705 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11706 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11707 #define RTC_TR_HU_Pos (16U)
screamer 28:0e774865873d 11708 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 11709 #define RTC_TR_HU RTC_TR_HU_Msk
screamer 28:0e774865873d 11710 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11711 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11712 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11713 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11714 #define RTC_TR_MNT_Pos (12U)
screamer 28:0e774865873d 11715 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 11716 #define RTC_TR_MNT RTC_TR_MNT_Msk
screamer 28:0e774865873d 11717 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11718 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11719 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11720 #define RTC_TR_MNU_Pos (8U)
screamer 28:0e774865873d 11721 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 11722 #define RTC_TR_MNU RTC_TR_MNU_Msk
screamer 28:0e774865873d 11723 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11724 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11725 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11726 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11727 #define RTC_TR_ST_Pos (4U)
screamer 28:0e774865873d 11728 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 11729 #define RTC_TR_ST RTC_TR_ST_Msk
screamer 28:0e774865873d 11730 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11731 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11732 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11733 #define RTC_TR_SU_Pos (0U)
screamer 28:0e774865873d 11734 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 11735 #define RTC_TR_SU RTC_TR_SU_Msk
screamer 28:0e774865873d 11736 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11737 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11738 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11739 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11740
screamer 28:0e774865873d 11741 /******************** Bits definition for RTC_DR register *******************/
screamer 28:0e774865873d 11742 #define RTC_DR_YT_Pos (20U)
screamer 28:0e774865873d 11743 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 11744 #define RTC_DR_YT RTC_DR_YT_Msk
screamer 28:0e774865873d 11745 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11746 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11747 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11748 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11749 #define RTC_DR_YU_Pos (16U)
screamer 28:0e774865873d 11750 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 11751 #define RTC_DR_YU RTC_DR_YU_Msk
screamer 28:0e774865873d 11752 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11753 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11754 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11755 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11756 #define RTC_DR_WDU_Pos (13U)
screamer 28:0e774865873d 11757 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
screamer 28:0e774865873d 11758 #define RTC_DR_WDU RTC_DR_WDU_Msk
screamer 28:0e774865873d 11759 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11760 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11761 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11762 #define RTC_DR_MT_Pos (12U)
screamer 28:0e774865873d 11763 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11764 #define RTC_DR_MT RTC_DR_MT_Msk
screamer 28:0e774865873d 11765 #define RTC_DR_MU_Pos (8U)
screamer 28:0e774865873d 11766 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 11767 #define RTC_DR_MU RTC_DR_MU_Msk
screamer 28:0e774865873d 11768 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11769 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11770 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11771 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11772 #define RTC_DR_DT_Pos (4U)
screamer 28:0e774865873d 11773 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 11774 #define RTC_DR_DT RTC_DR_DT_Msk
screamer 28:0e774865873d 11775 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11776 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11777 #define RTC_DR_DU_Pos (0U)
screamer 28:0e774865873d 11778 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 11779 #define RTC_DR_DU RTC_DR_DU_Msk
screamer 28:0e774865873d 11780 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11781 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11782 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11783 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11784
screamer 28:0e774865873d 11785 /******************** Bits definition for RTC_CR register *******************/
screamer 28:0e774865873d 11786 #define RTC_CR_ITSE_Pos (24U)
screamer 28:0e774865873d 11787 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11788 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
screamer 28:0e774865873d 11789 #define RTC_CR_COE_Pos (23U)
screamer 28:0e774865873d 11790 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11791 #define RTC_CR_COE RTC_CR_COE_Msk
screamer 28:0e774865873d 11792 #define RTC_CR_OSEL_Pos (21U)
screamer 28:0e774865873d 11793 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
screamer 28:0e774865873d 11794 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
screamer 28:0e774865873d 11795 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11796 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11797 #define RTC_CR_POL_Pos (20U)
screamer 28:0e774865873d 11798 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11799 #define RTC_CR_POL RTC_CR_POL_Msk
screamer 28:0e774865873d 11800 #define RTC_CR_COSEL_Pos (19U)
screamer 28:0e774865873d 11801 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11802 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
screamer 28:0e774865873d 11803 #define RTC_CR_BKP_Pos (18U)
screamer 28:0e774865873d 11804 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11805 #define RTC_CR_BKP RTC_CR_BKP_Msk
screamer 28:0e774865873d 11806 #define RTC_CR_SUB1H_Pos (17U)
screamer 28:0e774865873d 11807 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11808 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
screamer 28:0e774865873d 11809 #define RTC_CR_ADD1H_Pos (16U)
screamer 28:0e774865873d 11810 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11811 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
screamer 28:0e774865873d 11812 #define RTC_CR_TSIE_Pos (15U)
screamer 28:0e774865873d 11813 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11814 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
screamer 28:0e774865873d 11815 #define RTC_CR_WUTIE_Pos (14U)
screamer 28:0e774865873d 11816 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11817 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
screamer 28:0e774865873d 11818 #define RTC_CR_ALRBIE_Pos (13U)
screamer 28:0e774865873d 11819 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11820 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
screamer 28:0e774865873d 11821 #define RTC_CR_ALRAIE_Pos (12U)
screamer 28:0e774865873d 11822 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11823 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
screamer 28:0e774865873d 11824 #define RTC_CR_TSE_Pos (11U)
screamer 28:0e774865873d 11825 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11826 #define RTC_CR_TSE RTC_CR_TSE_Msk
screamer 28:0e774865873d 11827 #define RTC_CR_WUTE_Pos (10U)
screamer 28:0e774865873d 11828 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11829 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
screamer 28:0e774865873d 11830 #define RTC_CR_ALRBE_Pos (9U)
screamer 28:0e774865873d 11831 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11832 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
screamer 28:0e774865873d 11833 #define RTC_CR_ALRAE_Pos (8U)
screamer 28:0e774865873d 11834 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11835 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
screamer 28:0e774865873d 11836 #define RTC_CR_FMT_Pos (6U)
screamer 28:0e774865873d 11837 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11838 #define RTC_CR_FMT RTC_CR_FMT_Msk
screamer 28:0e774865873d 11839 #define RTC_CR_BYPSHAD_Pos (5U)
screamer 28:0e774865873d 11840 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11841 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
screamer 28:0e774865873d 11842 #define RTC_CR_REFCKON_Pos (4U)
screamer 28:0e774865873d 11843 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11844 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
screamer 28:0e774865873d 11845 #define RTC_CR_TSEDGE_Pos (3U)
screamer 28:0e774865873d 11846 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11847 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
screamer 28:0e774865873d 11848 #define RTC_CR_WUCKSEL_Pos (0U)
screamer 28:0e774865873d 11849 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 11850 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
screamer 28:0e774865873d 11851 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11852 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11853 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11854
screamer 28:0e774865873d 11855 /* Legacy defines */
screamer 28:0e774865873d 11856 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
screamer 28:0e774865873d 11857 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
screamer 28:0e774865873d 11858 #define RTC_CR_BCK RTC_CR_BKP
screamer 28:0e774865873d 11859
screamer 28:0e774865873d 11860 /******************** Bits definition for RTC_ISR register ******************/
screamer 28:0e774865873d 11861 #define RTC_ISR_ITSF_Pos (17U)
screamer 28:0e774865873d 11862 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11863 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
screamer 28:0e774865873d 11864 #define RTC_ISR_RECALPF_Pos (16U)
screamer 28:0e774865873d 11865 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11866 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
screamer 28:0e774865873d 11867 #define RTC_ISR_TAMP3F_Pos (15U)
screamer 28:0e774865873d 11868 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11869 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
screamer 28:0e774865873d 11870 #define RTC_ISR_TAMP2F_Pos (14U)
screamer 28:0e774865873d 11871 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11872 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
screamer 28:0e774865873d 11873 #define RTC_ISR_TAMP1F_Pos (13U)
screamer 28:0e774865873d 11874 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11875 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
screamer 28:0e774865873d 11876 #define RTC_ISR_TSOVF_Pos (12U)
screamer 28:0e774865873d 11877 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11878 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
screamer 28:0e774865873d 11879 #define RTC_ISR_TSF_Pos (11U)
screamer 28:0e774865873d 11880 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11881 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
screamer 28:0e774865873d 11882 #define RTC_ISR_WUTF_Pos (10U)
screamer 28:0e774865873d 11883 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11884 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
screamer 28:0e774865873d 11885 #define RTC_ISR_ALRBF_Pos (9U)
screamer 28:0e774865873d 11886 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11887 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
screamer 28:0e774865873d 11888 #define RTC_ISR_ALRAF_Pos (8U)
screamer 28:0e774865873d 11889 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11890 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
screamer 28:0e774865873d 11891 #define RTC_ISR_INIT_Pos (7U)
screamer 28:0e774865873d 11892 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 11893 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
screamer 28:0e774865873d 11894 #define RTC_ISR_INITF_Pos (6U)
screamer 28:0e774865873d 11895 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11896 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
screamer 28:0e774865873d 11897 #define RTC_ISR_RSF_Pos (5U)
screamer 28:0e774865873d 11898 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11899 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
screamer 28:0e774865873d 11900 #define RTC_ISR_INITS_Pos (4U)
screamer 28:0e774865873d 11901 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11902 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
screamer 28:0e774865873d 11903 #define RTC_ISR_SHPF_Pos (3U)
screamer 28:0e774865873d 11904 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11905 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
screamer 28:0e774865873d 11906 #define RTC_ISR_WUTWF_Pos (2U)
screamer 28:0e774865873d 11907 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11908 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
screamer 28:0e774865873d 11909 #define RTC_ISR_ALRBWF_Pos (1U)
screamer 28:0e774865873d 11910 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11911 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
screamer 28:0e774865873d 11912 #define RTC_ISR_ALRAWF_Pos (0U)
screamer 28:0e774865873d 11913 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11914 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
screamer 28:0e774865873d 11915
screamer 28:0e774865873d 11916 /******************** Bits definition for RTC_PRER register *****************/
screamer 28:0e774865873d 11917 #define RTC_PRER_PREDIV_A_Pos (16U)
screamer 28:0e774865873d 11918 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
screamer 28:0e774865873d 11919 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
screamer 28:0e774865873d 11920 #define RTC_PRER_PREDIV_S_Pos (0U)
screamer 28:0e774865873d 11921 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
screamer 28:0e774865873d 11922 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
screamer 28:0e774865873d 11923
screamer 28:0e774865873d 11924 /******************** Bits definition for RTC_WUTR register *****************/
screamer 28:0e774865873d 11925 #define RTC_WUTR_WUT_Pos (0U)
screamer 28:0e774865873d 11926 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 11927 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
screamer 28:0e774865873d 11928
screamer 28:0e774865873d 11929 /******************** Bits definition for RTC_ALRMAR register ***************/
screamer 28:0e774865873d 11930 #define RTC_ALRMAR_MSK4_Pos (31U)
screamer 28:0e774865873d 11931 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 11932 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
screamer 28:0e774865873d 11933 #define RTC_ALRMAR_WDSEL_Pos (30U)
screamer 28:0e774865873d 11934 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 11935 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
screamer 28:0e774865873d 11936 #define RTC_ALRMAR_DT_Pos (28U)
screamer 28:0e774865873d 11937 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 11938 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
screamer 28:0e774865873d 11939 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 11940 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 11941 #define RTC_ALRMAR_DU_Pos (24U)
screamer 28:0e774865873d 11942 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 11943 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
screamer 28:0e774865873d 11944 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 11945 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 11946 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 11947 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 11948 #define RTC_ALRMAR_MSK3_Pos (23U)
screamer 28:0e774865873d 11949 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 11950 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
screamer 28:0e774865873d 11951 #define RTC_ALRMAR_PM_Pos (22U)
screamer 28:0e774865873d 11952 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 11953 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
screamer 28:0e774865873d 11954 #define RTC_ALRMAR_HT_Pos (20U)
screamer 28:0e774865873d 11955 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 11956 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
screamer 28:0e774865873d 11957 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 11958 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 11959 #define RTC_ALRMAR_HU_Pos (16U)
screamer 28:0e774865873d 11960 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 11961 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
screamer 28:0e774865873d 11962 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 11963 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 11964 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 11965 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 11966 #define RTC_ALRMAR_MSK2_Pos (15U)
screamer 28:0e774865873d 11967 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 11968 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
screamer 28:0e774865873d 11969 #define RTC_ALRMAR_MNT_Pos (12U)
screamer 28:0e774865873d 11970 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 11971 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
screamer 28:0e774865873d 11972 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 11973 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 11974 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 11975 #define RTC_ALRMAR_MNU_Pos (8U)
screamer 28:0e774865873d 11976 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 11977 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
screamer 28:0e774865873d 11978 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 11979 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 11980 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 11981 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 11982 #define RTC_ALRMAR_MSK1_Pos (7U)
screamer 28:0e774865873d 11983 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 11984 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
screamer 28:0e774865873d 11985 #define RTC_ALRMAR_ST_Pos (4U)
screamer 28:0e774865873d 11986 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 11987 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
screamer 28:0e774865873d 11988 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 11989 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 11990 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 11991 #define RTC_ALRMAR_SU_Pos (0U)
screamer 28:0e774865873d 11992 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 11993 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
screamer 28:0e774865873d 11994 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 11995 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 11996 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 11997 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 11998
screamer 28:0e774865873d 11999 /******************** Bits definition for RTC_ALRMBR register ***************/
screamer 28:0e774865873d 12000 #define RTC_ALRMBR_MSK4_Pos (31U)
screamer 28:0e774865873d 12001 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 12002 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
screamer 28:0e774865873d 12003 #define RTC_ALRMBR_WDSEL_Pos (30U)
screamer 28:0e774865873d 12004 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 12005 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
screamer 28:0e774865873d 12006 #define RTC_ALRMBR_DT_Pos (28U)
screamer 28:0e774865873d 12007 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
screamer 28:0e774865873d 12008 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
screamer 28:0e774865873d 12009 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 12010 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 12011 #define RTC_ALRMBR_DU_Pos (24U)
screamer 28:0e774865873d 12012 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 12013 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
screamer 28:0e774865873d 12014 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 12015 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 12016 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 12017 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 12018 #define RTC_ALRMBR_MSK3_Pos (23U)
screamer 28:0e774865873d 12019 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 12020 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
screamer 28:0e774865873d 12021 #define RTC_ALRMBR_PM_Pos (22U)
screamer 28:0e774865873d 12022 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 12023 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
screamer 28:0e774865873d 12024 #define RTC_ALRMBR_HT_Pos (20U)
screamer 28:0e774865873d 12025 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 12026 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
screamer 28:0e774865873d 12027 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 12028 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 12029 #define RTC_ALRMBR_HU_Pos (16U)
screamer 28:0e774865873d 12030 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 12031 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
screamer 28:0e774865873d 12032 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12033 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12034 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 12035 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 12036 #define RTC_ALRMBR_MSK2_Pos (15U)
screamer 28:0e774865873d 12037 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 12038 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
screamer 28:0e774865873d 12039 #define RTC_ALRMBR_MNT_Pos (12U)
screamer 28:0e774865873d 12040 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 12041 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
screamer 28:0e774865873d 12042 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12043 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12044 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12045 #define RTC_ALRMBR_MNU_Pos (8U)
screamer 28:0e774865873d 12046 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 12047 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
screamer 28:0e774865873d 12048 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12049 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12050 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12051 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12052 #define RTC_ALRMBR_MSK1_Pos (7U)
screamer 28:0e774865873d 12053 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12054 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
screamer 28:0e774865873d 12055 #define RTC_ALRMBR_ST_Pos (4U)
screamer 28:0e774865873d 12056 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 12057 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
screamer 28:0e774865873d 12058 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12059 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12060 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12061 #define RTC_ALRMBR_SU_Pos (0U)
screamer 28:0e774865873d 12062 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 12063 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
screamer 28:0e774865873d 12064 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12065 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12066 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12067 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12068
screamer 28:0e774865873d 12069 /******************** Bits definition for RTC_WPR register ******************/
screamer 28:0e774865873d 12070 #define RTC_WPR_KEY_Pos (0U)
screamer 28:0e774865873d 12071 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 12072 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
screamer 28:0e774865873d 12073
screamer 28:0e774865873d 12074 /******************** Bits definition for RTC_SSR register ******************/
screamer 28:0e774865873d 12075 #define RTC_SSR_SS_Pos (0U)
screamer 28:0e774865873d 12076 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 12077 #define RTC_SSR_SS RTC_SSR_SS_Msk
screamer 28:0e774865873d 12078
screamer 28:0e774865873d 12079 /******************** Bits definition for RTC_SHIFTR register ***************/
screamer 28:0e774865873d 12080 #define RTC_SHIFTR_SUBFS_Pos (0U)
screamer 28:0e774865873d 12081 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
screamer 28:0e774865873d 12082 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
screamer 28:0e774865873d 12083 #define RTC_SHIFTR_ADD1S_Pos (31U)
screamer 28:0e774865873d 12084 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 12085 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
screamer 28:0e774865873d 12086
screamer 28:0e774865873d 12087 /******************** Bits definition for RTC_TSTR register *****************/
screamer 28:0e774865873d 12088 #define RTC_TSTR_PM_Pos (22U)
screamer 28:0e774865873d 12089 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 12090 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
screamer 28:0e774865873d 12091 #define RTC_TSTR_HT_Pos (20U)
screamer 28:0e774865873d 12092 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 12093 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
screamer 28:0e774865873d 12094 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 12095 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 12096 #define RTC_TSTR_HU_Pos (16U)
screamer 28:0e774865873d 12097 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 12098 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
screamer 28:0e774865873d 12099 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12100 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12101 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 12102 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 12103 #define RTC_TSTR_MNT_Pos (12U)
screamer 28:0e774865873d 12104 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 12105 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
screamer 28:0e774865873d 12106 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12107 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12108 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12109 #define RTC_TSTR_MNU_Pos (8U)
screamer 28:0e774865873d 12110 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 12111 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
screamer 28:0e774865873d 12112 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12113 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12114 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12115 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12116 #define RTC_TSTR_ST_Pos (4U)
screamer 28:0e774865873d 12117 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 12118 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
screamer 28:0e774865873d 12119 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12120 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12121 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12122 #define RTC_TSTR_SU_Pos (0U)
screamer 28:0e774865873d 12123 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 12124 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
screamer 28:0e774865873d 12125 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12126 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12127 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12128 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12129
screamer 28:0e774865873d 12130 /******************** Bits definition for RTC_TSDR register *****************/
screamer 28:0e774865873d 12131 #define RTC_TSDR_WDU_Pos (13U)
screamer 28:0e774865873d 12132 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
screamer 28:0e774865873d 12133 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
screamer 28:0e774865873d 12134 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12135 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12136 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 12137 #define RTC_TSDR_MT_Pos (12U)
screamer 28:0e774865873d 12138 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12139 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
screamer 28:0e774865873d 12140 #define RTC_TSDR_MU_Pos (8U)
screamer 28:0e774865873d 12141 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 12142 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
screamer 28:0e774865873d 12143 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12144 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12145 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12146 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12147 #define RTC_TSDR_DT_Pos (4U)
screamer 28:0e774865873d 12148 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 12149 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
screamer 28:0e774865873d 12150 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12151 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12152 #define RTC_TSDR_DU_Pos (0U)
screamer 28:0e774865873d 12153 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 12154 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
screamer 28:0e774865873d 12155 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12156 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12157 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12158 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12159
screamer 28:0e774865873d 12160 /******************** Bits definition for RTC_TSSSR register ****************/
screamer 28:0e774865873d 12161 #define RTC_TSSSR_SS_Pos (0U)
screamer 28:0e774865873d 12162 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 12163 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
screamer 28:0e774865873d 12164
screamer 28:0e774865873d 12165 /******************** Bits definition for RTC_CAL register *****************/
screamer 28:0e774865873d 12166 #define RTC_CALR_CALP_Pos (15U)
screamer 28:0e774865873d 12167 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 12168 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
screamer 28:0e774865873d 12169 #define RTC_CALR_CALW8_Pos (14U)
screamer 28:0e774865873d 12170 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12171 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
screamer 28:0e774865873d 12172 #define RTC_CALR_CALW16_Pos (13U)
screamer 28:0e774865873d 12173 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12174 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
screamer 28:0e774865873d 12175 #define RTC_CALR_CALM_Pos (0U)
screamer 28:0e774865873d 12176 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
screamer 28:0e774865873d 12177 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
screamer 28:0e774865873d 12178 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12179 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12180 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12181 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12182 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12183 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12184 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12185 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12186 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12187
screamer 28:0e774865873d 12188 /******************** Bits definition for RTC_TAMPCR register ***************/
screamer 28:0e774865873d 12189 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
screamer 28:0e774865873d 12190 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 12191 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
screamer 28:0e774865873d 12192 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
screamer 28:0e774865873d 12193 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 12194 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
screamer 28:0e774865873d 12195 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
screamer 28:0e774865873d 12196 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 12197 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
screamer 28:0e774865873d 12198 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
screamer 28:0e774865873d 12199 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 12200 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
screamer 28:0e774865873d 12201 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
screamer 28:0e774865873d 12202 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 12203 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
screamer 28:0e774865873d 12204 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
screamer 28:0e774865873d 12205 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 12206 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
screamer 28:0e774865873d 12207 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
screamer 28:0e774865873d 12208 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 12209 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
screamer 28:0e774865873d 12210 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
screamer 28:0e774865873d 12211 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12212 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
screamer 28:0e774865873d 12213 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
screamer 28:0e774865873d 12214 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12215 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
screamer 28:0e774865873d 12216 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
screamer 28:0e774865873d 12217 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 12218 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
screamer 28:0e774865873d 12219 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
screamer 28:0e774865873d 12220 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
screamer 28:0e774865873d 12221 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
screamer 28:0e774865873d 12222 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12223 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12224 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
screamer 28:0e774865873d 12225 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
screamer 28:0e774865873d 12226 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
screamer 28:0e774865873d 12227 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12228 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12229 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
screamer 28:0e774865873d 12230 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 12231 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
screamer 28:0e774865873d 12232 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12233 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12234 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12235 #define RTC_TAMPCR_TAMPTS_Pos (7U)
screamer 28:0e774865873d 12236 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12237 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
screamer 28:0e774865873d 12238 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
screamer 28:0e774865873d 12239 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12240 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
screamer 28:0e774865873d 12241 #define RTC_TAMPCR_TAMP3E_Pos (5U)
screamer 28:0e774865873d 12242 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12243 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
screamer 28:0e774865873d 12244 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
screamer 28:0e774865873d 12245 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12246 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
screamer 28:0e774865873d 12247 #define RTC_TAMPCR_TAMP2E_Pos (3U)
screamer 28:0e774865873d 12248 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12249 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
screamer 28:0e774865873d 12250 #define RTC_TAMPCR_TAMPIE_Pos (2U)
screamer 28:0e774865873d 12251 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12252 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
screamer 28:0e774865873d 12253 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
screamer 28:0e774865873d 12254 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12255 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
screamer 28:0e774865873d 12256 #define RTC_TAMPCR_TAMP1E_Pos (0U)
screamer 28:0e774865873d 12257 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12258 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
screamer 28:0e774865873d 12259
screamer 28:0e774865873d 12260 /******************** Bits definition for RTC_ALRMASSR register *************/
screamer 28:0e774865873d 12261 #define RTC_ALRMASSR_MASKSS_Pos (24U)
screamer 28:0e774865873d 12262 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 12263 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
screamer 28:0e774865873d 12264 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 12265 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 12266 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 12267 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 12268 #define RTC_ALRMASSR_SS_Pos (0U)
screamer 28:0e774865873d 12269 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
screamer 28:0e774865873d 12270 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
screamer 28:0e774865873d 12271
screamer 28:0e774865873d 12272 /******************** Bits definition for RTC_ALRMBSSR register *************/
screamer 28:0e774865873d 12273 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
screamer 28:0e774865873d 12274 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 12275 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
screamer 28:0e774865873d 12276 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 12277 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 12278 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 12279 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 12280 #define RTC_ALRMBSSR_SS_Pos (0U)
screamer 28:0e774865873d 12281 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
screamer 28:0e774865873d 12282 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
screamer 28:0e774865873d 12283
screamer 28:0e774865873d 12284 /******************** Bits definition for RTC_0R register *******************/
screamer 28:0e774865873d 12285 #define RTC_OR_OUT_RMP_Pos (1U)
screamer 28:0e774865873d 12286 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12287 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
screamer 28:0e774865873d 12288 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
screamer 28:0e774865873d 12289 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12290 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
screamer 28:0e774865873d 12291
screamer 28:0e774865873d 12292
screamer 28:0e774865873d 12293 /******************** Bits definition for RTC_BKP0R register ****************/
screamer 28:0e774865873d 12294 #define RTC_BKP0R_Pos (0U)
screamer 28:0e774865873d 12295 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12296 #define RTC_BKP0R RTC_BKP0R_Msk
screamer 28:0e774865873d 12297
screamer 28:0e774865873d 12298 /******************** Bits definition for RTC_BKP1R register ****************/
screamer 28:0e774865873d 12299 #define RTC_BKP1R_Pos (0U)
screamer 28:0e774865873d 12300 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12301 #define RTC_BKP1R RTC_BKP1R_Msk
screamer 28:0e774865873d 12302
screamer 28:0e774865873d 12303 /******************** Bits definition for RTC_BKP2R register ****************/
screamer 28:0e774865873d 12304 #define RTC_BKP2R_Pos (0U)
screamer 28:0e774865873d 12305 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12306 #define RTC_BKP2R RTC_BKP2R_Msk
screamer 28:0e774865873d 12307
screamer 28:0e774865873d 12308 /******************** Bits definition for RTC_BKP3R register ****************/
screamer 28:0e774865873d 12309 #define RTC_BKP3R_Pos (0U)
screamer 28:0e774865873d 12310 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12311 #define RTC_BKP3R RTC_BKP3R_Msk
screamer 28:0e774865873d 12312
screamer 28:0e774865873d 12313 /******************** Bits definition for RTC_BKP4R register ****************/
screamer 28:0e774865873d 12314 #define RTC_BKP4R_Pos (0U)
screamer 28:0e774865873d 12315 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12316 #define RTC_BKP4R RTC_BKP4R_Msk
screamer 28:0e774865873d 12317
screamer 28:0e774865873d 12318 /******************** Bits definition for RTC_BKP5R register ****************/
screamer 28:0e774865873d 12319 #define RTC_BKP5R_Pos (0U)
screamer 28:0e774865873d 12320 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12321 #define RTC_BKP5R RTC_BKP5R_Msk
screamer 28:0e774865873d 12322
screamer 28:0e774865873d 12323 /******************** Bits definition for RTC_BKP6R register ****************/
screamer 28:0e774865873d 12324 #define RTC_BKP6R_Pos (0U)
screamer 28:0e774865873d 12325 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12326 #define RTC_BKP6R RTC_BKP6R_Msk
screamer 28:0e774865873d 12327
screamer 28:0e774865873d 12328 /******************** Bits definition for RTC_BKP7R register ****************/
screamer 28:0e774865873d 12329 #define RTC_BKP7R_Pos (0U)
screamer 28:0e774865873d 12330 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12331 #define RTC_BKP7R RTC_BKP7R_Msk
screamer 28:0e774865873d 12332
screamer 28:0e774865873d 12333 /******************** Bits definition for RTC_BKP8R register ****************/
screamer 28:0e774865873d 12334 #define RTC_BKP8R_Pos (0U)
screamer 28:0e774865873d 12335 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12336 #define RTC_BKP8R RTC_BKP8R_Msk
screamer 28:0e774865873d 12337
screamer 28:0e774865873d 12338 /******************** Bits definition for RTC_BKP9R register ****************/
screamer 28:0e774865873d 12339 #define RTC_BKP9R_Pos (0U)
screamer 28:0e774865873d 12340 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12341 #define RTC_BKP9R RTC_BKP9R_Msk
screamer 28:0e774865873d 12342
screamer 28:0e774865873d 12343 /******************** Bits definition for RTC_BKP10R register ***************/
screamer 28:0e774865873d 12344 #define RTC_BKP10R_Pos (0U)
screamer 28:0e774865873d 12345 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12346 #define RTC_BKP10R RTC_BKP10R_Msk
screamer 28:0e774865873d 12347
screamer 28:0e774865873d 12348 /******************** Bits definition for RTC_BKP11R register ***************/
screamer 28:0e774865873d 12349 #define RTC_BKP11R_Pos (0U)
screamer 28:0e774865873d 12350 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12351 #define RTC_BKP11R RTC_BKP11R_Msk
screamer 28:0e774865873d 12352
screamer 28:0e774865873d 12353 /******************** Bits definition for RTC_BKP12R register ***************/
screamer 28:0e774865873d 12354 #define RTC_BKP12R_Pos (0U)
screamer 28:0e774865873d 12355 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12356 #define RTC_BKP12R RTC_BKP12R_Msk
screamer 28:0e774865873d 12357
screamer 28:0e774865873d 12358 /******************** Bits definition for RTC_BKP13R register ***************/
screamer 28:0e774865873d 12359 #define RTC_BKP13R_Pos (0U)
screamer 28:0e774865873d 12360 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12361 #define RTC_BKP13R RTC_BKP13R_Msk
screamer 28:0e774865873d 12362
screamer 28:0e774865873d 12363 /******************** Bits definition for RTC_BKP14R register ***************/
screamer 28:0e774865873d 12364 #define RTC_BKP14R_Pos (0U)
screamer 28:0e774865873d 12365 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12366 #define RTC_BKP14R RTC_BKP14R_Msk
screamer 28:0e774865873d 12367
screamer 28:0e774865873d 12368 /******************** Bits definition for RTC_BKP15R register ***************/
screamer 28:0e774865873d 12369 #define RTC_BKP15R_Pos (0U)
screamer 28:0e774865873d 12370 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12371 #define RTC_BKP15R RTC_BKP15R_Msk
screamer 28:0e774865873d 12372
screamer 28:0e774865873d 12373 /******************** Bits definition for RTC_BKP16R register ***************/
screamer 28:0e774865873d 12374 #define RTC_BKP16R_Pos (0U)
screamer 28:0e774865873d 12375 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12376 #define RTC_BKP16R RTC_BKP16R_Msk
screamer 28:0e774865873d 12377
screamer 28:0e774865873d 12378 /******************** Bits definition for RTC_BKP17R register ***************/
screamer 28:0e774865873d 12379 #define RTC_BKP17R_Pos (0U)
screamer 28:0e774865873d 12380 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12381 #define RTC_BKP17R RTC_BKP17R_Msk
screamer 28:0e774865873d 12382
screamer 28:0e774865873d 12383 /******************** Bits definition for RTC_BKP18R register ***************/
screamer 28:0e774865873d 12384 #define RTC_BKP18R_Pos (0U)
screamer 28:0e774865873d 12385 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12386 #define RTC_BKP18R RTC_BKP18R_Msk
screamer 28:0e774865873d 12387
screamer 28:0e774865873d 12388 /******************** Bits definition for RTC_BKP19R register ***************/
screamer 28:0e774865873d 12389 #define RTC_BKP19R_Pos (0U)
screamer 28:0e774865873d 12390 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12391 #define RTC_BKP19R RTC_BKP19R_Msk
screamer 28:0e774865873d 12392
screamer 28:0e774865873d 12393 /******************** Bits definition for RTC_BKP20R register ***************/
screamer 28:0e774865873d 12394 #define RTC_BKP20R_Pos (0U)
screamer 28:0e774865873d 12395 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12396 #define RTC_BKP20R RTC_BKP20R_Msk
screamer 28:0e774865873d 12397
screamer 28:0e774865873d 12398 /******************** Bits definition for RTC_BKP21R register ***************/
screamer 28:0e774865873d 12399 #define RTC_BKP21R_Pos (0U)
screamer 28:0e774865873d 12400 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12401 #define RTC_BKP21R RTC_BKP21R_Msk
screamer 28:0e774865873d 12402
screamer 28:0e774865873d 12403 /******************** Bits definition for RTC_BKP22R register ***************/
screamer 28:0e774865873d 12404 #define RTC_BKP22R_Pos (0U)
screamer 28:0e774865873d 12405 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12406 #define RTC_BKP22R RTC_BKP22R_Msk
screamer 28:0e774865873d 12407
screamer 28:0e774865873d 12408 /******************** Bits definition for RTC_BKP23R register ***************/
screamer 28:0e774865873d 12409 #define RTC_BKP23R_Pos (0U)
screamer 28:0e774865873d 12410 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12411 #define RTC_BKP23R RTC_BKP23R_Msk
screamer 28:0e774865873d 12412
screamer 28:0e774865873d 12413 /******************** Bits definition for RTC_BKP24R register ***************/
screamer 28:0e774865873d 12414 #define RTC_BKP24R_Pos (0U)
screamer 28:0e774865873d 12415 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12416 #define RTC_BKP24R RTC_BKP24R_Msk
screamer 28:0e774865873d 12417
screamer 28:0e774865873d 12418 /******************** Bits definition for RTC_BKP25R register ***************/
screamer 28:0e774865873d 12419 #define RTC_BKP25R_Pos (0U)
screamer 28:0e774865873d 12420 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12421 #define RTC_BKP25R RTC_BKP25R_Msk
screamer 28:0e774865873d 12422
screamer 28:0e774865873d 12423 /******************** Bits definition for RTC_BKP26R register ***************/
screamer 28:0e774865873d 12424 #define RTC_BKP26R_Pos (0U)
screamer 28:0e774865873d 12425 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12426 #define RTC_BKP26R RTC_BKP26R_Msk
screamer 28:0e774865873d 12427
screamer 28:0e774865873d 12428 /******************** Bits definition for RTC_BKP27R register ***************/
screamer 28:0e774865873d 12429 #define RTC_BKP27R_Pos (0U)
screamer 28:0e774865873d 12430 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12431 #define RTC_BKP27R RTC_BKP27R_Msk
screamer 28:0e774865873d 12432
screamer 28:0e774865873d 12433 /******************** Bits definition for RTC_BKP28R register ***************/
screamer 28:0e774865873d 12434 #define RTC_BKP28R_Pos (0U)
screamer 28:0e774865873d 12435 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12436 #define RTC_BKP28R RTC_BKP28R_Msk
screamer 28:0e774865873d 12437
screamer 28:0e774865873d 12438 /******************** Bits definition for RTC_BKP29R register ***************/
screamer 28:0e774865873d 12439 #define RTC_BKP29R_Pos (0U)
screamer 28:0e774865873d 12440 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12441 #define RTC_BKP29R RTC_BKP29R_Msk
screamer 28:0e774865873d 12442
screamer 28:0e774865873d 12443 /******************** Bits definition for RTC_BKP30R register ***************/
screamer 28:0e774865873d 12444 #define RTC_BKP30R_Pos (0U)
screamer 28:0e774865873d 12445 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12446 #define RTC_BKP30R RTC_BKP30R_Msk
screamer 28:0e774865873d 12447
screamer 28:0e774865873d 12448 /******************** Bits definition for RTC_BKP31R register ***************/
screamer 28:0e774865873d 12449 #define RTC_BKP31R_Pos (0U)
screamer 28:0e774865873d 12450 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12451 #define RTC_BKP31R RTC_BKP31R_Msk
screamer 28:0e774865873d 12452
screamer 28:0e774865873d 12453 /******************** Number of backup registers ******************************/
screamer 28:0e774865873d 12454 #define RTC_BKP_NUMBER 32U
screamer 28:0e774865873d 12455
screamer 28:0e774865873d 12456 /******************************************************************************/
screamer 28:0e774865873d 12457 /* */
screamer 28:0e774865873d 12458 /* Serial Audio Interface */
screamer 28:0e774865873d 12459 /* */
screamer 28:0e774865873d 12460 /******************************************************************************/
screamer 28:0e774865873d 12461 /******************** Bit definition for SAI_GCR register *******************/
screamer 28:0e774865873d 12462 #define SAI_GCR_SYNCIN_Pos (0U)
screamer 28:0e774865873d 12463 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 12464 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
screamer 28:0e774865873d 12465 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12466 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12467
screamer 28:0e774865873d 12468 #define SAI_GCR_SYNCOUT_Pos (4U)
screamer 28:0e774865873d 12469 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 12470 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
screamer 28:0e774865873d 12471 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12472 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12473
screamer 28:0e774865873d 12474 /******************* Bit definition for SAI_xCR1 register *******************/
screamer 28:0e774865873d 12475 #define SAI_xCR1_MODE_Pos (0U)
screamer 28:0e774865873d 12476 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 12477 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
screamer 28:0e774865873d 12478 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12479 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12480
screamer 28:0e774865873d 12481 #define SAI_xCR1_PRTCFG_Pos (2U)
screamer 28:0e774865873d 12482 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 12483 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
screamer 28:0e774865873d 12484 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12485 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12486
screamer 28:0e774865873d 12487 #define SAI_xCR1_DS_Pos (5U)
screamer 28:0e774865873d 12488 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
screamer 28:0e774865873d 12489 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
screamer 28:0e774865873d 12490 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12491 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12492 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12493
screamer 28:0e774865873d 12494 #define SAI_xCR1_LSBFIRST_Pos (8U)
screamer 28:0e774865873d 12495 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12496 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
screamer 28:0e774865873d 12497 #define SAI_xCR1_CKSTR_Pos (9U)
screamer 28:0e774865873d 12498 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12499 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
screamer 28:0e774865873d 12500
screamer 28:0e774865873d 12501 #define SAI_xCR1_SYNCEN_Pos (10U)
screamer 28:0e774865873d 12502 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 12503 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
screamer 28:0e774865873d 12504 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12505 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12506
screamer 28:0e774865873d 12507 #define SAI_xCR1_MONO_Pos (12U)
screamer 28:0e774865873d 12508 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12509 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
screamer 28:0e774865873d 12510 #define SAI_xCR1_OUTDRIV_Pos (13U)
screamer 28:0e774865873d 12511 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12512 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
screamer 28:0e774865873d 12513 #define SAI_xCR1_SAIEN_Pos (16U)
screamer 28:0e774865873d 12514 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12515 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
screamer 28:0e774865873d 12516 #define SAI_xCR1_DMAEN_Pos (17U)
screamer 28:0e774865873d 12517 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12518 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
screamer 28:0e774865873d 12519 #define SAI_xCR1_NODIV_Pos (19U)
screamer 28:0e774865873d 12520 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 12521 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
screamer 28:0e774865873d 12522
screamer 28:0e774865873d 12523 #define SAI_xCR1_MCKDIV_Pos (20U)
screamer 28:0e774865873d 12524 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 12525 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
screamer 28:0e774865873d 12526 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
screamer 28:0e774865873d 12527 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
screamer 28:0e774865873d 12528 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
screamer 28:0e774865873d 12529 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
screamer 28:0e774865873d 12530
screamer 28:0e774865873d 12531 /******************* Bit definition for SAI_xCR2 register *******************/
screamer 28:0e774865873d 12532 #define SAI_xCR2_FTH_Pos (0U)
screamer 28:0e774865873d 12533 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 12534 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
screamer 28:0e774865873d 12535 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12536 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12537 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12538
screamer 28:0e774865873d 12539 #define SAI_xCR2_FFLUSH_Pos (3U)
screamer 28:0e774865873d 12540 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12541 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
screamer 28:0e774865873d 12542 #define SAI_xCR2_TRIS_Pos (4U)
screamer 28:0e774865873d 12543 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12544 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
screamer 28:0e774865873d 12545 #define SAI_xCR2_MUTE_Pos (5U)
screamer 28:0e774865873d 12546 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12547 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
screamer 28:0e774865873d 12548 #define SAI_xCR2_MUTEVAL_Pos (6U)
screamer 28:0e774865873d 12549 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12550 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
screamer 28:0e774865873d 12551
screamer 28:0e774865873d 12552
screamer 28:0e774865873d 12553 #define SAI_xCR2_MUTECNT_Pos (7U)
screamer 28:0e774865873d 12554 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
screamer 28:0e774865873d 12555 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
screamer 28:0e774865873d 12556 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12557 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12558 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12559 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12560 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12561 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12562
screamer 28:0e774865873d 12563 #define SAI_xCR2_CPL_Pos (13U)
screamer 28:0e774865873d 12564 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12565 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
screamer 28:0e774865873d 12566 #define SAI_xCR2_COMP_Pos (14U)
screamer 28:0e774865873d 12567 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 12568 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
screamer 28:0e774865873d 12569 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12570 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 12571
screamer 28:0e774865873d 12572
screamer 28:0e774865873d 12573 /****************** Bit definition for SAI_xFRCR register *******************/
screamer 28:0e774865873d 12574 #define SAI_xFRCR_FRL_Pos (0U)
screamer 28:0e774865873d 12575 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 12576 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
screamer 28:0e774865873d 12577 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12578 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12579 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12580 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12581 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12582 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12583 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12584 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12585
screamer 28:0e774865873d 12586 #define SAI_xFRCR_FSALL_Pos (8U)
screamer 28:0e774865873d 12587 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
screamer 28:0e774865873d 12588 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
screamer 28:0e774865873d 12589 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12590 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12591 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12592 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12593 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12594 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12595 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12596
screamer 28:0e774865873d 12597 #define SAI_xFRCR_FSDEF_Pos (16U)
screamer 28:0e774865873d 12598 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12599 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
screamer 28:0e774865873d 12600 #define SAI_xFRCR_FSPOL_Pos (17U)
screamer 28:0e774865873d 12601 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12602 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
screamer 28:0e774865873d 12603 #define SAI_xFRCR_FSOFF_Pos (18U)
screamer 28:0e774865873d 12604 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 12605 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
screamer 28:0e774865873d 12606
screamer 28:0e774865873d 12607 /****************** Bit definition for SAI_xSLOTR register *******************/
screamer 28:0e774865873d 12608 #define SAI_xSLOTR_FBOFF_Pos (0U)
screamer 28:0e774865873d 12609 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 12610 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
screamer 28:0e774865873d 12611 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12612 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12613 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12614 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12615 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12616
screamer 28:0e774865873d 12617 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
screamer 28:0e774865873d 12618 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 12619 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
screamer 28:0e774865873d 12620 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12621 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12622
screamer 28:0e774865873d 12623 #define SAI_xSLOTR_NBSLOT_Pos (8U)
screamer 28:0e774865873d 12624 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 12625 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
screamer 28:0e774865873d 12626 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12627 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12628 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12629 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12630
screamer 28:0e774865873d 12631 #define SAI_xSLOTR_SLOTEN_Pos (16U)
screamer 28:0e774865873d 12632 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 12633 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
screamer 28:0e774865873d 12634
screamer 28:0e774865873d 12635 /******************* Bit definition for SAI_xIMR register *******************/
screamer 28:0e774865873d 12636 #define SAI_xIMR_OVRUDRIE_Pos (0U)
screamer 28:0e774865873d 12637 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12638 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
screamer 28:0e774865873d 12639 #define SAI_xIMR_MUTEDETIE_Pos (1U)
screamer 28:0e774865873d 12640 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12641 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
screamer 28:0e774865873d 12642 #define SAI_xIMR_WCKCFGIE_Pos (2U)
screamer 28:0e774865873d 12643 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12644 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
screamer 28:0e774865873d 12645 #define SAI_xIMR_FREQIE_Pos (3U)
screamer 28:0e774865873d 12646 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12647 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
screamer 28:0e774865873d 12648 #define SAI_xIMR_CNRDYIE_Pos (4U)
screamer 28:0e774865873d 12649 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12650 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
screamer 28:0e774865873d 12651 #define SAI_xIMR_AFSDETIE_Pos (5U)
screamer 28:0e774865873d 12652 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12653 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
screamer 28:0e774865873d 12654 #define SAI_xIMR_LFSDETIE_Pos (6U)
screamer 28:0e774865873d 12655 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12656 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
screamer 28:0e774865873d 12657
screamer 28:0e774865873d 12658 /******************** Bit definition for SAI_xSR register *******************/
screamer 28:0e774865873d 12659 #define SAI_xSR_OVRUDR_Pos (0U)
screamer 28:0e774865873d 12660 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12661 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
screamer 28:0e774865873d 12662 #define SAI_xSR_MUTEDET_Pos (1U)
screamer 28:0e774865873d 12663 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12664 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
screamer 28:0e774865873d 12665 #define SAI_xSR_WCKCFG_Pos (2U)
screamer 28:0e774865873d 12666 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12667 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
screamer 28:0e774865873d 12668 #define SAI_xSR_FREQ_Pos (3U)
screamer 28:0e774865873d 12669 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12670 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
screamer 28:0e774865873d 12671 #define SAI_xSR_CNRDY_Pos (4U)
screamer 28:0e774865873d 12672 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12673 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
screamer 28:0e774865873d 12674 #define SAI_xSR_AFSDET_Pos (5U)
screamer 28:0e774865873d 12675 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12676 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
screamer 28:0e774865873d 12677 #define SAI_xSR_LFSDET_Pos (6U)
screamer 28:0e774865873d 12678 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12679 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
screamer 28:0e774865873d 12680
screamer 28:0e774865873d 12681 #define SAI_xSR_FLVL_Pos (16U)
screamer 28:0e774865873d 12682 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
screamer 28:0e774865873d 12683 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
screamer 28:0e774865873d 12684 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12685 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12686 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 12687
screamer 28:0e774865873d 12688 /****************** Bit definition for SAI_xCLRFR register ******************/
screamer 28:0e774865873d 12689 #define SAI_xCLRFR_COVRUDR_Pos (0U)
screamer 28:0e774865873d 12690 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12691 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
screamer 28:0e774865873d 12692 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
screamer 28:0e774865873d 12693 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12694 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
screamer 28:0e774865873d 12695 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
screamer 28:0e774865873d 12696 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12697 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
screamer 28:0e774865873d 12698 #define SAI_xCLRFR_CFREQ_Pos (3U)
screamer 28:0e774865873d 12699 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12700 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
screamer 28:0e774865873d 12701 #define SAI_xCLRFR_CCNRDY_Pos (4U)
screamer 28:0e774865873d 12702 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12703 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
screamer 28:0e774865873d 12704 #define SAI_xCLRFR_CAFSDET_Pos (5U)
screamer 28:0e774865873d 12705 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12706 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
screamer 28:0e774865873d 12707 #define SAI_xCLRFR_CLFSDET_Pos (6U)
screamer 28:0e774865873d 12708 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12709 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
screamer 28:0e774865873d 12710
screamer 28:0e774865873d 12711 /****************** Bit definition for SAI_xDR register ******************/
screamer 28:0e774865873d 12712 #define SAI_xDR_DATA_Pos (0U)
screamer 28:0e774865873d 12713 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12714 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
screamer 28:0e774865873d 12715
screamer 28:0e774865873d 12716 /******************************************************************************/
screamer 28:0e774865873d 12717 /* */
screamer 28:0e774865873d 12718 /* SDMMC Interface */
screamer 28:0e774865873d 12719 /* */
screamer 28:0e774865873d 12720 /******************************************************************************/
screamer 28:0e774865873d 12721 /****************** Bit definition for SDMMC_POWER register ******************/
screamer 28:0e774865873d 12722 #define SDMMC_POWER_PWRCTRL_Pos (0U)
screamer 28:0e774865873d 12723 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 12724 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
screamer 28:0e774865873d 12725 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12726 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12727
screamer 28:0e774865873d 12728 /****************** Bit definition for SDMMC_CLKCR register ******************/
screamer 28:0e774865873d 12729 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
screamer 28:0e774865873d 12730 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 12731 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
screamer 28:0e774865873d 12732 #define SDMMC_CLKCR_CLKEN_Pos (8U)
screamer 28:0e774865873d 12733 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12734 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
screamer 28:0e774865873d 12735 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
screamer 28:0e774865873d 12736 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12737 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
screamer 28:0e774865873d 12738 #define SDMMC_CLKCR_BYPASS_Pos (10U)
screamer 28:0e774865873d 12739 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12740 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
screamer 28:0e774865873d 12741
screamer 28:0e774865873d 12742 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
screamer 28:0e774865873d 12743 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
screamer 28:0e774865873d 12744 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
screamer 28:0e774865873d 12745 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12746 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12747
screamer 28:0e774865873d 12748 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
screamer 28:0e774865873d 12749 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12750 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
screamer 28:0e774865873d 12751 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
screamer 28:0e774865873d 12752 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12753 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
screamer 28:0e774865873d 12754
screamer 28:0e774865873d 12755 /******************* Bit definition for SDMMC_ARG register *******************/
screamer 28:0e774865873d 12756 #define SDMMC_ARG_CMDARG_Pos (0U)
screamer 28:0e774865873d 12757 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12758 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
screamer 28:0e774865873d 12759
screamer 28:0e774865873d 12760 /******************* Bit definition for SDMMC_CMD register *******************/
screamer 28:0e774865873d 12761 #define SDMMC_CMD_CMDINDEX_Pos (0U)
screamer 28:0e774865873d 12762 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
screamer 28:0e774865873d 12763 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
screamer 28:0e774865873d 12764
screamer 28:0e774865873d 12765 #define SDMMC_CMD_WAITRESP_Pos (6U)
screamer 28:0e774865873d 12766 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 12767 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
screamer 28:0e774865873d 12768 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12769 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12770
screamer 28:0e774865873d 12771 #define SDMMC_CMD_WAITINT_Pos (8U)
screamer 28:0e774865873d 12772 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12773 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
screamer 28:0e774865873d 12774 #define SDMMC_CMD_WAITPEND_Pos (9U)
screamer 28:0e774865873d 12775 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12776 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
screamer 28:0e774865873d 12777 #define SDMMC_CMD_CPSMEN_Pos (10U)
screamer 28:0e774865873d 12778 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12779 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
screamer 28:0e774865873d 12780 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
screamer 28:0e774865873d 12781 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12782 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
screamer 28:0e774865873d 12783
screamer 28:0e774865873d 12784 /***************** Bit definition for SDMMC_RESPCMD register *****************/
screamer 28:0e774865873d 12785 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
screamer 28:0e774865873d 12786 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
screamer 28:0e774865873d 12787 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
screamer 28:0e774865873d 12788
screamer 28:0e774865873d 12789 /****************** Bit definition for SDMMC_RESP1 register ******************/
screamer 28:0e774865873d 12790 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
screamer 28:0e774865873d 12791 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12792 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
screamer 28:0e774865873d 12793
screamer 28:0e774865873d 12794 /****************** Bit definition for SDMMC_RESP2 register ******************/
screamer 28:0e774865873d 12795 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
screamer 28:0e774865873d 12796 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12797 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
screamer 28:0e774865873d 12798
screamer 28:0e774865873d 12799 /****************** Bit definition for SDMMC_RESP3 register ******************/
screamer 28:0e774865873d 12800 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
screamer 28:0e774865873d 12801 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12802 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
screamer 28:0e774865873d 12803
screamer 28:0e774865873d 12804 /****************** Bit definition for SDMMC_RESP4 register ******************/
screamer 28:0e774865873d 12805 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
screamer 28:0e774865873d 12806 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12807 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
screamer 28:0e774865873d 12808
screamer 28:0e774865873d 12809 /****************** Bit definition for SDMMC_DTIMER register *****************/
screamer 28:0e774865873d 12810 #define SDMMC_DTIMER_DATATIME_Pos (0U)
screamer 28:0e774865873d 12811 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 12812 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
screamer 28:0e774865873d 12813
screamer 28:0e774865873d 12814 /****************** Bit definition for SDMMC_DLEN register *******************/
screamer 28:0e774865873d 12815 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
screamer 28:0e774865873d 12816 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
screamer 28:0e774865873d 12817 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
screamer 28:0e774865873d 12818
screamer 28:0e774865873d 12819 /****************** Bit definition for SDMMC_DCTRL register ******************/
screamer 28:0e774865873d 12820 #define SDMMC_DCTRL_DTEN_Pos (0U)
screamer 28:0e774865873d 12821 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12822 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
screamer 28:0e774865873d 12823 #define SDMMC_DCTRL_DTDIR_Pos (1U)
screamer 28:0e774865873d 12824 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12825 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
screamer 28:0e774865873d 12826 #define SDMMC_DCTRL_DTMODE_Pos (2U)
screamer 28:0e774865873d 12827 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12828 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
screamer 28:0e774865873d 12829 #define SDMMC_DCTRL_DMAEN_Pos (3U)
screamer 28:0e774865873d 12830 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12831 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
screamer 28:0e774865873d 12832
screamer 28:0e774865873d 12833 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
screamer 28:0e774865873d 12834 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 12835 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
screamer 28:0e774865873d 12836 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12837 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12838 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12839 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12840
screamer 28:0e774865873d 12841 #define SDMMC_DCTRL_RWSTART_Pos (8U)
screamer 28:0e774865873d 12842 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12843 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
screamer 28:0e774865873d 12844 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
screamer 28:0e774865873d 12845 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12846 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
screamer 28:0e774865873d 12847 #define SDMMC_DCTRL_RWMOD_Pos (10U)
screamer 28:0e774865873d 12848 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12849 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
screamer 28:0e774865873d 12850 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
screamer 28:0e774865873d 12851 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12852 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
screamer 28:0e774865873d 12853
screamer 28:0e774865873d 12854 /****************** Bit definition for SDMMC_DCOUNT register *****************/
screamer 28:0e774865873d 12855 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
screamer 28:0e774865873d 12856 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
screamer 28:0e774865873d 12857 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
screamer 28:0e774865873d 12858
screamer 28:0e774865873d 12859 /****************** Bit definition for SDMMC_STA register ********************/
screamer 28:0e774865873d 12860 #define SDMMC_STA_CCRCFAIL_Pos (0U)
screamer 28:0e774865873d 12861 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12862 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
screamer 28:0e774865873d 12863 #define SDMMC_STA_DCRCFAIL_Pos (1U)
screamer 28:0e774865873d 12864 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12865 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
screamer 28:0e774865873d 12866 #define SDMMC_STA_CTIMEOUT_Pos (2U)
screamer 28:0e774865873d 12867 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12868 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
screamer 28:0e774865873d 12869 #define SDMMC_STA_DTIMEOUT_Pos (3U)
screamer 28:0e774865873d 12870 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12871 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
screamer 28:0e774865873d 12872 #define SDMMC_STA_TXUNDERR_Pos (4U)
screamer 28:0e774865873d 12873 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12874 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
screamer 28:0e774865873d 12875 #define SDMMC_STA_RXOVERR_Pos (5U)
screamer 28:0e774865873d 12876 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12877 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
screamer 28:0e774865873d 12878 #define SDMMC_STA_CMDREND_Pos (6U)
screamer 28:0e774865873d 12879 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12880 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
screamer 28:0e774865873d 12881 #define SDMMC_STA_CMDSENT_Pos (7U)
screamer 28:0e774865873d 12882 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12883 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
screamer 28:0e774865873d 12884 #define SDMMC_STA_DATAEND_Pos (8U)
screamer 28:0e774865873d 12885 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12886 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
screamer 28:0e774865873d 12887 #define SDMMC_STA_STBITERR_Pos (9U)
screamer 28:0e774865873d 12888 #define SDMMC_STA_STBITERR_Msk (0x1U << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12889 #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
screamer 28:0e774865873d 12890 #define SDMMC_STA_DBCKEND_Pos (10U)
screamer 28:0e774865873d 12891 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12892 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
screamer 28:0e774865873d 12893 #define SDMMC_STA_CMDACT_Pos (11U)
screamer 28:0e774865873d 12894 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 12895 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
screamer 28:0e774865873d 12896 #define SDMMC_STA_TXACT_Pos (12U)
screamer 28:0e774865873d 12897 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 12898 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
screamer 28:0e774865873d 12899 #define SDMMC_STA_RXACT_Pos (13U)
screamer 28:0e774865873d 12900 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 12901 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
screamer 28:0e774865873d 12902 #define SDMMC_STA_TXFIFOHE_Pos (14U)
screamer 28:0e774865873d 12903 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 12904 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
screamer 28:0e774865873d 12905 #define SDMMC_STA_RXFIFOHF_Pos (15U)
screamer 28:0e774865873d 12906 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 12907 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
screamer 28:0e774865873d 12908 #define SDMMC_STA_TXFIFOF_Pos (16U)
screamer 28:0e774865873d 12909 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 12910 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
screamer 28:0e774865873d 12911 #define SDMMC_STA_RXFIFOF_Pos (17U)
screamer 28:0e774865873d 12912 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 12913 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
screamer 28:0e774865873d 12914 #define SDMMC_STA_TXFIFOE_Pos (18U)
screamer 28:0e774865873d 12915 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 12916 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
screamer 28:0e774865873d 12917 #define SDMMC_STA_RXFIFOE_Pos (19U)
screamer 28:0e774865873d 12918 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 12919 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
screamer 28:0e774865873d 12920 #define SDMMC_STA_TXDAVL_Pos (20U)
screamer 28:0e774865873d 12921 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 12922 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
screamer 28:0e774865873d 12923 #define SDMMC_STA_RXDAVL_Pos (21U)
screamer 28:0e774865873d 12924 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 12925 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
screamer 28:0e774865873d 12926 #define SDMMC_STA_SDIOIT_Pos (22U)
screamer 28:0e774865873d 12927 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 12928 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
screamer 28:0e774865873d 12929
screamer 28:0e774865873d 12930 /******************* Bit definition for SDMMC_ICR register *******************/
screamer 28:0e774865873d 12931 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
screamer 28:0e774865873d 12932 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12933 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
screamer 28:0e774865873d 12934 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
screamer 28:0e774865873d 12935 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12936 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
screamer 28:0e774865873d 12937 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
screamer 28:0e774865873d 12938 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12939 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
screamer 28:0e774865873d 12940 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
screamer 28:0e774865873d 12941 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12942 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
screamer 28:0e774865873d 12943 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
screamer 28:0e774865873d 12944 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12945 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
screamer 28:0e774865873d 12946 #define SDMMC_ICR_RXOVERRC_Pos (5U)
screamer 28:0e774865873d 12947 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12948 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
screamer 28:0e774865873d 12949 #define SDMMC_ICR_CMDRENDC_Pos (6U)
screamer 28:0e774865873d 12950 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12951 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
screamer 28:0e774865873d 12952 #define SDMMC_ICR_CMDSENTC_Pos (7U)
screamer 28:0e774865873d 12953 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12954 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
screamer 28:0e774865873d 12955 #define SDMMC_ICR_DATAENDC_Pos (8U)
screamer 28:0e774865873d 12956 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12957 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
screamer 28:0e774865873d 12958 #define SDMMC_ICR_STBITERRC_Pos (9U)
screamer 28:0e774865873d 12959 #define SDMMC_ICR_STBITERRC_Msk (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 12960 #define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
screamer 28:0e774865873d 12961 #define SDMMC_ICR_DBCKENDC_Pos (10U)
screamer 28:0e774865873d 12962 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12963 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
screamer 28:0e774865873d 12964 #define SDMMC_ICR_SDIOITC_Pos (22U)
screamer 28:0e774865873d 12965 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 12966 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
screamer 28:0e774865873d 12967
screamer 28:0e774865873d 12968 /****************** Bit definition for SDMMC_MASK register *******************/
screamer 28:0e774865873d 12969 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
screamer 28:0e774865873d 12970 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 12971 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
screamer 28:0e774865873d 12972 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
screamer 28:0e774865873d 12973 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 12974 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
screamer 28:0e774865873d 12975 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
screamer 28:0e774865873d 12976 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 12977 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
screamer 28:0e774865873d 12978 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
screamer 28:0e774865873d 12979 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 12980 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
screamer 28:0e774865873d 12981 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
screamer 28:0e774865873d 12982 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 12983 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
screamer 28:0e774865873d 12984 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
screamer 28:0e774865873d 12985 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 12986 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
screamer 28:0e774865873d 12987 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
screamer 28:0e774865873d 12988 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 12989 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
screamer 28:0e774865873d 12990 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
screamer 28:0e774865873d 12991 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 12992 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
screamer 28:0e774865873d 12993 #define SDMMC_MASK_DATAENDIE_Pos (8U)
screamer 28:0e774865873d 12994 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 12995 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
screamer 28:0e774865873d 12996 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
screamer 28:0e774865873d 12997 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 12998 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
screamer 28:0e774865873d 12999 #define SDMMC_MASK_CMDACTIE_Pos (11U)
screamer 28:0e774865873d 13000 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13001 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
screamer 28:0e774865873d 13002 #define SDMMC_MASK_TXACTIE_Pos (12U)
screamer 28:0e774865873d 13003 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13004 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
screamer 28:0e774865873d 13005 #define SDMMC_MASK_RXACTIE_Pos (13U)
screamer 28:0e774865873d 13006 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13007 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
screamer 28:0e774865873d 13008 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
screamer 28:0e774865873d 13009 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13010 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
screamer 28:0e774865873d 13011 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
screamer 28:0e774865873d 13012 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 13013 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
screamer 28:0e774865873d 13014 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
screamer 28:0e774865873d 13015 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13016 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
screamer 28:0e774865873d 13017 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
screamer 28:0e774865873d 13018 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 13019 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
screamer 28:0e774865873d 13020 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
screamer 28:0e774865873d 13021 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 13022 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
screamer 28:0e774865873d 13023 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
screamer 28:0e774865873d 13024 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 13025 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
screamer 28:0e774865873d 13026 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
screamer 28:0e774865873d 13027 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 13028 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
screamer 28:0e774865873d 13029 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
screamer 28:0e774865873d 13030 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 13031 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
screamer 28:0e774865873d 13032 #define SDMMC_MASK_SDIOITIE_Pos (22U)
screamer 28:0e774865873d 13033 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 13034 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
screamer 28:0e774865873d 13035
screamer 28:0e774865873d 13036 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
screamer 28:0e774865873d 13037 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
screamer 28:0e774865873d 13038 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
screamer 28:0e774865873d 13039 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
screamer 28:0e774865873d 13040
screamer 28:0e774865873d 13041 /****************** Bit definition for SDMMC_FIFO register *******************/
screamer 28:0e774865873d 13042 #define SDMMC_FIFO_FIFODATA_Pos (0U)
screamer 28:0e774865873d 13043 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13044 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
screamer 28:0e774865873d 13045
screamer 28:0e774865873d 13046 /******************************************************************************/
screamer 28:0e774865873d 13047 /* */
screamer 28:0e774865873d 13048 /* Serial Peripheral Interface (SPI) */
screamer 28:0e774865873d 13049 /* */
screamer 28:0e774865873d 13050 /******************************************************************************/
screamer 28:0e774865873d 13051 /******************* Bit definition for SPI_CR1 register ********************/
screamer 28:0e774865873d 13052 #define SPI_CR1_CPHA_Pos (0U)
screamer 28:0e774865873d 13053 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13054 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
screamer 28:0e774865873d 13055 #define SPI_CR1_CPOL_Pos (1U)
screamer 28:0e774865873d 13056 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13057 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
screamer 28:0e774865873d 13058 #define SPI_CR1_MSTR_Pos (2U)
screamer 28:0e774865873d 13059 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13060 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
screamer 28:0e774865873d 13061
screamer 28:0e774865873d 13062 #define SPI_CR1_BR_Pos (3U)
screamer 28:0e774865873d 13063 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
screamer 28:0e774865873d 13064 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
screamer 28:0e774865873d 13065 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13066 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13067 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13068
screamer 28:0e774865873d 13069 #define SPI_CR1_SPE_Pos (6U)
screamer 28:0e774865873d 13070 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13071 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
screamer 28:0e774865873d 13072 #define SPI_CR1_LSBFIRST_Pos (7U)
screamer 28:0e774865873d 13073 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13074 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
screamer 28:0e774865873d 13075 #define SPI_CR1_SSI_Pos (8U)
screamer 28:0e774865873d 13076 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13077 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
screamer 28:0e774865873d 13078 #define SPI_CR1_SSM_Pos (9U)
screamer 28:0e774865873d 13079 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13080 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
screamer 28:0e774865873d 13081 #define SPI_CR1_RXONLY_Pos (10U)
screamer 28:0e774865873d 13082 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13083 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
screamer 28:0e774865873d 13084 #define SPI_CR1_CRCL_Pos (11U)
screamer 28:0e774865873d 13085 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13086 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
screamer 28:0e774865873d 13087 #define SPI_CR1_CRCNEXT_Pos (12U)
screamer 28:0e774865873d 13088 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13089 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
screamer 28:0e774865873d 13090 #define SPI_CR1_CRCEN_Pos (13U)
screamer 28:0e774865873d 13091 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13092 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
screamer 28:0e774865873d 13093 #define SPI_CR1_BIDIOE_Pos (14U)
screamer 28:0e774865873d 13094 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13095 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
screamer 28:0e774865873d 13096 #define SPI_CR1_BIDIMODE_Pos (15U)
screamer 28:0e774865873d 13097 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 13098 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
screamer 28:0e774865873d 13099
screamer 28:0e774865873d 13100 /******************* Bit definition for SPI_CR2 register ********************/
screamer 28:0e774865873d 13101 #define SPI_CR2_RXDMAEN_Pos (0U)
screamer 28:0e774865873d 13102 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13103 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
screamer 28:0e774865873d 13104 #define SPI_CR2_TXDMAEN_Pos (1U)
screamer 28:0e774865873d 13105 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13106 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
screamer 28:0e774865873d 13107 #define SPI_CR2_SSOE_Pos (2U)
screamer 28:0e774865873d 13108 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13109 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
screamer 28:0e774865873d 13110 #define SPI_CR2_NSSP_Pos (3U)
screamer 28:0e774865873d 13111 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13112 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
screamer 28:0e774865873d 13113 #define SPI_CR2_FRF_Pos (4U)
screamer 28:0e774865873d 13114 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13115 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
screamer 28:0e774865873d 13116 #define SPI_CR2_ERRIE_Pos (5U)
screamer 28:0e774865873d 13117 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13118 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
screamer 28:0e774865873d 13119 #define SPI_CR2_RXNEIE_Pos (6U)
screamer 28:0e774865873d 13120 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13121 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
screamer 28:0e774865873d 13122 #define SPI_CR2_TXEIE_Pos (7U)
screamer 28:0e774865873d 13123 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13124 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
screamer 28:0e774865873d 13125 #define SPI_CR2_DS_Pos (8U)
screamer 28:0e774865873d 13126 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 13127 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
screamer 28:0e774865873d 13128 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13129 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13130 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13131 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13132 #define SPI_CR2_FRXTH_Pos (12U)
screamer 28:0e774865873d 13133 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13134 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
screamer 28:0e774865873d 13135 #define SPI_CR2_LDMARX_Pos (13U)
screamer 28:0e774865873d 13136 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13137 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
screamer 28:0e774865873d 13138 #define SPI_CR2_LDMATX_Pos (14U)
screamer 28:0e774865873d 13139 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13140 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
screamer 28:0e774865873d 13141
screamer 28:0e774865873d 13142 /******************** Bit definition for SPI_SR register ********************/
screamer 28:0e774865873d 13143 #define SPI_SR_RXNE_Pos (0U)
screamer 28:0e774865873d 13144 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13145 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
screamer 28:0e774865873d 13146 #define SPI_SR_TXE_Pos (1U)
screamer 28:0e774865873d 13147 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13148 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
screamer 28:0e774865873d 13149 #define SPI_SR_CHSIDE_Pos (2U)
screamer 28:0e774865873d 13150 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13151 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
screamer 28:0e774865873d 13152 #define SPI_SR_UDR_Pos (3U)
screamer 28:0e774865873d 13153 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13154 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
screamer 28:0e774865873d 13155 #define SPI_SR_CRCERR_Pos (4U)
screamer 28:0e774865873d 13156 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13157 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
screamer 28:0e774865873d 13158 #define SPI_SR_MODF_Pos (5U)
screamer 28:0e774865873d 13159 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13160 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
screamer 28:0e774865873d 13161 #define SPI_SR_OVR_Pos (6U)
screamer 28:0e774865873d 13162 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13163 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
screamer 28:0e774865873d 13164 #define SPI_SR_BSY_Pos (7U)
screamer 28:0e774865873d 13165 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13166 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
screamer 28:0e774865873d 13167 #define SPI_SR_FRE_Pos (8U)
screamer 28:0e774865873d 13168 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13169 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
screamer 28:0e774865873d 13170 #define SPI_SR_FRLVL_Pos (9U)
screamer 28:0e774865873d 13171 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
screamer 28:0e774865873d 13172 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
screamer 28:0e774865873d 13173 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13174 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13175 #define SPI_SR_FTLVL_Pos (11U)
screamer 28:0e774865873d 13176 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
screamer 28:0e774865873d 13177 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
screamer 28:0e774865873d 13178 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13179 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13180
screamer 28:0e774865873d 13181 /******************** Bit definition for SPI_DR register ********************/
screamer 28:0e774865873d 13182 #define SPI_DR_DR_Pos (0U)
screamer 28:0e774865873d 13183 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 13184 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
screamer 28:0e774865873d 13185
screamer 28:0e774865873d 13186 /******************* Bit definition for SPI_CRCPR register ******************/
screamer 28:0e774865873d 13187 #define SPI_CRCPR_CRCPOLY_Pos (0U)
screamer 28:0e774865873d 13188 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 13189 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
screamer 28:0e774865873d 13190
screamer 28:0e774865873d 13191 /****************** Bit definition for SPI_RXCRCR register ******************/
screamer 28:0e774865873d 13192 #define SPI_RXCRCR_RXCRC_Pos (0U)
screamer 28:0e774865873d 13193 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 13194 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
screamer 28:0e774865873d 13195
screamer 28:0e774865873d 13196 /****************** Bit definition for SPI_TXCRCR register ******************/
screamer 28:0e774865873d 13197 #define SPI_TXCRCR_TXCRC_Pos (0U)
screamer 28:0e774865873d 13198 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 13199 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
screamer 28:0e774865873d 13200
screamer 28:0e774865873d 13201 /******************************************************************************/
screamer 28:0e774865873d 13202 /* */
screamer 28:0e774865873d 13203 /* QUADSPI */
screamer 28:0e774865873d 13204 /* */
screamer 28:0e774865873d 13205 /******************************************************************************/
screamer 28:0e774865873d 13206 /***************** Bit definition for QUADSPI_CR register *******************/
screamer 28:0e774865873d 13207 #define QUADSPI_CR_EN_Pos (0U)
screamer 28:0e774865873d 13208 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13209 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
screamer 28:0e774865873d 13210 #define QUADSPI_CR_ABORT_Pos (1U)
screamer 28:0e774865873d 13211 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13212 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
screamer 28:0e774865873d 13213 #define QUADSPI_CR_DMAEN_Pos (2U)
screamer 28:0e774865873d 13214 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13215 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
screamer 28:0e774865873d 13216 #define QUADSPI_CR_TCEN_Pos (3U)
screamer 28:0e774865873d 13217 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13218 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
screamer 28:0e774865873d 13219 #define QUADSPI_CR_SSHIFT_Pos (4U)
screamer 28:0e774865873d 13220 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13221 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
screamer 28:0e774865873d 13222 #define QUADSPI_CR_FTHRES_Pos (8U)
screamer 28:0e774865873d 13223 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 13224 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
screamer 28:0e774865873d 13225 #define QUADSPI_CR_TEIE_Pos (16U)
screamer 28:0e774865873d 13226 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13227 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
screamer 28:0e774865873d 13228 #define QUADSPI_CR_TCIE_Pos (17U)
screamer 28:0e774865873d 13229 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 13230 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
screamer 28:0e774865873d 13231 #define QUADSPI_CR_FTIE_Pos (18U)
screamer 28:0e774865873d 13232 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 13233 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
screamer 28:0e774865873d 13234 #define QUADSPI_CR_SMIE_Pos (19U)
screamer 28:0e774865873d 13235 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 13236 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
screamer 28:0e774865873d 13237 #define QUADSPI_CR_TOIE_Pos (20U)
screamer 28:0e774865873d 13238 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 13239 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
screamer 28:0e774865873d 13240 #define QUADSPI_CR_APMS_Pos (22U)
screamer 28:0e774865873d 13241 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 13242 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
screamer 28:0e774865873d 13243 #define QUADSPI_CR_PMM_Pos (23U)
screamer 28:0e774865873d 13244 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 13245 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
screamer 28:0e774865873d 13246 #define QUADSPI_CR_PRESCALER_Pos (24U)
screamer 28:0e774865873d 13247 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 13248 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
screamer 28:0e774865873d 13249
screamer 28:0e774865873d 13250 /***************** Bit definition for QUADSPI_DCR register ******************/
screamer 28:0e774865873d 13251 #define QUADSPI_DCR_CKMODE_Pos (0U)
screamer 28:0e774865873d 13252 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13253 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
screamer 28:0e774865873d 13254 #define QUADSPI_DCR_CSHT_Pos (8U)
screamer 28:0e774865873d 13255 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 13256 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
screamer 28:0e774865873d 13257 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13258 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13259 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13260 #define QUADSPI_DCR_FSIZE_Pos (16U)
screamer 28:0e774865873d 13261 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
screamer 28:0e774865873d 13262 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
screamer 28:0e774865873d 13263
screamer 28:0e774865873d 13264 /****************** Bit definition for QUADSPI_SR register *******************/
screamer 28:0e774865873d 13265 #define QUADSPI_SR_TEF_Pos (0U)
screamer 28:0e774865873d 13266 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13267 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
screamer 28:0e774865873d 13268 #define QUADSPI_SR_TCF_Pos (1U)
screamer 28:0e774865873d 13269 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13270 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
screamer 28:0e774865873d 13271 #define QUADSPI_SR_FTF_Pos (2U)
screamer 28:0e774865873d 13272 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13273 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
screamer 28:0e774865873d 13274 #define QUADSPI_SR_SMF_Pos (3U)
screamer 28:0e774865873d 13275 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13276 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
screamer 28:0e774865873d 13277 #define QUADSPI_SR_TOF_Pos (4U)
screamer 28:0e774865873d 13278 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13279 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
screamer 28:0e774865873d 13280 #define QUADSPI_SR_BUSY_Pos (5U)
screamer 28:0e774865873d 13281 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13282 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
screamer 28:0e774865873d 13283 #define QUADSPI_SR_FLEVEL_Pos (8U)
screamer 28:0e774865873d 13284 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 13285 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
screamer 28:0e774865873d 13286
screamer 28:0e774865873d 13287 /****************** Bit definition for QUADSPI_FCR register ******************/
screamer 28:0e774865873d 13288 #define QUADSPI_FCR_CTEF_Pos (0U)
screamer 28:0e774865873d 13289 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13290 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
screamer 28:0e774865873d 13291 #define QUADSPI_FCR_CTCF_Pos (1U)
screamer 28:0e774865873d 13292 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13293 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
screamer 28:0e774865873d 13294 #define QUADSPI_FCR_CSMF_Pos (3U)
screamer 28:0e774865873d 13295 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13296 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
screamer 28:0e774865873d 13297 #define QUADSPI_FCR_CTOF_Pos (4U)
screamer 28:0e774865873d 13298 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13299 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
screamer 28:0e774865873d 13300
screamer 28:0e774865873d 13301 /****************** Bit definition for QUADSPI_DLR register ******************/
screamer 28:0e774865873d 13302 #define QUADSPI_DLR_DL_Pos (0U)
screamer 28:0e774865873d 13303 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13304 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
screamer 28:0e774865873d 13305
screamer 28:0e774865873d 13306 /****************** Bit definition for QUADSPI_CCR register ******************/
screamer 28:0e774865873d 13307 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
screamer 28:0e774865873d 13308 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 13309 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
screamer 28:0e774865873d 13310 #define QUADSPI_CCR_IMODE_Pos (8U)
screamer 28:0e774865873d 13311 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 13312 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
screamer 28:0e774865873d 13313 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13314 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13315 #define QUADSPI_CCR_ADMODE_Pos (10U)
screamer 28:0e774865873d 13316 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 13317 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
screamer 28:0e774865873d 13318 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13319 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13320 #define QUADSPI_CCR_ADSIZE_Pos (12U)
screamer 28:0e774865873d 13321 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 13322 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
screamer 28:0e774865873d 13323 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13324 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13325 #define QUADSPI_CCR_ABMODE_Pos (14U)
screamer 28:0e774865873d 13326 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 13327 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
screamer 28:0e774865873d 13328 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13329 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 13330 #define QUADSPI_CCR_ABSIZE_Pos (16U)
screamer 28:0e774865873d 13331 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 13332 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
screamer 28:0e774865873d 13333 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13334 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 13335 #define QUADSPI_CCR_DCYC_Pos (18U)
screamer 28:0e774865873d 13336 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
screamer 28:0e774865873d 13337 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
screamer 28:0e774865873d 13338 #define QUADSPI_CCR_DMODE_Pos (24U)
screamer 28:0e774865873d 13339 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 13340 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
screamer 28:0e774865873d 13341 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 13342 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 13343 #define QUADSPI_CCR_FMODE_Pos (26U)
screamer 28:0e774865873d 13344 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
screamer 28:0e774865873d 13345 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
screamer 28:0e774865873d 13346 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 13347 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 13348 #define QUADSPI_CCR_SIOO_Pos (28U)
screamer 28:0e774865873d 13349 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 13350 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
screamer 28:0e774865873d 13351 #define QUADSPI_CCR_DDRM_Pos (31U)
screamer 28:0e774865873d 13352 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 13353 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
screamer 28:0e774865873d 13354
screamer 28:0e774865873d 13355 /****************** Bit definition for QUADSPI_AR register *******************/
screamer 28:0e774865873d 13356 #define QUADSPI_AR_ADDRESS_Pos (0U)
screamer 28:0e774865873d 13357 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13358 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
screamer 28:0e774865873d 13359
screamer 28:0e774865873d 13360 /****************** Bit definition for QUADSPI_ABR register ******************/
screamer 28:0e774865873d 13361 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
screamer 28:0e774865873d 13362 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13363 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
screamer 28:0e774865873d 13364
screamer 28:0e774865873d 13365 /****************** Bit definition for QUADSPI_DR register *******************/
screamer 28:0e774865873d 13366 #define QUADSPI_DR_DATA_Pos (0U)
screamer 28:0e774865873d 13367 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13368 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
screamer 28:0e774865873d 13369
screamer 28:0e774865873d 13370 /****************** Bit definition for QUADSPI_PSMKR register ****************/
screamer 28:0e774865873d 13371 #define QUADSPI_PSMKR_MASK_Pos (0U)
screamer 28:0e774865873d 13372 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13373 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
screamer 28:0e774865873d 13374
screamer 28:0e774865873d 13375 /****************** Bit definition for QUADSPI_PSMAR register ****************/
screamer 28:0e774865873d 13376 #define QUADSPI_PSMAR_MATCH_Pos (0U)
screamer 28:0e774865873d 13377 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 13378 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
screamer 28:0e774865873d 13379
screamer 28:0e774865873d 13380 /****************** Bit definition for QUADSPI_PIR register *****************/
screamer 28:0e774865873d 13381 #define QUADSPI_PIR_INTERVAL_Pos (0U)
screamer 28:0e774865873d 13382 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 13383 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
screamer 28:0e774865873d 13384
screamer 28:0e774865873d 13385 /****************** Bit definition for QUADSPI_LPTR register *****************/
screamer 28:0e774865873d 13386 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
screamer 28:0e774865873d 13387 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 13388 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
screamer 28:0e774865873d 13389
screamer 28:0e774865873d 13390 /******************************************************************************/
screamer 28:0e774865873d 13391 /* */
screamer 28:0e774865873d 13392 /* SYSCFG */
screamer 28:0e774865873d 13393 /* */
screamer 28:0e774865873d 13394 /******************************************************************************/
screamer 28:0e774865873d 13395 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
screamer 28:0e774865873d 13396 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
screamer 28:0e774865873d 13397 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 13398 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
screamer 28:0e774865873d 13399 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13400 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13401 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13402
screamer 28:0e774865873d 13403 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
screamer 28:0e774865873d 13404 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13405 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
screamer 28:0e774865873d 13406
screamer 28:0e774865873d 13407 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
screamer 28:0e774865873d 13408 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
screamer 28:0e774865873d 13409 #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13410 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
screamer 28:0e774865873d 13411 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
screamer 28:0e774865873d 13412 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13413 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
screamer 28:0e774865873d 13414 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
screamer 28:0e774865873d 13415 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13416 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
screamer 28:0e774865873d 13417 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
screamer 28:0e774865873d 13418 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 13419 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
screamer 28:0e774865873d 13420 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
screamer 28:0e774865873d 13421 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 13422 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
screamer 28:0e774865873d 13423 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
screamer 28:0e774865873d 13424 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 13425 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
screamer 28:0e774865873d 13426 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
screamer 28:0e774865873d 13427 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 13428 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
screamer 28:0e774865873d 13429 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
screamer 28:0e774865873d 13430 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 13431 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
screamer 28:0e774865873d 13432 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
screamer 28:0e774865873d 13433 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 13434 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
screamer 28:0e774865873d 13435 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
screamer 28:0e774865873d 13436 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
screamer 28:0e774865873d 13437 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
screamer 28:0e774865873d 13438 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
screamer 28:0e774865873d 13439 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
screamer 28:0e774865873d 13440 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
screamer 28:0e774865873d 13441
screamer 28:0e774865873d 13442 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
screamer 28:0e774865873d 13443 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
screamer 28:0e774865873d 13444 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 13445 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
screamer 28:0e774865873d 13446 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
screamer 28:0e774865873d 13447 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 13448 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
screamer 28:0e774865873d 13449 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
screamer 28:0e774865873d 13450 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 13451 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
screamer 28:0e774865873d 13452 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
screamer 28:0e774865873d 13453 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 13454 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
screamer 28:0e774865873d 13455
screamer 28:0e774865873d 13456 /**
screamer 28:0e774865873d 13457 * @brief EXTI0 configuration
screamer 28:0e774865873d 13458 */
screamer 28:0e774865873d 13459 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
screamer 28:0e774865873d 13460 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
screamer 28:0e774865873d 13461 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
screamer 28:0e774865873d 13462 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
screamer 28:0e774865873d 13463 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
screamer 28:0e774865873d 13464 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
screamer 28:0e774865873d 13465 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
screamer 28:0e774865873d 13466 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
screamer 28:0e774865873d 13467
screamer 28:0e774865873d 13468 /**
screamer 28:0e774865873d 13469 * @brief EXTI1 configuration
screamer 28:0e774865873d 13470 */
screamer 28:0e774865873d 13471 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
screamer 28:0e774865873d 13472 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
screamer 28:0e774865873d 13473 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
screamer 28:0e774865873d 13474 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
screamer 28:0e774865873d 13475 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
screamer 28:0e774865873d 13476 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
screamer 28:0e774865873d 13477 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
screamer 28:0e774865873d 13478 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
screamer 28:0e774865873d 13479
screamer 28:0e774865873d 13480 /**
screamer 28:0e774865873d 13481 * @brief EXTI2 configuration
screamer 28:0e774865873d 13482 */
screamer 28:0e774865873d 13483 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
screamer 28:0e774865873d 13484 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
screamer 28:0e774865873d 13485 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
screamer 28:0e774865873d 13486 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
screamer 28:0e774865873d 13487 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
screamer 28:0e774865873d 13488 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
screamer 28:0e774865873d 13489 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
screamer 28:0e774865873d 13490
screamer 28:0e774865873d 13491 /**
screamer 28:0e774865873d 13492 * @brief EXTI3 configuration
screamer 28:0e774865873d 13493 */
screamer 28:0e774865873d 13494 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
screamer 28:0e774865873d 13495 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
screamer 28:0e774865873d 13496 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
screamer 28:0e774865873d 13497 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
screamer 28:0e774865873d 13498 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
screamer 28:0e774865873d 13499 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
screamer 28:0e774865873d 13500 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
screamer 28:0e774865873d 13501
screamer 28:0e774865873d 13502 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
screamer 28:0e774865873d 13503 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
screamer 28:0e774865873d 13504 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 13505 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
screamer 28:0e774865873d 13506 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
screamer 28:0e774865873d 13507 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 13508 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
screamer 28:0e774865873d 13509 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
screamer 28:0e774865873d 13510 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 13511 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
screamer 28:0e774865873d 13512 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
screamer 28:0e774865873d 13513 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 13514 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
screamer 28:0e774865873d 13515 /**
screamer 28:0e774865873d 13516 * @brief EXTI4 configuration
screamer 28:0e774865873d 13517 */
screamer 28:0e774865873d 13518 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
screamer 28:0e774865873d 13519 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
screamer 28:0e774865873d 13520 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
screamer 28:0e774865873d 13521 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
screamer 28:0e774865873d 13522 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
screamer 28:0e774865873d 13523 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
screamer 28:0e774865873d 13524 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
screamer 28:0e774865873d 13525
screamer 28:0e774865873d 13526 /**
screamer 28:0e774865873d 13527 * @brief EXTI5 configuration
screamer 28:0e774865873d 13528 */
screamer 28:0e774865873d 13529 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
screamer 28:0e774865873d 13530 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
screamer 28:0e774865873d 13531 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
screamer 28:0e774865873d 13532 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
screamer 28:0e774865873d 13533 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
screamer 28:0e774865873d 13534 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
screamer 28:0e774865873d 13535 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
screamer 28:0e774865873d 13536
screamer 28:0e774865873d 13537 /**
screamer 28:0e774865873d 13538 * @brief EXTI6 configuration
screamer 28:0e774865873d 13539 */
screamer 28:0e774865873d 13540 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
screamer 28:0e774865873d 13541 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
screamer 28:0e774865873d 13542 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
screamer 28:0e774865873d 13543 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
screamer 28:0e774865873d 13544 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
screamer 28:0e774865873d 13545 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
screamer 28:0e774865873d 13546 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
screamer 28:0e774865873d 13547
screamer 28:0e774865873d 13548 /**
screamer 28:0e774865873d 13549 * @brief EXTI7 configuration
screamer 28:0e774865873d 13550 */
screamer 28:0e774865873d 13551 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
screamer 28:0e774865873d 13552 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
screamer 28:0e774865873d 13553 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
screamer 28:0e774865873d 13554 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
screamer 28:0e774865873d 13555 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
screamer 28:0e774865873d 13556 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
screamer 28:0e774865873d 13557 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
screamer 28:0e774865873d 13558
screamer 28:0e774865873d 13559 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
screamer 28:0e774865873d 13560 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
screamer 28:0e774865873d 13561 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 13562 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
screamer 28:0e774865873d 13563 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
screamer 28:0e774865873d 13564 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 13565 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
screamer 28:0e774865873d 13566 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
screamer 28:0e774865873d 13567 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 13568 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
screamer 28:0e774865873d 13569 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
screamer 28:0e774865873d 13570 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 13571 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
screamer 28:0e774865873d 13572
screamer 28:0e774865873d 13573 /**
screamer 28:0e774865873d 13574 * @brief EXTI8 configuration
screamer 28:0e774865873d 13575 */
screamer 28:0e774865873d 13576 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
screamer 28:0e774865873d 13577 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
screamer 28:0e774865873d 13578 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
screamer 28:0e774865873d 13579 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
screamer 28:0e774865873d 13580 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
screamer 28:0e774865873d 13581 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
screamer 28:0e774865873d 13582 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
screamer 28:0e774865873d 13583
screamer 28:0e774865873d 13584 /**
screamer 28:0e774865873d 13585 * @brief EXTI9 configuration
screamer 28:0e774865873d 13586 */
screamer 28:0e774865873d 13587 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
screamer 28:0e774865873d 13588 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
screamer 28:0e774865873d 13589 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
screamer 28:0e774865873d 13590 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
screamer 28:0e774865873d 13591 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
screamer 28:0e774865873d 13592 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
screamer 28:0e774865873d 13593 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
screamer 28:0e774865873d 13594
screamer 28:0e774865873d 13595 /**
screamer 28:0e774865873d 13596 * @brief EXTI10 configuration
screamer 28:0e774865873d 13597 */
screamer 28:0e774865873d 13598 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
screamer 28:0e774865873d 13599 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
screamer 28:0e774865873d 13600 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
screamer 28:0e774865873d 13601 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
screamer 28:0e774865873d 13602 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
screamer 28:0e774865873d 13603 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
screamer 28:0e774865873d 13604 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
screamer 28:0e774865873d 13605
screamer 28:0e774865873d 13606 /**
screamer 28:0e774865873d 13607 * @brief EXTI11 configuration
screamer 28:0e774865873d 13608 */
screamer 28:0e774865873d 13609 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
screamer 28:0e774865873d 13610 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
screamer 28:0e774865873d 13611 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
screamer 28:0e774865873d 13612 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
screamer 28:0e774865873d 13613 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
screamer 28:0e774865873d 13614 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
screamer 28:0e774865873d 13615 #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
screamer 28:0e774865873d 13616
screamer 28:0e774865873d 13617 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
screamer 28:0e774865873d 13618 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
screamer 28:0e774865873d 13619 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 13620 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
screamer 28:0e774865873d 13621 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
screamer 28:0e774865873d 13622 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 13623 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
screamer 28:0e774865873d 13624 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
screamer 28:0e774865873d 13625 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
screamer 28:0e774865873d 13626 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
screamer 28:0e774865873d 13627 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
screamer 28:0e774865873d 13628 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 13629 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
screamer 28:0e774865873d 13630
screamer 28:0e774865873d 13631 /**
screamer 28:0e774865873d 13632 * @brief EXTI12 configuration
screamer 28:0e774865873d 13633 */
screamer 28:0e774865873d 13634 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
screamer 28:0e774865873d 13635 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
screamer 28:0e774865873d 13636 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
screamer 28:0e774865873d 13637 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
screamer 28:0e774865873d 13638 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
screamer 28:0e774865873d 13639 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
screamer 28:0e774865873d 13640 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
screamer 28:0e774865873d 13641
screamer 28:0e774865873d 13642 /**
screamer 28:0e774865873d 13643 * @brief EXTI13 configuration
screamer 28:0e774865873d 13644 */
screamer 28:0e774865873d 13645 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
screamer 28:0e774865873d 13646 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
screamer 28:0e774865873d 13647 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
screamer 28:0e774865873d 13648 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
screamer 28:0e774865873d 13649 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
screamer 28:0e774865873d 13650 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
screamer 28:0e774865873d 13651 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
screamer 28:0e774865873d 13652
screamer 28:0e774865873d 13653 /**
screamer 28:0e774865873d 13654 * @brief EXTI14 configuration
screamer 28:0e774865873d 13655 */
screamer 28:0e774865873d 13656 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
screamer 28:0e774865873d 13657 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
screamer 28:0e774865873d 13658 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
screamer 28:0e774865873d 13659 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
screamer 28:0e774865873d 13660 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
screamer 28:0e774865873d 13661 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
screamer 28:0e774865873d 13662 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
screamer 28:0e774865873d 13663
screamer 28:0e774865873d 13664 /**
screamer 28:0e774865873d 13665 * @brief EXTI15 configuration
screamer 28:0e774865873d 13666 */
screamer 28:0e774865873d 13667 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
screamer 28:0e774865873d 13668 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
screamer 28:0e774865873d 13669 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
screamer 28:0e774865873d 13670 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
screamer 28:0e774865873d 13671 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
screamer 28:0e774865873d 13672 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
screamer 28:0e774865873d 13673 #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
screamer 28:0e774865873d 13674
screamer 28:0e774865873d 13675 /****************** Bit definition for SYSCFG_SCSR register ****************/
screamer 28:0e774865873d 13676 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
screamer 28:0e774865873d 13677 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13678 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
screamer 28:0e774865873d 13679 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
screamer 28:0e774865873d 13680 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13681 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
screamer 28:0e774865873d 13682
screamer 28:0e774865873d 13683 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
screamer 28:0e774865873d 13684 #define SYSCFG_CFGR2_CLL_Pos (0U)
screamer 28:0e774865873d 13685 #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13686 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
screamer 28:0e774865873d 13687 #define SYSCFG_CFGR2_SPL_Pos (1U)
screamer 28:0e774865873d 13688 #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13689 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
screamer 28:0e774865873d 13690 #define SYSCFG_CFGR2_PVDL_Pos (2U)
screamer 28:0e774865873d 13691 #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13692 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
screamer 28:0e774865873d 13693 #define SYSCFG_CFGR2_ECCL_Pos (3U)
screamer 28:0e774865873d 13694 #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13695 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
screamer 28:0e774865873d 13696 #define SYSCFG_CFGR2_SPF_Pos (8U)
screamer 28:0e774865873d 13697 #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13698 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
screamer 28:0e774865873d 13699
screamer 28:0e774865873d 13700 /****************** Bit definition for SYSCFG_SWPR register ****************/
screamer 28:0e774865873d 13701 #define SYSCFG_SWPR_PAGE0_Pos (0U)
screamer 28:0e774865873d 13702 #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13703 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
screamer 28:0e774865873d 13704 #define SYSCFG_SWPR_PAGE1_Pos (1U)
screamer 28:0e774865873d 13705 #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13706 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
screamer 28:0e774865873d 13707 #define SYSCFG_SWPR_PAGE2_Pos (2U)
screamer 28:0e774865873d 13708 #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13709 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
screamer 28:0e774865873d 13710 #define SYSCFG_SWPR_PAGE3_Pos (3U)
screamer 28:0e774865873d 13711 #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13712 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
screamer 28:0e774865873d 13713 #define SYSCFG_SWPR_PAGE4_Pos (4U)
screamer 28:0e774865873d 13714 #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13715 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
screamer 28:0e774865873d 13716 #define SYSCFG_SWPR_PAGE5_Pos (5U)
screamer 28:0e774865873d 13717 #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13718 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
screamer 28:0e774865873d 13719 #define SYSCFG_SWPR_PAGE6_Pos (6U)
screamer 28:0e774865873d 13720 #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13721 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
screamer 28:0e774865873d 13722 #define SYSCFG_SWPR_PAGE7_Pos (7U)
screamer 28:0e774865873d 13723 #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13724 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
screamer 28:0e774865873d 13725 #define SYSCFG_SWPR_PAGE8_Pos (8U)
screamer 28:0e774865873d 13726 #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13727 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
screamer 28:0e774865873d 13728 #define SYSCFG_SWPR_PAGE9_Pos (9U)
screamer 28:0e774865873d 13729 #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13730 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
screamer 28:0e774865873d 13731 #define SYSCFG_SWPR_PAGE10_Pos (10U)
screamer 28:0e774865873d 13732 #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13733 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
screamer 28:0e774865873d 13734 #define SYSCFG_SWPR_PAGE11_Pos (11U)
screamer 28:0e774865873d 13735 #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13736 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
screamer 28:0e774865873d 13737 #define SYSCFG_SWPR_PAGE12_Pos (12U)
screamer 28:0e774865873d 13738 #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13739 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
screamer 28:0e774865873d 13740 #define SYSCFG_SWPR_PAGE13_Pos (13U)
screamer 28:0e774865873d 13741 #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13742 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
screamer 28:0e774865873d 13743 #define SYSCFG_SWPR_PAGE14_Pos (14U)
screamer 28:0e774865873d 13744 #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13745 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
screamer 28:0e774865873d 13746 #define SYSCFG_SWPR_PAGE15_Pos (15U)
screamer 28:0e774865873d 13747 #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 13748 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
screamer 28:0e774865873d 13749 #define SYSCFG_SWPR_PAGE16_Pos (16U)
screamer 28:0e774865873d 13750 #define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13751 #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
screamer 28:0e774865873d 13752 #define SYSCFG_SWPR_PAGE17_Pos (17U)
screamer 28:0e774865873d 13753 #define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 13754 #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
screamer 28:0e774865873d 13755 #define SYSCFG_SWPR_PAGE18_Pos (18U)
screamer 28:0e774865873d 13756 #define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 13757 #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
screamer 28:0e774865873d 13758 #define SYSCFG_SWPR_PAGE19_Pos (19U)
screamer 28:0e774865873d 13759 #define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 13760 #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
screamer 28:0e774865873d 13761 #define SYSCFG_SWPR_PAGE20_Pos (20U)
screamer 28:0e774865873d 13762 #define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 13763 #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
screamer 28:0e774865873d 13764 #define SYSCFG_SWPR_PAGE21_Pos (21U)
screamer 28:0e774865873d 13765 #define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 13766 #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
screamer 28:0e774865873d 13767 #define SYSCFG_SWPR_PAGE22_Pos (22U)
screamer 28:0e774865873d 13768 #define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 13769 #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
screamer 28:0e774865873d 13770 #define SYSCFG_SWPR_PAGE23_Pos (23U)
screamer 28:0e774865873d 13771 #define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 13772 #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
screamer 28:0e774865873d 13773 #define SYSCFG_SWPR_PAGE24_Pos (24U)
screamer 28:0e774865873d 13774 #define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 13775 #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
screamer 28:0e774865873d 13776 #define SYSCFG_SWPR_PAGE25_Pos (25U)
screamer 28:0e774865873d 13777 #define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 13778 #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
screamer 28:0e774865873d 13779 #define SYSCFG_SWPR_PAGE26_Pos (26U)
screamer 28:0e774865873d 13780 #define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 13781 #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
screamer 28:0e774865873d 13782 #define SYSCFG_SWPR_PAGE27_Pos (27U)
screamer 28:0e774865873d 13783 #define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 13784 #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
screamer 28:0e774865873d 13785 #define SYSCFG_SWPR_PAGE28_Pos (28U)
screamer 28:0e774865873d 13786 #define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 13787 #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
screamer 28:0e774865873d 13788 #define SYSCFG_SWPR_PAGE29_Pos (29U)
screamer 28:0e774865873d 13789 #define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 13790 #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
screamer 28:0e774865873d 13791 #define SYSCFG_SWPR_PAGE30_Pos (30U)
screamer 28:0e774865873d 13792 #define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 13793 #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
screamer 28:0e774865873d 13794 #define SYSCFG_SWPR_PAGE31_Pos (31U)
screamer 28:0e774865873d 13795 #define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 13796 #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
screamer 28:0e774865873d 13797
screamer 28:0e774865873d 13798 /****************** Bit definition for SYSCFG_SKR register ****************/
screamer 28:0e774865873d 13799 #define SYSCFG_SKR_KEY_Pos (0U)
screamer 28:0e774865873d 13800 #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 13801 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
screamer 28:0e774865873d 13802
screamer 28:0e774865873d 13803
screamer 28:0e774865873d 13804
screamer 28:0e774865873d 13805
screamer 28:0e774865873d 13806 /******************************************************************************/
screamer 28:0e774865873d 13807 /* */
screamer 28:0e774865873d 13808 /* TIM */
screamer 28:0e774865873d 13809 /* */
screamer 28:0e774865873d 13810 /******************************************************************************/
screamer 28:0e774865873d 13811 /******************* Bit definition for TIM_CR1 register ********************/
screamer 28:0e774865873d 13812 #define TIM_CR1_CEN_Pos (0U)
screamer 28:0e774865873d 13813 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13814 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
screamer 28:0e774865873d 13815 #define TIM_CR1_UDIS_Pos (1U)
screamer 28:0e774865873d 13816 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13817 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
screamer 28:0e774865873d 13818 #define TIM_CR1_URS_Pos (2U)
screamer 28:0e774865873d 13819 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13820 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
screamer 28:0e774865873d 13821 #define TIM_CR1_OPM_Pos (3U)
screamer 28:0e774865873d 13822 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13823 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
screamer 28:0e774865873d 13824 #define TIM_CR1_DIR_Pos (4U)
screamer 28:0e774865873d 13825 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13826 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
screamer 28:0e774865873d 13827
screamer 28:0e774865873d 13828 #define TIM_CR1_CMS_Pos (5U)
screamer 28:0e774865873d 13829 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
screamer 28:0e774865873d 13830 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
screamer 28:0e774865873d 13831 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13832 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13833
screamer 28:0e774865873d 13834 #define TIM_CR1_ARPE_Pos (7U)
screamer 28:0e774865873d 13835 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13836 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
screamer 28:0e774865873d 13837
screamer 28:0e774865873d 13838 #define TIM_CR1_CKD_Pos (8U)
screamer 28:0e774865873d 13839 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 13840 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
screamer 28:0e774865873d 13841 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13842 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13843
screamer 28:0e774865873d 13844 #define TIM_CR1_UIFREMAP_Pos (11U)
screamer 28:0e774865873d 13845 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13846 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
screamer 28:0e774865873d 13847
screamer 28:0e774865873d 13848 /******************* Bit definition for TIM_CR2 register ********************/
screamer 28:0e774865873d 13849 #define TIM_CR2_CCPC_Pos (0U)
screamer 28:0e774865873d 13850 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13851 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
screamer 28:0e774865873d 13852 #define TIM_CR2_CCUS_Pos (2U)
screamer 28:0e774865873d 13853 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13854 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
screamer 28:0e774865873d 13855 #define TIM_CR2_CCDS_Pos (3U)
screamer 28:0e774865873d 13856 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13857 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
screamer 28:0e774865873d 13858
screamer 28:0e774865873d 13859 #define TIM_CR2_MMS_Pos (4U)
screamer 28:0e774865873d 13860 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 13861 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
screamer 28:0e774865873d 13862 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13863 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13864 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13865
screamer 28:0e774865873d 13866 #define TIM_CR2_TI1S_Pos (7U)
screamer 28:0e774865873d 13867 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13868 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
screamer 28:0e774865873d 13869 #define TIM_CR2_OIS1_Pos (8U)
screamer 28:0e774865873d 13870 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13871 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
screamer 28:0e774865873d 13872 #define TIM_CR2_OIS1N_Pos (9U)
screamer 28:0e774865873d 13873 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13874 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
screamer 28:0e774865873d 13875 #define TIM_CR2_OIS2_Pos (10U)
screamer 28:0e774865873d 13876 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13877 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
screamer 28:0e774865873d 13878 #define TIM_CR2_OIS2N_Pos (11U)
screamer 28:0e774865873d 13879 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13880 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
screamer 28:0e774865873d 13881 #define TIM_CR2_OIS3_Pos (12U)
screamer 28:0e774865873d 13882 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13883 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
screamer 28:0e774865873d 13884 #define TIM_CR2_OIS3N_Pos (13U)
screamer 28:0e774865873d 13885 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13886 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
screamer 28:0e774865873d 13887 #define TIM_CR2_OIS4_Pos (14U)
screamer 28:0e774865873d 13888 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13889 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
screamer 28:0e774865873d 13890 #define TIM_CR2_OIS5_Pos (16U)
screamer 28:0e774865873d 13891 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13892 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
screamer 28:0e774865873d 13893 #define TIM_CR2_OIS6_Pos (18U)
screamer 28:0e774865873d 13894 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 13895 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
screamer 28:0e774865873d 13896
screamer 28:0e774865873d 13897 #define TIM_CR2_MMS2_Pos (20U)
screamer 28:0e774865873d 13898 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 13899 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
screamer 28:0e774865873d 13900 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 13901 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 13902 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 13903 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 13904
screamer 28:0e774865873d 13905 /******************* Bit definition for TIM_SMCR register *******************/
screamer 28:0e774865873d 13906 #define TIM_SMCR_SMS_Pos (0U)
screamer 28:0e774865873d 13907 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
screamer 28:0e774865873d 13908 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
screamer 28:0e774865873d 13909 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13910 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13911 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13912 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 13913
screamer 28:0e774865873d 13914 #define TIM_SMCR_OCCS_Pos (3U)
screamer 28:0e774865873d 13915 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13916 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
screamer 28:0e774865873d 13917
screamer 28:0e774865873d 13918 #define TIM_SMCR_TS_Pos (4U)
screamer 28:0e774865873d 13919 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 13920 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
screamer 28:0e774865873d 13921 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13922 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13923 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13924
screamer 28:0e774865873d 13925 #define TIM_SMCR_MSM_Pos (7U)
screamer 28:0e774865873d 13926 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13927 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
screamer 28:0e774865873d 13928
screamer 28:0e774865873d 13929 #define TIM_SMCR_ETF_Pos (8U)
screamer 28:0e774865873d 13930 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 13931 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
screamer 28:0e774865873d 13932 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13933 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13934 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13935 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13936
screamer 28:0e774865873d 13937 #define TIM_SMCR_ETPS_Pos (12U)
screamer 28:0e774865873d 13938 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 13939 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
screamer 28:0e774865873d 13940 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13941 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13942
screamer 28:0e774865873d 13943 #define TIM_SMCR_ECE_Pos (14U)
screamer 28:0e774865873d 13944 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13945 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
screamer 28:0e774865873d 13946 #define TIM_SMCR_ETP_Pos (15U)
screamer 28:0e774865873d 13947 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 13948 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
screamer 28:0e774865873d 13949
screamer 28:0e774865873d 13950 /******************* Bit definition for TIM_DIER register *******************/
screamer 28:0e774865873d 13951 #define TIM_DIER_UIE_Pos (0U)
screamer 28:0e774865873d 13952 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 13953 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
screamer 28:0e774865873d 13954 #define TIM_DIER_CC1IE_Pos (1U)
screamer 28:0e774865873d 13955 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 13956 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
screamer 28:0e774865873d 13957 #define TIM_DIER_CC2IE_Pos (2U)
screamer 28:0e774865873d 13958 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 13959 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
screamer 28:0e774865873d 13960 #define TIM_DIER_CC3IE_Pos (3U)
screamer 28:0e774865873d 13961 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 13962 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
screamer 28:0e774865873d 13963 #define TIM_DIER_CC4IE_Pos (4U)
screamer 28:0e774865873d 13964 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 13965 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
screamer 28:0e774865873d 13966 #define TIM_DIER_COMIE_Pos (5U)
screamer 28:0e774865873d 13967 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 13968 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
screamer 28:0e774865873d 13969 #define TIM_DIER_TIE_Pos (6U)
screamer 28:0e774865873d 13970 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 13971 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
screamer 28:0e774865873d 13972 #define TIM_DIER_BIE_Pos (7U)
screamer 28:0e774865873d 13973 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 13974 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
screamer 28:0e774865873d 13975 #define TIM_DIER_UDE_Pos (8U)
screamer 28:0e774865873d 13976 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 13977 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
screamer 28:0e774865873d 13978 #define TIM_DIER_CC1DE_Pos (9U)
screamer 28:0e774865873d 13979 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 13980 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
screamer 28:0e774865873d 13981 #define TIM_DIER_CC2DE_Pos (10U)
screamer 28:0e774865873d 13982 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 13983 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
screamer 28:0e774865873d 13984 #define TIM_DIER_CC3DE_Pos (11U)
screamer 28:0e774865873d 13985 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 13986 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
screamer 28:0e774865873d 13987 #define TIM_DIER_CC4DE_Pos (12U)
screamer 28:0e774865873d 13988 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 13989 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
screamer 28:0e774865873d 13990 #define TIM_DIER_COMDE_Pos (13U)
screamer 28:0e774865873d 13991 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 13992 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
screamer 28:0e774865873d 13993 #define TIM_DIER_TDE_Pos (14U)
screamer 28:0e774865873d 13994 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 13995 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
screamer 28:0e774865873d 13996
screamer 28:0e774865873d 13997 /******************** Bit definition for TIM_SR register ********************/
screamer 28:0e774865873d 13998 #define TIM_SR_UIF_Pos (0U)
screamer 28:0e774865873d 13999 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14000 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
screamer 28:0e774865873d 14001 #define TIM_SR_CC1IF_Pos (1U)
screamer 28:0e774865873d 14002 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14003 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
screamer 28:0e774865873d 14004 #define TIM_SR_CC2IF_Pos (2U)
screamer 28:0e774865873d 14005 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14006 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
screamer 28:0e774865873d 14007 #define TIM_SR_CC3IF_Pos (3U)
screamer 28:0e774865873d 14008 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14009 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
screamer 28:0e774865873d 14010 #define TIM_SR_CC4IF_Pos (4U)
screamer 28:0e774865873d 14011 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14012 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
screamer 28:0e774865873d 14013 #define TIM_SR_COMIF_Pos (5U)
screamer 28:0e774865873d 14014 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14015 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
screamer 28:0e774865873d 14016 #define TIM_SR_TIF_Pos (6U)
screamer 28:0e774865873d 14017 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14018 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
screamer 28:0e774865873d 14019 #define TIM_SR_BIF_Pos (7U)
screamer 28:0e774865873d 14020 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14021 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
screamer 28:0e774865873d 14022 #define TIM_SR_B2IF_Pos (8U)
screamer 28:0e774865873d 14023 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14024 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
screamer 28:0e774865873d 14025 #define TIM_SR_CC1OF_Pos (9U)
screamer 28:0e774865873d 14026 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14027 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
screamer 28:0e774865873d 14028 #define TIM_SR_CC2OF_Pos (10U)
screamer 28:0e774865873d 14029 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14030 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
screamer 28:0e774865873d 14031 #define TIM_SR_CC3OF_Pos (11U)
screamer 28:0e774865873d 14032 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14033 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
screamer 28:0e774865873d 14034 #define TIM_SR_CC4OF_Pos (12U)
screamer 28:0e774865873d 14035 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14036 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
screamer 28:0e774865873d 14037 #define TIM_SR_SBIF_Pos (13U)
screamer 28:0e774865873d 14038 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14039 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
screamer 28:0e774865873d 14040 #define TIM_SR_CC5IF_Pos (16U)
screamer 28:0e774865873d 14041 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14042 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
screamer 28:0e774865873d 14043 #define TIM_SR_CC6IF_Pos (17U)
screamer 28:0e774865873d 14044 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 14045 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
screamer 28:0e774865873d 14046
screamer 28:0e774865873d 14047
screamer 28:0e774865873d 14048 /******************* Bit definition for TIM_EGR register ********************/
screamer 28:0e774865873d 14049 #define TIM_EGR_UG_Pos (0U)
screamer 28:0e774865873d 14050 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14051 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
screamer 28:0e774865873d 14052 #define TIM_EGR_CC1G_Pos (1U)
screamer 28:0e774865873d 14053 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14054 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
screamer 28:0e774865873d 14055 #define TIM_EGR_CC2G_Pos (2U)
screamer 28:0e774865873d 14056 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14057 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
screamer 28:0e774865873d 14058 #define TIM_EGR_CC3G_Pos (3U)
screamer 28:0e774865873d 14059 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14060 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
screamer 28:0e774865873d 14061 #define TIM_EGR_CC4G_Pos (4U)
screamer 28:0e774865873d 14062 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14063 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
screamer 28:0e774865873d 14064 #define TIM_EGR_COMG_Pos (5U)
screamer 28:0e774865873d 14065 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14066 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
screamer 28:0e774865873d 14067 #define TIM_EGR_TG_Pos (6U)
screamer 28:0e774865873d 14068 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14069 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
screamer 28:0e774865873d 14070 #define TIM_EGR_BG_Pos (7U)
screamer 28:0e774865873d 14071 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14072 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
screamer 28:0e774865873d 14073 #define TIM_EGR_B2G_Pos (8U)
screamer 28:0e774865873d 14074 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14075 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
screamer 28:0e774865873d 14076
screamer 28:0e774865873d 14077
screamer 28:0e774865873d 14078 /****************** Bit definition for TIM_CCMR1 register *******************/
screamer 28:0e774865873d 14079 #define TIM_CCMR1_CC1S_Pos (0U)
screamer 28:0e774865873d 14080 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14081 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
screamer 28:0e774865873d 14082 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14083 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14084
screamer 28:0e774865873d 14085 #define TIM_CCMR1_OC1FE_Pos (2U)
screamer 28:0e774865873d 14086 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14087 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
screamer 28:0e774865873d 14088 #define TIM_CCMR1_OC1PE_Pos (3U)
screamer 28:0e774865873d 14089 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14090 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
screamer 28:0e774865873d 14091
screamer 28:0e774865873d 14092 #define TIM_CCMR1_OC1M_Pos (4U)
screamer 28:0e774865873d 14093 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
screamer 28:0e774865873d 14094 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
screamer 28:0e774865873d 14095 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14096 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14097 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14098 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14099
screamer 28:0e774865873d 14100 #define TIM_CCMR1_OC1CE_Pos (7U)
screamer 28:0e774865873d 14101 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14102 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
screamer 28:0e774865873d 14103
screamer 28:0e774865873d 14104 #define TIM_CCMR1_CC2S_Pos (8U)
screamer 28:0e774865873d 14105 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 14106 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
screamer 28:0e774865873d 14107 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14108 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14109
screamer 28:0e774865873d 14110 #define TIM_CCMR1_OC2FE_Pos (10U)
screamer 28:0e774865873d 14111 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14112 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
screamer 28:0e774865873d 14113 #define TIM_CCMR1_OC2PE_Pos (11U)
screamer 28:0e774865873d 14114 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14115 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
screamer 28:0e774865873d 14116
screamer 28:0e774865873d 14117 #define TIM_CCMR1_OC2M_Pos (12U)
screamer 28:0e774865873d 14118 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
screamer 28:0e774865873d 14119 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
screamer 28:0e774865873d 14120 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14121 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14122 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14123 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 14124
screamer 28:0e774865873d 14125 #define TIM_CCMR1_OC2CE_Pos (15U)
screamer 28:0e774865873d 14126 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14127 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
screamer 28:0e774865873d 14128
screamer 28:0e774865873d 14129 /*----------------------------------------------------------------------------*/
screamer 28:0e774865873d 14130 #define TIM_CCMR1_IC1PSC_Pos (2U)
screamer 28:0e774865873d 14131 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14132 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
screamer 28:0e774865873d 14133 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14134 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14135
screamer 28:0e774865873d 14136 #define TIM_CCMR1_IC1F_Pos (4U)
screamer 28:0e774865873d 14137 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 14138 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
screamer 28:0e774865873d 14139 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14140 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14141 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14142 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14143
screamer 28:0e774865873d 14144 #define TIM_CCMR1_IC2PSC_Pos (10U)
screamer 28:0e774865873d 14145 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 14146 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
screamer 28:0e774865873d 14147 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14148 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14149
screamer 28:0e774865873d 14150 #define TIM_CCMR1_IC2F_Pos (12U)
screamer 28:0e774865873d 14151 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
screamer 28:0e774865873d 14152 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
screamer 28:0e774865873d 14153 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14154 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14155 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14156 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14157
screamer 28:0e774865873d 14158 /****************** Bit definition for TIM_CCMR2 register *******************/
screamer 28:0e774865873d 14159 #define TIM_CCMR2_CC3S_Pos (0U)
screamer 28:0e774865873d 14160 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14161 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
screamer 28:0e774865873d 14162 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14163 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14164
screamer 28:0e774865873d 14165 #define TIM_CCMR2_OC3FE_Pos (2U)
screamer 28:0e774865873d 14166 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14167 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
screamer 28:0e774865873d 14168 #define TIM_CCMR2_OC3PE_Pos (3U)
screamer 28:0e774865873d 14169 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14170 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
screamer 28:0e774865873d 14171
screamer 28:0e774865873d 14172 #define TIM_CCMR2_OC3M_Pos (4U)
screamer 28:0e774865873d 14173 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
screamer 28:0e774865873d 14174 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
screamer 28:0e774865873d 14175 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14176 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14177 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14178 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14179
screamer 28:0e774865873d 14180 #define TIM_CCMR2_OC3CE_Pos (7U)
screamer 28:0e774865873d 14181 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14182 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
screamer 28:0e774865873d 14183
screamer 28:0e774865873d 14184 #define TIM_CCMR2_CC4S_Pos (8U)
screamer 28:0e774865873d 14185 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 14186 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
screamer 28:0e774865873d 14187 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14188 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14189
screamer 28:0e774865873d 14190 #define TIM_CCMR2_OC4FE_Pos (10U)
screamer 28:0e774865873d 14191 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14192 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
screamer 28:0e774865873d 14193 #define TIM_CCMR2_OC4PE_Pos (11U)
screamer 28:0e774865873d 14194 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14195 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
screamer 28:0e774865873d 14196
screamer 28:0e774865873d 14197 #define TIM_CCMR2_OC4M_Pos (12U)
screamer 28:0e774865873d 14198 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
screamer 28:0e774865873d 14199 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
screamer 28:0e774865873d 14200 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14201 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14202 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14203 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 14204
screamer 28:0e774865873d 14205 #define TIM_CCMR2_OC4CE_Pos (15U)
screamer 28:0e774865873d 14206 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14207 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
screamer 28:0e774865873d 14208
screamer 28:0e774865873d 14209 /*----------------------------------------------------------------------------*/
screamer 28:0e774865873d 14210 #define TIM_CCMR2_IC3PSC_Pos (2U)
screamer 28:0e774865873d 14211 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14212 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
screamer 28:0e774865873d 14213 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14214 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14215
screamer 28:0e774865873d 14216 #define TIM_CCMR2_IC3F_Pos (4U)
screamer 28:0e774865873d 14217 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
screamer 28:0e774865873d 14218 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
screamer 28:0e774865873d 14219 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14220 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14221 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14222 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14223
screamer 28:0e774865873d 14224 #define TIM_CCMR2_IC4PSC_Pos (10U)
screamer 28:0e774865873d 14225 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 14226 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
screamer 28:0e774865873d 14227 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14228 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14229
screamer 28:0e774865873d 14230 #define TIM_CCMR2_IC4F_Pos (12U)
screamer 28:0e774865873d 14231 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
screamer 28:0e774865873d 14232 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
screamer 28:0e774865873d 14233 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14234 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14235 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14236 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14237
screamer 28:0e774865873d 14238 /****************** Bit definition for TIM_CCMR3 register *******************/
screamer 28:0e774865873d 14239 #define TIM_CCMR3_OC5FE_Pos (2U)
screamer 28:0e774865873d 14240 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14241 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
screamer 28:0e774865873d 14242 #define TIM_CCMR3_OC5PE_Pos (3U)
screamer 28:0e774865873d 14243 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14244 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
screamer 28:0e774865873d 14245
screamer 28:0e774865873d 14246 #define TIM_CCMR3_OC5M_Pos (4U)
screamer 28:0e774865873d 14247 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
screamer 28:0e774865873d 14248 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
screamer 28:0e774865873d 14249 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14250 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14251 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14252 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14253
screamer 28:0e774865873d 14254 #define TIM_CCMR3_OC5CE_Pos (7U)
screamer 28:0e774865873d 14255 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14256 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
screamer 28:0e774865873d 14257
screamer 28:0e774865873d 14258 #define TIM_CCMR3_OC6FE_Pos (10U)
screamer 28:0e774865873d 14259 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14260 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
screamer 28:0e774865873d 14261 #define TIM_CCMR3_OC6PE_Pos (11U)
screamer 28:0e774865873d 14262 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14263 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
screamer 28:0e774865873d 14264
screamer 28:0e774865873d 14265 #define TIM_CCMR3_OC6M_Pos (12U)
screamer 28:0e774865873d 14266 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
screamer 28:0e774865873d 14267 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
screamer 28:0e774865873d 14268 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14269 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14270 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14271 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 14272
screamer 28:0e774865873d 14273 #define TIM_CCMR3_OC6CE_Pos (15U)
screamer 28:0e774865873d 14274 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14275 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
screamer 28:0e774865873d 14276
screamer 28:0e774865873d 14277 /******************* Bit definition for TIM_CCER register *******************/
screamer 28:0e774865873d 14278 #define TIM_CCER_CC1E_Pos (0U)
screamer 28:0e774865873d 14279 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14280 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
screamer 28:0e774865873d 14281 #define TIM_CCER_CC1P_Pos (1U)
screamer 28:0e774865873d 14282 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14283 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
screamer 28:0e774865873d 14284 #define TIM_CCER_CC1NE_Pos (2U)
screamer 28:0e774865873d 14285 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14286 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
screamer 28:0e774865873d 14287 #define TIM_CCER_CC1NP_Pos (3U)
screamer 28:0e774865873d 14288 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14289 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
screamer 28:0e774865873d 14290 #define TIM_CCER_CC2E_Pos (4U)
screamer 28:0e774865873d 14291 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14292 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
screamer 28:0e774865873d 14293 #define TIM_CCER_CC2P_Pos (5U)
screamer 28:0e774865873d 14294 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14295 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
screamer 28:0e774865873d 14296 #define TIM_CCER_CC2NE_Pos (6U)
screamer 28:0e774865873d 14297 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14298 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
screamer 28:0e774865873d 14299 #define TIM_CCER_CC2NP_Pos (7U)
screamer 28:0e774865873d 14300 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14301 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
screamer 28:0e774865873d 14302 #define TIM_CCER_CC3E_Pos (8U)
screamer 28:0e774865873d 14303 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14304 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
screamer 28:0e774865873d 14305 #define TIM_CCER_CC3P_Pos (9U)
screamer 28:0e774865873d 14306 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14307 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
screamer 28:0e774865873d 14308 #define TIM_CCER_CC3NE_Pos (10U)
screamer 28:0e774865873d 14309 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14310 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
screamer 28:0e774865873d 14311 #define TIM_CCER_CC3NP_Pos (11U)
screamer 28:0e774865873d 14312 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14313 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
screamer 28:0e774865873d 14314 #define TIM_CCER_CC4E_Pos (12U)
screamer 28:0e774865873d 14315 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14316 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
screamer 28:0e774865873d 14317 #define TIM_CCER_CC4P_Pos (13U)
screamer 28:0e774865873d 14318 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14319 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
screamer 28:0e774865873d 14320 #define TIM_CCER_CC4NP_Pos (15U)
screamer 28:0e774865873d 14321 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14322 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
screamer 28:0e774865873d 14323 #define TIM_CCER_CC5E_Pos (16U)
screamer 28:0e774865873d 14324 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14325 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
screamer 28:0e774865873d 14326 #define TIM_CCER_CC5P_Pos (17U)
screamer 28:0e774865873d 14327 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 14328 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
screamer 28:0e774865873d 14329 #define TIM_CCER_CC6E_Pos (20U)
screamer 28:0e774865873d 14330 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 14331 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
screamer 28:0e774865873d 14332 #define TIM_CCER_CC6P_Pos (21U)
screamer 28:0e774865873d 14333 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 14334 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
screamer 28:0e774865873d 14335
screamer 28:0e774865873d 14336 /******************* Bit definition for TIM_CNT register ********************/
screamer 28:0e774865873d 14337 #define TIM_CNT_CNT_Pos (0U)
screamer 28:0e774865873d 14338 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 14339 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
screamer 28:0e774865873d 14340 #define TIM_CNT_UIFCPY_Pos (31U)
screamer 28:0e774865873d 14341 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 14342 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
screamer 28:0e774865873d 14343
screamer 28:0e774865873d 14344 /******************* Bit definition for TIM_PSC register ********************/
screamer 28:0e774865873d 14345 #define TIM_PSC_PSC_Pos (0U)
screamer 28:0e774865873d 14346 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14347 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
screamer 28:0e774865873d 14348
screamer 28:0e774865873d 14349 /******************* Bit definition for TIM_ARR register ********************/
screamer 28:0e774865873d 14350 #define TIM_ARR_ARR_Pos (0U)
screamer 28:0e774865873d 14351 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 14352 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
screamer 28:0e774865873d 14353
screamer 28:0e774865873d 14354 /******************* Bit definition for TIM_RCR register ********************/
screamer 28:0e774865873d 14355 #define TIM_RCR_REP_Pos (0U)
screamer 28:0e774865873d 14356 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14357 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
screamer 28:0e774865873d 14358
screamer 28:0e774865873d 14359 /******************* Bit definition for TIM_CCR1 register *******************/
screamer 28:0e774865873d 14360 #define TIM_CCR1_CCR1_Pos (0U)
screamer 28:0e774865873d 14361 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14362 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
screamer 28:0e774865873d 14363
screamer 28:0e774865873d 14364 /******************* Bit definition for TIM_CCR2 register *******************/
screamer 28:0e774865873d 14365 #define TIM_CCR2_CCR2_Pos (0U)
screamer 28:0e774865873d 14366 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14367 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
screamer 28:0e774865873d 14368
screamer 28:0e774865873d 14369 /******************* Bit definition for TIM_CCR3 register *******************/
screamer 28:0e774865873d 14370 #define TIM_CCR3_CCR3_Pos (0U)
screamer 28:0e774865873d 14371 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14372 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
screamer 28:0e774865873d 14373
screamer 28:0e774865873d 14374 /******************* Bit definition for TIM_CCR4 register *******************/
screamer 28:0e774865873d 14375 #define TIM_CCR4_CCR4_Pos (0U)
screamer 28:0e774865873d 14376 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14377 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
screamer 28:0e774865873d 14378
screamer 28:0e774865873d 14379 /******************* Bit definition for TIM_CCR5 register *******************/
screamer 28:0e774865873d 14380 #define TIM_CCR5_CCR5_Pos (0U)
screamer 28:0e774865873d 14381 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 14382 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
screamer 28:0e774865873d 14383 #define TIM_CCR5_GC5C1_Pos (29U)
screamer 28:0e774865873d 14384 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 14385 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
screamer 28:0e774865873d 14386 #define TIM_CCR5_GC5C2_Pos (30U)
screamer 28:0e774865873d 14387 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 14388 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
screamer 28:0e774865873d 14389 #define TIM_CCR5_GC5C3_Pos (31U)
screamer 28:0e774865873d 14390 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 14391 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
screamer 28:0e774865873d 14392
screamer 28:0e774865873d 14393 /******************* Bit definition for TIM_CCR6 register *******************/
screamer 28:0e774865873d 14394 #define TIM_CCR6_CCR6_Pos (0U)
screamer 28:0e774865873d 14395 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14396 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
screamer 28:0e774865873d 14397
screamer 28:0e774865873d 14398 /******************* Bit definition for TIM_BDTR register *******************/
screamer 28:0e774865873d 14399 #define TIM_BDTR_DTG_Pos (0U)
screamer 28:0e774865873d 14400 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 14401 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
screamer 28:0e774865873d 14402 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14403 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14404 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14405 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14406 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14407 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14408 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14409 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14410
screamer 28:0e774865873d 14411 #define TIM_BDTR_LOCK_Pos (8U)
screamer 28:0e774865873d 14412 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 14413 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
screamer 28:0e774865873d 14414 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14415 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14416
screamer 28:0e774865873d 14417 #define TIM_BDTR_OSSI_Pos (10U)
screamer 28:0e774865873d 14418 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14419 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
screamer 28:0e774865873d 14420 #define TIM_BDTR_OSSR_Pos (11U)
screamer 28:0e774865873d 14421 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14422 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
screamer 28:0e774865873d 14423 #define TIM_BDTR_BKE_Pos (12U)
screamer 28:0e774865873d 14424 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14425 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
screamer 28:0e774865873d 14426 #define TIM_BDTR_BKP_Pos (13U)
screamer 28:0e774865873d 14427 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14428 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
screamer 28:0e774865873d 14429 #define TIM_BDTR_AOE_Pos (14U)
screamer 28:0e774865873d 14430 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14431 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
screamer 28:0e774865873d 14432 #define TIM_BDTR_MOE_Pos (15U)
screamer 28:0e774865873d 14433 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14434 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
screamer 28:0e774865873d 14435
screamer 28:0e774865873d 14436 #define TIM_BDTR_BKF_Pos (16U)
screamer 28:0e774865873d 14437 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
screamer 28:0e774865873d 14438 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
screamer 28:0e774865873d 14439 #define TIM_BDTR_BK2F_Pos (20U)
screamer 28:0e774865873d 14440 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
screamer 28:0e774865873d 14441 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
screamer 28:0e774865873d 14442
screamer 28:0e774865873d 14443 #define TIM_BDTR_BK2E_Pos (24U)
screamer 28:0e774865873d 14444 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 14445 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
screamer 28:0e774865873d 14446 #define TIM_BDTR_BK2P_Pos (25U)
screamer 28:0e774865873d 14447 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 14448 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
screamer 28:0e774865873d 14449
screamer 28:0e774865873d 14450 /******************* Bit definition for TIM_DCR register ********************/
screamer 28:0e774865873d 14451 #define TIM_DCR_DBA_Pos (0U)
screamer 28:0e774865873d 14452 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 14453 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
screamer 28:0e774865873d 14454 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14455 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14456 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14457 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14458 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14459
screamer 28:0e774865873d 14460 #define TIM_DCR_DBL_Pos (8U)
screamer 28:0e774865873d 14461 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 14462 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
screamer 28:0e774865873d 14463 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14464 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14465 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14466 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14467 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 14468
screamer 28:0e774865873d 14469 /******************* Bit definition for TIM_DMAR register *******************/
screamer 28:0e774865873d 14470 #define TIM_DMAR_DMAB_Pos (0U)
screamer 28:0e774865873d 14471 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14472 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
screamer 28:0e774865873d 14473
screamer 28:0e774865873d 14474 /******************* Bit definition for TIM1_OR1 register *******************/
screamer 28:0e774865873d 14475 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
screamer 28:0e774865873d 14476 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14477 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
screamer 28:0e774865873d 14478 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14479 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14480
screamer 28:0e774865873d 14481 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
screamer 28:0e774865873d 14482 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14483 #define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
screamer 28:0e774865873d 14484 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14485 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14486
screamer 28:0e774865873d 14487 #define TIM1_OR1_TI1_RMP_Pos (4U)
screamer 28:0e774865873d 14488 #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14489 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
screamer 28:0e774865873d 14490
screamer 28:0e774865873d 14491 /******************* Bit definition for TIM1_OR2 register *******************/
screamer 28:0e774865873d 14492 #define TIM1_OR2_BKINE_Pos (0U)
screamer 28:0e774865873d 14493 #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14494 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
screamer 28:0e774865873d 14495 #define TIM1_OR2_BKCMP1E_Pos (1U)
screamer 28:0e774865873d 14496 #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14497 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
screamer 28:0e774865873d 14498 #define TIM1_OR2_BKCMP2E_Pos (2U)
screamer 28:0e774865873d 14499 #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14500 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
screamer 28:0e774865873d 14501 #define TIM1_OR2_BKDF1BK0E_Pos (8U)
screamer 28:0e774865873d 14502 #define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14503 #define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
screamer 28:0e774865873d 14504 #define TIM1_OR2_BKINP_Pos (9U)
screamer 28:0e774865873d 14505 #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14506 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
screamer 28:0e774865873d 14507 #define TIM1_OR2_BKCMP1P_Pos (10U)
screamer 28:0e774865873d 14508 #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14509 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
screamer 28:0e774865873d 14510 #define TIM1_OR2_BKCMP2P_Pos (11U)
screamer 28:0e774865873d 14511 #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14512 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
screamer 28:0e774865873d 14513
screamer 28:0e774865873d 14514 #define TIM1_OR2_ETRSEL_Pos (14U)
screamer 28:0e774865873d 14515 #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
screamer 28:0e774865873d 14516 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
screamer 28:0e774865873d 14517 #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14518 #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14519 #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14520
screamer 28:0e774865873d 14521 /******************* Bit definition for TIM1_OR3 register *******************/
screamer 28:0e774865873d 14522 #define TIM1_OR3_BK2INE_Pos (0U)
screamer 28:0e774865873d 14523 #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14524 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
screamer 28:0e774865873d 14525 #define TIM1_OR3_BK2CMP1E_Pos (1U)
screamer 28:0e774865873d 14526 #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14527 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
screamer 28:0e774865873d 14528 #define TIM1_OR3_BK2CMP2E_Pos (2U)
screamer 28:0e774865873d 14529 #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14530 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
screamer 28:0e774865873d 14531 #define TIM1_OR3_BK2DF1BK1E_Pos (8U)
screamer 28:0e774865873d 14532 #define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14533 #define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
screamer 28:0e774865873d 14534 #define TIM1_OR3_BK2INP_Pos (9U)
screamer 28:0e774865873d 14535 #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14536 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
screamer 28:0e774865873d 14537 #define TIM1_OR3_BK2CMP1P_Pos (10U)
screamer 28:0e774865873d 14538 #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14539 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
screamer 28:0e774865873d 14540 #define TIM1_OR3_BK2CMP2P_Pos (11U)
screamer 28:0e774865873d 14541 #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14542 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
screamer 28:0e774865873d 14543
screamer 28:0e774865873d 14544 /******************* Bit definition for TIM8_OR1 register *******************/
screamer 28:0e774865873d 14545 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
screamer 28:0e774865873d 14546 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14547 #define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
screamer 28:0e774865873d 14548 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14549 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14550
screamer 28:0e774865873d 14551 #define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
screamer 28:0e774865873d 14552 #define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14553 #define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
screamer 28:0e774865873d 14554 #define TIM8_OR1_ETR_ADC3_RMP_0 (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14555 #define TIM8_OR1_ETR_ADC3_RMP_1 (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14556
screamer 28:0e774865873d 14557 #define TIM8_OR1_TI1_RMP_Pos (4U)
screamer 28:0e774865873d 14558 #define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14559 #define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
screamer 28:0e774865873d 14560
screamer 28:0e774865873d 14561 /******************* Bit definition for TIM8_OR2 register *******************/
screamer 28:0e774865873d 14562 #define TIM8_OR2_BKINE_Pos (0U)
screamer 28:0e774865873d 14563 #define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14564 #define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
screamer 28:0e774865873d 14565 #define TIM8_OR2_BKCMP1E_Pos (1U)
screamer 28:0e774865873d 14566 #define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14567 #define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
screamer 28:0e774865873d 14568 #define TIM8_OR2_BKCMP2E_Pos (2U)
screamer 28:0e774865873d 14569 #define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14570 #define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
screamer 28:0e774865873d 14571 #define TIM8_OR2_BKDF1BK2E_Pos (8U)
screamer 28:0e774865873d 14572 #define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14573 #define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
screamer 28:0e774865873d 14574 #define TIM8_OR2_BKINP_Pos (9U)
screamer 28:0e774865873d 14575 #define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14576 #define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
screamer 28:0e774865873d 14577 #define TIM8_OR2_BKCMP1P_Pos (10U)
screamer 28:0e774865873d 14578 #define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14579 #define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
screamer 28:0e774865873d 14580 #define TIM8_OR2_BKCMP2P_Pos (11U)
screamer 28:0e774865873d 14581 #define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14582 #define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
screamer 28:0e774865873d 14583
screamer 28:0e774865873d 14584 #define TIM8_OR2_ETRSEL_Pos (14U)
screamer 28:0e774865873d 14585 #define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
screamer 28:0e774865873d 14586 #define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
screamer 28:0e774865873d 14587 #define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14588 #define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14589 #define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14590
screamer 28:0e774865873d 14591 /******************* Bit definition for TIM8_OR3 register *******************/
screamer 28:0e774865873d 14592 #define TIM8_OR3_BK2INE_Pos (0U)
screamer 28:0e774865873d 14593 #define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14594 #define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
screamer 28:0e774865873d 14595 #define TIM8_OR3_BK2CMP1E_Pos (1U)
screamer 28:0e774865873d 14596 #define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14597 #define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
screamer 28:0e774865873d 14598 #define TIM8_OR3_BK2CMP2E_Pos (2U)
screamer 28:0e774865873d 14599 #define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14600 #define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
screamer 28:0e774865873d 14601 #define TIM8_OR3_BK2DF1BK3E_Pos (8U)
screamer 28:0e774865873d 14602 #define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14603 #define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
screamer 28:0e774865873d 14604 #define TIM8_OR3_BK2INP_Pos (9U)
screamer 28:0e774865873d 14605 #define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14606 #define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
screamer 28:0e774865873d 14607 #define TIM8_OR3_BK2CMP1P_Pos (10U)
screamer 28:0e774865873d 14608 #define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14609 #define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
screamer 28:0e774865873d 14610 #define TIM8_OR3_BK2CMP2P_Pos (11U)
screamer 28:0e774865873d 14611 #define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14612 #define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
screamer 28:0e774865873d 14613
screamer 28:0e774865873d 14614 /******************* Bit definition for TIM2_OR1 register *******************/
screamer 28:0e774865873d 14615 #define TIM2_OR1_ITR1_RMP_Pos (0U)
screamer 28:0e774865873d 14616 #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14617 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
screamer 28:0e774865873d 14618 #define TIM2_OR1_ETR1_RMP_Pos (1U)
screamer 28:0e774865873d 14619 #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14620 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
screamer 28:0e774865873d 14621
screamer 28:0e774865873d 14622 #define TIM2_OR1_TI4_RMP_Pos (2U)
screamer 28:0e774865873d 14623 #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14624 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
screamer 28:0e774865873d 14625 #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14626 #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14627
screamer 28:0e774865873d 14628 /******************* Bit definition for TIM2_OR2 register *******************/
screamer 28:0e774865873d 14629 #define TIM2_OR2_ETRSEL_Pos (14U)
screamer 28:0e774865873d 14630 #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
screamer 28:0e774865873d 14631 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
screamer 28:0e774865873d 14632 #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14633 #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14634 #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14635
screamer 28:0e774865873d 14636 /******************* Bit definition for TIM3_OR1 register *******************/
screamer 28:0e774865873d 14637 #define TIM3_OR1_TI1_RMP_Pos (0U)
screamer 28:0e774865873d 14638 #define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14639 #define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
screamer 28:0e774865873d 14640 #define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14641 #define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14642
screamer 28:0e774865873d 14643 /******************* Bit definition for TIM3_OR2 register *******************/
screamer 28:0e774865873d 14644 #define TIM3_OR2_ETRSEL_Pos (14U)
screamer 28:0e774865873d 14645 #define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
screamer 28:0e774865873d 14646 #define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
screamer 28:0e774865873d 14647 #define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14648 #define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14649 #define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14650
screamer 28:0e774865873d 14651 /******************* Bit definition for TIM15_OR1 register ******************/
screamer 28:0e774865873d 14652 #define TIM15_OR1_TI1_RMP_Pos (0U)
screamer 28:0e774865873d 14653 #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14654 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
screamer 28:0e774865873d 14655
screamer 28:0e774865873d 14656 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
screamer 28:0e774865873d 14657 #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
screamer 28:0e774865873d 14658 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
screamer 28:0e774865873d 14659 #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14660 #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14661
screamer 28:0e774865873d 14662 /******************* Bit definition for TIM15_OR2 register ******************/
screamer 28:0e774865873d 14663 #define TIM15_OR2_BKINE_Pos (0U)
screamer 28:0e774865873d 14664 #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14665 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
screamer 28:0e774865873d 14666 #define TIM15_OR2_BKCMP1E_Pos (1U)
screamer 28:0e774865873d 14667 #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14668 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
screamer 28:0e774865873d 14669 #define TIM15_OR2_BKCMP2E_Pos (2U)
screamer 28:0e774865873d 14670 #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14671 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
screamer 28:0e774865873d 14672 #define TIM15_OR2_BKDF1BK0E_Pos (8U)
screamer 28:0e774865873d 14673 #define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14674 #define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
screamer 28:0e774865873d 14675 #define TIM15_OR2_BKINP_Pos (9U)
screamer 28:0e774865873d 14676 #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14677 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
screamer 28:0e774865873d 14678 #define TIM15_OR2_BKCMP1P_Pos (10U)
screamer 28:0e774865873d 14679 #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14680 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
screamer 28:0e774865873d 14681 #define TIM15_OR2_BKCMP2P_Pos (11U)
screamer 28:0e774865873d 14682 #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14683 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
screamer 28:0e774865873d 14684
screamer 28:0e774865873d 14685 /******************* Bit definition for TIM16_OR1 register ******************/
screamer 28:0e774865873d 14686 #define TIM16_OR1_TI1_RMP_Pos (0U)
screamer 28:0e774865873d 14687 #define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14688 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
screamer 28:0e774865873d 14689 #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14690 #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14691
screamer 28:0e774865873d 14692 /******************* Bit definition for TIM16_OR2 register ******************/
screamer 28:0e774865873d 14693 #define TIM16_OR2_BKINE_Pos (0U)
screamer 28:0e774865873d 14694 #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14695 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
screamer 28:0e774865873d 14696 #define TIM16_OR2_BKCMP1E_Pos (1U)
screamer 28:0e774865873d 14697 #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14698 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
screamer 28:0e774865873d 14699 #define TIM16_OR2_BKCMP2E_Pos (2U)
screamer 28:0e774865873d 14700 #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14701 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
screamer 28:0e774865873d 14702 #define TIM16_OR2_BKDF1BK1E_Pos (8U)
screamer 28:0e774865873d 14703 #define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14704 #define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
screamer 28:0e774865873d 14705 #define TIM16_OR2_BKINP_Pos (9U)
screamer 28:0e774865873d 14706 #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14707 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
screamer 28:0e774865873d 14708 #define TIM16_OR2_BKCMP1P_Pos (10U)
screamer 28:0e774865873d 14709 #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14710 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
screamer 28:0e774865873d 14711 #define TIM16_OR2_BKCMP2P_Pos (11U)
screamer 28:0e774865873d 14712 #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14713 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
screamer 28:0e774865873d 14714
screamer 28:0e774865873d 14715 /******************* Bit definition for TIM17_OR1 register ******************/
screamer 28:0e774865873d 14716 #define TIM17_OR1_TI1_RMP_Pos (0U)
screamer 28:0e774865873d 14717 #define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14718 #define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
screamer 28:0e774865873d 14719 #define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14720 #define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14721
screamer 28:0e774865873d 14722 /******************* Bit definition for TIM17_OR2 register ******************/
screamer 28:0e774865873d 14723 #define TIM17_OR2_BKINE_Pos (0U)
screamer 28:0e774865873d 14724 #define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14725 #define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
screamer 28:0e774865873d 14726 #define TIM17_OR2_BKCMP1E_Pos (1U)
screamer 28:0e774865873d 14727 #define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14728 #define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
screamer 28:0e774865873d 14729 #define TIM17_OR2_BKCMP2E_Pos (2U)
screamer 28:0e774865873d 14730 #define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14731 #define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
screamer 28:0e774865873d 14732 #define TIM17_OR2_BKDF1BK2E_Pos (8U)
screamer 28:0e774865873d 14733 #define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 14734 #define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
screamer 28:0e774865873d 14735 #define TIM17_OR2_BKINP_Pos (9U)
screamer 28:0e774865873d 14736 #define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14737 #define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
screamer 28:0e774865873d 14738 #define TIM17_OR2_BKCMP1P_Pos (10U)
screamer 28:0e774865873d 14739 #define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14740 #define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
screamer 28:0e774865873d 14741 #define TIM17_OR2_BKCMP2P_Pos (11U)
screamer 28:0e774865873d 14742 #define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14743 #define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
screamer 28:0e774865873d 14744
screamer 28:0e774865873d 14745 /******************************************************************************/
screamer 28:0e774865873d 14746 /* */
screamer 28:0e774865873d 14747 /* Low Power Timer (LPTTIM) */
screamer 28:0e774865873d 14748 /* */
screamer 28:0e774865873d 14749 /******************************************************************************/
screamer 28:0e774865873d 14750 /****************** Bit definition for LPTIM_ISR register *******************/
screamer 28:0e774865873d 14751 #define LPTIM_ISR_CMPM_Pos (0U)
screamer 28:0e774865873d 14752 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14753 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
screamer 28:0e774865873d 14754 #define LPTIM_ISR_ARRM_Pos (1U)
screamer 28:0e774865873d 14755 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14756 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
screamer 28:0e774865873d 14757 #define LPTIM_ISR_EXTTRIG_Pos (2U)
screamer 28:0e774865873d 14758 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14759 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
screamer 28:0e774865873d 14760 #define LPTIM_ISR_CMPOK_Pos (3U)
screamer 28:0e774865873d 14761 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14762 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
screamer 28:0e774865873d 14763 #define LPTIM_ISR_ARROK_Pos (4U)
screamer 28:0e774865873d 14764 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14765 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
screamer 28:0e774865873d 14766 #define LPTIM_ISR_UP_Pos (5U)
screamer 28:0e774865873d 14767 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14768 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
screamer 28:0e774865873d 14769 #define LPTIM_ISR_DOWN_Pos (6U)
screamer 28:0e774865873d 14770 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14771 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
screamer 28:0e774865873d 14772
screamer 28:0e774865873d 14773 /****************** Bit definition for LPTIM_ICR register *******************/
screamer 28:0e774865873d 14774 #define LPTIM_ICR_CMPMCF_Pos (0U)
screamer 28:0e774865873d 14775 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14776 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
screamer 28:0e774865873d 14777 #define LPTIM_ICR_ARRMCF_Pos (1U)
screamer 28:0e774865873d 14778 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14779 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
screamer 28:0e774865873d 14780 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
screamer 28:0e774865873d 14781 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14782 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
screamer 28:0e774865873d 14783 #define LPTIM_ICR_CMPOKCF_Pos (3U)
screamer 28:0e774865873d 14784 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14785 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
screamer 28:0e774865873d 14786 #define LPTIM_ICR_ARROKCF_Pos (4U)
screamer 28:0e774865873d 14787 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14788 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
screamer 28:0e774865873d 14789 #define LPTIM_ICR_UPCF_Pos (5U)
screamer 28:0e774865873d 14790 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14791 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
screamer 28:0e774865873d 14792 #define LPTIM_ICR_DOWNCF_Pos (6U)
screamer 28:0e774865873d 14793 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14794 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
screamer 28:0e774865873d 14795
screamer 28:0e774865873d 14796 /****************** Bit definition for LPTIM_IER register ********************/
screamer 28:0e774865873d 14797 #define LPTIM_IER_CMPMIE_Pos (0U)
screamer 28:0e774865873d 14798 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14799 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
screamer 28:0e774865873d 14800 #define LPTIM_IER_ARRMIE_Pos (1U)
screamer 28:0e774865873d 14801 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14802 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
screamer 28:0e774865873d 14803 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
screamer 28:0e774865873d 14804 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14805 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
screamer 28:0e774865873d 14806 #define LPTIM_IER_CMPOKIE_Pos (3U)
screamer 28:0e774865873d 14807 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14808 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
screamer 28:0e774865873d 14809 #define LPTIM_IER_ARROKIE_Pos (4U)
screamer 28:0e774865873d 14810 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14811 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
screamer 28:0e774865873d 14812 #define LPTIM_IER_UPIE_Pos (5U)
screamer 28:0e774865873d 14813 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14814 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
screamer 28:0e774865873d 14815 #define LPTIM_IER_DOWNIE_Pos (6U)
screamer 28:0e774865873d 14816 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14817 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
screamer 28:0e774865873d 14818
screamer 28:0e774865873d 14819 /****************** Bit definition for LPTIM_CFGR register *******************/
screamer 28:0e774865873d 14820 #define LPTIM_CFGR_CKSEL_Pos (0U)
screamer 28:0e774865873d 14821 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14822 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
screamer 28:0e774865873d 14823
screamer 28:0e774865873d 14824 #define LPTIM_CFGR_CKPOL_Pos (1U)
screamer 28:0e774865873d 14825 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
screamer 28:0e774865873d 14826 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
screamer 28:0e774865873d 14827 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14828 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14829
screamer 28:0e774865873d 14830 #define LPTIM_CFGR_CKFLT_Pos (3U)
screamer 28:0e774865873d 14831 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
screamer 28:0e774865873d 14832 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
screamer 28:0e774865873d 14833 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14834 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14835
screamer 28:0e774865873d 14836 #define LPTIM_CFGR_TRGFLT_Pos (6U)
screamer 28:0e774865873d 14837 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 14838 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
screamer 28:0e774865873d 14839 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14840 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14841
screamer 28:0e774865873d 14842 #define LPTIM_CFGR_PRESC_Pos (9U)
screamer 28:0e774865873d 14843 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
screamer 28:0e774865873d 14844 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
screamer 28:0e774865873d 14845 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14846 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 14847 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 14848
screamer 28:0e774865873d 14849 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
screamer 28:0e774865873d 14850 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
screamer 28:0e774865873d 14851 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
screamer 28:0e774865873d 14852 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 14853 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 14854 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14855
screamer 28:0e774865873d 14856 #define LPTIM_CFGR_TRIGEN_Pos (17U)
screamer 28:0e774865873d 14857 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
screamer 28:0e774865873d 14858 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
screamer 28:0e774865873d 14859 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 14860 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 14861
screamer 28:0e774865873d 14862 #define LPTIM_CFGR_TIMOUT_Pos (19U)
screamer 28:0e774865873d 14863 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 14864 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
screamer 28:0e774865873d 14865 #define LPTIM_CFGR_WAVE_Pos (20U)
screamer 28:0e774865873d 14866 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 14867 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
screamer 28:0e774865873d 14868 #define LPTIM_CFGR_WAVPOL_Pos (21U)
screamer 28:0e774865873d 14869 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 14870 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
screamer 28:0e774865873d 14871 #define LPTIM_CFGR_PRELOAD_Pos (22U)
screamer 28:0e774865873d 14872 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 14873 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
screamer 28:0e774865873d 14874 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
screamer 28:0e774865873d 14875 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 14876 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
screamer 28:0e774865873d 14877 #define LPTIM_CFGR_ENC_Pos (24U)
screamer 28:0e774865873d 14878 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 14879 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
screamer 28:0e774865873d 14880
screamer 28:0e774865873d 14881 /****************** Bit definition for LPTIM_CR register ********************/
screamer 28:0e774865873d 14882 #define LPTIM_CR_ENABLE_Pos (0U)
screamer 28:0e774865873d 14883 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14884 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
screamer 28:0e774865873d 14885 #define LPTIM_CR_SNGSTRT_Pos (1U)
screamer 28:0e774865873d 14886 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14887 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
screamer 28:0e774865873d 14888 #define LPTIM_CR_CNTSTRT_Pos (2U)
screamer 28:0e774865873d 14889 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14890 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
screamer 28:0e774865873d 14891
screamer 28:0e774865873d 14892 /****************** Bit definition for LPTIM_CMP register *******************/
screamer 28:0e774865873d 14893 #define LPTIM_CMP_CMP_Pos (0U)
screamer 28:0e774865873d 14894 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14895 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
screamer 28:0e774865873d 14896
screamer 28:0e774865873d 14897 /****************** Bit definition for LPTIM_ARR register *******************/
screamer 28:0e774865873d 14898 #define LPTIM_ARR_ARR_Pos (0U)
screamer 28:0e774865873d 14899 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14900 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
screamer 28:0e774865873d 14901
screamer 28:0e774865873d 14902 /****************** Bit definition for LPTIM_CNT register *******************/
screamer 28:0e774865873d 14903 #define LPTIM_CNT_CNT_Pos (0U)
screamer 28:0e774865873d 14904 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 14905 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
screamer 28:0e774865873d 14906
screamer 28:0e774865873d 14907 /****************** Bit definition for LPTIM_OR register ********************/
screamer 28:0e774865873d 14908 #define LPTIM_OR_OR_Pos (0U)
screamer 28:0e774865873d 14909 #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 14910 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
screamer 28:0e774865873d 14911 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14912 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14913
screamer 28:0e774865873d 14914 /******************************************************************************/
screamer 28:0e774865873d 14915 /* */
screamer 28:0e774865873d 14916 /* Analog Comparators (COMP) */
screamer 28:0e774865873d 14917 /* */
screamer 28:0e774865873d 14918 /******************************************************************************/
screamer 28:0e774865873d 14919 /********************** Bit definition for COMP_CSR register ****************/
screamer 28:0e774865873d 14920 #define COMP_CSR_EN_Pos (0U)
screamer 28:0e774865873d 14921 #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14922 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
screamer 28:0e774865873d 14923
screamer 28:0e774865873d 14924 #define COMP_CSR_PWRMODE_Pos (2U)
screamer 28:0e774865873d 14925 #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14926 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
screamer 28:0e774865873d 14927 #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14928 #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14929
screamer 28:0e774865873d 14930 #define COMP_CSR_INMSEL_Pos (4U)
screamer 28:0e774865873d 14931 #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 14932 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
screamer 28:0e774865873d 14933 #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 14934 #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 14935 #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 14936
screamer 28:0e774865873d 14937 #define COMP_CSR_INPSEL_Pos (7U)
screamer 28:0e774865873d 14938 #define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14939 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
screamer 28:0e774865873d 14940 #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 14941
screamer 28:0e774865873d 14942 #define COMP_CSR_WINMODE_Pos (9U)
screamer 28:0e774865873d 14943 #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 14944 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
screamer 28:0e774865873d 14945
screamer 28:0e774865873d 14946 #define COMP_CSR_POLARITY_Pos (15U)
screamer 28:0e774865873d 14947 #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 14948 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
screamer 28:0e774865873d 14949
screamer 28:0e774865873d 14950 #define COMP_CSR_HYST_Pos (16U)
screamer 28:0e774865873d 14951 #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
screamer 28:0e774865873d 14952 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
screamer 28:0e774865873d 14953 #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 14954 #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 14955
screamer 28:0e774865873d 14956 #define COMP_CSR_BLANKING_Pos (18U)
screamer 28:0e774865873d 14957 #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
screamer 28:0e774865873d 14958 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
screamer 28:0e774865873d 14959 #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 14960 #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 14961 #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 14962
screamer 28:0e774865873d 14963 #define COMP_CSR_BRGEN_Pos (22U)
screamer 28:0e774865873d 14964 #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 14965 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
screamer 28:0e774865873d 14966 #define COMP_CSR_SCALEN_Pos (23U)
screamer 28:0e774865873d 14967 #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 14968 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
screamer 28:0e774865873d 14969
screamer 28:0e774865873d 14970 #define COMP_CSR_VALUE_Pos (30U)
screamer 28:0e774865873d 14971 #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 14972 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
screamer 28:0e774865873d 14973
screamer 28:0e774865873d 14974 #define COMP_CSR_LOCK_Pos (31U)
screamer 28:0e774865873d 14975 #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 14976 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
screamer 28:0e774865873d 14977
screamer 28:0e774865873d 14978 /******************************************************************************/
screamer 28:0e774865873d 14979 /* */
screamer 28:0e774865873d 14980 /* Operational Amplifier (OPAMP) */
screamer 28:0e774865873d 14981 /* */
screamer 28:0e774865873d 14982 /******************************************************************************/
screamer 28:0e774865873d 14983 /********************* Bit definition for OPAMPx_CSR register ***************/
screamer 28:0e774865873d 14984 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
screamer 28:0e774865873d 14985 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 14986 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
screamer 28:0e774865873d 14987 #define OPAMP_CSR_OPALPM_Pos (1U)
screamer 28:0e774865873d 14988 #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 14989 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
screamer 28:0e774865873d 14990
screamer 28:0e774865873d 14991 #define OPAMP_CSR_OPAMODE_Pos (2U)
screamer 28:0e774865873d 14992 #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 14993 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
screamer 28:0e774865873d 14994 #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 14995 #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 14996
screamer 28:0e774865873d 14997 #define OPAMP_CSR_PGGAIN_Pos (4U)
screamer 28:0e774865873d 14998 #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 14999 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
screamer 28:0e774865873d 15000 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15001 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15002
screamer 28:0e774865873d 15003 #define OPAMP_CSR_VMSEL_Pos (8U)
screamer 28:0e774865873d 15004 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 15005 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
screamer 28:0e774865873d 15006 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15007 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15008
screamer 28:0e774865873d 15009 #define OPAMP_CSR_VPSEL_Pos (10U)
screamer 28:0e774865873d 15010 #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15011 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
screamer 28:0e774865873d 15012 #define OPAMP_CSR_CALON_Pos (12U)
screamer 28:0e774865873d 15013 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15014 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
screamer 28:0e774865873d 15015 #define OPAMP_CSR_CALSEL_Pos (13U)
screamer 28:0e774865873d 15016 #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15017 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
screamer 28:0e774865873d 15018 #define OPAMP_CSR_USERTRIM_Pos (14U)
screamer 28:0e774865873d 15019 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15020 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
screamer 28:0e774865873d 15021 #define OPAMP_CSR_CALOUT_Pos (15U)
screamer 28:0e774865873d 15022 #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15023 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
screamer 28:0e774865873d 15024
screamer 28:0e774865873d 15025 /********************* Bit definition for OPAMP1_CSR register ***************/
screamer 28:0e774865873d 15026 #define OPAMP1_CSR_OPAEN_Pos (0U)
screamer 28:0e774865873d 15027 #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15028 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
screamer 28:0e774865873d 15029 #define OPAMP1_CSR_OPALPM_Pos (1U)
screamer 28:0e774865873d 15030 #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15031 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
screamer 28:0e774865873d 15032
screamer 28:0e774865873d 15033 #define OPAMP1_CSR_OPAMODE_Pos (2U)
screamer 28:0e774865873d 15034 #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 15035 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
screamer 28:0e774865873d 15036 #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15037 #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15038
screamer 28:0e774865873d 15039 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
screamer 28:0e774865873d 15040 #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 15041 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
screamer 28:0e774865873d 15042 #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15043 #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15044
screamer 28:0e774865873d 15045 #define OPAMP1_CSR_VMSEL_Pos (8U)
screamer 28:0e774865873d 15046 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 15047 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
screamer 28:0e774865873d 15048 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15049 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15050
screamer 28:0e774865873d 15051 #define OPAMP1_CSR_VPSEL_Pos (10U)
screamer 28:0e774865873d 15052 #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15053 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
screamer 28:0e774865873d 15054 #define OPAMP1_CSR_CALON_Pos (12U)
screamer 28:0e774865873d 15055 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15056 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
screamer 28:0e774865873d 15057 #define OPAMP1_CSR_CALSEL_Pos (13U)
screamer 28:0e774865873d 15058 #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15059 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
screamer 28:0e774865873d 15060 #define OPAMP1_CSR_USERTRIM_Pos (14U)
screamer 28:0e774865873d 15061 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15062 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
screamer 28:0e774865873d 15063 #define OPAMP1_CSR_CALOUT_Pos (15U)
screamer 28:0e774865873d 15064 #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15065 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
screamer 28:0e774865873d 15066
screamer 28:0e774865873d 15067 #define OPAMP1_CSR_OPARANGE_Pos (31U)
screamer 28:0e774865873d 15068 #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 15069 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
screamer 28:0e774865873d 15070
screamer 28:0e774865873d 15071 /********************* Bit definition for OPAMP2_CSR register ***************/
screamer 28:0e774865873d 15072 #define OPAMP2_CSR_OPAEN_Pos (0U)
screamer 28:0e774865873d 15073 #define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15074 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
screamer 28:0e774865873d 15075 #define OPAMP2_CSR_OPALPM_Pos (1U)
screamer 28:0e774865873d 15076 #define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15077 #define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
screamer 28:0e774865873d 15078
screamer 28:0e774865873d 15079 #define OPAMP2_CSR_OPAMODE_Pos (2U)
screamer 28:0e774865873d 15080 #define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
screamer 28:0e774865873d 15081 #define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
screamer 28:0e774865873d 15082 #define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15083 #define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15084
screamer 28:0e774865873d 15085 #define OPAMP2_CSR_PGAGAIN_Pos (4U)
screamer 28:0e774865873d 15086 #define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
screamer 28:0e774865873d 15087 #define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
screamer 28:0e774865873d 15088 #define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15089 #define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15090
screamer 28:0e774865873d 15091 #define OPAMP2_CSR_VMSEL_Pos (8U)
screamer 28:0e774865873d 15092 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
screamer 28:0e774865873d 15093 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
screamer 28:0e774865873d 15094 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15095 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15096
screamer 28:0e774865873d 15097 #define OPAMP2_CSR_VPSEL_Pos (10U)
screamer 28:0e774865873d 15098 #define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15099 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
screamer 28:0e774865873d 15100 #define OPAMP2_CSR_CALON_Pos (12U)
screamer 28:0e774865873d 15101 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15102 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
screamer 28:0e774865873d 15103 #define OPAMP2_CSR_CALSEL_Pos (13U)
screamer 28:0e774865873d 15104 #define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15105 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
screamer 28:0e774865873d 15106 #define OPAMP2_CSR_USERTRIM_Pos (14U)
screamer 28:0e774865873d 15107 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15108 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
screamer 28:0e774865873d 15109 #define OPAMP2_CSR_CALOUT_Pos (15U)
screamer 28:0e774865873d 15110 #define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15111 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
screamer 28:0e774865873d 15112
screamer 28:0e774865873d 15113 /******************* Bit definition for OPAMP_OTR register ******************/
screamer 28:0e774865873d 15114 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
screamer 28:0e774865873d 15115 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 15116 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
screamer 28:0e774865873d 15117 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
screamer 28:0e774865873d 15118 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 15119 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
screamer 28:0e774865873d 15120
screamer 28:0e774865873d 15121 /******************* Bit definition for OPAMP1_OTR register ******************/
screamer 28:0e774865873d 15122 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
screamer 28:0e774865873d 15123 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 15124 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
screamer 28:0e774865873d 15125 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
screamer 28:0e774865873d 15126 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 15127 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
screamer 28:0e774865873d 15128
screamer 28:0e774865873d 15129 /******************* Bit definition for OPAMP2_OTR register ******************/
screamer 28:0e774865873d 15130 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
screamer 28:0e774865873d 15131 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 15132 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
screamer 28:0e774865873d 15133 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
screamer 28:0e774865873d 15134 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 15135 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
screamer 28:0e774865873d 15136
screamer 28:0e774865873d 15137 /******************* Bit definition for OPAMP_LPOTR register ****************/
screamer 28:0e774865873d 15138 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
screamer 28:0e774865873d 15139 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 15140 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
screamer 28:0e774865873d 15141 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
screamer 28:0e774865873d 15142 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 15143 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
screamer 28:0e774865873d 15144
screamer 28:0e774865873d 15145 /******************* Bit definition for OPAMP1_LPOTR register ****************/
screamer 28:0e774865873d 15146 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
screamer 28:0e774865873d 15147 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 15148 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
screamer 28:0e774865873d 15149 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
screamer 28:0e774865873d 15150 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 15151 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
screamer 28:0e774865873d 15152
screamer 28:0e774865873d 15153 /******************* Bit definition for OPAMP2_LPOTR register ****************/
screamer 28:0e774865873d 15154 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
screamer 28:0e774865873d 15155 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 15156 #define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
screamer 28:0e774865873d 15157 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
screamer 28:0e774865873d 15158 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
screamer 28:0e774865873d 15159 #define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
screamer 28:0e774865873d 15160
screamer 28:0e774865873d 15161 /******************************************************************************/
screamer 28:0e774865873d 15162 /* */
screamer 28:0e774865873d 15163 /* Touch Sensing Controller (TSC) */
screamer 28:0e774865873d 15164 /* */
screamer 28:0e774865873d 15165 /******************************************************************************/
screamer 28:0e774865873d 15166 /******************* Bit definition for TSC_CR register *********************/
screamer 28:0e774865873d 15167 #define TSC_CR_TSCE_Pos (0U)
screamer 28:0e774865873d 15168 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15169 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
screamer 28:0e774865873d 15170 #define TSC_CR_START_Pos (1U)
screamer 28:0e774865873d 15171 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15172 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
screamer 28:0e774865873d 15173 #define TSC_CR_AM_Pos (2U)
screamer 28:0e774865873d 15174 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15175 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
screamer 28:0e774865873d 15176 #define TSC_CR_SYNCPOL_Pos (3U)
screamer 28:0e774865873d 15177 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15178 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
screamer 28:0e774865873d 15179 #define TSC_CR_IODEF_Pos (4U)
screamer 28:0e774865873d 15180 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15181 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
screamer 28:0e774865873d 15182
screamer 28:0e774865873d 15183 #define TSC_CR_MCV_Pos (5U)
screamer 28:0e774865873d 15184 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
screamer 28:0e774865873d 15185 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
screamer 28:0e774865873d 15186 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15187 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15188 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15189
screamer 28:0e774865873d 15190 #define TSC_CR_PGPSC_Pos (12U)
screamer 28:0e774865873d 15191 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
screamer 28:0e774865873d 15192 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
screamer 28:0e774865873d 15193 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15194 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15195 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15196
screamer 28:0e774865873d 15197 #define TSC_CR_SSPSC_Pos (15U)
screamer 28:0e774865873d 15198 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15199 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
screamer 28:0e774865873d 15200 #define TSC_CR_SSE_Pos (16U)
screamer 28:0e774865873d 15201 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15202 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
screamer 28:0e774865873d 15203
screamer 28:0e774865873d 15204 #define TSC_CR_SSD_Pos (17U)
screamer 28:0e774865873d 15205 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
screamer 28:0e774865873d 15206 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
screamer 28:0e774865873d 15207 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15208 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15209 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15210 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15211 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15212 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15213 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15214
screamer 28:0e774865873d 15215 #define TSC_CR_CTPL_Pos (24U)
screamer 28:0e774865873d 15216 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
screamer 28:0e774865873d 15217 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
screamer 28:0e774865873d 15218 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 15219 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 15220 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 15221 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 15222
screamer 28:0e774865873d 15223 #define TSC_CR_CTPH_Pos (28U)
screamer 28:0e774865873d 15224 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
screamer 28:0e774865873d 15225 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
screamer 28:0e774865873d 15226 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 15227 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 15228 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 15229 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 15230
screamer 28:0e774865873d 15231 /******************* Bit definition for TSC_IER register ********************/
screamer 28:0e774865873d 15232 #define TSC_IER_EOAIE_Pos (0U)
screamer 28:0e774865873d 15233 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15234 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
screamer 28:0e774865873d 15235 #define TSC_IER_MCEIE_Pos (1U)
screamer 28:0e774865873d 15236 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15237 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
screamer 28:0e774865873d 15238
screamer 28:0e774865873d 15239 /******************* Bit definition for TSC_ICR register ********************/
screamer 28:0e774865873d 15240 #define TSC_ICR_EOAIC_Pos (0U)
screamer 28:0e774865873d 15241 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15242 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
screamer 28:0e774865873d 15243 #define TSC_ICR_MCEIC_Pos (1U)
screamer 28:0e774865873d 15244 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15245 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
screamer 28:0e774865873d 15246
screamer 28:0e774865873d 15247 /******************* Bit definition for TSC_ISR register ********************/
screamer 28:0e774865873d 15248 #define TSC_ISR_EOAF_Pos (0U)
screamer 28:0e774865873d 15249 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15250 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
screamer 28:0e774865873d 15251 #define TSC_ISR_MCEF_Pos (1U)
screamer 28:0e774865873d 15252 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15253 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
screamer 28:0e774865873d 15254
screamer 28:0e774865873d 15255 /******************* Bit definition for TSC_IOHCR register ******************/
screamer 28:0e774865873d 15256 #define TSC_IOHCR_G1_IO1_Pos (0U)
screamer 28:0e774865873d 15257 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15258 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15259 #define TSC_IOHCR_G1_IO2_Pos (1U)
screamer 28:0e774865873d 15260 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15261 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15262 #define TSC_IOHCR_G1_IO3_Pos (2U)
screamer 28:0e774865873d 15263 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15264 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15265 #define TSC_IOHCR_G1_IO4_Pos (3U)
screamer 28:0e774865873d 15266 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15267 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15268 #define TSC_IOHCR_G2_IO1_Pos (4U)
screamer 28:0e774865873d 15269 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15270 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15271 #define TSC_IOHCR_G2_IO2_Pos (5U)
screamer 28:0e774865873d 15272 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15273 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15274 #define TSC_IOHCR_G2_IO3_Pos (6U)
screamer 28:0e774865873d 15275 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15276 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15277 #define TSC_IOHCR_G2_IO4_Pos (7U)
screamer 28:0e774865873d 15278 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15279 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15280 #define TSC_IOHCR_G3_IO1_Pos (8U)
screamer 28:0e774865873d 15281 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15282 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15283 #define TSC_IOHCR_G3_IO2_Pos (9U)
screamer 28:0e774865873d 15284 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15285 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15286 #define TSC_IOHCR_G3_IO3_Pos (10U)
screamer 28:0e774865873d 15287 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15288 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15289 #define TSC_IOHCR_G3_IO4_Pos (11U)
screamer 28:0e774865873d 15290 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15291 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15292 #define TSC_IOHCR_G4_IO1_Pos (12U)
screamer 28:0e774865873d 15293 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15294 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15295 #define TSC_IOHCR_G4_IO2_Pos (13U)
screamer 28:0e774865873d 15296 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15297 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15298 #define TSC_IOHCR_G4_IO3_Pos (14U)
screamer 28:0e774865873d 15299 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15300 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15301 #define TSC_IOHCR_G4_IO4_Pos (15U)
screamer 28:0e774865873d 15302 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15303 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15304 #define TSC_IOHCR_G5_IO1_Pos (16U)
screamer 28:0e774865873d 15305 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15306 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15307 #define TSC_IOHCR_G5_IO2_Pos (17U)
screamer 28:0e774865873d 15308 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15309 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15310 #define TSC_IOHCR_G5_IO3_Pos (18U)
screamer 28:0e774865873d 15311 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15312 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15313 #define TSC_IOHCR_G5_IO4_Pos (19U)
screamer 28:0e774865873d 15314 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15315 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15316 #define TSC_IOHCR_G6_IO1_Pos (20U)
screamer 28:0e774865873d 15317 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15318 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15319 #define TSC_IOHCR_G6_IO2_Pos (21U)
screamer 28:0e774865873d 15320 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15321 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15322 #define TSC_IOHCR_G6_IO3_Pos (22U)
screamer 28:0e774865873d 15323 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15324 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15325 #define TSC_IOHCR_G6_IO4_Pos (23U)
screamer 28:0e774865873d 15326 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15327 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15328 #define TSC_IOHCR_G7_IO1_Pos (24U)
screamer 28:0e774865873d 15329 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 15330 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15331 #define TSC_IOHCR_G7_IO2_Pos (25U)
screamer 28:0e774865873d 15332 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 15333 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15334 #define TSC_IOHCR_G7_IO3_Pos (26U)
screamer 28:0e774865873d 15335 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 15336 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15337 #define TSC_IOHCR_G7_IO4_Pos (27U)
screamer 28:0e774865873d 15338 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 15339 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15340 #define TSC_IOHCR_G8_IO1_Pos (28U)
screamer 28:0e774865873d 15341 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 15342 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15343 #define TSC_IOHCR_G8_IO2_Pos (29U)
screamer 28:0e774865873d 15344 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 15345 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15346 #define TSC_IOHCR_G8_IO3_Pos (30U)
screamer 28:0e774865873d 15347 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 15348 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15349 #define TSC_IOHCR_G8_IO4_Pos (31U)
screamer 28:0e774865873d 15350 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 15351 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
screamer 28:0e774865873d 15352
screamer 28:0e774865873d 15353 /******************* Bit definition for TSC_IOASCR register *****************/
screamer 28:0e774865873d 15354 #define TSC_IOASCR_G1_IO1_Pos (0U)
screamer 28:0e774865873d 15355 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15356 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
screamer 28:0e774865873d 15357 #define TSC_IOASCR_G1_IO2_Pos (1U)
screamer 28:0e774865873d 15358 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15359 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
screamer 28:0e774865873d 15360 #define TSC_IOASCR_G1_IO3_Pos (2U)
screamer 28:0e774865873d 15361 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15362 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
screamer 28:0e774865873d 15363 #define TSC_IOASCR_G1_IO4_Pos (3U)
screamer 28:0e774865873d 15364 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15365 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
screamer 28:0e774865873d 15366 #define TSC_IOASCR_G2_IO1_Pos (4U)
screamer 28:0e774865873d 15367 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15368 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
screamer 28:0e774865873d 15369 #define TSC_IOASCR_G2_IO2_Pos (5U)
screamer 28:0e774865873d 15370 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15371 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
screamer 28:0e774865873d 15372 #define TSC_IOASCR_G2_IO3_Pos (6U)
screamer 28:0e774865873d 15373 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15374 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
screamer 28:0e774865873d 15375 #define TSC_IOASCR_G2_IO4_Pos (7U)
screamer 28:0e774865873d 15376 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15377 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
screamer 28:0e774865873d 15378 #define TSC_IOASCR_G3_IO1_Pos (8U)
screamer 28:0e774865873d 15379 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15380 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
screamer 28:0e774865873d 15381 #define TSC_IOASCR_G3_IO2_Pos (9U)
screamer 28:0e774865873d 15382 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15383 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
screamer 28:0e774865873d 15384 #define TSC_IOASCR_G3_IO3_Pos (10U)
screamer 28:0e774865873d 15385 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15386 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
screamer 28:0e774865873d 15387 #define TSC_IOASCR_G3_IO4_Pos (11U)
screamer 28:0e774865873d 15388 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15389 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
screamer 28:0e774865873d 15390 #define TSC_IOASCR_G4_IO1_Pos (12U)
screamer 28:0e774865873d 15391 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15392 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
screamer 28:0e774865873d 15393 #define TSC_IOASCR_G4_IO2_Pos (13U)
screamer 28:0e774865873d 15394 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15395 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
screamer 28:0e774865873d 15396 #define TSC_IOASCR_G4_IO3_Pos (14U)
screamer 28:0e774865873d 15397 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15398 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
screamer 28:0e774865873d 15399 #define TSC_IOASCR_G4_IO4_Pos (15U)
screamer 28:0e774865873d 15400 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15401 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
screamer 28:0e774865873d 15402 #define TSC_IOASCR_G5_IO1_Pos (16U)
screamer 28:0e774865873d 15403 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15404 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
screamer 28:0e774865873d 15405 #define TSC_IOASCR_G5_IO2_Pos (17U)
screamer 28:0e774865873d 15406 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15407 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
screamer 28:0e774865873d 15408 #define TSC_IOASCR_G5_IO3_Pos (18U)
screamer 28:0e774865873d 15409 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15410 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
screamer 28:0e774865873d 15411 #define TSC_IOASCR_G5_IO4_Pos (19U)
screamer 28:0e774865873d 15412 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15413 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
screamer 28:0e774865873d 15414 #define TSC_IOASCR_G6_IO1_Pos (20U)
screamer 28:0e774865873d 15415 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15416 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
screamer 28:0e774865873d 15417 #define TSC_IOASCR_G6_IO2_Pos (21U)
screamer 28:0e774865873d 15418 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15419 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
screamer 28:0e774865873d 15420 #define TSC_IOASCR_G6_IO3_Pos (22U)
screamer 28:0e774865873d 15421 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15422 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
screamer 28:0e774865873d 15423 #define TSC_IOASCR_G6_IO4_Pos (23U)
screamer 28:0e774865873d 15424 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15425 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
screamer 28:0e774865873d 15426 #define TSC_IOASCR_G7_IO1_Pos (24U)
screamer 28:0e774865873d 15427 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 15428 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
screamer 28:0e774865873d 15429 #define TSC_IOASCR_G7_IO2_Pos (25U)
screamer 28:0e774865873d 15430 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 15431 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
screamer 28:0e774865873d 15432 #define TSC_IOASCR_G7_IO3_Pos (26U)
screamer 28:0e774865873d 15433 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 15434 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
screamer 28:0e774865873d 15435 #define TSC_IOASCR_G7_IO4_Pos (27U)
screamer 28:0e774865873d 15436 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 15437 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
screamer 28:0e774865873d 15438 #define TSC_IOASCR_G8_IO1_Pos (28U)
screamer 28:0e774865873d 15439 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 15440 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
screamer 28:0e774865873d 15441 #define TSC_IOASCR_G8_IO2_Pos (29U)
screamer 28:0e774865873d 15442 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 15443 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
screamer 28:0e774865873d 15444 #define TSC_IOASCR_G8_IO3_Pos (30U)
screamer 28:0e774865873d 15445 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 15446 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
screamer 28:0e774865873d 15447 #define TSC_IOASCR_G8_IO4_Pos (31U)
screamer 28:0e774865873d 15448 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 15449 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
screamer 28:0e774865873d 15450
screamer 28:0e774865873d 15451 /******************* Bit definition for TSC_IOSCR register ******************/
screamer 28:0e774865873d 15452 #define TSC_IOSCR_G1_IO1_Pos (0U)
screamer 28:0e774865873d 15453 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15454 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
screamer 28:0e774865873d 15455 #define TSC_IOSCR_G1_IO2_Pos (1U)
screamer 28:0e774865873d 15456 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15457 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
screamer 28:0e774865873d 15458 #define TSC_IOSCR_G1_IO3_Pos (2U)
screamer 28:0e774865873d 15459 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15460 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
screamer 28:0e774865873d 15461 #define TSC_IOSCR_G1_IO4_Pos (3U)
screamer 28:0e774865873d 15462 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15463 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
screamer 28:0e774865873d 15464 #define TSC_IOSCR_G2_IO1_Pos (4U)
screamer 28:0e774865873d 15465 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15466 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
screamer 28:0e774865873d 15467 #define TSC_IOSCR_G2_IO2_Pos (5U)
screamer 28:0e774865873d 15468 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15469 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
screamer 28:0e774865873d 15470 #define TSC_IOSCR_G2_IO3_Pos (6U)
screamer 28:0e774865873d 15471 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15472 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
screamer 28:0e774865873d 15473 #define TSC_IOSCR_G2_IO4_Pos (7U)
screamer 28:0e774865873d 15474 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15475 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
screamer 28:0e774865873d 15476 #define TSC_IOSCR_G3_IO1_Pos (8U)
screamer 28:0e774865873d 15477 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15478 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
screamer 28:0e774865873d 15479 #define TSC_IOSCR_G3_IO2_Pos (9U)
screamer 28:0e774865873d 15480 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15481 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
screamer 28:0e774865873d 15482 #define TSC_IOSCR_G3_IO3_Pos (10U)
screamer 28:0e774865873d 15483 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15484 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
screamer 28:0e774865873d 15485 #define TSC_IOSCR_G3_IO4_Pos (11U)
screamer 28:0e774865873d 15486 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15487 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
screamer 28:0e774865873d 15488 #define TSC_IOSCR_G4_IO1_Pos (12U)
screamer 28:0e774865873d 15489 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15490 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
screamer 28:0e774865873d 15491 #define TSC_IOSCR_G4_IO2_Pos (13U)
screamer 28:0e774865873d 15492 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15493 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
screamer 28:0e774865873d 15494 #define TSC_IOSCR_G4_IO3_Pos (14U)
screamer 28:0e774865873d 15495 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15496 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
screamer 28:0e774865873d 15497 #define TSC_IOSCR_G4_IO4_Pos (15U)
screamer 28:0e774865873d 15498 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15499 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
screamer 28:0e774865873d 15500 #define TSC_IOSCR_G5_IO1_Pos (16U)
screamer 28:0e774865873d 15501 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15502 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
screamer 28:0e774865873d 15503 #define TSC_IOSCR_G5_IO2_Pos (17U)
screamer 28:0e774865873d 15504 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15505 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
screamer 28:0e774865873d 15506 #define TSC_IOSCR_G5_IO3_Pos (18U)
screamer 28:0e774865873d 15507 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15508 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
screamer 28:0e774865873d 15509 #define TSC_IOSCR_G5_IO4_Pos (19U)
screamer 28:0e774865873d 15510 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15511 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
screamer 28:0e774865873d 15512 #define TSC_IOSCR_G6_IO1_Pos (20U)
screamer 28:0e774865873d 15513 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15514 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
screamer 28:0e774865873d 15515 #define TSC_IOSCR_G6_IO2_Pos (21U)
screamer 28:0e774865873d 15516 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15517 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
screamer 28:0e774865873d 15518 #define TSC_IOSCR_G6_IO3_Pos (22U)
screamer 28:0e774865873d 15519 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15520 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
screamer 28:0e774865873d 15521 #define TSC_IOSCR_G6_IO4_Pos (23U)
screamer 28:0e774865873d 15522 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15523 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
screamer 28:0e774865873d 15524 #define TSC_IOSCR_G7_IO1_Pos (24U)
screamer 28:0e774865873d 15525 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 15526 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
screamer 28:0e774865873d 15527 #define TSC_IOSCR_G7_IO2_Pos (25U)
screamer 28:0e774865873d 15528 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 15529 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
screamer 28:0e774865873d 15530 #define TSC_IOSCR_G7_IO3_Pos (26U)
screamer 28:0e774865873d 15531 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 15532 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
screamer 28:0e774865873d 15533 #define TSC_IOSCR_G7_IO4_Pos (27U)
screamer 28:0e774865873d 15534 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 15535 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
screamer 28:0e774865873d 15536 #define TSC_IOSCR_G8_IO1_Pos (28U)
screamer 28:0e774865873d 15537 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 15538 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
screamer 28:0e774865873d 15539 #define TSC_IOSCR_G8_IO2_Pos (29U)
screamer 28:0e774865873d 15540 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 15541 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
screamer 28:0e774865873d 15542 #define TSC_IOSCR_G8_IO3_Pos (30U)
screamer 28:0e774865873d 15543 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 15544 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
screamer 28:0e774865873d 15545 #define TSC_IOSCR_G8_IO4_Pos (31U)
screamer 28:0e774865873d 15546 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 15547 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
screamer 28:0e774865873d 15548
screamer 28:0e774865873d 15549 /******************* Bit definition for TSC_IOCCR register ******************/
screamer 28:0e774865873d 15550 #define TSC_IOCCR_G1_IO1_Pos (0U)
screamer 28:0e774865873d 15551 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15552 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
screamer 28:0e774865873d 15553 #define TSC_IOCCR_G1_IO2_Pos (1U)
screamer 28:0e774865873d 15554 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15555 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
screamer 28:0e774865873d 15556 #define TSC_IOCCR_G1_IO3_Pos (2U)
screamer 28:0e774865873d 15557 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15558 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
screamer 28:0e774865873d 15559 #define TSC_IOCCR_G1_IO4_Pos (3U)
screamer 28:0e774865873d 15560 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15561 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
screamer 28:0e774865873d 15562 #define TSC_IOCCR_G2_IO1_Pos (4U)
screamer 28:0e774865873d 15563 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15564 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
screamer 28:0e774865873d 15565 #define TSC_IOCCR_G2_IO2_Pos (5U)
screamer 28:0e774865873d 15566 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15567 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
screamer 28:0e774865873d 15568 #define TSC_IOCCR_G2_IO3_Pos (6U)
screamer 28:0e774865873d 15569 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15570 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
screamer 28:0e774865873d 15571 #define TSC_IOCCR_G2_IO4_Pos (7U)
screamer 28:0e774865873d 15572 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15573 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
screamer 28:0e774865873d 15574 #define TSC_IOCCR_G3_IO1_Pos (8U)
screamer 28:0e774865873d 15575 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15576 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
screamer 28:0e774865873d 15577 #define TSC_IOCCR_G3_IO2_Pos (9U)
screamer 28:0e774865873d 15578 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15579 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
screamer 28:0e774865873d 15580 #define TSC_IOCCR_G3_IO3_Pos (10U)
screamer 28:0e774865873d 15581 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15582 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
screamer 28:0e774865873d 15583 #define TSC_IOCCR_G3_IO4_Pos (11U)
screamer 28:0e774865873d 15584 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15585 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
screamer 28:0e774865873d 15586 #define TSC_IOCCR_G4_IO1_Pos (12U)
screamer 28:0e774865873d 15587 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15588 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
screamer 28:0e774865873d 15589 #define TSC_IOCCR_G4_IO2_Pos (13U)
screamer 28:0e774865873d 15590 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15591 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
screamer 28:0e774865873d 15592 #define TSC_IOCCR_G4_IO3_Pos (14U)
screamer 28:0e774865873d 15593 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15594 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
screamer 28:0e774865873d 15595 #define TSC_IOCCR_G4_IO4_Pos (15U)
screamer 28:0e774865873d 15596 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15597 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
screamer 28:0e774865873d 15598 #define TSC_IOCCR_G5_IO1_Pos (16U)
screamer 28:0e774865873d 15599 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15600 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
screamer 28:0e774865873d 15601 #define TSC_IOCCR_G5_IO2_Pos (17U)
screamer 28:0e774865873d 15602 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15603 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
screamer 28:0e774865873d 15604 #define TSC_IOCCR_G5_IO3_Pos (18U)
screamer 28:0e774865873d 15605 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15606 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
screamer 28:0e774865873d 15607 #define TSC_IOCCR_G5_IO4_Pos (19U)
screamer 28:0e774865873d 15608 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15609 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
screamer 28:0e774865873d 15610 #define TSC_IOCCR_G6_IO1_Pos (20U)
screamer 28:0e774865873d 15611 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15612 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
screamer 28:0e774865873d 15613 #define TSC_IOCCR_G6_IO2_Pos (21U)
screamer 28:0e774865873d 15614 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15615 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
screamer 28:0e774865873d 15616 #define TSC_IOCCR_G6_IO3_Pos (22U)
screamer 28:0e774865873d 15617 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15618 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
screamer 28:0e774865873d 15619 #define TSC_IOCCR_G6_IO4_Pos (23U)
screamer 28:0e774865873d 15620 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15621 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
screamer 28:0e774865873d 15622 #define TSC_IOCCR_G7_IO1_Pos (24U)
screamer 28:0e774865873d 15623 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 15624 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
screamer 28:0e774865873d 15625 #define TSC_IOCCR_G7_IO2_Pos (25U)
screamer 28:0e774865873d 15626 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 15627 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
screamer 28:0e774865873d 15628 #define TSC_IOCCR_G7_IO3_Pos (26U)
screamer 28:0e774865873d 15629 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 15630 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
screamer 28:0e774865873d 15631 #define TSC_IOCCR_G7_IO4_Pos (27U)
screamer 28:0e774865873d 15632 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 15633 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
screamer 28:0e774865873d 15634 #define TSC_IOCCR_G8_IO1_Pos (28U)
screamer 28:0e774865873d 15635 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 15636 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
screamer 28:0e774865873d 15637 #define TSC_IOCCR_G8_IO2_Pos (29U)
screamer 28:0e774865873d 15638 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 15639 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
screamer 28:0e774865873d 15640 #define TSC_IOCCR_G8_IO3_Pos (30U)
screamer 28:0e774865873d 15641 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 15642 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
screamer 28:0e774865873d 15643 #define TSC_IOCCR_G8_IO4_Pos (31U)
screamer 28:0e774865873d 15644 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 15645 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
screamer 28:0e774865873d 15646
screamer 28:0e774865873d 15647 /******************* Bit definition for TSC_IOGCSR register *****************/
screamer 28:0e774865873d 15648 #define TSC_IOGCSR_G1E_Pos (0U)
screamer 28:0e774865873d 15649 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15650 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
screamer 28:0e774865873d 15651 #define TSC_IOGCSR_G2E_Pos (1U)
screamer 28:0e774865873d 15652 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15653 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
screamer 28:0e774865873d 15654 #define TSC_IOGCSR_G3E_Pos (2U)
screamer 28:0e774865873d 15655 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15656 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
screamer 28:0e774865873d 15657 #define TSC_IOGCSR_G4E_Pos (3U)
screamer 28:0e774865873d 15658 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15659 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
screamer 28:0e774865873d 15660 #define TSC_IOGCSR_G5E_Pos (4U)
screamer 28:0e774865873d 15661 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15662 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
screamer 28:0e774865873d 15663 #define TSC_IOGCSR_G6E_Pos (5U)
screamer 28:0e774865873d 15664 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15665 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
screamer 28:0e774865873d 15666 #define TSC_IOGCSR_G7E_Pos (6U)
screamer 28:0e774865873d 15667 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15668 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
screamer 28:0e774865873d 15669 #define TSC_IOGCSR_G8E_Pos (7U)
screamer 28:0e774865873d 15670 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15671 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
screamer 28:0e774865873d 15672 #define TSC_IOGCSR_G1S_Pos (16U)
screamer 28:0e774865873d 15673 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15674 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
screamer 28:0e774865873d 15675 #define TSC_IOGCSR_G2S_Pos (17U)
screamer 28:0e774865873d 15676 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15677 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
screamer 28:0e774865873d 15678 #define TSC_IOGCSR_G3S_Pos (18U)
screamer 28:0e774865873d 15679 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15680 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
screamer 28:0e774865873d 15681 #define TSC_IOGCSR_G4S_Pos (19U)
screamer 28:0e774865873d 15682 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15683 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
screamer 28:0e774865873d 15684 #define TSC_IOGCSR_G5S_Pos (20U)
screamer 28:0e774865873d 15685 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15686 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
screamer 28:0e774865873d 15687 #define TSC_IOGCSR_G6S_Pos (21U)
screamer 28:0e774865873d 15688 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15689 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
screamer 28:0e774865873d 15690 #define TSC_IOGCSR_G7S_Pos (22U)
screamer 28:0e774865873d 15691 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15692 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
screamer 28:0e774865873d 15693 #define TSC_IOGCSR_G8S_Pos (23U)
screamer 28:0e774865873d 15694 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15695 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
screamer 28:0e774865873d 15696
screamer 28:0e774865873d 15697 /******************* Bit definition for TSC_IOGXCR register *****************/
screamer 28:0e774865873d 15698 #define TSC_IOGXCR_CNT_Pos (0U)
screamer 28:0e774865873d 15699 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
screamer 28:0e774865873d 15700 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
screamer 28:0e774865873d 15701
screamer 28:0e774865873d 15702 /******************************************************************************/
screamer 28:0e774865873d 15703 /* */
screamer 28:0e774865873d 15704 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
screamer 28:0e774865873d 15705 /* */
screamer 28:0e774865873d 15706 /******************************************************************************/
screamer 28:0e774865873d 15707 /****************** Bit definition for USART_CR1 register *******************/
screamer 28:0e774865873d 15708 #define USART_CR1_UE_Pos (0U)
screamer 28:0e774865873d 15709 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15710 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
screamer 28:0e774865873d 15711 #define USART_CR1_UESM_Pos (1U)
screamer 28:0e774865873d 15712 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15713 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
screamer 28:0e774865873d 15714 #define USART_CR1_RE_Pos (2U)
screamer 28:0e774865873d 15715 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15716 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
screamer 28:0e774865873d 15717 #define USART_CR1_TE_Pos (3U)
screamer 28:0e774865873d 15718 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15719 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
screamer 28:0e774865873d 15720 #define USART_CR1_IDLEIE_Pos (4U)
screamer 28:0e774865873d 15721 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15722 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
screamer 28:0e774865873d 15723 #define USART_CR1_RXNEIE_Pos (5U)
screamer 28:0e774865873d 15724 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15725 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
screamer 28:0e774865873d 15726 #define USART_CR1_TCIE_Pos (6U)
screamer 28:0e774865873d 15727 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15728 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
screamer 28:0e774865873d 15729 #define USART_CR1_TXEIE_Pos (7U)
screamer 28:0e774865873d 15730 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15731 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
screamer 28:0e774865873d 15732 #define USART_CR1_PEIE_Pos (8U)
screamer 28:0e774865873d 15733 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15734 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
screamer 28:0e774865873d 15735 #define USART_CR1_PS_Pos (9U)
screamer 28:0e774865873d 15736 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15737 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
screamer 28:0e774865873d 15738 #define USART_CR1_PCE_Pos (10U)
screamer 28:0e774865873d 15739 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15740 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
screamer 28:0e774865873d 15741 #define USART_CR1_WAKE_Pos (11U)
screamer 28:0e774865873d 15742 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15743 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
screamer 28:0e774865873d 15744 #define USART_CR1_M_Pos (12U)
screamer 28:0e774865873d 15745 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
screamer 28:0e774865873d 15746 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
screamer 28:0e774865873d 15747 #define USART_CR1_M0_Pos (12U)
screamer 28:0e774865873d 15748 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15749 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
screamer 28:0e774865873d 15750 #define USART_CR1_MME_Pos (13U)
screamer 28:0e774865873d 15751 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15752 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
screamer 28:0e774865873d 15753 #define USART_CR1_CMIE_Pos (14U)
screamer 28:0e774865873d 15754 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15755 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
screamer 28:0e774865873d 15756 #define USART_CR1_OVER8_Pos (15U)
screamer 28:0e774865873d 15757 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15758 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
screamer 28:0e774865873d 15759 #define USART_CR1_DEDT_Pos (16U)
screamer 28:0e774865873d 15760 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
screamer 28:0e774865873d 15761 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
screamer 28:0e774865873d 15762 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15763 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15764 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15765 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15766 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15767 #define USART_CR1_DEAT_Pos (21U)
screamer 28:0e774865873d 15768 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
screamer 28:0e774865873d 15769 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
screamer 28:0e774865873d 15770 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15771 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15772 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15773 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 15774 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 15775 #define USART_CR1_RTOIE_Pos (26U)
screamer 28:0e774865873d 15776 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 15777 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
screamer 28:0e774865873d 15778 #define USART_CR1_EOBIE_Pos (27U)
screamer 28:0e774865873d 15779 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 15780 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
screamer 28:0e774865873d 15781 #define USART_CR1_M1_Pos (28U)
screamer 28:0e774865873d 15782 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 15783 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
screamer 28:0e774865873d 15784
screamer 28:0e774865873d 15785 /****************** Bit definition for USART_CR2 register *******************/
screamer 28:0e774865873d 15786 #define USART_CR2_ADDM7_Pos (4U)
screamer 28:0e774865873d 15787 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15788 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
screamer 28:0e774865873d 15789 #define USART_CR2_LBDL_Pos (5U)
screamer 28:0e774865873d 15790 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15791 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
screamer 28:0e774865873d 15792 #define USART_CR2_LBDIE_Pos (6U)
screamer 28:0e774865873d 15793 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15794 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
screamer 28:0e774865873d 15795 #define USART_CR2_LBCL_Pos (8U)
screamer 28:0e774865873d 15796 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15797 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
screamer 28:0e774865873d 15798 #define USART_CR2_CPHA_Pos (9U)
screamer 28:0e774865873d 15799 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15800 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
screamer 28:0e774865873d 15801 #define USART_CR2_CPOL_Pos (10U)
screamer 28:0e774865873d 15802 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15803 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
screamer 28:0e774865873d 15804 #define USART_CR2_CLKEN_Pos (11U)
screamer 28:0e774865873d 15805 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15806 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
screamer 28:0e774865873d 15807 #define USART_CR2_STOP_Pos (12U)
screamer 28:0e774865873d 15808 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
screamer 28:0e774865873d 15809 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
screamer 28:0e774865873d 15810 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15811 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15812 #define USART_CR2_LINEN_Pos (14U)
screamer 28:0e774865873d 15813 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15814 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
screamer 28:0e774865873d 15815 #define USART_CR2_SWAP_Pos (15U)
screamer 28:0e774865873d 15816 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15817 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
screamer 28:0e774865873d 15818 #define USART_CR2_RXINV_Pos (16U)
screamer 28:0e774865873d 15819 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 15820 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
screamer 28:0e774865873d 15821 #define USART_CR2_TXINV_Pos (17U)
screamer 28:0e774865873d 15822 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15823 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
screamer 28:0e774865873d 15824 #define USART_CR2_DATAINV_Pos (18U)
screamer 28:0e774865873d 15825 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15826 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
screamer 28:0e774865873d 15827 #define USART_CR2_MSBFIRST_Pos (19U)
screamer 28:0e774865873d 15828 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15829 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
screamer 28:0e774865873d 15830 #define USART_CR2_ABREN_Pos (20U)
screamer 28:0e774865873d 15831 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15832 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
screamer 28:0e774865873d 15833 #define USART_CR2_ABRMODE_Pos (21U)
screamer 28:0e774865873d 15834 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
screamer 28:0e774865873d 15835 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
screamer 28:0e774865873d 15836 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15837 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15838 #define USART_CR2_RTOEN_Pos (23U)
screamer 28:0e774865873d 15839 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15840 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
screamer 28:0e774865873d 15841 #define USART_CR2_ADD_Pos (24U)
screamer 28:0e774865873d 15842 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 15843 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
screamer 28:0e774865873d 15844
screamer 28:0e774865873d 15845 /****************** Bit definition for USART_CR3 register *******************/
screamer 28:0e774865873d 15846 #define USART_CR3_EIE_Pos (0U)
screamer 28:0e774865873d 15847 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15848 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
screamer 28:0e774865873d 15849 #define USART_CR3_IREN_Pos (1U)
screamer 28:0e774865873d 15850 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15851 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
screamer 28:0e774865873d 15852 #define USART_CR3_IRLP_Pos (2U)
screamer 28:0e774865873d 15853 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15854 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
screamer 28:0e774865873d 15855 #define USART_CR3_HDSEL_Pos (3U)
screamer 28:0e774865873d 15856 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15857 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
screamer 28:0e774865873d 15858 #define USART_CR3_NACK_Pos (4U)
screamer 28:0e774865873d 15859 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15860 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
screamer 28:0e774865873d 15861 #define USART_CR3_SCEN_Pos (5U)
screamer 28:0e774865873d 15862 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15863 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
screamer 28:0e774865873d 15864 #define USART_CR3_DMAR_Pos (6U)
screamer 28:0e774865873d 15865 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15866 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
screamer 28:0e774865873d 15867 #define USART_CR3_DMAT_Pos (7U)
screamer 28:0e774865873d 15868 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15869 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
screamer 28:0e774865873d 15870 #define USART_CR3_RTSE_Pos (8U)
screamer 28:0e774865873d 15871 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15872 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
screamer 28:0e774865873d 15873 #define USART_CR3_CTSE_Pos (9U)
screamer 28:0e774865873d 15874 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15875 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
screamer 28:0e774865873d 15876 #define USART_CR3_CTSIE_Pos (10U)
screamer 28:0e774865873d 15877 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15878 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
screamer 28:0e774865873d 15879 #define USART_CR3_ONEBIT_Pos (11U)
screamer 28:0e774865873d 15880 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15881 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
screamer 28:0e774865873d 15882 #define USART_CR3_OVRDIS_Pos (12U)
screamer 28:0e774865873d 15883 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15884 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
screamer 28:0e774865873d 15885 #define USART_CR3_DDRE_Pos (13U)
screamer 28:0e774865873d 15886 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 15887 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
screamer 28:0e774865873d 15888 #define USART_CR3_DEM_Pos (14U)
screamer 28:0e774865873d 15889 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15890 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
screamer 28:0e774865873d 15891 #define USART_CR3_DEP_Pos (15U)
screamer 28:0e774865873d 15892 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 15893 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
screamer 28:0e774865873d 15894 #define USART_CR3_SCARCNT_Pos (17U)
screamer 28:0e774865873d 15895 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
screamer 28:0e774865873d 15896 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
screamer 28:0e774865873d 15897 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 15898 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 15899 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 15900 #define USART_CR3_WUS_Pos (20U)
screamer 28:0e774865873d 15901 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 15902 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
screamer 28:0e774865873d 15903 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 15904 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 15905 #define USART_CR3_WUFIE_Pos (22U)
screamer 28:0e774865873d 15906 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 15907 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
screamer 28:0e774865873d 15908 /* MBED */
screamer 28:0e774865873d 15909 #define USART_CR3_UCESM_Pos (23U)
screamer 28:0e774865873d 15910 #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 15911 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
screamer 28:0e774865873d 15912 /* MBED */
screamer 28:0e774865873d 15913
screamer 28:0e774865873d 15914 /****************** Bit definition for USART_BRR register *******************/
screamer 28:0e774865873d 15915 #define USART_BRR_DIV_FRACTION_Pos (0U)
screamer 28:0e774865873d 15916 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 15917 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
screamer 28:0e774865873d 15918 #define USART_BRR_DIV_MANTISSA_Pos (4U)
screamer 28:0e774865873d 15919 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
screamer 28:0e774865873d 15920 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
screamer 28:0e774865873d 15921
screamer 28:0e774865873d 15922 /****************** Bit definition for USART_GTPR register ******************/
screamer 28:0e774865873d 15923 #define USART_GTPR_PSC_Pos (0U)
screamer 28:0e774865873d 15924 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
screamer 28:0e774865873d 15925 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
screamer 28:0e774865873d 15926 #define USART_GTPR_GT_Pos (8U)
screamer 28:0e774865873d 15927 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
screamer 28:0e774865873d 15928 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
screamer 28:0e774865873d 15929
screamer 28:0e774865873d 15930 /******************* Bit definition for USART_RTOR register *****************/
screamer 28:0e774865873d 15931 #define USART_RTOR_RTO_Pos (0U)
screamer 28:0e774865873d 15932 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
screamer 28:0e774865873d 15933 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
screamer 28:0e774865873d 15934 #define USART_RTOR_BLEN_Pos (24U)
screamer 28:0e774865873d 15935 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 15936 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
screamer 28:0e774865873d 15937
screamer 28:0e774865873d 15938 /******************* Bit definition for USART_RQR register ******************/
screamer 28:0e774865873d 15939 #define USART_RQR_ABRRQ_Pos (0U)
screamer 28:0e774865873d 15940 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15941 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
screamer 28:0e774865873d 15942 #define USART_RQR_SBKRQ_Pos (1U)
screamer 28:0e774865873d 15943 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15944 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
screamer 28:0e774865873d 15945 #define USART_RQR_MMRQ_Pos (2U)
screamer 28:0e774865873d 15946 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15947 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
screamer 28:0e774865873d 15948 #define USART_RQR_RXFRQ_Pos (3U)
screamer 28:0e774865873d 15949 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15950 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
screamer 28:0e774865873d 15951 #define USART_RQR_TXFRQ_Pos (4U)
screamer 28:0e774865873d 15952 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15953 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
screamer 28:0e774865873d 15954
screamer 28:0e774865873d 15955 /******************* Bit definition for USART_ISR register ******************/
screamer 28:0e774865873d 15956 #define USART_ISR_PE_Pos (0U)
screamer 28:0e774865873d 15957 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 15958 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
screamer 28:0e774865873d 15959 #define USART_ISR_FE_Pos (1U)
screamer 28:0e774865873d 15960 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 15961 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
screamer 28:0e774865873d 15962 #define USART_ISR_NE_Pos (2U)
screamer 28:0e774865873d 15963 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 15964 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
screamer 28:0e774865873d 15965 #define USART_ISR_ORE_Pos (3U)
screamer 28:0e774865873d 15966 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 15967 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
screamer 28:0e774865873d 15968 #define USART_ISR_IDLE_Pos (4U)
screamer 28:0e774865873d 15969 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 15970 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
screamer 28:0e774865873d 15971 #define USART_ISR_RXNE_Pos (5U)
screamer 28:0e774865873d 15972 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 15973 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
screamer 28:0e774865873d 15974 #define USART_ISR_TC_Pos (6U)
screamer 28:0e774865873d 15975 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 15976 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
screamer 28:0e774865873d 15977 #define USART_ISR_TXE_Pos (7U)
screamer 28:0e774865873d 15978 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 15979 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
screamer 28:0e774865873d 15980 #define USART_ISR_LBDF_Pos (8U)
screamer 28:0e774865873d 15981 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 15982 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
screamer 28:0e774865873d 15983 #define USART_ISR_CTSIF_Pos (9U)
screamer 28:0e774865873d 15984 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 15985 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
screamer 28:0e774865873d 15986 #define USART_ISR_CTS_Pos (10U)
screamer 28:0e774865873d 15987 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 15988 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
screamer 28:0e774865873d 15989 #define USART_ISR_RTOF_Pos (11U)
screamer 28:0e774865873d 15990 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 15991 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
screamer 28:0e774865873d 15992 #define USART_ISR_EOBF_Pos (12U)
screamer 28:0e774865873d 15993 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 15994 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
screamer 28:0e774865873d 15995 #define USART_ISR_ABRE_Pos (14U)
screamer 28:0e774865873d 15996 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 15997 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
screamer 28:0e774865873d 15998 #define USART_ISR_ABRF_Pos (15U)
screamer 28:0e774865873d 15999 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 16000 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
screamer 28:0e774865873d 16001 #define USART_ISR_BUSY_Pos (16U)
screamer 28:0e774865873d 16002 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 16003 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
screamer 28:0e774865873d 16004 #define USART_ISR_CMF_Pos (17U)
screamer 28:0e774865873d 16005 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16006 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
screamer 28:0e774865873d 16007 #define USART_ISR_SBKF_Pos (18U)
screamer 28:0e774865873d 16008 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16009 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
screamer 28:0e774865873d 16010 #define USART_ISR_RWU_Pos (19U)
screamer 28:0e774865873d 16011 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16012 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
screamer 28:0e774865873d 16013 #define USART_ISR_WUF_Pos (20U)
screamer 28:0e774865873d 16014 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16015 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
screamer 28:0e774865873d 16016 #define USART_ISR_TEACK_Pos (21U)
screamer 28:0e774865873d 16017 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 16018 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
screamer 28:0e774865873d 16019 #define USART_ISR_REACK_Pos (22U)
screamer 28:0e774865873d 16020 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 16021 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
screamer 28:0e774865873d 16022
screamer 28:0e774865873d 16023 /******************* Bit definition for USART_ICR register ******************/
screamer 28:0e774865873d 16024 #define USART_ICR_PECF_Pos (0U)
screamer 28:0e774865873d 16025 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16026 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
screamer 28:0e774865873d 16027 #define USART_ICR_FECF_Pos (1U)
screamer 28:0e774865873d 16028 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16029 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
screamer 28:0e774865873d 16030 #define USART_ICR_NECF_Pos (2U)
screamer 28:0e774865873d 16031 #define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16032 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
screamer 28:0e774865873d 16033 #define USART_ICR_ORECF_Pos (3U)
screamer 28:0e774865873d 16034 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16035 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
screamer 28:0e774865873d 16036 #define USART_ICR_IDLECF_Pos (4U)
screamer 28:0e774865873d 16037 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16038 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
screamer 28:0e774865873d 16039 #define USART_ICR_TCCF_Pos (6U)
screamer 28:0e774865873d 16040 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16041 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
screamer 28:0e774865873d 16042 #define USART_ICR_LBDCF_Pos (8U)
screamer 28:0e774865873d 16043 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16044 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
screamer 28:0e774865873d 16045 #define USART_ICR_CTSCF_Pos (9U)
screamer 28:0e774865873d 16046 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16047 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
screamer 28:0e774865873d 16048 #define USART_ICR_RTOCF_Pos (11U)
screamer 28:0e774865873d 16049 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16050 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
screamer 28:0e774865873d 16051 #define USART_ICR_EOBCF_Pos (12U)
screamer 28:0e774865873d 16052 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 16053 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
screamer 28:0e774865873d 16054 #define USART_ICR_CMCF_Pos (17U)
screamer 28:0e774865873d 16055 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16056 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
screamer 28:0e774865873d 16057 #define USART_ICR_WUCF_Pos (20U)
screamer 28:0e774865873d 16058 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16059 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
screamer 28:0e774865873d 16060
screamer 28:0e774865873d 16061 /* Legacy defines */
screamer 28:0e774865873d 16062 #define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
screamer 28:0e774865873d 16063 #define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
screamer 28:0e774865873d 16064 #define USART_ICR_NCF USART_ICR_NECF
screamer 28:0e774865873d 16065
screamer 28:0e774865873d 16066 /******************* Bit definition for USART_RDR register ******************/
screamer 28:0e774865873d 16067 #define USART_RDR_RDR_Pos (0U)
screamer 28:0e774865873d 16068 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
screamer 28:0e774865873d 16069 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
screamer 28:0e774865873d 16070
screamer 28:0e774865873d 16071 /******************* Bit definition for USART_TDR register ******************/
screamer 28:0e774865873d 16072 #define USART_TDR_TDR_Pos (0U)
screamer 28:0e774865873d 16073 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
screamer 28:0e774865873d 16074 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
screamer 28:0e774865873d 16075
screamer 28:0e774865873d 16076 /******************************************************************************/
screamer 28:0e774865873d 16077 /* */
screamer 28:0e774865873d 16078 /* Single Wire Protocol Master Interface (SWPMI) */
screamer 28:0e774865873d 16079 /* */
screamer 28:0e774865873d 16080 /******************************************************************************/
screamer 28:0e774865873d 16081
screamer 28:0e774865873d 16082 /******************* Bit definition for SWPMI_CR register ********************/
screamer 28:0e774865873d 16083 #define SWPMI_CR_RXDMA_Pos (0U)
screamer 28:0e774865873d 16084 #define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16085 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
screamer 28:0e774865873d 16086 #define SWPMI_CR_TXDMA_Pos (1U)
screamer 28:0e774865873d 16087 #define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16088 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
screamer 28:0e774865873d 16089 #define SWPMI_CR_RXMODE_Pos (2U)
screamer 28:0e774865873d 16090 #define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16091 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
screamer 28:0e774865873d 16092 #define SWPMI_CR_TXMODE_Pos (3U)
screamer 28:0e774865873d 16093 #define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16094 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
screamer 28:0e774865873d 16095 #define SWPMI_CR_LPBK_Pos (4U)
screamer 28:0e774865873d 16096 #define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16097 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
screamer 28:0e774865873d 16098 #define SWPMI_CR_SWPACT_Pos (5U)
screamer 28:0e774865873d 16099 #define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16100 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
screamer 28:0e774865873d 16101 #define SWPMI_CR_DEACT_Pos (10U)
screamer 28:0e774865873d 16102 #define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16103 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
screamer 28:0e774865873d 16104
screamer 28:0e774865873d 16105 /******************* Bit definition for SWPMI_BRR register ********************/
screamer 28:0e774865873d 16106 #define SWPMI_BRR_BR_Pos (0U)
screamer 28:0e774865873d 16107 #define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
screamer 28:0e774865873d 16108 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
screamer 28:0e774865873d 16109
screamer 28:0e774865873d 16110 /******************* Bit definition for SWPMI_ISR register ********************/
screamer 28:0e774865873d 16111 #define SWPMI_ISR_RXBFF_Pos (0U)
screamer 28:0e774865873d 16112 #define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16113 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
screamer 28:0e774865873d 16114 #define SWPMI_ISR_TXBEF_Pos (1U)
screamer 28:0e774865873d 16115 #define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16116 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
screamer 28:0e774865873d 16117 #define SWPMI_ISR_RXBERF_Pos (2U)
screamer 28:0e774865873d 16118 #define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16119 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
screamer 28:0e774865873d 16120 #define SWPMI_ISR_RXOVRF_Pos (3U)
screamer 28:0e774865873d 16121 #define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16122 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
screamer 28:0e774865873d 16123 #define SWPMI_ISR_TXUNRF_Pos (4U)
screamer 28:0e774865873d 16124 #define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16125 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
screamer 28:0e774865873d 16126 #define SWPMI_ISR_RXNE_Pos (5U)
screamer 28:0e774865873d 16127 #define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16128 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
screamer 28:0e774865873d 16129 #define SWPMI_ISR_TXE_Pos (6U)
screamer 28:0e774865873d 16130 #define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16131 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
screamer 28:0e774865873d 16132 #define SWPMI_ISR_TCF_Pos (7U)
screamer 28:0e774865873d 16133 #define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16134 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
screamer 28:0e774865873d 16135 #define SWPMI_ISR_SRF_Pos (8U)
screamer 28:0e774865873d 16136 #define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16137 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
screamer 28:0e774865873d 16138 #define SWPMI_ISR_SUSP_Pos (9U)
screamer 28:0e774865873d 16139 #define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16140 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
screamer 28:0e774865873d 16141 #define SWPMI_ISR_DEACTF_Pos (10U)
screamer 28:0e774865873d 16142 #define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16143 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
screamer 28:0e774865873d 16144
screamer 28:0e774865873d 16145 /******************* Bit definition for SWPMI_ICR register ********************/
screamer 28:0e774865873d 16146 #define SWPMI_ICR_CRXBFF_Pos (0U)
screamer 28:0e774865873d 16147 #define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16148 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
screamer 28:0e774865873d 16149 #define SWPMI_ICR_CTXBEF_Pos (1U)
screamer 28:0e774865873d 16150 #define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16151 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
screamer 28:0e774865873d 16152 #define SWPMI_ICR_CRXBERF_Pos (2U)
screamer 28:0e774865873d 16153 #define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16154 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
screamer 28:0e774865873d 16155 #define SWPMI_ICR_CRXOVRF_Pos (3U)
screamer 28:0e774865873d 16156 #define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16157 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
screamer 28:0e774865873d 16158 #define SWPMI_ICR_CTXUNRF_Pos (4U)
screamer 28:0e774865873d 16159 #define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16160 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
screamer 28:0e774865873d 16161 #define SWPMI_ICR_CTCF_Pos (7U)
screamer 28:0e774865873d 16162 #define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16163 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
screamer 28:0e774865873d 16164 #define SWPMI_ICR_CSRF_Pos (8U)
screamer 28:0e774865873d 16165 #define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16166 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
screamer 28:0e774865873d 16167
screamer 28:0e774865873d 16168 /******************* Bit definition for SWPMI_IER register ********************/
screamer 28:0e774865873d 16169 #define SWPMI_IER_SRIE_Pos (8U)
screamer 28:0e774865873d 16170 #define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16171 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
screamer 28:0e774865873d 16172 #define SWPMI_IER_TCIE_Pos (7U)
screamer 28:0e774865873d 16173 #define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16174 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
screamer 28:0e774865873d 16175 #define SWPMI_IER_TIE_Pos (6U)
screamer 28:0e774865873d 16176 #define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16177 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
screamer 28:0e774865873d 16178 #define SWPMI_IER_RIE_Pos (5U)
screamer 28:0e774865873d 16179 #define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16180 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
screamer 28:0e774865873d 16181 #define SWPMI_IER_TXUNRIE_Pos (4U)
screamer 28:0e774865873d 16182 #define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16183 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
screamer 28:0e774865873d 16184 #define SWPMI_IER_RXOVRIE_Pos (3U)
screamer 28:0e774865873d 16185 #define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16186 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
screamer 28:0e774865873d 16187 #define SWPMI_IER_RXBERIE_Pos (2U)
screamer 28:0e774865873d 16188 #define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16189 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
screamer 28:0e774865873d 16190 #define SWPMI_IER_TXBEIE_Pos (1U)
screamer 28:0e774865873d 16191 #define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16192 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
screamer 28:0e774865873d 16193 #define SWPMI_IER_RXBFIE_Pos (0U)
screamer 28:0e774865873d 16194 #define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16195 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
screamer 28:0e774865873d 16196
screamer 28:0e774865873d 16197 /******************* Bit definition for SWPMI_RFL register ********************/
screamer 28:0e774865873d 16198 #define SWPMI_RFL_RFL_Pos (0U)
screamer 28:0e774865873d 16199 #define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
screamer 28:0e774865873d 16200 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
screamer 28:0e774865873d 16201 #define SWPMI_RFL_RFL_0_1_Pos (0U)
screamer 28:0e774865873d 16202 #define SWPMI_RFL_RFL_0_1_Msk (0x3U << SWPMI_RFL_RFL_0_1_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 16203 #define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
screamer 28:0e774865873d 16204
screamer 28:0e774865873d 16205 /******************* Bit definition for SWPMI_TDR register ********************/
screamer 28:0e774865873d 16206 #define SWPMI_TDR_TD_Pos (0U)
screamer 28:0e774865873d 16207 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 16208 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
screamer 28:0e774865873d 16209
screamer 28:0e774865873d 16210 /******************* Bit definition for SWPMI_RDR register ********************/
screamer 28:0e774865873d 16211 #define SWPMI_RDR_RD_Pos (0U)
screamer 28:0e774865873d 16212 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 16213 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
screamer 28:0e774865873d 16214
screamer 28:0e774865873d 16215 /******************* Bit definition for SWPMI_OR register ********************/
screamer 28:0e774865873d 16216 #define SWPMI_OR_TBYP_Pos (0U)
screamer 28:0e774865873d 16217 #define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16218 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
screamer 28:0e774865873d 16219 #define SWPMI_OR_CLASS_Pos (1U)
screamer 28:0e774865873d 16220 #define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16221 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
screamer 28:0e774865873d 16222
screamer 28:0e774865873d 16223 /******************************************************************************/
screamer 28:0e774865873d 16224 /* */
screamer 28:0e774865873d 16225 /* VREFBUF */
screamer 28:0e774865873d 16226 /* */
screamer 28:0e774865873d 16227 /******************************************************************************/
screamer 28:0e774865873d 16228 /******************* Bit definition for VREFBUF_CSR register ****************/
screamer 28:0e774865873d 16229 #define VREFBUF_CSR_ENVR_Pos (0U)
screamer 28:0e774865873d 16230 #define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16231 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
screamer 28:0e774865873d 16232 #define VREFBUF_CSR_HIZ_Pos (1U)
screamer 28:0e774865873d 16233 #define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16234 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
screamer 28:0e774865873d 16235 #define VREFBUF_CSR_VRS_Pos (2U)
screamer 28:0e774865873d 16236 #define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16237 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
screamer 28:0e774865873d 16238 #define VREFBUF_CSR_VRR_Pos (3U)
screamer 28:0e774865873d 16239 #define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16240 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
screamer 28:0e774865873d 16241
screamer 28:0e774865873d 16242 /******************* Bit definition for VREFBUF_CCR register ******************/
screamer 28:0e774865873d 16243 #define VREFBUF_CCR_TRIM_Pos (0U)
screamer 28:0e774865873d 16244 #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
screamer 28:0e774865873d 16245 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
screamer 28:0e774865873d 16246
screamer 28:0e774865873d 16247 /******************************************************************************/
screamer 28:0e774865873d 16248 /* */
screamer 28:0e774865873d 16249 /* Window WATCHDOG */
screamer 28:0e774865873d 16250 /* */
screamer 28:0e774865873d 16251 /******************************************************************************/
screamer 28:0e774865873d 16252 /******************* Bit definition for WWDG_CR register ********************/
screamer 28:0e774865873d 16253 #define WWDG_CR_T_Pos (0U)
screamer 28:0e774865873d 16254 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
screamer 28:0e774865873d 16255 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
screamer 28:0e774865873d 16256 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16257 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16258 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16259 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16260 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16261 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16262 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16263
screamer 28:0e774865873d 16264 #define WWDG_CR_WDGA_Pos (7U)
screamer 28:0e774865873d 16265 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16266 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
screamer 28:0e774865873d 16267
screamer 28:0e774865873d 16268 /******************* Bit definition for WWDG_CFR register *******************/
screamer 28:0e774865873d 16269 #define WWDG_CFR_W_Pos (0U)
screamer 28:0e774865873d 16270 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
screamer 28:0e774865873d 16271 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
screamer 28:0e774865873d 16272 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16273 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16274 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16275 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16276 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16277 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16278 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16279
screamer 28:0e774865873d 16280 #define WWDG_CFR_WDGTB_Pos (7U)
screamer 28:0e774865873d 16281 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
screamer 28:0e774865873d 16282 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
screamer 28:0e774865873d 16283 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16284 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16285
screamer 28:0e774865873d 16286 #define WWDG_CFR_EWI_Pos (9U)
screamer 28:0e774865873d 16287 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16288 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
screamer 28:0e774865873d 16289
screamer 28:0e774865873d 16290 /******************* Bit definition for WWDG_SR register ********************/
screamer 28:0e774865873d 16291 #define WWDG_SR_EWIF_Pos (0U)
screamer 28:0e774865873d 16292 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16293 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
screamer 28:0e774865873d 16294
screamer 28:0e774865873d 16295
screamer 28:0e774865873d 16296 /******************************************************************************/
screamer 28:0e774865873d 16297 /* */
screamer 28:0e774865873d 16298 /* Debug MCU */
screamer 28:0e774865873d 16299 /* */
screamer 28:0e774865873d 16300 /******************************************************************************/
screamer 28:0e774865873d 16301 /******************** Bit definition for DBGMCU_IDCODE register *************/
screamer 28:0e774865873d 16302 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
screamer 28:0e774865873d 16303 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 16304 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
screamer 28:0e774865873d 16305 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
screamer 28:0e774865873d 16306 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 16307 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
screamer 28:0e774865873d 16308
screamer 28:0e774865873d 16309 /******************** Bit definition for DBGMCU_CR register *****************/
screamer 28:0e774865873d 16310 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
screamer 28:0e774865873d 16311 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16312 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
screamer 28:0e774865873d 16313 #define DBGMCU_CR_DBG_STOP_Pos (1U)
screamer 28:0e774865873d 16314 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16315 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
screamer 28:0e774865873d 16316 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
screamer 28:0e774865873d 16317 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16318 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
screamer 28:0e774865873d 16319 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
screamer 28:0e774865873d 16320 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16321 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
screamer 28:0e774865873d 16322
screamer 28:0e774865873d 16323 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
screamer 28:0e774865873d 16324 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
screamer 28:0e774865873d 16325 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
screamer 28:0e774865873d 16326 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16327 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16328
screamer 28:0e774865873d 16329 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
screamer 28:0e774865873d 16330 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
screamer 28:0e774865873d 16331 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16332 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
screamer 28:0e774865873d 16333 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
screamer 28:0e774865873d 16334 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16335 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
screamer 28:0e774865873d 16336 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
screamer 28:0e774865873d 16337 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16338 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
screamer 28:0e774865873d 16339 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
screamer 28:0e774865873d 16340 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16341 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
screamer 28:0e774865873d 16342 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
screamer 28:0e774865873d 16343 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16344 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
screamer 28:0e774865873d 16345 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
screamer 28:0e774865873d 16346 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16347 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
screamer 28:0e774865873d 16348 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
screamer 28:0e774865873d 16349 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16350 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
screamer 28:0e774865873d 16351 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
screamer 28:0e774865873d 16352 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16353 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
screamer 28:0e774865873d 16354 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
screamer 28:0e774865873d 16355 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 16356 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
screamer 28:0e774865873d 16357 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
screamer 28:0e774865873d 16358 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 16359 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
screamer 28:0e774865873d 16360 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
screamer 28:0e774865873d 16361 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 16362 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
screamer 28:0e774865873d 16363 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
screamer 28:0e774865873d 16364 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 16365 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
screamer 28:0e774865873d 16366 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
screamer 28:0e774865873d 16367 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 16368 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
screamer 28:0e774865873d 16369 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
screamer 28:0e774865873d 16370 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 16371 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
screamer 28:0e774865873d 16372
screamer 28:0e774865873d 16373 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
screamer 28:0e774865873d 16374 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
screamer 28:0e774865873d 16375 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16376 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
screamer 28:0e774865873d 16377
screamer 28:0e774865873d 16378 /******************** Bit definition for DBGMCU_APB2FZ register ************/
screamer 28:0e774865873d 16379 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
screamer 28:0e774865873d 16380 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16381 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
screamer 28:0e774865873d 16382 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
screamer 28:0e774865873d 16383 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 16384 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
screamer 28:0e774865873d 16385 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
screamer 28:0e774865873d 16386 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 16387 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
screamer 28:0e774865873d 16388 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
screamer 28:0e774865873d 16389 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16390 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
screamer 28:0e774865873d 16391 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
screamer 28:0e774865873d 16392 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16393 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
screamer 28:0e774865873d 16394
screamer 28:0e774865873d 16395 /******************************************************************************/
screamer 28:0e774865873d 16396 /* */
screamer 28:0e774865873d 16397 /* USB_OTG */
screamer 28:0e774865873d 16398 /* */
screamer 28:0e774865873d 16399 /******************************************************************************/
screamer 28:0e774865873d 16400 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
screamer 28:0e774865873d 16401 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
screamer 28:0e774865873d 16402 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16403 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
screamer 28:0e774865873d 16404 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
screamer 28:0e774865873d 16405 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16406 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
screamer 28:0e774865873d 16407 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
screamer 28:0e774865873d 16408 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16409 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
screamer 28:0e774865873d 16410 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
screamer 28:0e774865873d 16411 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16412 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
screamer 28:0e774865873d 16413 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
screamer 28:0e774865873d 16414 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16415 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
screamer 28:0e774865873d 16416 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
screamer 28:0e774865873d 16417 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16418 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
screamer 28:0e774865873d 16419 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
screamer 28:0e774865873d 16420 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16421 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
screamer 28:0e774865873d 16422 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
screamer 28:0e774865873d 16423 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16424 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
screamer 28:0e774865873d 16425 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
screamer 28:0e774865873d 16426 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16427 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
screamer 28:0e774865873d 16428
screamer 28:0e774865873d 16429 /******************** Bit definition for USB_OTG_HCFG register ********************/
screamer 28:0e774865873d 16430
screamer 28:0e774865873d 16431 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
screamer 28:0e774865873d 16432 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 16433 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
screamer 28:0e774865873d 16434 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16435 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16436 #define USB_OTG_HCFG_FSLSS_Pos (2U)
screamer 28:0e774865873d 16437 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16438 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
screamer 28:0e774865873d 16439
screamer 28:0e774865873d 16440 /******************** Bit definition for USB_OTG_DCFG register ********************/
screamer 28:0e774865873d 16441
screamer 28:0e774865873d 16442 #define USB_OTG_DCFG_DSPD_Pos (0U)
screamer 28:0e774865873d 16443 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
screamer 28:0e774865873d 16444 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
screamer 28:0e774865873d 16445 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16446 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16447 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
screamer 28:0e774865873d 16448 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16449 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
screamer 28:0e774865873d 16450 #define USB_OTG_DCFG_DAD_Pos (4U)
screamer 28:0e774865873d 16451 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
screamer 28:0e774865873d 16452 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
screamer 28:0e774865873d 16453 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16454 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16455 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16456 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16457 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16458 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16459 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16460 #define USB_OTG_DCFG_PFIVL_Pos (11U)
screamer 28:0e774865873d 16461 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
screamer 28:0e774865873d 16462 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
screamer 28:0e774865873d 16463 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16464 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 16465 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
screamer 28:0e774865873d 16466 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
screamer 28:0e774865873d 16467 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
screamer 28:0e774865873d 16468 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 16469 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 16470
screamer 28:0e774865873d 16471 /******************** Bit definition for USB_OTG_PCGCR register ********************/
screamer 28:0e774865873d 16472 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
screamer 28:0e774865873d 16473 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16474 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
screamer 28:0e774865873d 16475 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
screamer 28:0e774865873d 16476 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16477 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
screamer 28:0e774865873d 16478 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
screamer 28:0e774865873d 16479 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16480 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
screamer 28:0e774865873d 16481
screamer 28:0e774865873d 16482 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
screamer 28:0e774865873d 16483 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
screamer 28:0e774865873d 16484 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16485 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
screamer 28:0e774865873d 16486 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
screamer 28:0e774865873d 16487 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16488 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
screamer 28:0e774865873d 16489 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
screamer 28:0e774865873d 16490 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16491 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
screamer 28:0e774865873d 16492 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
screamer 28:0e774865873d 16493 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16494 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
screamer 28:0e774865873d 16495 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
screamer 28:0e774865873d 16496 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16497 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
screamer 28:0e774865873d 16498 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
screamer 28:0e774865873d 16499 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16500 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
screamer 28:0e774865873d 16501
screamer 28:0e774865873d 16502 /******************** Bit definition for USB_OTG_DCTL register ********************/
screamer 28:0e774865873d 16503 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
screamer 28:0e774865873d 16504 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16505 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
screamer 28:0e774865873d 16506 #define USB_OTG_DCTL_SDIS_Pos (1U)
screamer 28:0e774865873d 16507 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16508 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
screamer 28:0e774865873d 16509 #define USB_OTG_DCTL_GINSTS_Pos (2U)
screamer 28:0e774865873d 16510 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16511 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
screamer 28:0e774865873d 16512 #define USB_OTG_DCTL_GONSTS_Pos (3U)
screamer 28:0e774865873d 16513 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16514 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
screamer 28:0e774865873d 16515
screamer 28:0e774865873d 16516 #define USB_OTG_DCTL_TCTL_Pos (4U)
screamer 28:0e774865873d 16517 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
screamer 28:0e774865873d 16518 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
screamer 28:0e774865873d 16519 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16520 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16521 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16522 #define USB_OTG_DCTL_SGINAK_Pos (7U)
screamer 28:0e774865873d 16523 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16524 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
screamer 28:0e774865873d 16525 #define USB_OTG_DCTL_CGINAK_Pos (8U)
screamer 28:0e774865873d 16526 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16527 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
screamer 28:0e774865873d 16528 #define USB_OTG_DCTL_SGONAK_Pos (9U)
screamer 28:0e774865873d 16529 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16530 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
screamer 28:0e774865873d 16531 #define USB_OTG_DCTL_CGONAK_Pos (10U)
screamer 28:0e774865873d 16532 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16533 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
screamer 28:0e774865873d 16534 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
screamer 28:0e774865873d 16535 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16536 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
screamer 28:0e774865873d 16537
screamer 28:0e774865873d 16538 /******************** Bit definition for USB_OTG_HFIR register ********************/
screamer 28:0e774865873d 16539 #define USB_OTG_HFIR_FRIVL_Pos (0U)
screamer 28:0e774865873d 16540 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16541 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
screamer 28:0e774865873d 16542
screamer 28:0e774865873d 16543 /******************** Bit definition for USB_OTG_HFNUM register ********************/
screamer 28:0e774865873d 16544 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
screamer 28:0e774865873d 16545 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16546 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
screamer 28:0e774865873d 16547 #define USB_OTG_HFNUM_FTREM_Pos (16U)
screamer 28:0e774865873d 16548 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 16549 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
screamer 28:0e774865873d 16550
screamer 28:0e774865873d 16551 /******************** Bit definition for USB_OTG_DSTS register ********************/
screamer 28:0e774865873d 16552 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
screamer 28:0e774865873d 16553 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16554 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
screamer 28:0e774865873d 16555
screamer 28:0e774865873d 16556 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
screamer 28:0e774865873d 16557 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
screamer 28:0e774865873d 16558 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
screamer 28:0e774865873d 16559 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16560 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16561 #define USB_OTG_DSTS_EERR_Pos (3U)
screamer 28:0e774865873d 16562 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16563 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
screamer 28:0e774865873d 16564 #define USB_OTG_DSTS_FNSOF_Pos (8U)
screamer 28:0e774865873d 16565 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
screamer 28:0e774865873d 16566 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
screamer 28:0e774865873d 16567
screamer 28:0e774865873d 16568 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
screamer 28:0e774865873d 16569 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
screamer 28:0e774865873d 16570 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16571 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
screamer 28:0e774865873d 16572 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
screamer 28:0e774865873d 16573 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
screamer 28:0e774865873d 16574 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
screamer 28:0e774865873d 16575 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16576 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16577 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16578 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16579 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
screamer 28:0e774865873d 16580 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16581 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
screamer 28:0e774865873d 16582 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
screamer 28:0e774865873d 16583 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16584 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
screamer 28:0e774865873d 16585 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
screamer 28:0e774865873d 16586 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16587 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
screamer 28:0e774865873d 16588
screamer 28:0e774865873d 16589 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
screamer 28:0e774865873d 16590
screamer 28:0e774865873d 16591 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
screamer 28:0e774865873d 16592 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
screamer 28:0e774865873d 16593 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
screamer 28:0e774865873d 16594 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16595 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16596 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16597 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
screamer 28:0e774865873d 16598 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16599 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
screamer 28:0e774865873d 16600 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
screamer 28:0e774865873d 16601 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16602 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
screamer 28:0e774865873d 16603 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
screamer 28:0e774865873d 16604 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16605 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
screamer 28:0e774865873d 16606 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
screamer 28:0e774865873d 16607 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
screamer 28:0e774865873d 16608 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
screamer 28:0e774865873d 16609 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16610 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16611 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 16612 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 16613 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
screamer 28:0e774865873d 16614 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 16615 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
screamer 28:0e774865873d 16616 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
screamer 28:0e774865873d 16617 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16618 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
screamer 28:0e774865873d 16619 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
screamer 28:0e774865873d 16620 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16621 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
screamer 28:0e774865873d 16622 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
screamer 28:0e774865873d 16623 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16624 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
screamer 28:0e774865873d 16625 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
screamer 28:0e774865873d 16626 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16627 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
screamer 28:0e774865873d 16628 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
screamer 28:0e774865873d 16629 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 16630 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
screamer 28:0e774865873d 16631 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
screamer 28:0e774865873d 16632 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 16633 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
screamer 28:0e774865873d 16634 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
screamer 28:0e774865873d 16635 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 16636 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
screamer 28:0e774865873d 16637 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
screamer 28:0e774865873d 16638 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 16639 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
screamer 28:0e774865873d 16640 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
screamer 28:0e774865873d 16641 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 16642 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
screamer 28:0e774865873d 16643 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
screamer 28:0e774865873d 16644 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 16645 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
screamer 28:0e774865873d 16646 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
screamer 28:0e774865873d 16647 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 16648 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
screamer 28:0e774865873d 16649 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
screamer 28:0e774865873d 16650 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 16651 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
screamer 28:0e774865873d 16652
screamer 28:0e774865873d 16653 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
screamer 28:0e774865873d 16654 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
screamer 28:0e774865873d 16655 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16656 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
screamer 28:0e774865873d 16657 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
screamer 28:0e774865873d 16658 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16659 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
screamer 28:0e774865873d 16660 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
screamer 28:0e774865873d 16661 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16662 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
screamer 28:0e774865873d 16663 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
screamer 28:0e774865873d 16664 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16665 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
screamer 28:0e774865873d 16666 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
screamer 28:0e774865873d 16667 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16668 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
screamer 28:0e774865873d 16669 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
screamer 28:0e774865873d 16670 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
screamer 28:0e774865873d 16671 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
screamer 28:0e774865873d 16672 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16673 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16674 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16675 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16676 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16677 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
screamer 28:0e774865873d 16678 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 16679 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
screamer 28:0e774865873d 16680 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
screamer 28:0e774865873d 16681 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 16682 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
screamer 28:0e774865873d 16683
screamer 28:0e774865873d 16684 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
screamer 28:0e774865873d 16685 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
screamer 28:0e774865873d 16686 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16687 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
screamer 28:0e774865873d 16688 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
screamer 28:0e774865873d 16689 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16690 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
screamer 28:0e774865873d 16691 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
screamer 28:0e774865873d 16692 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16693 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
screamer 28:0e774865873d 16694 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
screamer 28:0e774865873d 16695 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16696 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
screamer 28:0e774865873d 16697 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
screamer 28:0e774865873d 16698 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16699 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
screamer 28:0e774865873d 16700 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
screamer 28:0e774865873d 16701 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16702 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
screamer 28:0e774865873d 16703 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
screamer 28:0e774865873d 16704 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16705 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
screamer 28:0e774865873d 16706 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
screamer 28:0e774865873d 16707 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16708 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
screamer 28:0e774865873d 16709
screamer 28:0e774865873d 16710 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
screamer 28:0e774865873d 16711 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
screamer 28:0e774865873d 16712 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16713 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
screamer 28:0e774865873d 16714 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
screamer 28:0e774865873d 16715 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 16716 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
screamer 28:0e774865873d 16717 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 16718 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16719 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16720 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16721 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16722 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 16723 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 16724 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 16725
screamer 28:0e774865873d 16726 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
screamer 28:0e774865873d 16727 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
screamer 28:0e774865873d 16728 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
screamer 28:0e774865873d 16729 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 16730 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 16731 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 16732 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 16733 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 16734 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 16735 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 16736 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 16737
screamer 28:0e774865873d 16738 /******************** Bit definition for USB_OTG_HAINT register ********************/
screamer 28:0e774865873d 16739 #define USB_OTG_HAINT_HAINT_Pos (0U)
screamer 28:0e774865873d 16740 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16741 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
screamer 28:0e774865873d 16742
screamer 28:0e774865873d 16743 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
screamer 28:0e774865873d 16744 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
screamer 28:0e774865873d 16745 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16746 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
screamer 28:0e774865873d 16747 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
screamer 28:0e774865873d 16748 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16749 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
screamer 28:0e774865873d 16750 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
screamer 28:0e774865873d 16751 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16752 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
screamer 28:0e774865873d 16753 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
screamer 28:0e774865873d 16754 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16755 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
screamer 28:0e774865873d 16756 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
screamer 28:0e774865873d 16757 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16758 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
screamer 28:0e774865873d 16759 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
screamer 28:0e774865873d 16760 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 16761 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
screamer 28:0e774865873d 16762 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
screamer 28:0e774865873d 16763 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 16764 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
screamer 28:0e774865873d 16765
screamer 28:0e774865873d 16766 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
screamer 28:0e774865873d 16767 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
screamer 28:0e774865873d 16768 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16769 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
screamer 28:0e774865873d 16770 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
screamer 28:0e774865873d 16771 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16772 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
screamer 28:0e774865873d 16773 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
screamer 28:0e774865873d 16774 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16775 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
screamer 28:0e774865873d 16776 #define USB_OTG_GINTSTS_SOF_Pos (3U)
screamer 28:0e774865873d 16777 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16778 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
screamer 28:0e774865873d 16779 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
screamer 28:0e774865873d 16780 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16781 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
screamer 28:0e774865873d 16782 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
screamer 28:0e774865873d 16783 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16784 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
screamer 28:0e774865873d 16785 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
screamer 28:0e774865873d 16786 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16787 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
screamer 28:0e774865873d 16788 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
screamer 28:0e774865873d 16789 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16790 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
screamer 28:0e774865873d 16791 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
screamer 28:0e774865873d 16792 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16793 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
screamer 28:0e774865873d 16794 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
screamer 28:0e774865873d 16795 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16796 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
screamer 28:0e774865873d 16797 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
screamer 28:0e774865873d 16798 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 16799 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
screamer 28:0e774865873d 16800 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
screamer 28:0e774865873d 16801 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 16802 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
screamer 28:0e774865873d 16803 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
screamer 28:0e774865873d 16804 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 16805 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
screamer 28:0e774865873d 16806 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
screamer 28:0e774865873d 16807 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 16808 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
screamer 28:0e774865873d 16809 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
screamer 28:0e774865873d 16810 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16811 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
screamer 28:0e774865873d 16812 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
screamer 28:0e774865873d 16813 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16814 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
screamer 28:0e774865873d 16815 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
screamer 28:0e774865873d 16816 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16817 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
screamer 28:0e774865873d 16818 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
screamer 28:0e774865873d 16819 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 16820 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
screamer 28:0e774865873d 16821 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
screamer 28:0e774865873d 16822 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 16823 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
screamer 28:0e774865873d 16824 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
screamer 28:0e774865873d 16825 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 16826 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
screamer 28:0e774865873d 16827 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
screamer 28:0e774865873d 16828 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 16829 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
screamer 28:0e774865873d 16830 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
screamer 28:0e774865873d 16831 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 16832 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
screamer 28:0e774865873d 16833 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
screamer 28:0e774865873d 16834 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 16835 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
screamer 28:0e774865873d 16836 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
screamer 28:0e774865873d 16837 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 16838 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
screamer 28:0e774865873d 16839 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
screamer 28:0e774865873d 16840 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 16841 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
screamer 28:0e774865873d 16842 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
screamer 28:0e774865873d 16843 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 16844 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
screamer 28:0e774865873d 16845 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
screamer 28:0e774865873d 16846 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 16847 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
screamer 28:0e774865873d 16848
screamer 28:0e774865873d 16849 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
screamer 28:0e774865873d 16850
screamer 28:0e774865873d 16851 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
screamer 28:0e774865873d 16852 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16853 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
screamer 28:0e774865873d 16854 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
screamer 28:0e774865873d 16855 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16856 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
screamer 28:0e774865873d 16857 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
screamer 28:0e774865873d 16858 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16859 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
screamer 28:0e774865873d 16860 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
screamer 28:0e774865873d 16861 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 16862 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
screamer 28:0e774865873d 16863 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
screamer 28:0e774865873d 16864 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 16865 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
screamer 28:0e774865873d 16866 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
screamer 28:0e774865873d 16867 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 16868 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
screamer 28:0e774865873d 16869 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
screamer 28:0e774865873d 16870 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 16871 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
screamer 28:0e774865873d 16872 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
screamer 28:0e774865873d 16873 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 16874 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
screamer 28:0e774865873d 16875 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
screamer 28:0e774865873d 16876 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 16877 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
screamer 28:0e774865873d 16878 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
screamer 28:0e774865873d 16879 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 16880 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
screamer 28:0e774865873d 16881 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
screamer 28:0e774865873d 16882 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 16883 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
screamer 28:0e774865873d 16884 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
screamer 28:0e774865873d 16885 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 16886 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
screamer 28:0e774865873d 16887 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
screamer 28:0e774865873d 16888 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 16889 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
screamer 28:0e774865873d 16890 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
screamer 28:0e774865873d 16891 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16892 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
screamer 28:0e774865873d 16893 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
screamer 28:0e774865873d 16894 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16895 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
screamer 28:0e774865873d 16896 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
screamer 28:0e774865873d 16897 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16898 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
screamer 28:0e774865873d 16899 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
screamer 28:0e774865873d 16900 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16901 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
screamer 28:0e774865873d 16902 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
screamer 28:0e774865873d 16903 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 16904 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
screamer 28:0e774865873d 16905 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
screamer 28:0e774865873d 16906 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 16907 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
screamer 28:0e774865873d 16908 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
screamer 28:0e774865873d 16909 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 16910 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
screamer 28:0e774865873d 16911 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
screamer 28:0e774865873d 16912 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 16913 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
screamer 28:0e774865873d 16914 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
screamer 28:0e774865873d 16915 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 16916 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
screamer 28:0e774865873d 16917 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
screamer 28:0e774865873d 16918 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 16919 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
screamer 28:0e774865873d 16920 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
screamer 28:0e774865873d 16921 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 16922 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
screamer 28:0e774865873d 16923 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
screamer 28:0e774865873d 16924 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 16925 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
screamer 28:0e774865873d 16926 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
screamer 28:0e774865873d 16927 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 16928 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
screamer 28:0e774865873d 16929 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
screamer 28:0e774865873d 16930 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 16931 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
screamer 28:0e774865873d 16932
screamer 28:0e774865873d 16933 /******************** Bit definition for USB_OTG_DAINT register ********************/
screamer 28:0e774865873d 16934 #define USB_OTG_DAINT_IEPINT_Pos (0U)
screamer 28:0e774865873d 16935 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16936 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
screamer 28:0e774865873d 16937 #define USB_OTG_DAINT_OEPINT_Pos (16U)
screamer 28:0e774865873d 16938 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 16939 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
screamer 28:0e774865873d 16940
screamer 28:0e774865873d 16941 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
screamer 28:0e774865873d 16942 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
screamer 28:0e774865873d 16943 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16944 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
screamer 28:0e774865873d 16945
screamer 28:0e774865873d 16946 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
screamer 28:0e774865873d 16947 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
screamer 28:0e774865873d 16948 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 16949 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
screamer 28:0e774865873d 16950 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
screamer 28:0e774865873d 16951 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
screamer 28:0e774865873d 16952 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
screamer 28:0e774865873d 16953 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
screamer 28:0e774865873d 16954 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
screamer 28:0e774865873d 16955 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
screamer 28:0e774865873d 16956 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
screamer 28:0e774865873d 16957 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
screamer 28:0e774865873d 16958 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
screamer 28:0e774865873d 16959
screamer 28:0e774865873d 16960 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
screamer 28:0e774865873d 16961 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
screamer 28:0e774865873d 16962 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 16963 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
screamer 28:0e774865873d 16964 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
screamer 28:0e774865873d 16965 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 16966 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
screamer 28:0e774865873d 16967
screamer 28:0e774865873d 16968 /******************** Bit definition for OTG register ********************/
screamer 28:0e774865873d 16969
screamer 28:0e774865873d 16970 #define USB_OTG_CHNUM_Pos (0U)
screamer 28:0e774865873d 16971 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 16972 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
screamer 28:0e774865873d 16973 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16974 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16975 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16976 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16977 #define USB_OTG_BCNT_Pos (4U)
screamer 28:0e774865873d 16978 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
screamer 28:0e774865873d 16979 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
screamer 28:0e774865873d 16980 #define USB_OTG_DPID_Pos (15U)
screamer 28:0e774865873d 16981 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
screamer 28:0e774865873d 16982 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
screamer 28:0e774865873d 16983 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 16984 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 16985 #define USB_OTG_PKTSTS_Pos (17U)
screamer 28:0e774865873d 16986 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
screamer 28:0e774865873d 16987 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
screamer 28:0e774865873d 16988 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 16989 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 16990 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 16991 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 16992 #define USB_OTG_EPNUM_Pos (0U)
screamer 28:0e774865873d 16993 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 16994 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
screamer 28:0e774865873d 16995 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 16996 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 16997 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 16998 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 16999 #define USB_OTG_FRMNUM_Pos (21U)
screamer 28:0e774865873d 17000 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
screamer 28:0e774865873d 17001 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
screamer 28:0e774865873d 17002 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17003 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 17004 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 17005 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17006
screamer 28:0e774865873d 17007 /******************** Bit definition for OTG register ********************/
screamer 28:0e774865873d 17008
screamer 28:0e774865873d 17009 #define USB_OTG_CHNUM_Pos (0U)
screamer 28:0e774865873d 17010 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 17011 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
screamer 28:0e774865873d 17012 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17013 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17014 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17015 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17016 #define USB_OTG_BCNT_Pos (4U)
screamer 28:0e774865873d 17017 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
screamer 28:0e774865873d 17018 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
screamer 28:0e774865873d 17019 #define USB_OTG_DPID_Pos (15U)
screamer 28:0e774865873d 17020 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
screamer 28:0e774865873d 17021 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
screamer 28:0e774865873d 17022 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17023 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17024 #define USB_OTG_PKTSTS_Pos (17U)
screamer 28:0e774865873d 17025 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
screamer 28:0e774865873d 17026 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
screamer 28:0e774865873d 17027 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17028 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17029 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17030 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 17031 #define USB_OTG_EPNUM_Pos (0U)
screamer 28:0e774865873d 17032 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
screamer 28:0e774865873d 17033 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
screamer 28:0e774865873d 17034 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17035 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17036 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17037 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17038 #define USB_OTG_FRMNUM_Pos (21U)
screamer 28:0e774865873d 17039 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
screamer 28:0e774865873d 17040 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
screamer 28:0e774865873d 17041 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17042 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 17043 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 17044 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17045
screamer 28:0e774865873d 17046 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
screamer 28:0e774865873d 17047 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
screamer 28:0e774865873d 17048 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17049 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
screamer 28:0e774865873d 17050
screamer 28:0e774865873d 17051 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
screamer 28:0e774865873d 17052 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
screamer 28:0e774865873d 17053 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17054 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
screamer 28:0e774865873d 17055
screamer 28:0e774865873d 17056 /******************** Bit definition for OTG register ********************/
screamer 28:0e774865873d 17057 #define USB_OTG_NPTXFSA_Pos (0U)
screamer 28:0e774865873d 17058 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17059 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
screamer 28:0e774865873d 17060 #define USB_OTG_NPTXFD_Pos (16U)
screamer 28:0e774865873d 17061 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 17062 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
screamer 28:0e774865873d 17063 #define USB_OTG_TX0FSA_Pos (0U)
screamer 28:0e774865873d 17064 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17065 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
screamer 28:0e774865873d 17066 #define USB_OTG_TX0FD_Pos (16U)
screamer 28:0e774865873d 17067 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 17068 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
screamer 28:0e774865873d 17069
screamer 28:0e774865873d 17070 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
screamer 28:0e774865873d 17071 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
screamer 28:0e774865873d 17072 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
screamer 28:0e774865873d 17073 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
screamer 28:0e774865873d 17074
screamer 28:0e774865873d 17075 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
screamer 28:0e774865873d 17076 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
screamer 28:0e774865873d 17077 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17078 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
screamer 28:0e774865873d 17079
screamer 28:0e774865873d 17080 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
screamer 28:0e774865873d 17081 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
screamer 28:0e774865873d 17082 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
screamer 28:0e774865873d 17083 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17084 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17085 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17086 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17087 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 17088 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17089 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 17090 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 17091
screamer 28:0e774865873d 17092 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
screamer 28:0e774865873d 17093 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
screamer 28:0e774865873d 17094 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
screamer 28:0e774865873d 17095 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17096 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 17097 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 17098 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 17099 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 17100 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 17101 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 17102
screamer 28:0e774865873d 17103 /******************** Bit definition for USB_OTG_DTHRCTL register ***************/
screamer 28:0e774865873d 17104 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
screamer 28:0e774865873d 17105 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17106 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
screamer 28:0e774865873d 17107 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
screamer 28:0e774865873d 17108 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17109 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
screamer 28:0e774865873d 17110
screamer 28:0e774865873d 17111 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
screamer 28:0e774865873d 17112 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
screamer 28:0e774865873d 17113 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
screamer 28:0e774865873d 17114 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17115 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17116 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17117 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17118 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17119 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17120 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17121 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17122 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 17123 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
screamer 28:0e774865873d 17124 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17125 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
screamer 28:0e774865873d 17126
screamer 28:0e774865873d 17127 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
screamer 28:0e774865873d 17128 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
screamer 28:0e774865873d 17129 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
screamer 28:0e774865873d 17130 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17131 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17132 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17133 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 17134 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17135 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 17136 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 17137 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17138 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 17139 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
screamer 28:0e774865873d 17140 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 17141 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
screamer 28:0e774865873d 17142
screamer 28:0e774865873d 17143 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
screamer 28:0e774865873d 17144 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
screamer 28:0e774865873d 17145 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17146 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
screamer 28:0e774865873d 17147
screamer 28:0e774865873d 17148 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
screamer 28:0e774865873d 17149 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
screamer 28:0e774865873d 17150 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17151 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
screamer 28:0e774865873d 17152 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
screamer 28:0e774865873d 17153 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17154 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
screamer 28:0e774865873d 17155
screamer 28:0e774865873d 17156 /******************** Bit definition for USB_OTG_GCCFG register ********************/
screamer 28:0e774865873d 17157 #define USB_OTG_GCCFG_DCDET_Pos (0U)
screamer 28:0e774865873d 17158 #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17159 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
screamer 28:0e774865873d 17160 #define USB_OTG_GCCFG_PDET_Pos (1U)
screamer 28:0e774865873d 17161 #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17162 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
screamer 28:0e774865873d 17163 #define USB_OTG_GCCFG_SDET_Pos (2U)
screamer 28:0e774865873d 17164 #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17165 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
screamer 28:0e774865873d 17166 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
screamer 28:0e774865873d 17167 #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17168 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
screamer 28:0e774865873d 17169 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
screamer 28:0e774865873d 17170 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17171 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
screamer 28:0e774865873d 17172 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
screamer 28:0e774865873d 17173 #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17174 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
screamer 28:0e774865873d 17175 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
screamer 28:0e774865873d 17176 #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17177 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
screamer 28:0e774865873d 17178 #define USB_OTG_GCCFG_PDEN_Pos (19U)
screamer 28:0e774865873d 17179 #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17180 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
screamer 28:0e774865873d 17181 #define USB_OTG_GCCFG_SDEN_Pos (20U)
screamer 28:0e774865873d 17182 #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 17183 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
screamer 28:0e774865873d 17184 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
screamer 28:0e774865873d 17185 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17186 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
screamer 28:0e774865873d 17187
screamer 28:0e774865873d 17188 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
screamer 28:0e774865873d 17189 #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
screamer 28:0e774865873d 17190 #define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17191 #define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
screamer 28:0e774865873d 17192
screamer 28:0e774865873d 17193 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
screamer 28:0e774865873d 17194 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
screamer 28:0e774865873d 17195 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17196 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
screamer 28:0e774865873d 17197 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
screamer 28:0e774865873d 17198 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17199 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
screamer 28:0e774865873d 17200
screamer 28:0e774865873d 17201 /******************** Bit definition for USB_OTG_CID register ********************/
screamer 28:0e774865873d 17202 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
screamer 28:0e774865873d 17203 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 17204 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
screamer 28:0e774865873d 17205
screamer 28:0e774865873d 17206
screamer 28:0e774865873d 17207 /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
screamer 28:0e774865873d 17208 #define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
screamer 28:0e774865873d 17209 #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 17210 #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
screamer 28:0e774865873d 17211
screamer 28:0e774865873d 17212 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
screamer 28:0e774865873d 17213 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
screamer 28:0e774865873d 17214 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 17215 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
screamer 28:0e774865873d 17216 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
screamer 28:0e774865873d 17217 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
screamer 28:0e774865873d 17218 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
screamer 28:0e774865873d 17219 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
screamer 28:0e774865873d 17220 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17221 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
screamer 28:0e774865873d 17222 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
screamer 28:0e774865873d 17223 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
screamer 28:0e774865873d 17224 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
screamer 28:0e774865873d 17225 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
screamer 28:0e774865873d 17226 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
screamer 28:0e774865873d 17227 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
screamer 28:0e774865873d 17228 #define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
screamer 28:0e774865873d 17229 #define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17230 #define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
screamer 28:0e774865873d 17231 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
screamer 28:0e774865873d 17232 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17233 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
screamer 28:0e774865873d 17234 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
screamer 28:0e774865873d 17235 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
screamer 28:0e774865873d 17236 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
screamer 28:0e774865873d 17237 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
screamer 28:0e774865873d 17238 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 17239 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
screamer 28:0e774865873d 17240 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
screamer 28:0e774865873d 17241 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
screamer 28:0e774865873d 17242 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
screamer 28:0e774865873d 17243 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
screamer 28:0e774865873d 17244 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17245 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
screamer 28:0e774865873d 17246 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
screamer 28:0e774865873d 17247 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17248 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
screamer 28:0e774865873d 17249 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
screamer 28:0e774865873d 17250 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
screamer 28:0e774865873d 17251 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
screamer 28:0e774865873d 17252 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
screamer 28:0e774865873d 17253 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17254 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
screamer 28:0e774865873d 17255 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
screamer 28:0e774865873d 17256 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17257 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
screamer 28:0e774865873d 17258
screamer 28:0e774865873d 17259
screamer 28:0e774865873d 17260 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
screamer 28:0e774865873d 17261 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
screamer 28:0e774865873d 17262 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17263 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
screamer 28:0e774865873d 17264 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
screamer 28:0e774865873d 17265 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17266 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
screamer 28:0e774865873d 17267 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
screamer 28:0e774865873d 17268 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17269 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
screamer 28:0e774865873d 17270 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
screamer 28:0e774865873d 17271 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17272 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
screamer 28:0e774865873d 17273 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
screamer 28:0e774865873d 17274 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17275 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
screamer 28:0e774865873d 17276 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
screamer 28:0e774865873d 17277 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17278 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
screamer 28:0e774865873d 17279 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
screamer 28:0e774865873d 17280 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17281 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
screamer 28:0e774865873d 17282 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
screamer 28:0e774865873d 17283 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17284 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
screamer 28:0e774865873d 17285 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
screamer 28:0e774865873d 17286 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 17287 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
screamer 28:0e774865873d 17288
screamer 28:0e774865873d 17289 /******************** Bit definition for USB_OTG_HPRT register ********************/
screamer 28:0e774865873d 17290 #define USB_OTG_HPRT_PCSTS_Pos (0U)
screamer 28:0e774865873d 17291 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17292 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
screamer 28:0e774865873d 17293 #define USB_OTG_HPRT_PCDET_Pos (1U)
screamer 28:0e774865873d 17294 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17295 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
screamer 28:0e774865873d 17296 #define USB_OTG_HPRT_PENA_Pos (2U)
screamer 28:0e774865873d 17297 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17298 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
screamer 28:0e774865873d 17299 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
screamer 28:0e774865873d 17300 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17301 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
screamer 28:0e774865873d 17302 #define USB_OTG_HPRT_POCA_Pos (4U)
screamer 28:0e774865873d 17303 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17304 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
screamer 28:0e774865873d 17305 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
screamer 28:0e774865873d 17306 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17307 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
screamer 28:0e774865873d 17308 #define USB_OTG_HPRT_PRES_Pos (6U)
screamer 28:0e774865873d 17309 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17310 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
screamer 28:0e774865873d 17311 #define USB_OTG_HPRT_PSUSP_Pos (7U)
screamer 28:0e774865873d 17312 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17313 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
screamer 28:0e774865873d 17314 #define USB_OTG_HPRT_PRST_Pos (8U)
screamer 28:0e774865873d 17315 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17316 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
screamer 28:0e774865873d 17317
screamer 28:0e774865873d 17318 #define USB_OTG_HPRT_PLSTS_Pos (10U)
screamer 28:0e774865873d 17319 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
screamer 28:0e774865873d 17320 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
screamer 28:0e774865873d 17321 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 17322 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 17323 #define USB_OTG_HPRT_PPWR_Pos (12U)
screamer 28:0e774865873d 17324 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 17325 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
screamer 28:0e774865873d 17326
screamer 28:0e774865873d 17327 #define USB_OTG_HPRT_PTCTL_Pos (13U)
screamer 28:0e774865873d 17328 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
screamer 28:0e774865873d 17329 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
screamer 28:0e774865873d 17330 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 17331 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 17332 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17333 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17334
screamer 28:0e774865873d 17335 #define USB_OTG_HPRT_PSPD_Pos (17U)
screamer 28:0e774865873d 17336 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
screamer 28:0e774865873d 17337 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
screamer 28:0e774865873d 17338 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17339 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17340
screamer 28:0e774865873d 17341 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
screamer 28:0e774865873d 17342 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
screamer 28:0e774865873d 17343 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17344 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
screamer 28:0e774865873d 17345 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
screamer 28:0e774865873d 17346 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17347 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
screamer 28:0e774865873d 17348 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
screamer 28:0e774865873d 17349 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17350 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
screamer 28:0e774865873d 17351 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
screamer 28:0e774865873d 17352 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17353 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
screamer 28:0e774865873d 17354 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
screamer 28:0e774865873d 17355 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17356 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
screamer 28:0e774865873d 17357 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
screamer 28:0e774865873d 17358 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17359 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
screamer 28:0e774865873d 17360 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
screamer 28:0e774865873d 17361 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17362 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
screamer 28:0e774865873d 17363 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
screamer 28:0e774865873d 17364 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17365 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
screamer 28:0e774865873d 17366 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
screamer 28:0e774865873d 17367 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 17368 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
screamer 28:0e774865873d 17369 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
screamer 28:0e774865873d 17370 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 17371 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
screamer 28:0e774865873d 17372 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
screamer 28:0e774865873d 17373 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 17374 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
screamer 28:0e774865873d 17375
screamer 28:0e774865873d 17376 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
screamer 28:0e774865873d 17377 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
screamer 28:0e774865873d 17378 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17379 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
screamer 28:0e774865873d 17380 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
screamer 28:0e774865873d 17381 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 17382 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
screamer 28:0e774865873d 17383
screamer 28:0e774865873d 17384 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
screamer 28:0e774865873d 17385 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
screamer 28:0e774865873d 17386 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
screamer 28:0e774865873d 17387 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
screamer 28:0e774865873d 17388 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
screamer 28:0e774865873d 17389 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17390 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
screamer 28:0e774865873d 17391 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
screamer 28:0e774865873d 17392 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17393 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
screamer 28:0e774865873d 17394 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
screamer 28:0e774865873d 17395 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17396 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
screamer 28:0e774865873d 17397
screamer 28:0e774865873d 17398 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
screamer 28:0e774865873d 17399 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 17400 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
screamer 28:0e774865873d 17401 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17402 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17403 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
screamer 28:0e774865873d 17404 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17405 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
screamer 28:0e774865873d 17406
screamer 28:0e774865873d 17407 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
screamer 28:0e774865873d 17408 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
screamer 28:0e774865873d 17409 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
screamer 28:0e774865873d 17410 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 17411 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 17412 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17413 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 17414 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
screamer 28:0e774865873d 17415 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 17416 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
screamer 28:0e774865873d 17417 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
screamer 28:0e774865873d 17418 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 17419 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
screamer 28:0e774865873d 17420 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
screamer 28:0e774865873d 17421 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 17422 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
screamer 28:0e774865873d 17423 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
screamer 28:0e774865873d 17424 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 17425 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
screamer 28:0e774865873d 17426 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
screamer 28:0e774865873d 17427 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 17428 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
screamer 28:0e774865873d 17429 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
screamer 28:0e774865873d 17430 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 17431 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
screamer 28:0e774865873d 17432
screamer 28:0e774865873d 17433 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
screamer 28:0e774865873d 17434 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
screamer 28:0e774865873d 17435 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
screamer 28:0e774865873d 17436 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
screamer 28:0e774865873d 17437
screamer 28:0e774865873d 17438 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
screamer 28:0e774865873d 17439 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
screamer 28:0e774865873d 17440 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
screamer 28:0e774865873d 17441 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 17442 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 17443 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 17444 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 17445 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
screamer 28:0e774865873d 17446 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17447 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
screamer 28:0e774865873d 17448 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
screamer 28:0e774865873d 17449 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17450 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
screamer 28:0e774865873d 17451
screamer 28:0e774865873d 17452 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
screamer 28:0e774865873d 17453 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 17454 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
screamer 28:0e774865873d 17455 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17456 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17457
screamer 28:0e774865873d 17458 #define USB_OTG_HCCHAR_MC_Pos (20U)
screamer 28:0e774865873d 17459 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
screamer 28:0e774865873d 17460 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
screamer 28:0e774865873d 17461 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 17462 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17463
screamer 28:0e774865873d 17464 #define USB_OTG_HCCHAR_DAD_Pos (22U)
screamer 28:0e774865873d 17465 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
screamer 28:0e774865873d 17466 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
screamer 28:0e774865873d 17467 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
screamer 28:0e774865873d 17468 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
screamer 28:0e774865873d 17469 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
screamer 28:0e774865873d 17470 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
screamer 28:0e774865873d 17471 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 17472 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 17473 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 17474 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
screamer 28:0e774865873d 17475 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 17476 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
screamer 28:0e774865873d 17477 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
screamer 28:0e774865873d 17478 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 17479 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
screamer 28:0e774865873d 17480 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
screamer 28:0e774865873d 17481 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 17482 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
screamer 28:0e774865873d 17483
screamer 28:0e774865873d 17484 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
screamer 28:0e774865873d 17485
screamer 28:0e774865873d 17486 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
screamer 28:0e774865873d 17487 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
screamer 28:0e774865873d 17488 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
screamer 28:0e774865873d 17489 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17490 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17491 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17492 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17493 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17494 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17495 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17496
screamer 28:0e774865873d 17497 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
screamer 28:0e774865873d 17498 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
screamer 28:0e774865873d 17499 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
screamer 28:0e774865873d 17500 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17501 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17502 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17503 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 17504 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 17505 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 17506 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 17507
screamer 28:0e774865873d 17508 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
screamer 28:0e774865873d 17509 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
screamer 28:0e774865873d 17510 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
screamer 28:0e774865873d 17511 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 17512 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17513 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
screamer 28:0e774865873d 17514 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
screamer 28:0e774865873d 17515 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
screamer 28:0e774865873d 17516 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
screamer 28:0e774865873d 17517 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 17518 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
screamer 28:0e774865873d 17519
screamer 28:0e774865873d 17520 /******************** Bit definition for USB_OTG_HCINT register ********************/
screamer 28:0e774865873d 17521 #define USB_OTG_HCINT_XFRC_Pos (0U)
screamer 28:0e774865873d 17522 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17523 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
screamer 28:0e774865873d 17524 #define USB_OTG_HCINT_CHH_Pos (1U)
screamer 28:0e774865873d 17525 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17526 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
screamer 28:0e774865873d 17527 #define USB_OTG_HCINT_AHBERR_Pos (2U)
screamer 28:0e774865873d 17528 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17529 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
screamer 28:0e774865873d 17530 #define USB_OTG_HCINT_STALL_Pos (3U)
screamer 28:0e774865873d 17531 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17532 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
screamer 28:0e774865873d 17533 #define USB_OTG_HCINT_NAK_Pos (4U)
screamer 28:0e774865873d 17534 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17535 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
screamer 28:0e774865873d 17536 #define USB_OTG_HCINT_ACK_Pos (5U)
screamer 28:0e774865873d 17537 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17538 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
screamer 28:0e774865873d 17539 #define USB_OTG_HCINT_NYET_Pos (6U)
screamer 28:0e774865873d 17540 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17541 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
screamer 28:0e774865873d 17542 #define USB_OTG_HCINT_TXERR_Pos (7U)
screamer 28:0e774865873d 17543 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17544 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
screamer 28:0e774865873d 17545 #define USB_OTG_HCINT_BBERR_Pos (8U)
screamer 28:0e774865873d 17546 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17547 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
screamer 28:0e774865873d 17548 #define USB_OTG_HCINT_FRMOR_Pos (9U)
screamer 28:0e774865873d 17549 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17550 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
screamer 28:0e774865873d 17551 #define USB_OTG_HCINT_DTERR_Pos (10U)
screamer 28:0e774865873d 17552 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 17553 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
screamer 28:0e774865873d 17554
screamer 28:0e774865873d 17555 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
screamer 28:0e774865873d 17556 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
screamer 28:0e774865873d 17557 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17558 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
screamer 28:0e774865873d 17559 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
screamer 28:0e774865873d 17560 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17561 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
screamer 28:0e774865873d 17562 #define USB_OTG_DIEPINT_TOC_Pos (3U)
screamer 28:0e774865873d 17563 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17564 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
screamer 28:0e774865873d 17565 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
screamer 28:0e774865873d 17566 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17567 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
screamer 28:0e774865873d 17568 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
screamer 28:0e774865873d 17569 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17570 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
screamer 28:0e774865873d 17571 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
screamer 28:0e774865873d 17572 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17573 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
screamer 28:0e774865873d 17574 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
screamer 28:0e774865873d 17575 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17576 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
screamer 28:0e774865873d 17577 #define USB_OTG_DIEPINT_BNA_Pos (9U)
screamer 28:0e774865873d 17578 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17579 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
screamer 28:0e774865873d 17580 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
screamer 28:0e774865873d 17581 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
screamer 28:0e774865873d 17582 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
screamer 28:0e774865873d 17583 #define USB_OTG_DIEPINT_BERR_Pos (12U)
screamer 28:0e774865873d 17584 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
screamer 28:0e774865873d 17585 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
screamer 28:0e774865873d 17586 #define USB_OTG_DIEPINT_NAK_Pos (13U)
screamer 28:0e774865873d 17587 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
screamer 28:0e774865873d 17588 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
screamer 28:0e774865873d 17589
screamer 28:0e774865873d 17590 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
screamer 28:0e774865873d 17591 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
screamer 28:0e774865873d 17592 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17593 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
screamer 28:0e774865873d 17594 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
screamer 28:0e774865873d 17595 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17596 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
screamer 28:0e774865873d 17597 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
screamer 28:0e774865873d 17598 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
screamer 28:0e774865873d 17599 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
screamer 28:0e774865873d 17600 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
screamer 28:0e774865873d 17601 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17602 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
screamer 28:0e774865873d 17603 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
screamer 28:0e774865873d 17604 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17605 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
screamer 28:0e774865873d 17606 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
screamer 28:0e774865873d 17607 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
screamer 28:0e774865873d 17608 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
screamer 28:0e774865873d 17609 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
screamer 28:0e774865873d 17610 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17611 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
screamer 28:0e774865873d 17612 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
screamer 28:0e774865873d 17613 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
screamer 28:0e774865873d 17614 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
screamer 28:0e774865873d 17615 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
screamer 28:0e774865873d 17616 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
screamer 28:0e774865873d 17617 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
screamer 28:0e774865873d 17618 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
screamer 28:0e774865873d 17619 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
screamer 28:0e774865873d 17620 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
screamer 28:0e774865873d 17621 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
screamer 28:0e774865873d 17622 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
screamer 28:0e774865873d 17623 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
screamer 28:0e774865873d 17624
screamer 28:0e774865873d 17625 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
screamer 28:0e774865873d 17626
screamer 28:0e774865873d 17627 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
screamer 28:0e774865873d 17628 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 17629 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
screamer 28:0e774865873d 17630 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
screamer 28:0e774865873d 17631 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
screamer 28:0e774865873d 17632 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
screamer 28:0e774865873d 17633 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
screamer 28:0e774865873d 17634 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
screamer 28:0e774865873d 17635 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
screamer 28:0e774865873d 17636 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
screamer 28:0e774865873d 17637 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
screamer 28:0e774865873d 17638 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 17639 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
screamer 28:0e774865873d 17640 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
screamer 28:0e774865873d 17641 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
screamer 28:0e774865873d 17642 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
screamer 28:0e774865873d 17643 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
screamer 28:0e774865873d 17644 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 17645 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
screamer 28:0e774865873d 17646 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
screamer 28:0e774865873d 17647 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
screamer 28:0e774865873d 17648 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
screamer 28:0e774865873d 17649 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 17650 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 17651
screamer 28:0e774865873d 17652 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
screamer 28:0e774865873d 17653 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
screamer 28:0e774865873d 17654 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 17655 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
screamer 28:0e774865873d 17656
screamer 28:0e774865873d 17657 /******************** Bit definition for USB_OTG_HCDMA register ********************/
screamer 28:0e774865873d 17658 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
screamer 28:0e774865873d 17659 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
screamer 28:0e774865873d 17660 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
screamer 28:0e774865873d 17661
screamer 28:0e774865873d 17662 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
screamer 28:0e774865873d 17663 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
screamer 28:0e774865873d 17664 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17665 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
screamer 28:0e774865873d 17666
screamer 28:0e774865873d 17667 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
screamer 28:0e774865873d 17668 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
screamer 28:0e774865873d 17669 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
screamer 28:0e774865873d 17670 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
screamer 28:0e774865873d 17671 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
screamer 28:0e774865873d 17672 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
screamer 28:0e774865873d 17673 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
screamer 28:0e774865873d 17674
screamer 28:0e774865873d 17675 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
screamer 28:0e774865873d 17676
screamer 28:0e774865873d 17677 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
screamer 28:0e774865873d 17678 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
screamer 28:0e774865873d 17679 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
screamer 28:0e774865873d 17680 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
screamer 28:0e774865873d 17681 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
screamer 28:0e774865873d 17682 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
screamer 28:0e774865873d 17683 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
screamer 28:0e774865873d 17684 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
screamer 28:0e774865873d 17685 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
screamer 28:0e774865873d 17686 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
screamer 28:0e774865873d 17687 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
screamer 28:0e774865873d 17688 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
screamer 28:0e774865873d 17689 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
screamer 28:0e774865873d 17690 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 17691 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
screamer 28:0e774865873d 17692 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
screamer 28:0e774865873d 17693 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
screamer 28:0e774865873d 17694 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
screamer 28:0e774865873d 17695 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
screamer 28:0e774865873d 17696 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
screamer 28:0e774865873d 17697 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
screamer 28:0e774865873d 17698 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
screamer 28:0e774865873d 17699 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
screamer 28:0e774865873d 17700 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
screamer 28:0e774865873d 17701 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
screamer 28:0e774865873d 17702 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
screamer 28:0e774865873d 17703 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
screamer 28:0e774865873d 17704 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
screamer 28:0e774865873d 17705 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
screamer 28:0e774865873d 17706 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
screamer 28:0e774865873d 17707 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
screamer 28:0e774865873d 17708 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
screamer 28:0e774865873d 17709 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
screamer 28:0e774865873d 17710 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 17711 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
screamer 28:0e774865873d 17712 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
screamer 28:0e774865873d 17713 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
screamer 28:0e774865873d 17714 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
screamer 28:0e774865873d 17715
screamer 28:0e774865873d 17716 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
screamer 28:0e774865873d 17717 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
screamer 28:0e774865873d 17718 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17719 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
screamer 28:0e774865873d 17720 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
screamer 28:0e774865873d 17721 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17722 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
screamer 28:0e774865873d 17723 #define USB_OTG_DOEPINT_STUP_Pos (3U)
screamer 28:0e774865873d 17724 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
screamer 28:0e774865873d 17725 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
screamer 28:0e774865873d 17726 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
screamer 28:0e774865873d 17727 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17728 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
screamer 28:0e774865873d 17729 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
screamer 28:0e774865873d 17730 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
screamer 28:0e774865873d 17731 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
screamer 28:0e774865873d 17732 #define USB_OTG_DOEPINT_NYET_Pos (14U)
screamer 28:0e774865873d 17733 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
screamer 28:0e774865873d 17734 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
screamer 28:0e774865873d 17735
screamer 28:0e774865873d 17736 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
screamer 28:0e774865873d 17737
screamer 28:0e774865873d 17738 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
screamer 28:0e774865873d 17739 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
screamer 28:0e774865873d 17740 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
screamer 28:0e774865873d 17741 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
screamer 28:0e774865873d 17742 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
screamer 28:0e774865873d 17743 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
screamer 28:0e774865873d 17744
screamer 28:0e774865873d 17745 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
screamer 28:0e774865873d 17746 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
screamer 28:0e774865873d 17747 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
screamer 28:0e774865873d 17748 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
screamer 28:0e774865873d 17749 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
screamer 28:0e774865873d 17750
screamer 28:0e774865873d 17751 /******************** Bit definition for PCGCCTL register ********************/
screamer 28:0e774865873d 17752 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
screamer 28:0e774865873d 17753 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
screamer 28:0e774865873d 17754 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
screamer 28:0e774865873d 17755 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
screamer 28:0e774865873d 17756 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
screamer 28:0e774865873d 17757 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
screamer 28:0e774865873d 17758 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
screamer 28:0e774865873d 17759 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
screamer 28:0e774865873d 17760 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
screamer 28:0e774865873d 17761
screamer 28:0e774865873d 17762
screamer 28:0e774865873d 17763 /**
screamer 28:0e774865873d 17764 * @}
screamer 28:0e774865873d 17765 */
screamer 28:0e774865873d 17766
screamer 28:0e774865873d 17767 /**
screamer 28:0e774865873d 17768 * @}
screamer 28:0e774865873d 17769 */
screamer 28:0e774865873d 17770
screamer 28:0e774865873d 17771 /** @addtogroup Exported_macros
screamer 28:0e774865873d 17772 * @{
screamer 28:0e774865873d 17773 */
screamer 28:0e774865873d 17774
screamer 28:0e774865873d 17775 /******************************* ADC Instances ********************************/
screamer 28:0e774865873d 17776 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
screamer 28:0e774865873d 17777 ((INSTANCE) == ADC2) || \
screamer 28:0e774865873d 17778 ((INSTANCE) == ADC3))
screamer 28:0e774865873d 17779
screamer 28:0e774865873d 17780 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
screamer 28:0e774865873d 17781
screamer 28:0e774865873d 17782 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
screamer 28:0e774865873d 17783
screamer 28:0e774865873d 17784 /******************************** CAN Instances ******************************/
screamer 28:0e774865873d 17785 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
screamer 28:0e774865873d 17786
screamer 28:0e774865873d 17787 /******************************** COMP Instances ******************************/
screamer 28:0e774865873d 17788 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
screamer 28:0e774865873d 17789 ((INSTANCE) == COMP2))
screamer 28:0e774865873d 17790
screamer 28:0e774865873d 17791 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
screamer 28:0e774865873d 17792
screamer 28:0e774865873d 17793 /******************** COMP Instances with window mode capability **************/
screamer 28:0e774865873d 17794 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
screamer 28:0e774865873d 17795
screamer 28:0e774865873d 17796 /******************************* CRC Instances ********************************/
screamer 28:0e774865873d 17797 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
screamer 28:0e774865873d 17798
screamer 28:0e774865873d 17799 /******************************* DAC Instances ********************************/
screamer 28:0e774865873d 17800 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
screamer 28:0e774865873d 17801
screamer 28:0e774865873d 17802 /****************************** DFSDM Instances *******************************/
screamer 28:0e774865873d 17803 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
screamer 28:0e774865873d 17804 ((INSTANCE) == DFSDM1_Filter1) || \
screamer 28:0e774865873d 17805 ((INSTANCE) == DFSDM1_Filter2) || \
screamer 28:0e774865873d 17806 ((INSTANCE) == DFSDM1_Filter3))
screamer 28:0e774865873d 17807
screamer 28:0e774865873d 17808 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
screamer 28:0e774865873d 17809 ((INSTANCE) == DFSDM1_Channel1) || \
screamer 28:0e774865873d 17810 ((INSTANCE) == DFSDM1_Channel2) || \
screamer 28:0e774865873d 17811 ((INSTANCE) == DFSDM1_Channel3) || \
screamer 28:0e774865873d 17812 ((INSTANCE) == DFSDM1_Channel4) || \
screamer 28:0e774865873d 17813 ((INSTANCE) == DFSDM1_Channel5) || \
screamer 28:0e774865873d 17814 ((INSTANCE) == DFSDM1_Channel6) || \
screamer 28:0e774865873d 17815 ((INSTANCE) == DFSDM1_Channel7))
screamer 28:0e774865873d 17816
screamer 28:0e774865873d 17817 /******************************** DMA Instances *******************************/
screamer 28:0e774865873d 17818 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
screamer 28:0e774865873d 17819 ((INSTANCE) == DMA1_Channel2) || \
screamer 28:0e774865873d 17820 ((INSTANCE) == DMA1_Channel3) || \
screamer 28:0e774865873d 17821 ((INSTANCE) == DMA1_Channel4) || \
screamer 28:0e774865873d 17822 ((INSTANCE) == DMA1_Channel5) || \
screamer 28:0e774865873d 17823 ((INSTANCE) == DMA1_Channel6) || \
screamer 28:0e774865873d 17824 ((INSTANCE) == DMA1_Channel7) || \
screamer 28:0e774865873d 17825 ((INSTANCE) == DMA2_Channel1) || \
screamer 28:0e774865873d 17826 ((INSTANCE) == DMA2_Channel2) || \
screamer 28:0e774865873d 17827 ((INSTANCE) == DMA2_Channel3) || \
screamer 28:0e774865873d 17828 ((INSTANCE) == DMA2_Channel4) || \
screamer 28:0e774865873d 17829 ((INSTANCE) == DMA2_Channel5) || \
screamer 28:0e774865873d 17830 ((INSTANCE) == DMA2_Channel6) || \
screamer 28:0e774865873d 17831 ((INSTANCE) == DMA2_Channel7))
screamer 28:0e774865873d 17832
screamer 28:0e774865873d 17833 /******************************* GPIO Instances *******************************/
screamer 28:0e774865873d 17834 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
screamer 28:0e774865873d 17835 ((INSTANCE) == GPIOB) || \
screamer 28:0e774865873d 17836 ((INSTANCE) == GPIOC) || \
screamer 28:0e774865873d 17837 ((INSTANCE) == GPIOD) || \
screamer 28:0e774865873d 17838 ((INSTANCE) == GPIOE) || \
screamer 28:0e774865873d 17839 ((INSTANCE) == GPIOF) || \
screamer 28:0e774865873d 17840 ((INSTANCE) == GPIOG) || \
screamer 28:0e774865873d 17841 ((INSTANCE) == GPIOH))
screamer 28:0e774865873d 17842
screamer 28:0e774865873d 17843 /******************************* GPIO AF Instances ****************************/
screamer 28:0e774865873d 17844 /* On L4, all GPIO Bank support AF */
screamer 28:0e774865873d 17845 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
screamer 28:0e774865873d 17846
screamer 28:0e774865873d 17847 /**************************** GPIO Lock Instances *****************************/
screamer 28:0e774865873d 17848 /* On L4, all GPIO Bank support the Lock mechanism */
screamer 28:0e774865873d 17849 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
screamer 28:0e774865873d 17850
screamer 28:0e774865873d 17851 /******************************** I2C Instances *******************************/
screamer 28:0e774865873d 17852 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
screamer 28:0e774865873d 17853 ((INSTANCE) == I2C2) || \
screamer 28:0e774865873d 17854 ((INSTANCE) == I2C3))
screamer 28:0e774865873d 17855
screamer 28:0e774865873d 17856 /****************** I2C Instances : wakeup capability from stop modes *********/
screamer 28:0e774865873d 17857 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
screamer 28:0e774865873d 17858
screamer 28:0e774865873d 17859 /******************************* HCD Instances *******************************/
screamer 28:0e774865873d 17860 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
screamer 28:0e774865873d 17861
screamer 28:0e774865873d 17862 /****************************** OPAMP Instances *******************************/
screamer 28:0e774865873d 17863 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
screamer 28:0e774865873d 17864 ((INSTANCE) == OPAMP2))
screamer 28:0e774865873d 17865
screamer 28:0e774865873d 17866 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
screamer 28:0e774865873d 17867
screamer 28:0e774865873d 17868 /******************************* PCD Instances *******************************/
screamer 28:0e774865873d 17869 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
screamer 28:0e774865873d 17870
screamer 28:0e774865873d 17871 /******************************* QSPI Instances *******************************/
screamer 28:0e774865873d 17872 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
screamer 28:0e774865873d 17873
screamer 28:0e774865873d 17874 /******************************* RNG Instances ********************************/
screamer 28:0e774865873d 17875 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
screamer 28:0e774865873d 17876
screamer 28:0e774865873d 17877 /****************************** RTC Instances *********************************/
screamer 28:0e774865873d 17878 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
screamer 28:0e774865873d 17879
screamer 28:0e774865873d 17880 /******************************** SAI Instances *******************************/
screamer 28:0e774865873d 17881 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
screamer 28:0e774865873d 17882 ((INSTANCE) == SAI1_Block_B) || \
screamer 28:0e774865873d 17883 ((INSTANCE) == SAI2_Block_A) || \
screamer 28:0e774865873d 17884 ((INSTANCE) == SAI2_Block_B))
screamer 28:0e774865873d 17885
screamer 28:0e774865873d 17886 /****************************** SDMMC Instances *******************************/
screamer 28:0e774865873d 17887 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
screamer 28:0e774865873d 17888
screamer 28:0e774865873d 17889 /****************************** SMBUS Instances *******************************/
screamer 28:0e774865873d 17890 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
screamer 28:0e774865873d 17891 ((INSTANCE) == I2C2) || \
screamer 28:0e774865873d 17892 ((INSTANCE) == I2C3))
screamer 28:0e774865873d 17893
screamer 28:0e774865873d 17894 /******************************** SPI Instances *******************************/
screamer 28:0e774865873d 17895 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
screamer 28:0e774865873d 17896 ((INSTANCE) == SPI2) || \
screamer 28:0e774865873d 17897 ((INSTANCE) == SPI3))
screamer 28:0e774865873d 17898
screamer 28:0e774865873d 17899 /******************************** SWPMI Instances *****************************/
screamer 28:0e774865873d 17900 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
screamer 28:0e774865873d 17901
screamer 28:0e774865873d 17902 /****************** LPTIM Instances : All supported instances *****************/
screamer 28:0e774865873d 17903 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
screamer 28:0e774865873d 17904 ((INSTANCE) == LPTIM2))
screamer 28:0e774865873d 17905
screamer 28:0e774865873d 17906 /****************** TIM Instances : All supported instances *******************/
screamer 28:0e774865873d 17907 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17908 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17909 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 17910 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 17911 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 17912 ((INSTANCE) == TIM6) || \
screamer 28:0e774865873d 17913 ((INSTANCE) == TIM7) || \
screamer 28:0e774865873d 17914 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 17915 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 17916 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 17917 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 17918
screamer 28:0e774865873d 17919 /****************** TIM Instances : supporting 32 bits counter ****************/
screamer 28:0e774865873d 17920 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17921 ((INSTANCE) == TIM5))
screamer 28:0e774865873d 17922
screamer 28:0e774865873d 17923 /****************** TIM Instances : supporting the break function *************/
screamer 28:0e774865873d 17924 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17925 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 17926 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 17927 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 17928 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 17929
screamer 28:0e774865873d 17930 /************** TIM Instances : supporting Break source selection *************/
screamer 28:0e774865873d 17931 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17932 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 17933 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 17934 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 17935 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 17936
screamer 28:0e774865873d 17937 /****************** TIM Instances : supporting 2 break inputs *****************/
screamer 28:0e774865873d 17938 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17939 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 17940
screamer 28:0e774865873d 17941 /************* TIM Instances : at least 1 capture/compare channel *************/
screamer 28:0e774865873d 17942 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17943 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17944 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 17945 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 17946 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 17947 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 17948 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 17949 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 17950 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 17951
screamer 28:0e774865873d 17952 /************ TIM Instances : at least 2 capture/compare channels *************/
screamer 28:0e774865873d 17953 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17954 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17955 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 17956 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 17957 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 17958 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 17959 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 17960
screamer 28:0e774865873d 17961 /************ TIM Instances : at least 3 capture/compare channels *************/
screamer 28:0e774865873d 17962 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17963 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17964 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 17965 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 17966 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 17967 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 17968
screamer 28:0e774865873d 17969 /************ TIM Instances : at least 4 capture/compare channels *************/
screamer 28:0e774865873d 17970 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17971 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17972 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 17973 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 17974 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 17975 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 17976
screamer 28:0e774865873d 17977 /****************** TIM Instances : at least 5 capture/compare channels *******/
screamer 28:0e774865873d 17978 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17979 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 17980
screamer 28:0e774865873d 17981 /****************** TIM Instances : at least 6 capture/compare channels *******/
screamer 28:0e774865873d 17982 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17983 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 17984
screamer 28:0e774865873d 17985 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
screamer 28:0e774865873d 17986 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17987 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 17988 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 17989 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 17990 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 17991
screamer 28:0e774865873d 17992 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
screamer 28:0e774865873d 17993 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 17994 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 17995 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 17996 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 17997 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 17998 ((INSTANCE) == TIM6) || \
screamer 28:0e774865873d 17999 ((INSTANCE) == TIM7) || \
screamer 28:0e774865873d 18000 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18001 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18002 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18003 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18004
screamer 28:0e774865873d 18005 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
screamer 28:0e774865873d 18006 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18007 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18008 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18009 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18010 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18011 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18012 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18013 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18014 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18015
screamer 28:0e774865873d 18016 /******************** TIM Instances : DMA burst feature ***********************/
screamer 28:0e774865873d 18017 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18018 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18019 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18020 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18021 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18022 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18023 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18024 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18025 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18026
screamer 28:0e774865873d 18027 /******************* TIM Instances : output(s) available **********************/
screamer 28:0e774865873d 18028 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
screamer 28:0e774865873d 18029 ((((INSTANCE) == TIM1) && \
screamer 28:0e774865873d 18030 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18031 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18032 ((CHANNEL) == TIM_CHANNEL_3) || \
screamer 28:0e774865873d 18033 ((CHANNEL) == TIM_CHANNEL_4) || \
screamer 28:0e774865873d 18034 ((CHANNEL) == TIM_CHANNEL_5) || \
screamer 28:0e774865873d 18035 ((CHANNEL) == TIM_CHANNEL_6))) \
screamer 28:0e774865873d 18036 || \
screamer 28:0e774865873d 18037 (((INSTANCE) == TIM2) && \
screamer 28:0e774865873d 18038 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18039 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18040 ((CHANNEL) == TIM_CHANNEL_3) || \
screamer 28:0e774865873d 18041 ((CHANNEL) == TIM_CHANNEL_4))) \
screamer 28:0e774865873d 18042 || \
screamer 28:0e774865873d 18043 (((INSTANCE) == TIM3) && \
screamer 28:0e774865873d 18044 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18045 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18046 ((CHANNEL) == TIM_CHANNEL_3) || \
screamer 28:0e774865873d 18047 ((CHANNEL) == TIM_CHANNEL_4))) \
screamer 28:0e774865873d 18048 || \
screamer 28:0e774865873d 18049 (((INSTANCE) == TIM4) && \
screamer 28:0e774865873d 18050 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18051 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18052 ((CHANNEL) == TIM_CHANNEL_3) || \
screamer 28:0e774865873d 18053 ((CHANNEL) == TIM_CHANNEL_4))) \
screamer 28:0e774865873d 18054 || \
screamer 28:0e774865873d 18055 (((INSTANCE) == TIM5) && \
screamer 28:0e774865873d 18056 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18057 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18058 ((CHANNEL) == TIM_CHANNEL_3) || \
screamer 28:0e774865873d 18059 ((CHANNEL) == TIM_CHANNEL_4))) \
screamer 28:0e774865873d 18060 || \
screamer 28:0e774865873d 18061 (((INSTANCE) == TIM8) && \
screamer 28:0e774865873d 18062 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18063 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18064 ((CHANNEL) == TIM_CHANNEL_3) || \
screamer 28:0e774865873d 18065 ((CHANNEL) == TIM_CHANNEL_4) || \
screamer 28:0e774865873d 18066 ((CHANNEL) == TIM_CHANNEL_5) || \
screamer 28:0e774865873d 18067 ((CHANNEL) == TIM_CHANNEL_6))) \
screamer 28:0e774865873d 18068 || \
screamer 28:0e774865873d 18069 (((INSTANCE) == TIM15) && \
screamer 28:0e774865873d 18070 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18071 ((CHANNEL) == TIM_CHANNEL_2))) \
screamer 28:0e774865873d 18072 || \
screamer 28:0e774865873d 18073 (((INSTANCE) == TIM16) && \
screamer 28:0e774865873d 18074 (((CHANNEL) == TIM_CHANNEL_1))) \
screamer 28:0e774865873d 18075 || \
screamer 28:0e774865873d 18076 (((INSTANCE) == TIM17) && \
screamer 28:0e774865873d 18077 (((CHANNEL) == TIM_CHANNEL_1))))
screamer 28:0e774865873d 18078
screamer 28:0e774865873d 18079 /****************** TIM Instances : supporting complementary output(s) ********/
screamer 28:0e774865873d 18080 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
screamer 28:0e774865873d 18081 ((((INSTANCE) == TIM1) && \
screamer 28:0e774865873d 18082 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18083 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18084 ((CHANNEL) == TIM_CHANNEL_3))) \
screamer 28:0e774865873d 18085 || \
screamer 28:0e774865873d 18086 (((INSTANCE) == TIM8) && \
screamer 28:0e774865873d 18087 (((CHANNEL) == TIM_CHANNEL_1) || \
screamer 28:0e774865873d 18088 ((CHANNEL) == TIM_CHANNEL_2) || \
screamer 28:0e774865873d 18089 ((CHANNEL) == TIM_CHANNEL_3))) \
screamer 28:0e774865873d 18090 || \
screamer 28:0e774865873d 18091 (((INSTANCE) == TIM15) && \
screamer 28:0e774865873d 18092 ((CHANNEL) == TIM_CHANNEL_1)) \
screamer 28:0e774865873d 18093 || \
screamer 28:0e774865873d 18094 (((INSTANCE) == TIM16) && \
screamer 28:0e774865873d 18095 ((CHANNEL) == TIM_CHANNEL_1)) \
screamer 28:0e774865873d 18096 || \
screamer 28:0e774865873d 18097 (((INSTANCE) == TIM17) && \
screamer 28:0e774865873d 18098 ((CHANNEL) == TIM_CHANNEL_1)))
screamer 28:0e774865873d 18099
screamer 28:0e774865873d 18100 /****************** TIM Instances : supporting clock division *****************/
screamer 28:0e774865873d 18101 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18102 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18103 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18104 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18105 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18106 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18107 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18108 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18109 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18110
screamer 28:0e774865873d 18111 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
screamer 28:0e774865873d 18112 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18113 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18114 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18115 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18116 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18117 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18118 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 18119
screamer 28:0e774865873d 18120 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
screamer 28:0e774865873d 18121 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18122 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18123 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18124 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18125 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18126 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18127
screamer 28:0e774865873d 18128 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
screamer 28:0e774865873d 18129 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18130 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18131 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18132 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18133 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18134 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18135 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 18136
screamer 28:0e774865873d 18137 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
screamer 28:0e774865873d 18138 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18139 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18140 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18141 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18142 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18143 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18144 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 18145
screamer 28:0e774865873d 18146 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
screamer 28:0e774865873d 18147 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18148 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18149
screamer 28:0e774865873d 18150 /****************** TIM Instances : supporting commutation event generation ***/
screamer 28:0e774865873d 18151 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18152 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18153 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18154 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18155 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18156
screamer 28:0e774865873d 18157 /****************** TIM Instances : supporting counting mode selection ********/
screamer 28:0e774865873d 18158 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18159 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18160 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18161 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18162 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18163 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18164
screamer 28:0e774865873d 18165 /****************** TIM Instances : supporting encoder interface **************/
screamer 28:0e774865873d 18166 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18167 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18168 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18169 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18170 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18171 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18172
screamer 28:0e774865873d 18173 /****************** TIM Instances : supporting Hall sensor interface **********/
screamer 28:0e774865873d 18174 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18175 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18176 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18177 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18178 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18179 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18180
screamer 28:0e774865873d 18181 /**************** TIM Instances : external trigger input available ************/
screamer 28:0e774865873d 18182 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18183 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18184 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18185 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18186 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18187 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18188
screamer 28:0e774865873d 18189 /************* TIM Instances : supporting ETR source selection ***************/
screamer 28:0e774865873d 18190 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18191 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18192 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18193 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18194
screamer 28:0e774865873d 18195 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
screamer 28:0e774865873d 18196 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18197 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18198 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18199 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18200 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18201 ((INSTANCE) == TIM6) || \
screamer 28:0e774865873d 18202 ((INSTANCE) == TIM7) || \
screamer 28:0e774865873d 18203 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18204 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 18205
screamer 28:0e774865873d 18206 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
screamer 28:0e774865873d 18207 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18208 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18209 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18210 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18211 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18212 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18213 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 18214
screamer 28:0e774865873d 18215 /****************** TIM Instances : supporting OCxREF clear *******************/
screamer 28:0e774865873d 18216 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18217 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18218 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18219 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18220 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18221 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18222
screamer 28:0e774865873d 18223 /****************** TIM Instances : remapping capability **********************/
screamer 28:0e774865873d 18224 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18225 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18226 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18227 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18228 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18229 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18230 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18231
screamer 28:0e774865873d 18232 /****************** TIM Instances : supporting repetition counter *************/
screamer 28:0e774865873d 18233 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18234 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18235 ((INSTANCE) == TIM15) || \
screamer 28:0e774865873d 18236 ((INSTANCE) == TIM16) || \
screamer 28:0e774865873d 18237 ((INSTANCE) == TIM17))
screamer 28:0e774865873d 18238
screamer 28:0e774865873d 18239 /****************** TIM Instances : supporting synchronization ****************/
screamer 28:0e774865873d 18240 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
screamer 28:0e774865873d 18241
screamer 28:0e774865873d 18242 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
screamer 28:0e774865873d 18243 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18244 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18245
screamer 28:0e774865873d 18246 /******************* TIM Instances : Timer input XOR function *****************/
screamer 28:0e774865873d 18247 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18248 ((INSTANCE) == TIM2) || \
screamer 28:0e774865873d 18249 ((INSTANCE) == TIM3) || \
screamer 28:0e774865873d 18250 ((INSTANCE) == TIM4) || \
screamer 28:0e774865873d 18251 ((INSTANCE) == TIM5) || \
screamer 28:0e774865873d 18252 ((INSTANCE) == TIM8) || \
screamer 28:0e774865873d 18253 ((INSTANCE) == TIM15))
screamer 28:0e774865873d 18254
screamer 28:0e774865873d 18255 /****************** TIM Instances : Advanced timer instances *******************/
screamer 28:0e774865873d 18256 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
screamer 28:0e774865873d 18257 ((INSTANCE) == TIM8))
screamer 28:0e774865873d 18258
screamer 28:0e774865873d 18259 /****************************** TSC Instances *********************************/
screamer 28:0e774865873d 18260 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
screamer 28:0e774865873d 18261
screamer 28:0e774865873d 18262 /******************** USART Instances : Synchronous mode **********************/
screamer 28:0e774865873d 18263 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18264 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18265 ((INSTANCE) == USART3))
screamer 28:0e774865873d 18266
screamer 28:0e774865873d 18267 /******************** UART Instances : Asynchronous mode **********************/
screamer 28:0e774865873d 18268 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18269 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18270 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18271 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18272 ((INSTANCE) == UART5))
screamer 28:0e774865873d 18273
screamer 28:0e774865873d 18274 /****************** UART Instances : Auto Baud Rate detection ****************/
screamer 28:0e774865873d 18275 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18276 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18277 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18278 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18279 ((INSTANCE) == UART5))
screamer 28:0e774865873d 18280
screamer 28:0e774865873d 18281 /****************** UART Instances : Driver Enable *****************/
screamer 28:0e774865873d 18282 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18283 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18284 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18285 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18286 ((INSTANCE) == UART5) || \
screamer 28:0e774865873d 18287 ((INSTANCE) == LPUART1))
screamer 28:0e774865873d 18288
screamer 28:0e774865873d 18289 /******************** UART Instances : Half-Duplex mode **********************/
screamer 28:0e774865873d 18290 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18291 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18292 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18293 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18294 ((INSTANCE) == UART5) || \
screamer 28:0e774865873d 18295 ((INSTANCE) == LPUART1))
screamer 28:0e774865873d 18296
screamer 28:0e774865873d 18297 /****************** UART Instances : Hardware Flow control ********************/
screamer 28:0e774865873d 18298 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18299 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18300 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18301 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18302 ((INSTANCE) == UART5) || \
screamer 28:0e774865873d 18303 ((INSTANCE) == LPUART1))
screamer 28:0e774865873d 18304
screamer 28:0e774865873d 18305 /******************** UART Instances : LIN mode **********************/
screamer 28:0e774865873d 18306 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18307 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18308 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18309 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18310 ((INSTANCE) == UART5))
screamer 28:0e774865873d 18311
screamer 28:0e774865873d 18312 /******************** UART Instances : Wake-up from Stop mode **********************/
screamer 28:0e774865873d 18313 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18314 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18315 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18316 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18317 ((INSTANCE) == UART5) || \
screamer 28:0e774865873d 18318 ((INSTANCE) == LPUART1))
screamer 28:0e774865873d 18319
screamer 28:0e774865873d 18320 /*********************** UART Instances : IRDA mode ***************************/
screamer 28:0e774865873d 18321 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18322 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18323 ((INSTANCE) == USART3) || \
screamer 28:0e774865873d 18324 ((INSTANCE) == UART4) || \
screamer 28:0e774865873d 18325 ((INSTANCE) == UART5))
screamer 28:0e774865873d 18326
screamer 28:0e774865873d 18327 /********************* USART Instances : Smard card mode ***********************/
screamer 28:0e774865873d 18328 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
screamer 28:0e774865873d 18329 ((INSTANCE) == USART2) || \
screamer 28:0e774865873d 18330 ((INSTANCE) == USART3))
screamer 28:0e774865873d 18331
screamer 28:0e774865873d 18332 /******************** LPUART Instance *****************************************/
screamer 28:0e774865873d 18333 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
screamer 28:0e774865873d 18334
screamer 28:0e774865873d 18335 /****************************** IWDG Instances ********************************/
screamer 28:0e774865873d 18336 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
screamer 28:0e774865873d 18337
screamer 28:0e774865873d 18338 /****************************** WWDG Instances ********************************/
screamer 28:0e774865873d 18339 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
screamer 28:0e774865873d 18340
screamer 28:0e774865873d 18341 /**
screamer 28:0e774865873d 18342 * @}
screamer 28:0e774865873d 18343 */
screamer 28:0e774865873d 18344
screamer 28:0e774865873d 18345
screamer 28:0e774865873d 18346 /******************************************************************************/
screamer 28:0e774865873d 18347 /* For a painless codes migration between the STM32L4xx device product */
screamer 28:0e774865873d 18348 /* lines, the aliases defined below are put in place to overcome the */
screamer 28:0e774865873d 18349 /* differences in the interrupt handlers and IRQn definitions. */
screamer 28:0e774865873d 18350 /* No need to update developed interrupt code when moving across */
screamer 28:0e774865873d 18351 /* product lines within the same STM32L4 Family */
screamer 28:0e774865873d 18352 /******************************************************************************/
screamer 28:0e774865873d 18353
screamer 28:0e774865873d 18354 /* Aliases for __IRQn */
screamer 28:0e774865873d 18355 #define ADC1_IRQn ADC1_2_IRQn
screamer 28:0e774865873d 18356 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
screamer 28:0e774865873d 18357 #define TIM8_IRQn TIM8_UP_IRQn
screamer 28:0e774865873d 18358 #define HASH_RNG_IRQn RNG_IRQn
screamer 28:0e774865873d 18359 #define DFSDM0_IRQn DFSDM1_FLT0_IRQn
screamer 28:0e774865873d 18360 #define DFSDM1_IRQn DFSDM1_FLT1_IRQn
screamer 28:0e774865873d 18361 #define DFSDM2_IRQn DFSDM1_FLT2_IRQn
screamer 28:0e774865873d 18362 #define DFSDM3_IRQn DFSDM1_FLT3_IRQn
screamer 28:0e774865873d 18363
screamer 28:0e774865873d 18364 /* Aliases for __IRQHandler */
screamer 28:0e774865873d 18365 #define ADC1_IRQHandler ADC1_2_IRQHandler
screamer 28:0e774865873d 18366 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
screamer 28:0e774865873d 18367 #define TIM8_IRQHandler TIM8_UP_IRQHandler
screamer 28:0e774865873d 18368 #define HASH_RNG_IRQHandler RNG_IRQHandler
screamer 28:0e774865873d 18369 #define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
screamer 28:0e774865873d 18370 #define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
screamer 28:0e774865873d 18371 #define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
screamer 28:0e774865873d 18372 #define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
screamer 28:0e774865873d 18373
screamer 28:0e774865873d 18374 #ifdef __cplusplus
screamer 28:0e774865873d 18375 }
screamer 28:0e774865873d 18376 #endif /* __cplusplus */
screamer 28:0e774865873d 18377
screamer 28:0e774865873d 18378 #endif /* __STM32L475xx_H */
screamer 28:0e774865873d 18379
screamer 28:0e774865873d 18380 /**
screamer 28:0e774865873d 18381 * @}
screamer 28:0e774865873d 18382 */
screamer 28:0e774865873d 18383
screamer 28:0e774865873d 18384 /**
screamer 28:0e774865873d 18385 * @}
screamer 28:0e774865873d 18386 */
screamer 28:0e774865873d 18387
screamer 28:0e774865873d 18388 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/